CN118192006A - Method of manufacturing optical device - Google Patents

Abstract

Embodiments of the present application provide an optical device and a method of manufacturing that forms a first active layer of the optical device. After forming the first active layer of the optical device, a second active layer of the optical device is fabricated over the first active layer of the optical device, wherein the second active layer of the optical device is formed to produce an optical device having a crystalline material. Embodiments of the application also relate to methods of manufacturing optical devices.

Description

Method of manufacturing optical device

Technical Field

Embodiments of the application relate to methods of manufacturing optical devices.

Background

Electrical signal conduction and processing is a technique for signal transmission and processing. In recent years, optical signal transmission and processing has been used for more and more applications, in particular because of the use of optical fiber related applications for signal transmission.

Optical signal conduction and processing is often combined with electrical signal conduction and processing to provide a comprehensive application. For example, optical fibers may be used for remote signal transmission, while electrical signals may be used for short range signal transmission and processing and control. Thus, a device is formed that integrates both long-range optical and short-range electronic components for conversion between optical signals and electrical signals and processing of optical signals and electrical signals. Thus, the package may comprise an optical (photonic) die comprising the optical device and an electronic die comprising the electronic device.

Disclosure of Invention

According to an embodiment of the present application, there is provided a method of manufacturing an optical device, the method including: forming a first active layer of a first optical component on a substrate; and after forming the first active layer, fabricating a second optical component from the crystalline semiconductor material.

According to another embodiment of the present application, there is provided a method of manufacturing an optical device, the method including: depositing a core material on a substrate; annealing the core material; and forming an optical device over the core material after annealing the core material, the optical device comprising a crystalline material after forming the optical device.

According to yet another embodiment of the present application, there is provided a method of manufacturing an optical device, the method including: receiving a substrate; depositing a cladding material over the substrate; depositing a core material over the cladding material; annealing the core material at a temperature above 1100 ℃ to remove defects; forming a crystalline material over the core material after annealing; patterning the crystalline material to form an optical component; and forming a metallization layer over the optical component.

Drawings

Aspects of the disclosure may be best understood from the following detailed description when read in connection with the accompanying drawings. It should be noted that the various components are not drawn to scale according to standard practice in the industry. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1 illustrates formation of a first active layer of an optical assembly according to some embodiments.

Fig. 2 illustrates deposition of a crystalline insulator layer according to some embodiments.

Fig. 3 illustrates deposition of a crystalline layer according to some embodiments.

Fig. 4 illustrates the formation of an optical assembly according to some embodiments.

Fig. 5 illustrates the formation of cladding material around an optical component according to some embodiments.

Fig. 6 illustrates the formation of a metallization layer according to some embodiments.

Fig. 7-11 illustrate the formation of an optical component using an amorphous layer and an annealing process, according to some embodiments.

Fig. 12-15 illustrate the formation of an optical component using a silicon-on-insulator substrate.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component, such that the first component and the second component may not be in direct contact. Further, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the embodiments and/or configurations discussed.

In addition, spatially relative terms such as "below …," "below …," "lower," "above …," "upper," and the like may be used herein for ease of description to describe one element or component's relationship to another element or component as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise positioned (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Embodiments will now be described with respect to particular embodiments of Optical Engines (OE) in which optical waveguides (and/or other optical components) are fabricated prior to fabrication of the optical components' front-end-of-line processes, to avoid thermal limitations after the front-end-of-line optical components have been formed. However, the embodiments presented herein are intended to illustrate the ideas presented and are not intended to be limiting. Thus, the ideas presented may be implemented in various embodiments, such as in Optical Computing (OC) or co-packaged optics (CPO) in an N3-N7 process node, and all such embodiments are fully intended to be included within the scope of the embodiments.

Referring now to fig. 1, an initial structure of a first substrate 101 is shown, with a first active layer 103 of a first optical component 104 formed over the first substrate 101, which is the first step in the formation of the optical engine 100 (shown more fully in fig. 6, and intermediate steps in the manufacturing process are shown in fig. 1). Looking first at the first substrate 101, the first substrate 101 may include an active layer of doped or undoped bulk silicon, or a silicon-on-insulator (SOI) substrate. Typically, the SOI substrate comprises a layer of semiconductor material, such as silicon, germanium, silicon germanium, SOI, silicon Germanium On Insulator (SGOI), or a combination thereof. Other substrates that may be used include multilayer substrates, gradient substrates, or hybrid orientation substrates. Further, at this time of the process, the first substrate 101 may be a portion of a semiconductor wafer (the entire wafer is not shown in fig. 1) to be divided in a subsequent step.

A first active layer 103 of a first optical component 104 is formed over the first substrate 101. In an embodiment, the first optical component 104 located within the first active layer 103 includes a variety of optical components that can be annealed at higher temperatures than subsequently fabricated devices (discussed further below), such as optical waveguides (e.g., ridge waveguides, rib waveguides, buried channel waveguides, diffusion waveguides, etc.), couplers (e.g., grating couplers, edge couplers, which are narrow waveguides having a width between about 1nm and about 200 nm), directional couplers, optical modulators (e.g., mach-zehnder silicon photon converters, microelectromechanical converters, micro-ring resonators, etc.), amplifiers, multiplexers, demultiplexers, combinations of these, and the like. However, any suitable first optical assembly 104 may be used.

In a particular embodiment, and as particularly shown in fig. 1, the first optical component 104 within the first active layer 103 includes a first cladding layer 105, a first waveguide 107, a second cladding layer 109, a second waveguide 111, a third cladding layer 113, a third waveguide 115, and a fourth cladding layer 117. In an embodiment, the first cladding layer 105 may be a cladding material and/or a dielectric layer, such as silicon oxide, silicon nitride, germanium oxide, germanium nitride, combinations of these, and the like, formed using deposition methods such as thermal oxidation, low temperature plasma enhanced chemical vapor deposition, other chemical vapor deposition processes, atomic layer deposition, physical vapor deposition, combinations of these, and the like. However, any suitable materials and manufacturing methods may be utilized.

Further, the first cladding layer 105 may be formed to a reduced thickness from previous manufacturing methods in view of the benefits obtained using the embodiments described herein. For example, in some embodiments, the first cladding layer 105 may be fabricated to a first thickness T1 of less than about 4 μm, such as between about 2 μm and about 4 μm. If the first thickness T1 is less than this thickness, the first cladding layer 105 may not be sufficient to provide a suitable cladding layer for the first waveguide 107 (and/or other optical components). Also, if the first thickness T1 is greater than this thickness, the total thickness of the device may be greater than desired.

Once the first cladding layer 105 has been formed, the first waveguide 107 may be formed over the first cladding layer 105. In embodiments, the first waveguide 107 may be any suitable type of waveguide (e.g., ridge waveguide, rib waveguide, buried channel waveguide, diffusion waveguide, etc.), and may be formed to a thickness of between about 0.1 μm and about 1 μm by initially depositing a core material (such as silicon nitride, a-silicon (amorphous silicon), alN, al ₂O₃、Ta₂O₅, a combination of these, etc.) using a deposition method (such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, a combination of these, etc.). Once the core material has been deposited over the first cladding layer 105, the core material is patterned into the design shape of the first waveguide 107 using, for example, photolithographic masking and etching processes. However, any suitable material, thickness, and method of manufacture may be utilized.

After the first waveguide 107 has been formed, a cladding layer 109 is formed over the first waveguide 107. In an embodiment, the second cladding layer 109 may be formed using similar materials and formation methods as the first cladding layer 105 described above, such as depositing a material such as silicon oxide using a deposition method (such as low temperature plasma enhanced chemical vapor deposition). However, any suitable materials and manufacturing methods may be utilized.

After the second cladding layer 109 has been formed, a second waveguide 111 may be formed over the second cladding layer 109. In an embodiment, the second waveguide 111 may be formed using similar materials and similar fabrication methods as the first waveguide 107 described above, such as using chemical vapor deposition to deposit a material such as silicon nitride. However, any suitable materials and manufacturing methods may be utilized.

After the second waveguide 111 has been formed, a third cladding layer 113 may be formed over the second waveguide 111. In an embodiment, the third cladding layer 113 may be formed using similar materials and formation methods as the first cladding layer 105 described above, such as depositing a material such as silicon oxide using a deposition method (such as low temperature plasma enhanced chemical vapor deposition). However, any suitable materials and manufacturing methods may be utilized.

After the third cladding layer 113 has been formed, the third waveguide 115 may be formed over the third cladding layer 113. In an embodiment, the third waveguide 115 may be formed using similar materials and similar fabrication methods as the first waveguide 107 described above, such as using chemical vapor deposition to deposit a material such as silicon nitride. However, any suitable materials and manufacturing methods may be utilized.

Once the third waveguide 115 has been formed, a fourth cladding layer 117 may be formed over the third waveguide 115. In an embodiment, fourth cladding layer 117 may be a cladding material formed using a deposition method (such as thermal oxidation, low temperature plasma enhanced chemical vapor deposition, other chemical vapor deposition processes, atomic layer deposition, physical vapor deposition, combinations of these, etc.), such as silicon oxide, silicon nitride, germanium oxide, germanium nitride, combinations of these, and the like.

Further, the fourth cladding layer 117 may be formed to a reduced thickness from the previous manufacturing method in view of the benefits obtained using the embodiments described herein. For example, in some embodiments, fourth cladding layer 117 may be fabricated to a second thickness T2 of less than about 4 μm, such as between about 2 μm and about 4 μm. If the second thickness T2 is less than this thickness, the fourth cladding layer 117 may not be sufficient to provide a suitable cladding layer for the third waveguide 115 (and/or other optical components). Moreover, if the second thickness T2 is greater than this thickness, the total thickness of the device may be greater than desired.

Once the first, second and third waveguides 107, 111, 115 have been formed, the first, second and third waveguides 107, 111, 115 may be annealed using, for example, a first annealing process (represented in fig. 1 by curved arrows labeled 119). In an embodiment, the first annealing process 119 may be a thermal annealing process performed at a temperature that is not constrained by the presence of other optical devices that have not yet been fabricated (e.g., the second active layer 401 seen below with respect to fig. 4). In a particular embodiment, the first annealing process 119 may be performed at a temperature between about 1100 ℃ and about 1250 ℃. However, any other suitable annealing process and suitable temperature may be utilized.

Further, while the above is described as performing the first annealing process 119 after each of the first, second, and third waveguides 107, 111, 115 has been formed, this is intended to be illustrative and not intended to be limiting. Rather, any number of anneals may be performed at any suitable time within the manufacturing process. For example, the first annealing process 119 may be repeated a plurality of times, such as by being performed after each of the first waveguide 107, the second waveguide 111, and the third waveguide 115 is manufactured. Any suitable number of anneals at any suitable time in the manufacturing process may be utilized, and all such combinations are fully intended to be included within the scope of the embodiments.

By forming the first waveguide 107, the second waveguide 111, and the third waveguide 115 before forming other optical components, the first annealing process 119 may be performed at a higher temperature, which reduces impurities within the first waveguide 107, the second waveguide 111, and the third waveguide 115. By reducing impurities within the first waveguide 107, the second waveguide 111, and the third waveguide 115, less cladding material may be used around the first waveguide 107, the second waveguide 111, and the third waveguide 115, and the thickness of surrounding cladding material (e.g., the first cladding layer 105 and the fourth cladding layer 117) may be further reduced. Furthermore, higher temperatures can be performed without negatively affecting other optical components that have not yet been manufactured.

Fig. 2 shows that the fabrication of the additional optical component begins once the first annealing process 119 has been performed. In a particular embodiment, fabrication of the additional optical component may begin by first forming a crystalline insulator layer 201 over the fourth cladding layer 117 as a first step in an Epitaxial On Insulator (EOI) process. In an embodiment, the crystalline insulator layer 201 is a material (not shown in fig. 2, but further shown and described below with respect to fig. 3) that may be used as a seed layer for subsequent epitaxial growth, such as beryllium oxide (BeO), aluminum nitride (AlN), combinations of these, and the like. The crystalline insulator layer 201 may be formed using a deposition process (such as atomic layer deposition, chemical vapor deposition, physical vapor deposition, combinations of these, etc.), which may deposit the material as a single crystal, even though the underlying material is not crystalline. However, any suitable material and any suitable deposition process may be utilized.

Fig. 3 shows the deposition of a layer of material 301 for the second active layer 401 of the second optical component 403. The material 301 for the second active layer 401 is initially (prior to patterning) a conformal layer of crystalline material that will be used to begin fabrication of the second active layer 401 of the second optical component 403 (not shown in fig. 3, but further shown and described below with respect to fig. 4). In embodiments, the material 301 for the second active layer 401 may be a translucent material that may be used as a core material for the second optical component 403, such as a semiconductor material, e.g., silicon, germanium, silicon germanium, combinations of these, etc., while in other embodiments, the material 301 for the second active layer 401 may be a dielectric material, such as silicon nitride, etc., but in other embodiments, the material 301 for the second active layer 401 may be a group III-V material, a lithium niobate material, or a polymer. Any suitable material may be utilized.

In embodiments where the material 301 of the second active layer 401 is monocrystalline silicon, the material 301 may be deposited using a method such as epitaxial growth using the crystalline insulator layer 201 as a seed layer, but in other embodiments other deposition methods may be used, such as chemical vapor deposition, atomic layer deposition, physical vapor deposition, combinations of these, and the like. Further, in this embodiment, the layer of material 301 may be grown or otherwise deposited to a thickness between about 200nm and about 500 nm. However, any suitable manufacturing method and thickness may be utilized.

Fig. 4 shows that the material 301 for the second active layer 401 is used to fabricate a second optical component 403 of the second active layer 401 once the material 301 for the second active layer 401 is ready. Furthermore, any remaining material of the crystalline insulator layer 201 is not shown for clarity purposes. In an embodiment, the second optical component 403 of the second active layer 401 may include any of a variety of photonic devices according to the device being designed, and may include any such components, such as optical waveguides, couplers, modulators, amplifiers, multiplexers, demultiplexers, optoelectronic converters, electro-optic converters, lasers, combinations of these, and the like. Fig. 4 shows four such devices, such as a first device, a second device, a third device, and a fourth device, which may be one or more optical devices, active devices (e.g., transistors), passive devices, or a combination thereof. However, any suitable second optical assembly 403 and any suitable combination of devices may be used.

To begin forming the second active layer 401 of the second optical assembly 403 from the material 301, the material 301 for the second active layer 401 may be patterned into a design shape for the second active layer 401 of the second optical assembly 403. In an embodiment, the material 301 for the second active layer 401 may be patterned using, for example, one or more photolithographic masking and etching processes. However, any suitable method of patterning the material 301 for the second active layer 401 may be utilized.

For those components that utilize further fabrication processes, additional processing may be performed before or after patterning of the material 301 for the second active layer 401. For example, implantation processes, additional deposition and patterning processes for different materials, combinations of all of these processes, and the like may be utilized to help further manufacture the various second optical components 403. In certain embodiments, and as particularly shown in fig. 4, in some embodiments, epitaxial deposition of a semiconductor material 405 (such as germanium) may be performed on the patterned portion of material 301 of the second active layer 401. In such embodiments, the material 301 may be epitaxially grown to aid in the fabrication of the second optical component 403 of the second active layer 401. All such fabrication processes may be utilized, and all suitable second optical assemblies 403 may be fabricated, and all such combinations are fully intended to be included within the scope of the embodiments.

Fig. 5 shows that once the second optical component 403 of the separate second active layer 401 has been formed, a second insulator layer 501 may be deposited to cover the second optical component 403 and provide additional cladding material. In an embodiment, the second insulator layer 501 may be a dielectric layer that separates the individual components of the second active layer 401 from each other and from the structure above, and may additionally serve as another portion of the cladding material surrounding the second optical component 403. In an embodiment, the second insulator layer 501 may be silicon oxide, silicon nitride, germanium oxide, germanium nitride, combinations of these, and the like, formed using a deposition method such as chemical vapor deposition, atomic layer deposition, physical vapor deposition, combinations of these, and the like. Once the material of the second insulator layer 501 has been deposited, it may be planarized using, for example, a chemical mechanical polishing process, in order to planarize the top surface of the second insulator layer 501 (in embodiments where the second insulator layer 501 is intended to completely cover the second optical component 403) or to flush the second insulator layer 501 with the top surface of the second optical component 403. However, any suitable materials and manufacturing methods may be used.

Fig. 6 shows that once the second optical component 403 of the second active layer 401 has been manufactured and the second insulator layer 501 has been formed, the first metallization layer 503 is formed to electrically connect the second active layers 401 of the second optical component 403 to the control circuitry, to each other, and to subsequently attached devices (not shown in fig. 6). In an embodiment, the first metallization layer 503 is formed of alternating layers of dielectric material and conductive material, and may be formed by any suitable process, such as deposition, damascene, dual damascene, etc. In certain embodiments, there may be multiple metallization layers interconnecting the individual second optical components 403, but the exact number of first metallization layers 503 depends at least in part on the design of the device.

Optionally, one or more third optical components (not separately shown) may be formed as part of the first metallization layer 503 during the fabrication of the first metallization layer 503. In some embodiments, the third optical component of the first metallization layer 503 may include components such as a coupler (e.g., edge coupler, grating coupler, etc.), an optical waveguide (e.g., ridge waveguide, rib waveguide, buried channel waveguide, diffusion waveguide, etc.), an optical modulator (e.g., mach-zehnder silicon photonic converter, microelectromechanical converter, micro-ring resonator, etc.), an amplifier, a multiplexer, a demultiplexer, an optical-to-electrical converter (e.g., P-N junction), an electro-optical converter, a laser, combinations of these, etc., for connecting to an external signal. However, any suitable optical component may be used for the one or more third optical components.

In an embodiment, the one or more third optical components may be formed by initially depositing a material for the one or more third optical components. In an embodiment, the material for the one or more third optical components may be a dielectric material such as silicon nitride, silicon oxide, combinations of these, or the like, or a semiconductor material such as silicon, deposited using a deposition method such as chemical vapor deposition, atomic layer deposition, physical vapor deposition, combinations of these, or the like. However, any suitable material and any suitable deposition method may be utilized.

Once the material for the one or more third optical components has been deposited or otherwise formed, the material may be patterned into a desired shape for the one or more third optical components. In embodiments, the material of the one or more third optical components may be patterned using, for example, one or more photolithographic masking and etching processes. However, any suitable method of patterning the material for the one or more third optical components may be utilized.

For some of the one or more third optical components, such as waveguides or edge couplers, the patterning process may be all or at least a majority of the fabrication used to form these components. Furthermore, for those components that utilize further fabrication processes, such as mach-zehnder silicon photon converters that utilize resistive heating elements, additional processing may be performed before or after patterning of the material for the one or more third optical components. For example, implantation processes, additional deposition and patterning processes for different materials, combinations of all of these processes, etc. may be used to help further manufacture various one or more third optical components. All such fabrication processes may be utilized, all suitable one or more third optical components may be fabricated, and all such combinations are fully intended to be included within the scope of the embodiments.

Furthermore, in some embodiments, the third optical component may be annealed after patterning. In such an embodiment, the annealing of the third optical component takes into account the presence of the already manufactured second optical component 403. Thus, the third optical component may be annealed at a temperature of less than about 450 ℃. However, any suitable temperature may be utilized.

Once the one or more third optical components of the first metallization layer 503 have been manufactured, a first bonding layer 505 is formed over the first metallization layer 503. In an embodiment, the first bonding layer 505 may be used for subsequent dielectric-to-dielectric bonding as well as metal-to-metal bonding. According to some embodiments, the first bonding layer 505 is formed of a first dielectric material 507 such as silicon oxide, silicon nitride, or the like. The first dielectric material 507 may be deposited using any suitable method such as CVD, high Density Plasma Chemical Vapor Deposition (HDPCVD), PVD, atomic Layer Deposition (ALD), and the like. However, any suitable materials and deposition processes may be utilized.

Once the first dielectric material 507 has been formed, a first opening is formed in the first dielectric material 507 to expose a conductive portion of the underlying layer in preparation for forming a first bond pad 509 within the first bond layer 505. Once the first openings have been formed in the first dielectric material 507, the first openings may be filled with a seed layer and metallization to form first bond pads 509 in the first dielectric material 507. A seed layer may be blanket deposited over the top surface of the first dielectric material 507, the exposed conductive portions of the underlying layer, and the sidewalls of the first opening. The seed layer may comprise a copper layer. Depending on the material, a process such as sputtering, evaporation, or Plasma Enhanced Chemical Vapor Deposition (PECVD) may be used to deposit the seed layer. The metallization may be deposited over the seed layer by a plating process such as electroplating or electroless plating. The metallization may include copper, copper alloys, and the like. The metallization may be a filler material. A barrier layer (not separately shown) may be blanket deposited over the top surface of the first dielectric material 507 and over the sidewalls of the first opening prior to the seed layer. The barrier layer may include titanium, titanium nitride, tantalum nitride, and the like.

After filling the first openings, a planarization process such as CMP is performed to remove the seed layer and the excess portion of the metallization, forming first bond pads 509 within the first bond layer 505. In some embodiments, bond pad vias may also be used to connect the first bond pad 509 with the underlying conductive portion and to connect the first bond pad 509 with the first metallization layer 503 through the underlying conductive portion.

In addition, the first bonding layer 505 may also include one or more fourth optical components (not separately shown) that are incorporated within the first bonding layer 505. In such embodiments, prior to depositing the first dielectric material 507, one or more fourth optical components, such as waveguides and other structures formed at least in part by deposition and patterning processes, may be fabricated using similar methods and similar materials as the one or more third optical components (described above). However, any suitable structure, material, and any suitable method of manufacture may be utilized.

By forming the first active layer 103 of the first optical component 104 prior to forming any crystalline material (e.g., for forming the second optical component 403 in the second active layer 401), the material within the first active layer 103 of the first optical component 104 may be annealed at a higher temperature that is not limited by the temperature of the subsequent crystalline material (typically below 450 ℃). Thereby, a higher temperature may be used to reduce defects in the material of the first active layer 103 for the first optical component 104, thereby improving the overall quality of the material of the first active layer 103 for the first optical component 104 and optical losses may be reduced. As the optical loss within the first optical assembly 104 decreases, the surrounding cladding materials (e.g., first cladding layer 105, second cladding layer 109, third cladding layer 113, and fourth cladding layer 117) may also be formed to a smaller thickness, such as a 50% reduction in thickness, thereby reducing the overall thickness of the device.

Furthermore, by forming the first active layer 103 of the first optical component 104 on the first substrate 101, the use of a silicon-on-insulator (SOI) substrate may become optional throughout the manufacturing process. For example, a commonly used SOI substrate may be substituted for a single material substrate such as a silicon substrate. Thus, cheaper substrates can be used and a more cost-effective manufacturing process can be obtained.

Fig. 7 to 9 illustrate another method of forming the second active layer 401 of the second optical assembly 403 after forming the first active layer 103. In the present embodiment, referring first to fig. 7, instead of depositing the crystalline insulator layer 201 on the fourth cladding layer 117 as shown and discussed above with respect to fig. 2, the crystalline insulator layer 201 is not deposited and the amorphous layer 701 is directly deposited on the fourth cladding layer 117. In this embodiment, amorphous layer 701 may be a material similar to material 301 (described above with respect to fig. 3), but is deposited in an amorphous, non-crystalline form. In embodiments where silicon is used to form the second optical component 403, the amorphous layer 701 may be amorphous silicon deposited using a deposition process such as CVD, PVD, ALD, a combination of these, or the like. However, any suitable material and any suitable process may be utilized.

Fig. 8 shows patterning of an amorphous layer 701. In an embodiment, the amorphous layer 701 may be patterned into a design shape of the second active layer 401 for the second optical component 403. In an embodiment, amorphous layer 701 may be patterned using, for example, one or more photolithographic masking and etching processes. For some second optical components 403, such as waveguides and couplers, this is all the patterning performed. However, any suitable method of patterning the amorphous layer 701 may be utilized.

Fig. 9 shows that once the amorphous layer 701 has been patterned into the design shape of the second optical components 403, further processing may be performed to form additional components for some of the second optical components 403. For example, for those components that utilize further fabrication processes, such as mach-zehnder silicon photon converters that utilize resistive heating elements, additional processing may be performed before or after patterning of the material for the second active layer 401. For example, implantation processes, additional deposition and patterning processes for different materials (e.g., resistive heating elements, III-V materials for the converter), combinations of all of these processes, etc., may be utilized to help further fabricate the various second optical components 403.

Further, in certain embodiments, and as specifically shown in fig. 9, in some embodiments, deposition of a second amorphous material 901 may be performed on the patterned portions of amorphous layer 701. In an embodiment, the second amorphous material 901 may be a material similar to the semiconductor material 405 (discussed above with respect to fig. 4), but it is deposited in an amorphous, non-crystalline form. In embodiments where the semiconductor material 405 is germanium (e.g., for electrical/optical signal modulation and conversion), a second amorphous material 901 is deposited over the patterned amorphous layer 701. All such fabrication processes may be employed, and all suitable second optical assemblies 403 may be fabricated, and all such combinations are fully intended to be included within the scope of the embodiments.

Fig. 10 shows that once the various materials for the second optical component 403 have been formed from amorphous materials, such as amorphous layer 701 and second amorphous material 901, the patterned materials of amorphous layer 701 and second amorphous material 901 are annealed using a second annealing process (represented by wavy lines labeled 1001 in fig. 10) to change the materials of amorphous layer 701 and second amorphous material 901 to crystalline materials in order to improve the quality of the second optical component 403.

In an embodiment, the second annealing process 1001 may be a laser annealing performed on each individual device of the second optical assembly 403 in turn. In such embodiments, the laser annealing process may be performed at an energy density between about 0.2J/cm ² and about 2J/cm ² for a period of time between about 10 nanoseconds and about 1 microsecond. Thus, the laser annealing can raise the temperature of various amorphous materials and convert the amorphous materials into single-crystal materials. However, any suitable process conditions may be utilized.

However, in other embodiments, furnace anneals may be utilized to anneal all of the second optical components 403 simultaneously. In this embodiment, the second annealing process 1001 may be a thermal annealing process using a furnace performed at a temperature between about 1100 ℃ and about 1300 ℃ for a period of between about 60 minutes and about 120 minutes. However, any other suitable annealing process and suitable temperature may be utilized.

Of course, while a particular set of depositions and anneals has been described below, this is intended to be illustrative only and is not intended to limit the embodiments. Rather, any suitable combination of deposition, annealing, and subsequent deposition of amorphous material may be utilized. For example, in still other embodiments, an amorphous layer 701 may be deposited and patterned, and a second annealing process 1001 may be performed to crystallize the amorphous layer 701 into the material 301, and then build up various devices after the crystals are formed. For example, the semiconductor material 405 may be deposited using, for example, an epitaxial deposition process after the second annealing process 1001 is performed. Any suitable method and combination of steps may be utilized to utilize amorphous deposition and crystallization processes as part of the formation of the second optical component 403. All such steps and combinations are fully intended to be included within the scope of the embodiments.

Fig. 11 shows that once the second annealing process 1001 has been performed, the remainder of the process steps described above with respect to fig. 5-6 may be performed. For example, a second insulator layer 501 may be deposited, a first metallization layer 503 may be formed over the second insulator layer 501, and a first bonding layer 505 may be formed over the first metallization layer 503. However, any suitable number of process steps and structures may be used.

Additional options for forming the second optical component 403 are possible by utilizing a method of forming the second optical component 403 using amorphous deposition and crystallization processes. Thus, the manufacturer may still form the first optical assembly 104 as described herein while still finding the most efficient process for manufacturing the entire device.

Fig. 12 to 15 show another embodiment in which the first active layer 103 is formed and annealed before the second active layer 401 is formed. However, in this embodiment, instead of depositing a crystalline layer (as described above with respect to fig. 1-6) or depositing an amorphous layer and crystallizing the material (as described above with respect to fig. 7-11), a second active layer 401 is formed using a Substrate On Insulator (SOI) 1201. In a particular embodiment, the SOI 1201 includes a second substrate 1203, a first insulator layer 1205, and a material 1207 for the second optical component 403. Looking first to the second substrate 1203, the second substrate 1103 can be a semiconductor material such as silicon or germanium, a dielectric material such as glass, or any other suitable material that allows for structural support for the layers above.

The first insulator layer 1205 may be a dielectric layer separating the second substrate 1203 from the overlying material 1207. In an embodiment, the first insulator layer 1205 may be silicon oxide, silicon nitride, germanium oxide, germanium nitride, combinations of these, or the like, formed using a method such as implantation (e.g., forming a Buried Oxide (BOX) layer) or may be deposited on the second substrate 1203 using a deposition method such as chemical vapor deposition, atomic layer deposition, physical vapor deposition, combinations of these, or the like. However, any suitable materials and manufacturing methods may be used.

Material 1207 is initially (prior to patterning) a conformal layer of material that will be used to begin fabrication of the second active layer 401 of the second optical component 403. In embodiments, the material 1207 for the second active layer 401 may be a translucent material such as a semiconductor material, such as silicon, germanium, silicon germanium, combinations of these, or the like, that may be used as a core material for the second optical component 403, while in other embodiments, the material 1207 for the second active layer 401 may be a dielectric material such as silicon nitride, or the like, but in other embodiments, the material 1207 for the second active layer 401 may be a group III-V material, a lithium niobate material, or a polymer. In embodiments where the material 1207 of the second active layer 401 is deposited, methods such as epitaxial growth, chemical vapor deposition, atomic layer deposition, physical vapor deposition, combinations of these, and the like may be used to deposit the material 1207 for the second active layer 401. In other embodiments where the first insulator layer 1205 is formed using an implantation method, the material 1207 of the second active layer 401 may initially be part of the second substrate 1203 prior to the implantation process forming the first insulator layer 1205. However, the material 1207 of the second active layer 401 may be formed using any suitable material and manufacturing method.

Fig. 12 also shows SOI 1201 bonded to fourth cladding layer 117. To begin the process of bonding the SOI 1201 to the fourth cladding layer 117, the surface of the SOI 1201 and the surface of the fourth cladding layer 117 may be initially activated. As an example, activating the top surfaces of the SOI 1201 and the fourth cladding layer 117 may include, for example, a dry process, a wet process, a plasma process, an exposure to an inert gas plasma, an exposure to H ₂, an exposure to N ₂, an exposure to O ₂, combinations thereof, and the like. In embodiments using wet processing, RCA cleaning may be used, for example. In another embodiment, the activation process may include other types of processing. The activation process helps bond the SOI 1201 to the fourth cladding layer 117.

After the activation process, SOI 1201 and fourth cladding layer 117 may be placed in physical contact. In an embodiment, SOI 1201 is placed in physical contact with fourth cladding layer 117 using, for example, an alignment process, so as to minimize overlay variations during the placement process. In the case of an activation process that chemically modifies the surface, the bonding process between the materials begins upon physical contact.

Once the physical contact begins the bonding process, the assembly may then be subjected to a heat treatment to strengthen the bond. In an embodiment, SOI 1201 and fourth cladding layer 117 may be subjected to a temperature between about 200 ℃ and about 400 ℃ to strengthen the bond. In this way, the melting of SOI 1201 and fourth cladding layer 117 forms a bonded device.

Further, while specific processes have been described to initiate and strengthen the bond between the SOI 1201 and the fourth cladding layer 117, these descriptions are intended to be illustrative and not intended to limit the embodiments. For example, in other embodiments, portions of material 1207 may be oxidized prior to the start of the bonding process to start the oxide-to-oxide bonding process. Thus, any suitable combination of baking, annealing, pressing, or combinations of processes may be utilized. All such processes are fully intended to be included within the scope of the examples.

Moreover, while one type of bonding has been described for bonding the SOI 1201 to the fourth cladding layer 117, this is also intended to be illustrative only and is not intended to limit the embodiments. Instead, any suitable bonding method may be utilized, such as dielectric-to-dielectric bonding, metal-to-metal bonding, and the like. Any suitable method of bonding the SOI 1201 to the fourth cladding layer 117 may be utilized and all such methods are fully intended to be included within the scope of the embodiments.

Fig. 13 shows that once the SOI 1201 is bonded to the fourth cladding layer 117, the second substrate 1203 and the first insulator layer 1205 are removed. In an embodiment, the second substrate 1203 and the first insulator layer 1205 may be removed using a planarization process, such as a chemical mechanical polishing process, a grinding process, or the like. However, any suitable removal process may be used, such as one or more etching processes that sequentially remove material of the second substrate 1203 and the first insulator layer 1205. All such removal processes are fully intended to be included within the scope of the embodiments.

Fig. 14 shows that once the second substrate 1203 and the first insulator layer 1205 have been removed to expose the material 1207, the material 1207 may be patterned into the design shape of the second optical assembly 403. In an embodiment, material 1207 may be patterned using, for example, one or more photolithographic masking and etching processes. However, any suitable method of patterning the material 1207 for the second active layer 401 may be utilized. For some second optical components 403, such as waveguides or edge couplers, the patterning process may be all or at least a majority of the fabrication used to form these second optical components 403.

Once the material 1207 has been patterned, further processing may be performed to form a second optical component 403 for other optical components that utilize further processing. For example, for those components that utilize further fabrication processes, such as mach-zehnder silicon photon converters that utilize resistive heating elements, additional processing may be performed before or after patterning of the material for the second active layer 401. For example, implantation processes, additional deposition and patterning processes for different materials (e.g., resistive heating elements, III-V materials for the converter), combinations of all of these processes, etc., may be utilized to help further fabricate the various second optical components 403. In particular embodiments, and as particularly shown in fig. 14, in some embodiments, epitaxial deposition of a semiconductor material 405, such as germanium, may be performed on the patterned portions of material 1207 (e.g., for electrical/optical signal modulation and conversion). In such an embodiment, the semiconductor material 405 may be epitaxially grown to aid in the fabrication of a photodiode, for example, for a photoelectric converter. All such fabrication processes may be utilized, and all suitable second optical assemblies 403 may be fabricated, and all such combinations are fully intended to be included within the scope of the embodiments.

Fig. 15 shows that once the second optical component 403 has been formed, the remainder of the process steps described above with respect to fig. 5 to 6 can be performed. For example, a second insulator layer 501 may be deposited, a first metallization layer 503 may be formed over the second insulator layer 501, and a first bonding layer 505 may be formed over the first metallization film 503. However, any suitable number of process steps and structures may be used.

By forming the first active layer 103 of the first optical component 104 before any crystalline material is formed, e.g. for forming the second optical component 403 in the second active layer 401, the material within the first active layer 103 of the first optical component 104 may be annealed at a higher temperature than is suitable for subsequent crystalline materials, typically below 450 ℃. Thereby, a higher temperature may be used to reduce defects in the material of the first active layer 103 for the first optical component 104, thereby improving the overall quality of the material of the first active layer 103 for the first optical component 104 and optical losses may be reduced. As the optical loss within the first optical assembly 104 decreases, the surrounding cladding materials (e.g., first cladding layer 105, second cladding layer 109, third cladding layer 113, and fourth cladding layer 117) may also be formed to a smaller thickness, such as a 50% reduction in thickness, thereby reducing the overall thickness of the device.

In an embodiment, a method of manufacturing an optical device includes: forming a first active layer of a first optical component on a substrate; and after forming the first active layer, fabricating a second optical component from the crystalline semiconductor material. In an embodiment, the method further comprises annealing the first active layer of the first optical component before manufacturing the second optical component. In an embodiment, the first active layer is annealed at a temperature between about 1100 ℃ and 1250 ℃. In an embodiment, fabricating the second optical component further comprises depositing a crystalline seed layer. In an embodiment, fabricating the second optical component further comprises epitaxially growing a crystalline semiconductor material on the crystalline seed layer. In an embodiment, fabricating the second optical assembly further comprises bonding the crystalline semiconductor material to the first active layer. In an embodiment, fabricating the second optical assembly further comprises: depositing an amorphous material; and crystallizing the amorphous material.

In another embodiment, a method of manufacturing an optical device, the method comprising: depositing a core material on a substrate; annealing the core material; and forming an optical device over the core material after annealing the core material, the optical device comprising a crystalline material after forming the optical device. In an embodiment, the core material is annealed at a temperature between about 1100 ℃ and about 1250 ℃. In an embodiment, forming the optical device includes crystallizing the amorphous material. In an embodiment, the method further comprises bonding the silicon-on-insulator structure to the cladding material over the core material. In an embodiment, the method further comprises removing the semiconductor substrate and the insulating layer from the silicon-on-insulator structure. In an embodiment, the method further comprises depositing beryllium oxide material over the core material. In an embodiment, the method further comprises epitaxially growing a crystalline material on the beryllium oxide material.

In yet another embodiment, a method of manufacturing an optical device includes: receiving a substrate; depositing a cladding material over the substrate; depositing a core material over the cladding material; annealing the core material at a temperature above 1100 ℃ to remove defects; forming a crystalline material over the core material after annealing; patterning the crystalline material to form an optical component; and forming a metallization layer over the optical component. In an embodiment, the substrate is a single material substrate. In an embodiment, the cladding material has a first thickness of less than 4 μm. In an embodiment, the method further comprises depositing a second cladding material over the topmost portion of the core material, the second cladding material having a second thickness between 2 μm and 4 μm. In an embodiment, forming the crystalline material further comprises: depositing an aluminum nitride layer; and epitaxially growing a crystalline material on the aluminum nitride layer. In an embodiment, forming the crystalline material further comprises: depositing beryllium oxide material; and epitaxially growing a crystalline material on the beryllium oxide material.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art will appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims (10)

1. A method of manufacturing an optical device, the method comprising:

Forming a first active layer of a first optical component on a substrate; and

After the forming of the first active layer, a second optical component is fabricated from a crystalline semiconductor material.

2. The method of claim 1, further comprising: the first active layer of the first optical component is annealed prior to the fabrication of the second optical component.

3. The method of claim 2, wherein the first active layer is annealed at a temperature between 1100 ℃ and 1250 ℃.

4. The method of claim 1, wherein the fabricating the second optical component further comprises depositing a crystalline seed layer.

5. The method of claim 4, wherein the fabricating the second optical component further comprises epitaxially growing the crystalline semiconductor material on the crystalline seed layer.

6. The method of claim 1, wherein the fabricating the second optical component further comprises bonding the crystalline semiconductor material to the first active layer.

7. The method of claim 1, wherein the fabricating a second optical assembly further comprises:

Depositing an amorphous material; and

The amorphous material is crystallized.

8. A method of manufacturing an optical device, the method comprising:

Depositing a core material on a substrate;

Annealing the core material; and

After the annealing of the core material, an optical device is formed over the core material, the optical device comprising a crystalline material after the forming of the optical device.

9. The method of claim 8, wherein the annealing the core material is performed at a temperature between 1100 ℃ and 1250 ℃.

10. A method of manufacturing an optical device, the method comprising:

receiving a substrate;

Depositing a cladding material over the substrate;

Depositing a core material over the cladding material;

Annealing the core material at a temperature above 1100 ℃ to remove defects;

forming a crystalline material over the core material after the annealing;

patterning the crystalline material to form an optical component; and

A metallization layer is formed over the optical component.