CN118173528A - Semiconductor AIP packaging structure and manufacturing method thereof - Google Patents

Abstract

The invention discloses a semiconductor AIP packaging structure with a chip embedded in a carrier and a manufacturing method thereof, wherein the semiconductor AIP packaging structure comprises a first carrier, a semiconductor chip and a second carrier. The first carrier has at least two first redistribution layers stacked and each first redistribution layer has a first dielectric layer, a first patterned metal layer and/or a first conductive pillar layer. The semiconductor chip is embedded in the first carrier and coupled with the first redistribution layers. The second carrier has a second redistribution layer, a second conductive pillar layer and an air medium layer, wherein the second conductive pillar layer is protruding to the second redistribution layer. The second carrier plate is connected to the first carrier plate through the second conductive column layer, and the air medium layer is located among the second redistribution layer, the second conductive column layer and the first carrier plate.

Description

Semiconductor AIP packaging structure and manufacturing method thereof

Technical Field

The present invention relates to a package and a method for manufacturing the same, and more particularly, to a semiconductor AIP package and a method for manufacturing the same.

Background

Fifth generation mobile communication (5G) using millimeter waves (mmWave) has begun to enter the consumer market. As an important component in a wireless communication system, antennas have recently been most emphasized as Package Antennas (AiP) in a transceiver system formed with a chip.

Referring to fig. 1, a first prior art packaged antenna 10 is shown. The package antenna 10 includes a carrier 11, a first antenna structure 12, a second antenna structure 13, and a chip 14. The carrier 11 has a first surface 111 and a second surface 112 opposite to each other, and a plurality of dielectric layers 113 and a plurality of circuit layers 114 are disposed between the first surface 111 and the second surface 112. The first antenna structure 12 is disposed on the first surface 111 of the carrier 11, and has a dielectric layer 121, a conductive via 122, and a first antenna metal layer 123. The conductive via 122, the first antenna metal layer 123 and the portion of the circuit layer 114 exposed on the first surface 111 are electrically connected.

The second antenna structure 13 is disposed on the first antenna structure 12, and has a dielectric layer 131 and a second antenna metal layer 132 disposed on a surface 1311 of the dielectric layer 131. The flip chip (flip chip) of the die 14 is bonded to the second surface 112 of the carrier 11 and is electrically connected to a portion of the circuit layer 114 exposed on the second surface 112. In addition, the solder balls 15 are also disposed on the second surface 112 of the carrier 11 and electrically connected to another portion of the circuit layer 114 exposed on the second surface 112.

The carrier 11 and the antenna structure of the packaged antenna 10 form an integral flip chip package carrier structure, and the thickness of one side of the core layer and the thickness of the conductive circuit layer are asymmetric, especially the thickness of the dielectric layer of the antenna structure is far thicker than any circuit structure at the end of the carrier, and the integral flip chip package carrier structure is easy to form a flip chip on the carrier to affect the electrical property and has high processing cost.

In addition, the die 14 of the package antenna 10 is flip-chip bonded to the second surface 112 of the carrier 11, in other words, the die 14 is exposed. The exposed wafer also causes that the solder balls have to have enough height to support the accommodating space of the wafer, so that the height of the package is not easy to be thinned.

Referring again to fig. 2, a second prior art packaged antenna 90 is shown. The package antenna 90 includes a carrier 91, a chip 92, a supporting post 93 and an upper carrier 94. The wafer 92 and the support columns 93 are disposed on the carrier 91, respectively. The upper carrier 94 is disposed on the support columns 93, and an air gap 95 is formed between the upper carrier 94 and the carrier 91. In addition, an antenna layer 911 is formed on the upper surface of the carrier 91 and electrically connected to the chip 92. Furthermore, the upper surface of the upper plate 94 is further formed with a frequency selective surface structure 941, which is disposed above the antenna layer 911.

In the second type of package antenna 90 of the prior art, the dielectric constant is reduced and the antenna performance is improved by replacing the dielectric medium of the antenna with the air gap 95, however, the chip 92 is disposed in the air gap 95, so that the chip 92 will cause signal interference during operation, which in turn affects the antenna performance.

In summary, in the fifth generation mobile communication and future communication technologies, the integration of the antenna and the chip package is expected to solve the above-mentioned problems and make the antenna have better antenna performance or smaller package volume (e.g. reduced thickness), which is one of the important issues at present.

Disclosure of Invention

In view of the foregoing, an objective of the present invention is to provide a semiconductor AIP package structure and a manufacturing method thereof, which can improve the electrical problem of the asymmetric warpage of the prior art antenna package, so that the semiconductor AIP package structure has better antenna radiation performance under the same volume.

Another object of the present invention is to provide a semiconductor AIP package and a method for manufacturing the same, which can make the semiconductor AIP package have a smaller package volume under the same antenna radiation efficiency.

To achieve the above objective, the present invention provides a semiconductor AIP package structure, which includes a first carrier, a chip and a second carrier. The first carrier has at least two first redistribution layers stacked and each first redistribution layer has a first dielectric layer, a first patterned metal layer and/or a first conductive pillar layer. The chip is embedded in the first carrier and coupled with the first redistribution layers. The second carrier plate is arranged opposite to the first carrier plate and is provided with a second redistribution layer, a second conductive column layer and an air medium layer, wherein the second conductive column layer is convexly arranged on the second redistribution layer. The second carrier plate is connected to the first carrier plate through the second conductive column layer, the air medium layer is located among the second redistribution layer, the second conductive column layer and the first carrier plate, and the acting surface of the wafer faces away from the second carrier plate.

In an embodiment, the first redistribution layer of the first carrier has a metal susceptor, which is in contact with the wafer and is located between the wafer and the second carrier.

In an embodiment, a portion of the first redistribution layer, a portion of the second redistribution layer, and a portion of the second conductive pillar layer form a transmitting antenna, and another portion of the first redistribution layer, another portion of the second redistribution layer, and another portion of the second conductive pillar layer form a receiving antenna.

In one embodiment, a portion of the first conductive pillar layer and a portion of the second conductive pillar layer are used for adjusting the radiation pattern of the antenna, and the appropriate height is adjusted according to the bandwidth of the application, as if an antenna cavity is formed.

In one embodiment, the second conductive pillar layer is in a fence type or a continuous wall type, and the second conductive pillar layer may frame one or more air medium layer spaces.

In addition, the present invention provides a method for manufacturing a semiconductor AIP package structure, which includes forming a first carrier, forming a second carrier, and combining the first carrier and the second carrier. The step of forming the first carrier comprises sequentially forming at least two stacked first redistribution layers, and embedding a wafer in the at least two stacked first redistribution layers during the process of forming the at least two stacked first redistribution layers, wherein an active surface of the wafer faces away from the second carrier, and the active surface of the wafer is coupled with one of the first redistribution layers. The step of forming the second carrier includes forming a second redistribution layer and forming a second conductive pillar layer protruding from the second redistribution layer. The first carrier plate is combined with the second carrier plate, wherein the second conductive column layer is used for connecting the first carrier plate and the second carrier plate, and an air medium layer is formed among the second redistribution layer, the second conductive column layer and the first carrier plate.

In an embodiment, the step of forming the at least two stacked first redistribution layers of the first carrier further includes forming a second seed layer; forming a photoresist layer with at least one second through hole on the second seed crystal layer; electroplating to form a first patterned metal layer and/or a first conductive column layer in the second through hole; a wafer is connected to the first patterned metal layer, and the active surface of the wafer is coupled with the other first redistribution layer; removing the photoresist layer and the second seed layer; and forming a first dielectric layer to cover the first patterned metal layer and/or the first conductive pillar layer and the wafer.

In an embodiment, before forming the first dielectric layer, the method further includes attaching a wafer to the first patterned metal layer, wherein the active surface of the wafer faces away from the second carrier, and the first dielectric layer further encapsulates the wafer.

In an embodiment, the second conductive pillar layer of the second carrier is connected to the first patterned metal layer or the first conductive pillar layer of the first carrier through solder balls, conductive bumps or conductive adhesive.

In order to achieve the above objective, the present invention also provides another method for manufacturing an AIP package structure, which includes forming a first carrier and forming a second carrier on the first carrier. The step of forming the first carrier comprises sequentially forming at least two stacked first redistribution layers, and embedding a wafer in the at least two stacked first redistribution layers during the process of forming the at least two stacked first redistribution layers, wherein an active surface of the wafer faces away from the second carrier, and the active surface of the wafer is coupled with one of the first redistribution layers. The step of forming the second carrier comprises forming a first seed crystal layer on the first carrier; forming a patterned photoresist layer with at least one first through hole on the first seed layer; electroplating to form a second conductive column layer in the first through hole; forming a second redistribution layer connected to the second conductive pillar layer; and removing the patterned photoresist layer to form an air medium layer among the second redistribution layer, the second conductive column layer and the first carrier.

In summary, the semiconductor AIP package structure and the manufacturing method thereof disclosed in the present invention utilize the air dielectric layer as the dielectric material of the antenna radiation in the semiconductor AIP package structure, and the dielectric constant of air is close to "1", so that the bandwidth of the antenna can be effectively increased or the package volume can be reduced. In addition, the chip in the semiconductor AIP packaging structure is arranged in the packaging in an embedded mode, so that the electric connection of the chip can directly take copper as electric connection through a semiconductor process, no additional conductive bump or solder ball is needed, the packaging thickness can be further reduced, and the process procedure can be simplified.

Drawings

Fig. 1 is a schematic structural diagram of a first prior art package antenna.

Fig. 2 is a schematic structural diagram of a second prior art packaged antenna.

Fig. 3 is a schematic structural view of a semiconductor AIP package according to a first embodiment of the present invention.

Fig. 4A to 4C are schematic views illustrating a manufacturing process of a second carrier in a first manufacturing method corresponding to a semiconductor AIP package according to a first embodiment.

Fig. 4D is a schematic diagram of another second carrier having a different second patterned metal layer according to the first embodiment.

Fig. 5A to 5D are schematic views illustrating a manufacturing process for forming the second redistribution layer.

Fig. 6A to 6F are schematic views illustrating a manufacturing process of a first carrier in a first manufacturing method corresponding to a semiconductor AIP package according to a first embodiment.

Fig. 7A to 7D are schematic views of a manufacturing process corresponding to a second manufacturing method of the semiconductor AIP package according to the first embodiment.

Fig. 8 is a schematic structural view of a semiconductor AIP package according to a second embodiment of the present invention.

Fig. 9 is a schematic structural view of a semiconductor AIP package according to a third embodiment of the present invention.

Wherein, 10,90 is a packaged antenna; 11, a carrier plate; 111 a first surface; 112 a second surface; 113,121,131 a dielectric layer; 114, a circuit layer; a first antenna structure; 122 conductive blind holes; 123 a first antenna metal layer; a second antenna structure; 1311: a surface; 132a second antenna metal layer; 14,92 a wafer; 15, solder balls; 20,20A,20B of semiconductor AIP package structure; 21, a first carrier plate; 211,212,213,214: a first redistribution layer; 2111,2121,2131,2141 a first dielectric layer; 2112,2122,2132,2142 a first conductive pillar layer; 2113,2123,2133,2143 a first patterned metal layer; 2132a,2132b: conductive posts; 2132c conductive contacts; 2133a, metal susceptor; 22,22B a second carrier plate; 221a second conductive pillar layer; 221a,221b,221c, conductive posts; 222a second redistribution layer; 2221 a second dielectric layer; 2222,2222A a second patterned metal layer; 223 an air medium layer; a semiconductor wafer; 24, a conductive element; 25, conductive bumps; 26, a third carrier plate; 271,273 photoresist layer; 274, opening; a seed layer 28; 291, 292; 91, a carrier plate; 911 an antenna layer; 93, supporting columns; 94, uploading a plate; 941 frequency selective surface structure; 95, air gap.

Detailed Description

The following description is presented to enable one of ordinary skill in the art to make and use the invention and is provided in the context of a particular application and its requirements.

Fig. 3 is a schematic cross-sectional view of a semiconductor AIP package 20 according to a first embodiment of the present invention. As shown in fig. 3, the semiconductor AIP package 20 includes a first carrier 21, a second carrier 22, and a semiconductor chip 23. The semiconductor AIP package structure 20 is an antenna package (ANTENNA IN PACKAGE, aiP), where the antenna may be a flat antenna, a microstrip antenna, a phased array antenna (phased-ARRAY ANTENNA), a dipole antenna, or a slot antenna.

In the present embodiment, the first carrier 21 has multiple redistribution layers, such as four first redistribution layers 211 to 214. The first redistribution layer 211 has a first dielectric layer 2111, a first conductive pillar layer 2112 and a first patterned metal layer 2113. The first redistribution layer 212 is disposed on the first redistribution layer 211 and has a first dielectric layer 2121, a first conductive pillar layer 2122 and a first patterned metal layer 2123, wherein the first conductive pillar layer 2122 is electrically connected to the first patterned metal layer 2113. The first redistribution layer 213 has a first dielectric layer 2131, a first conductive pillar layer 2132 and a first patterned metal layer 2133, wherein the first conductive pillar layer 2132 is electrically connected to the first patterned metal layer 2123. The first redistribution layer 214 has a first dielectric layer 2141, a first conductive pillar layer 2142, and a first patterned metal layer 2143, wherein the first conductive pillar layer 2142 is electrically connected to the first patterned conductive layer 2133. In this embodiment, four first redistribution layers are taken as an example, and in other embodiments, more first redistribution layers or fewer first redistribution layers may be designed according to the actual function.

The semiconductor chip 23 is, for example, a radio frequency chip, which can process the functions of receiving and transmitting antenna radiation or electromagnetic signals. In the present embodiment, the semiconductor wafer 23 is embedded in the first dielectric layer 2131 of the first redistribution layer 213, and one side of the semiconductor wafer 23 is disposed on or near a metal susceptor 2133a of the first patterned metal layer 2133. The connection may be a conductive connection or a non-conductive connection. The metal susceptor 2133a may be grounded (grounding) as a shielding element for electromagnetic interference protection. One side of the semiconductor wafer 23 is connected to the conductive contact 2132c of the first conductive pillar layer 2132 for signal transmission purposes of the semiconductor wafer 23. In other embodiments, the semiconductor wafer 23 may be embedded in any first redistribution layer of the first carrier 21, which is not limited herein.

The second carrier 22 is disposed on the first carrier 21 and electrically connected to the first patterned metal layer of the first carrier 21. The second carrier 22 has a second conductive pillar layer 221, a second redistribution layer 222, and an air dielectric layer 223. One end of the second conductive pillar layer 221 is electrically connected to the first patterned metal layer 2143 of the first redistribution layer 214 through a conductive element 24, and the other end is electrically connected to the second redistribution layer 222. The second redistribution layer 222 has a second dielectric layer 2221 and a second patterned metal layer 2222, wherein the second patterned metal layer 2222 is electrically connected to the second conductive pillar layer 221. The air dielectric layer 223 is located between the second redistribution layer 222, the second conductive pillar layer 221 and the first carrier 21.

It should be noted that the first redistribution layer 214 may be a first antenna line, and the second redistribution layer 222 may be a second antenna line. In addition, the first redistribution layers 211, 212, 213 of the first carrier 21 and the semiconductor die 23 may form a package carrier with embedded die. The active surface of the semiconductor wafer 23 faces away from the second carrier 22.

It should be noted that the conductive pillars of the second conductive pillar layer 221 may be disposed at intervals or disposed in a continuous wall manner. The spacing means that the conductive posts form a barrier-like pattern, and the continuous wall means that the conductive posts form a wall-like pattern. When the second conductive pillar layer 221 is in a continuous wall type, the air dielectric layer 223 is located in a partially enclosed or a fully enclosed space. In addition, the conductive pillars of the second conductive pillar layer 221 may also be referred to as support pillars (as shown in fig. 9), which have a supporting function to maintain structural stability of the semiconductor AIP package structure 20 and to secure mechanical strength.

The semiconductor AIP package 20 as an antenna package, wherein the first redistribution layers 211-214 and the second redistribution layer 222 form a transceiver structure of the antenna.

Also, portions of the first conductive pillar layer and portions of the second conductive pillar layer in the semiconductor AIP package 20 may be the role of antenna radiation pattern tuning. In this embodiment, the conductive pillars 2132a and 2132b of the first conductive pillar layer 2132 and the conductive pillars 221a and 221b of the second conductive pillar layer 221 can be used to adjust the radiation pattern of the antenna.

Next, please refer to fig. 4A-4C, fig. 5A-5D, and fig. 6A-6F, to illustrate a first method for manufacturing the semiconductor AIP package 20 according to the first embodiment of the present invention. It should be noted that, in the present embodiment, the first carrier 21 and the second carrier 22 are mainly manufactured and then combined, and for convenience of description of the present embodiment, the manufacturing of the second carrier 22 is first described here, but this is not a limitation of the manufacturing sequence. Referring to fig. 4A to 4C, the method for manufacturing the second carrier 22 includes steps S01 to S03.

As shown in fig. 4A, step S01 provides a temporary carrier 291, and forms a second redistribution layer 222 on the temporary carrier 291. The temporary carrier 291 of the present embodiment may be a large-area carrier of panel level (PANEL LEVEL), i.e. a square carrier (but not limited to square) with a larger area relative to the wafer, so as to greatly improve the area utilization and productivity. Hereinafter, please refer to fig. 5A-5D, a method for forming the second redistribution layer 222 on the temporary carrier 291 is described.

As shown in fig. 5A to 5D, the fabrication method of the present invention is completed by using the patterned circuit build-up technique of the IC package carrier, and as shown in fig. 5A, a seed layer (SEED LAYER) 28 is formed on a surface of the temporary carrier 291. As shown in fig. 5B, a photoresist layer 271 is formed on the seed layer 28, a plurality of openings are formed on the photoresist layer 271 by a photolithography process of exposure and development, a desired patterned metal layer is formed in the openings by electroplating, and the above process steps are repeated to form a two-layer stacked second patterned metal layer 2222. Next, as shown in fig. 5C, the photoresist layer 271 is removed, and then the seed layer 28 exposed outside the second patterned metal layer 2222 is removed by an etching process, and finally, as shown in fig. 5D, a second dielectric layer 2221 is formed on the temporary carrier 291 and covers the second patterned metal layer 2222. In addition, a portion of the second patterned metal layer 2222 may be exposed by polishing and planarizing a surface of the second dielectric layer 2221.

The openings may be formed by laser drilling, in addition to the photolithography process. The seed layer 28 is illustrated only in fig. 5A-5D, and is omitted from other figures because it is thin. In addition, since the fabrication methods of the redistribution layers (including the conductive pillar layer) are similar, the detailed description of the other redistribution layers will not be repeated.

The material of the dielectric layer may be photosensitive or non-photosensitive dielectric material, including, but not limited to EMC, ABF, BT, FR, PI, LCP, etc. The material of the dielectric layer at the antenna end is a material with low dielectric constant and low dielectric loss, for example, film-like film sealing material EMC, ABF, BT or glass, but is not limited thereto.

Next, referring back to fig. 4B, in step S02, a second conductive pillar layer 221 is formed on the second redistribution layer 222, so that the second conductive pillar layer 221 protrudes from the second redistribution layer 222. Further describing, the second conductive pillar layer 221 is formed on an end surface of the second patterned metal layer 2222 exposed to the second dielectric layer 2221.

It should be noted that, in other embodiments, the conductive pillars of the second conductive pillar layer 221 may be electrically connected to the end surfaces of the second patterned metal layer 2222 by a conductive adhesive means, such as a conductive paste (not shown) after being molded in advance.

Next, referring to fig. 4C, step S03 removes the temporary carrier 291. Wherein temporary carrier 291 may be removed by a lift-off process, which is not limited herein. After removing temporary carrier 291, second dielectric layer 2221 may also be made substantially coplanar with a portion of the surface of second patterned metal layer 2222 by a polishing process.

It should be noted that, depending on the openings formed on the photoresist layer 271, a second patterned metal layer 2222A (shown in fig. 4D) may be formed.

Next, referring to fig. 6A to 6F, the method for manufacturing the first carrier 21 includes steps S11 to S16.

Referring to fig. 6A, step S11 provides a temporary carrier 292, and forms a first redistribution layer 214 on the temporary carrier 292. The detailed steps of forming the first redistribution layer 214 are similar to the process of forming the second redistribution layer 222, and will not be repeated here.

Referring to fig. 6B, in step S12, a portion of the first redistribution layer 213 is formed on the first redistribution layer 214, and in detail, a first patterned metal layer 2133 is formed, which has a metal susceptor 2133a.

Referring to fig. 6C, step S13 connects the semiconductor wafer 23 to the metal susceptor 2133a. In the present embodiment, the semiconductor wafer 23 is attached to the metal susceptor 2133a by an adhesive, and in other embodiments, if the semiconductor wafer 23 needs to be electrically connected to the metal susceptor 2133a, it can be implemented by a conductive bump or a conductive adhesive.

Referring to fig. 6D, step S14 continues to form a portion of the first redistribution layer 213, so that the semiconductor wafer 23 is embedded in the first dielectric layer 2131.

Referring to fig. 6E, in step S15, a first redistribution layer 212 is formed on the first redistribution layer 213. Step S16 further forms a first redistribution layer 211 on the first redistribution layer 212.

Referring to fig. 6F, step S17 removes the temporary carrier plate 292. The temporary carrier plate 292 may be removed by a lift-off process or an etching process, which is not limited thereto. After removing the temporary carrier plate 292, the first dielectric layer 2141 may also be substantially coplanar with a portion of the surface of the first patterned metal layer 2143 by a polishing process.

Finally, step S18 combines the first carrier 21 and the second carrier 22 through the conductive element 24 to form the semiconductor AIP package 20 shown in fig. 3. The conductive element 24 may be selected from solder balls, conductive bumps or conductive adhesive, so that the second conductive pillar layer 221 of the second carrier 22 is connected to the first patterned metal layer 2143 of the first carrier 21 through the solder balls, conductive bumps or conductive adhesive. In addition, if necessary, conductive bumps 25 or solder balls may be selectively attached to the end surfaces of the first conductive pillar layers 2112 exposed to the first dielectric layer 2111. It should be noted that, since the semiconductor wafer 23 is already embedded in the first redistribution layer, the conductive bumps 25 or the solder balls do not need to be increased in volume in consideration of the thickness of the semiconductor wafer 23. Accordingly, the pitch of the conductive pillars of the first conductive pillar layer 2112 can be reduced as much as possible depending on the process, so as to meet the requirement of fine pitch input/output (I/O) contacts.

Next, please refer to fig. 7A to 7D, which illustrate a second method for manufacturing the semiconductor AIP package 20 according to the first embodiment of the present invention. First, the manufacturing method of the first carrier 21 is the same as that of fig. 6A to 6F, and the difference is that the manufacturing method of the second carrier 22 is formed later, so the manufacturing method of the first carrier 21 is not described again. In addition, in the second manufacturing method, the manufacturing sequence of the first carrier 21 and the second carrier 22 needs to be matched.

Referring to fig. 7A, in step S21, a photoresist layer 273 is formed on the first redistribution layer 214 of the first carrier 21. In step S22, a plurality of openings 274 are formed on the photoresist layer 273 by a photolithography process of exposure and development.

Referring to fig. 7B, step S23 is to electroplate a desired metal layer in the opening 274 to form the second conductive pillar layer 221.

Referring to fig. 7C, in step S24, a second redistribution layer 222 is formed on the photoresist layer 273. The manufacturing method of the second redistribution layer 222 is similar to that of the above-mentioned redistribution layer, and will not be repeated here.

Referring to fig. 7D, in step S25, the photoresist layer 273 is removed to form an air dielectric layer 223 between the second redistribution layer 222, the second conductive pillar layer 221 and the first carrier 21.

Next, referring to fig. 8 again, in the semiconductor AIP package 20A according to the second embodiment of the present invention, a third carrier 26 is further disposed on the second carrier 22 of the conventional semiconductor AIP package 20 according to the requirement of antenna performance, which can be formed by the two manufacturing methods described above, and will not be described herein.

Finally, referring to fig. 9 again, the second carrier 22B of the semiconductor AIP package 20B according to the third embodiment of the present invention is different from the aforementioned second carrier 22 in that the space between the conductive pillars 221a and 221B can be divided into multiple frequency bands by disposing the conductive pillars 221c, so as to provide a more stable supporting structure. In other words, the second conductive pillar layer 221 may frame one or more air dielectric layer 223 spaces. In this embodiment, the space is divided into left and right in a cross-sectional view, and if the space is seen from a perspective or in other embodiments, the space may be divided into more spaces by a fence type or by a continuous wall type conductive column, and the sizes of the spaces may be the same or different, which is not limited.

In summary, the semiconductor AIP package structure and the manufacturing method thereof disclosed by the invention have the following advantages:

(1) The chip in the semiconductor AIP packaging structure is arranged in the packaging in an embedded mode, so that the electric connection of the chip can directly take copper as electric connection through a semiconductor process without additional conductive bumps or solder balls, the process can be simplified, the packaging can meet the requirement of fine-pitch I/O joints, and the packaging thickness can be further reduced.

(2) The metal crystal seat is integrated in the redistribution layer, and can be formed by a semiconductor build-up circuit process, so that the process can be simplified, and the metal crystal seat can also prevent the semiconductor chip from being interfered by electromagnetic signals, so that the antenna efficiency can be increased.

(3) The air dielectric layer is used as a dielectric material of antenna radiation in the semiconductor AIP packaging structure, and the dielectric constant of air is close to 1, so that the bandwidth of the antenna can be effectively increased, or the packaging volume can be reduced. In other words, the antenna performance can be better in the same volume state, and the package thickness can be thinner in the same antenna performance state.

(4) The chip is electrically connected by patterning the metal layer (copper material), and compared with the solder balls, the thermal resistance of the chip can be greatly reduced.

(5) The conductive pillars around the chip can be used for adjusting the radiation pattern of the antenna, so as to increase the antenna performance.

(6) The conductive columns of the second conductive column layer of the second carrier plate are used as the reinforcing ribs (stiffener), and the process can be simplified without additional manufacturing.

The foregoing is merely a preferred embodiment of the present invention and is not intended to limit the scope of the present invention. It is intended that all such equivalent modifications and variations as would be within the spirit of the present invention be included within the scope of the present invention.

Claims (10)

1. A semiconductor AIP package structure, comprising:

The first carrier plate is provided with at least two first redistribution layers which are arranged in a laminated way, and each first redistribution layer is provided with a first dielectric layer, a first patterned metal layer and/or a first conductive column layer;

a chip embedded in the first carrier and coupled to the first redistribution layers; and

A second carrier plate opposite to the first carrier plate and having a second redistribution layer, a second conductive pillar layer and an air medium layer, wherein the second conductive pillar layer is protruded from the second redistribution layer,

The second carrier plate is connected to the first carrier plate through the second conductive column layer, the air medium layer is located between the second redistribution layer, the second conductive column layer and the first carrier plate, and the acting surface of the wafer faces to the direction away from the second carrier plate.

2. The semiconductor AIP package according to claim 1, wherein the first redistribution layers of the first carrier have a metal susceptor in contact with the wafer and between the wafer and the second carrier.

3. The semiconductor AIP package according to claim 1, wherein a portion of the first redistribution layer, a portion of the second redistribution layer, and a portion of the second conductive pillar layer form a transmitting antenna, and another portion of the first redistribution layer, another portion of the second redistribution layer, and another portion of the second conductive pillar layer form a receiving antenna.

4. The semiconductor AIP package according to claim 3, wherein a portion of the first conductive pillar layer and a portion of the second conductive pillar layer are used for antenna radiation pattern tuning.

5. The semiconductor AIP package according to any one of claims 1-4, wherein the second conductive pillar layer is fence-type or continuous wall-type and the second conductive pillar layer is configured to frame one or more air dielectric layer spaces.

6. A method of manufacturing a semiconductor AIP package, comprising:

Forming a first carrier plate, which comprises sequentially forming at least two first redistribution layers, and embedding a wafer in the at least two first redistribution layers in the process of forming the at least two first redistribution layers, wherein the active surface of the wafer faces away from the second carrier plate, and the active surface of the wafer is coupled with one of the first redistribution layers;

Forming a second carrier plate, which includes forming a second redistribution layer and forming a second conductive pillar layer protruding from the second redistribution layer; and

And combining the first carrier plate and the second carrier plate, wherein the second conductive column layer is connected to the second carrier plate, and an air medium layer is formed among the second redistribution layer, the second conductive column layer and the first carrier plate.

7. The method of claim 6, wherein the second conductive pillar layer of the second carrier is connected to the first redistribution layer of the first carrier through solder balls, conductive bumps or conductive adhesive.

8. The method of claim 6, wherein forming the at least two first redistribution layers of the first carrier comprises:

forming a second seed layer;

Forming a photoresist layer with at least one second through hole on the second seed crystal layer;

electroplating to form a first patterned metal layer and/or a first conductive column layer in the second through hole;

A wafer is connected to the first patterned metal layer, and the active surface of the wafer is coupled with the other first redistribution layer;

removing the photoresist layer and the second seed layer; and

A first dielectric layer is formed to encapsulate the first patterned metal layer and/or the first conductive pillar layer and the wafer.

9. A method of manufacturing a semiconductor AIP package, comprising:

Forming a first carrier plate, which comprises sequentially forming at least two first redistribution layers, and embedding a wafer in the at least two first redistribution layers in the process of forming the at least two first redistribution layers, wherein the active surface of the wafer faces away from the second carrier plate, and the active surface of the wafer is coupled with one of the first redistribution layers; and

Forming a second carrier on the first carrier, comprising:

Forming a first seed crystal layer on the first carrier plate;

forming a photoresist layer with at least one first through hole on the first seed crystal layer;

Electroplating to form a second conductive column layer in the first through hole;

Forming a second redistribution layer connected to the second conductive pillar layer; and

And removing the photoresist layer to form an air medium layer among the second redistribution layer, the second conductive column layer and the first carrier.

10. The method of claim 9, wherein forming the at least two first redistribution layers of the first carrier comprises:

forming a second seed layer;

Forming a photoresist layer with at least one second through hole on the second seed crystal layer;

electroplating to form a first patterned metal layer and/or a first conductive pillar layer in the second through hole;

A wafer is connected to the first patterned metal layer, and the active surface of the wafer is coupled with the other first redistribution layer;

removing the photoresist layer and the second seed layer; and

A first dielectric layer is formed to encapsulate the first patterned metal layer and/or the first conductive pillar layer and the wafer.