CN118173498A

CN118173498A - Method and system for forming a via in a semiconductor structure

Info

Publication number: CN118173498A
Application number: CN202211589427.0A
Authority: CN
Inventors: 请求不公布姓名
Original assignee: Zhangjiang National Laboratory
Current assignee: Zhangjiang National Laboratory
Priority date: 2022-12-09
Filing date: 2022-12-09
Publication date: 2024-06-11

Abstract

The present invention relates to a method and system for forming a via in a semiconductor structure. The method comprises the following steps: providing a semiconductor structure; forming a first material layer on the semiconductor structure by using a first patterning process, wherein the first material layer is provided with a first pattern; forming a second material layer on the semiconductor structure using a second patterning process, the second material layer having a second pattern, wherein the first material layer and the second material layer overlap to define a plurality of independent exposed regions of the semiconductor structure; and etching the exposed semiconductor structure by using the first material layer and the second material layer as etching-resistant masks so as to form a plurality of through holes in the semiconductor structure.

Description

Method and system for forming a via in a semiconductor structure

Technical Field

The invention relates to the technical field of semiconductor microstructure processing, in particular to a method and a system for forming a through hole in a semiconductor structure.

Background

With the rapid development of semiconductor manufacturing technology, in order to achieve faster operation speed, larger data storage amount and more functions, semiconductor devices are developed in the direction of higher element density and higher integration. How to form smaller sized vias on semiconductor structures is a problem to be solved by those skilled in the art.

Disclosure of Invention

The invention aims to provide a method for forming a through hole with smaller size.

In order to solve the above-mentioned problems, the present invention provides a method for forming a via hole in a semiconductor structure, characterized in that the method comprises the steps of: providing a semiconductor structure; forming a first material layer on the semiconductor structure by using a first patterning process based on a bilayer photoresist, wherein the first material layer has a first pattern; forming a second material layer on the semiconductor structure using a bilayer photoresist-based second patterning process, the second material layer having a second pattern, wherein the first material layer and the second material layer overlap to define a plurality of independent exposed regions of the semiconductor structure; and etching the exposed semiconductor structure by using the first material layer and the second material layer as etching-resistant masks so as to form a plurality of through holes in the semiconductor structure.

The present invention also provides a system for forming a via in a semiconductor structure, comprising a patterning portion and an etching portion, the system being for performing the steps of: forming a first material layer on the semiconductor structure using a double-layer photoresist-based first patterning process using the patterning part, the first material layer having a first pattern; forming a second material layer on the semiconductor structure using a bilayer photoresist-based second patterning process using the patterning, the second material layer having a second pattern, wherein the first material layer and the second material layer overlap to define a plurality of independent exposed regions of the semiconductor structure; and etching the exposed semiconductor structure by using the etching part and taking the first material layer and the second material layer as etching-resistant masks so as to form a plurality of through holes in the semiconductor structure.

Preferably, at least one of the first patterning process and the second patterning process includes the steps of: forming a negative photoresist layer on the semiconductor structure, and forming a positive photoresist layer on the negative photoresist layer by using a positive photoresist; patterning the negative adhesive layer and the positive adhesive layer so as to form a positive pattern area and a negative pattern area on the positive adhesive layer and the negative adhesive layer respectively, wherein the positive pattern area is larger than the negative pattern area; developing the positive photoresist layer by using positive photoresist developing solution to remove positive photoresist in the positive graph area; developing the negative photoresist layer with a negative photoresist developer to remove negative photoresist located adjacent to the negative pattern region and thereby provide an exposed region associated with the positive pattern region and the negative pattern region in size to expose the semiconductor structure; and depositing a layer of material over the semiconductor structure.

Preferably, at least one of the first patterning process and the second patterning process includes the steps of: forming a negative photoresist layer on the semiconductor structure, forming an interlayer on the negative photoresist layer, and forming a positive photoresist layer on the interlayer by using a positive photoresist; patterning the negative adhesive layer and the positive adhesive layer so as to form a positive pattern area and a negative pattern area on the positive adhesive layer and the negative adhesive layer respectively, wherein the positive pattern area is larger than the negative pattern area; developing the positive photoresist layer by using positive photoresist developing solution to remove positive photoresist in the positive graph area; developing the interlayer by using interlayer developing solution, or etching the interlayer by taking the pattern of the developed positive photoresist layer as an etching-resistant mask so as to enable the pattern of the interlayer to be consistent with the pattern of the developed positive photoresist layer; and developing the negative photoresist layer with a negative photoresist developer to remove negative photoresist located adjacent the negative pattern region, thereby providing an exposed region associated with the positive pattern region, the negative pattern region, and the size of the negative pattern region to expose the semiconductor structure; and depositing a layer of material over the semiconductor structure.

Preferably, at least one of the first patterning process and the second patterning process includes the steps of: forming a positive photoresist layer on the semiconductor structure, forming an interlayer on the positive photoresist layer, and forming a negative photoresist layer on the interlayer by using a negative photoresist; patterning the negative adhesive layer and the positive adhesive layer so as to form a positive pattern area and a negative pattern area on the positive adhesive layer and the negative adhesive layer respectively, wherein the positive pattern area is larger than the negative pattern area; developing the negative photoresist layer by using a negative photoresist developing solution to remove negative photoresist outside the negative pattern area; developing the interlayer by using interlayer developing solution, or etching the interlayer by taking the pattern of the developed negative adhesive layer as an etching-resistant mask so as to enable the pattern of the interlayer to be consistent with the pattern of the developed negative adhesive layer; and developing the positive photoresist layer with a positive photoresist developer to remove positive photoresist from edge portions of the positive pattern region, thereby providing an exposed region associated with the dimensions of the positive pattern region and the negative pattern region to expose the semiconductor structure; and depositing a layer of material over the semiconductor structure.

Preferably, at least one of the first patterning process and the second patterning process includes the steps of: forming a positive photoresist layer on the semiconductor structure, and forming a negative photoresist layer on the positive photoresist layer by using a negative photoresist; patterning the negative adhesive layer and the positive adhesive layer so as to form a positive pattern area and a negative pattern area on the positive adhesive layer and the negative adhesive layer respectively, wherein the positive pattern area is larger than the negative pattern area; developing the negative photoresist layer by using a negative photoresist developing solution to remove negative photoresist in the negative pattern area; developing the positive photoresist layer with a positive photoresist developer to remove positive photoresist at an edge portion of the positive pattern region, thereby providing an exposed region associated with the dimensions of the positive pattern region and the negative pattern region to expose the semiconductor structure; and depositing a layer of material over the semiconductor structure.

Preferably, in the patterning step, the positive photoresist layer and the negative photoresist layer are exposed by using a photolithography mask carrying a template pattern or through focusing direct writing under an exposure source, so that a positive pattern area and a negative pattern area are respectively formed on the positive photoresist layer and the negative photoresist layer.

Preferably, the template pattern for the first patterning process includes a plurality of lines extending along a first direction, and the template pattern for the second patterning process includes a plurality of lines extending along a second direction.

Preferably, in the patterning step, the positive photoresist layer and the negative photoresist layer are exposed by using a projection exposure mode under an exposure source through a photoetching mask plate carrying the template pattern; or exposing the positive adhesive layer and the negative adhesive layer by using a shielding exposure mode under an exposure source through a photoetching mask plate carrying the template pattern; or using a reflection type exposure mode to expose the positive adhesive layer and the negative adhesive layer by reflecting on the photoetching mask plate carrying the template pattern under an exposure source.

Preferably, the focusing direct writing includes ultraviolet direct writing, deep ultraviolet direct writing, extreme ultraviolet direct writing, ion beam direct writing, electron beam direct writing or X-ray direct writing.

Preferably, depositing the layer of material includes using electrochemical deposition, electroplating, CVD deposition, laser sputtering, magnetron sputtering, thermal evaporation, electron beam evaporation, or atomic deposition.

The invention also provides a system control method for controlling the system to execute each step.

The present invention also provides a computer device comprising: the system comprises a memory, a processor and a computer program stored in the memory and capable of running on the processor, and is characterized in that the processor executes the computer program to realize the system control method.

The present invention also provides a computer readable medium having stored thereon a computer program which, when executed by a processor, implements the system control method described above.

Drawings

For a clearer description of embodiments of the invention or of solutions in the prior art, the drawings that are necessary for the description of the embodiments or of the prior art will be briefly described, it being apparent that the drawings in the description below are some embodiments of the invention and that, without the inventive effort, further drawings can be obtained by a person skilled in the art from these drawings, in which:

Fig. 1 is a flowchart of a method 100 for forming a via in a semiconductor structure according to an exemplary embodiment of the invention.

Fig. 2A-2D are schematic cross-sectional and top views of various stages in the formation of a semiconductor structure using the method of fig. 1 in accordance with an exemplary embodiment of the present invention.

Fig. 3A to 3G are schematic views respectively showing respective stages of the patterning process of embodiment 1 of the present invention for forming a semiconductor structure.

Fig. 4 is a schematic view showing a contour pattern obtained based on a mask pattern by a patterning process according to an embodiment of the present invention.

Fig. 5 is a schematic diagram illustrating the formation of multiple independent exposed regions of a semiconductor structure using a two-shot patterning process.

Fig. 6A to 6I are schematic views showing respective stages of patterning to form a semiconductor structure according to embodiment 2 of the present invention.

Fig. 7A-7G are schematic diagrams showing various stages of the patterning process of embodiment 3 of the present invention to form a semiconductor structure, respectively.

Fig. 8A and 8B show scanning electron micrographs of semiconductor structures formed using the methods of the present invention.

Fig. 9 shows an example of a selective area reticle.

Fig. 10 is a block diagram schematically illustrating a system for forming vias in a semiconductor structure of the present invention.

Description of the reference numerals

301A, 301B, 301C substrates

302A, 302B, 302C negative photoresist (negative photoresist layer)

303A, 303B, 303C positive photoresist (positive glue layer)

304A, 304B, 304C negative photoresist (negative pattern area)

305A, 305B, 305C exposure pattern (positive pattern area) on the negative photoresist

306A, 306B deposit

307A, 307B material layers

308A, 308B, 308C photoetching mask plate

310B, 310C barrier layer

1000 System

1001 Patterning portion

1002 Etching part

To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. The figures are not drawn to scale and may be simplified for clarity. Elements and features of one embodiment may be advantageously incorporated into other embodiments without further description.

Detailed Description

In order that the above objects, features and advantages of the invention will be readily understood, a more particular description of the invention will be rendered by reference to the appended drawings.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways other than those described herein, and persons skilled in the art will readily appreciate that the present invention is not limited to the specific embodiments disclosed below.

In the following detailed description of the embodiments of the present invention, reference is made to the accompanying drawings, which form a part hereof, and in which are shown by way of illustration only, and in which is shown by way of illustration only, and in which the scope of the invention is not limited for ease of illustration. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.

The reader is directed to all documents and documents filed concurrently with this specification and open to public inspection with this specification, and the contents of all such documents and documents are incorporated herein by reference. All the features disclosed in this specification (including any accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic set of equivalent or similar features.

The terms "above," "under," "between," and "on" as used herein refer to the relative position of this layer with respect to other layers. Likewise, for example, one layer deposited or placed above or below another layer may be in direct contact with the other layer or may have one or more intervening layers. Furthermore, a layer deposited or placed between layers may be in direct contact with the layers or may have one or more intermediate layers. In contrast, a first layer "on" a second layer is in contact with the second layer.

A method for forming a via hole in a semiconductor structure provided according to an embodiment of the present invention is described in detail below with reference to the accompanying drawings.

See fig. 1-2C. Fig. 1 is a flowchart of a method 100 for forming a via in a semiconductor structure according to an exemplary embodiment of the invention. Fig. 2A-2D are schematic cross-sectional and top views of various stages in the formation of a semiconductor structure using the method of fig. 1 in accordance with an exemplary embodiment of the present invention.

As shown in fig. 1, the method 100 may include the following steps S110 to S140.

In step S110, a semiconductor structure is provided.

In some embodiments of the present invention, the semiconductor structure 200 may include at least a substrate. The substrate is a semiconductor substrate, and may be, for example, a Si substrate, a Ge substrate, a SiGe substrate, SOI (silicon on insulator ), GOI (germanium on insulator, germanium On Insulator), or the like. In other embodiments, the semiconductor substrate may also be a substrate including other elemental semiconductors or compound semiconductors, such as GaAs, inP, siC, or the like, or may be a stacked structure, such as Si/SiGe, or the like, or other epitaxial structures, such as SGOI (silicon germanium on insulator), or the like. In some embodiments, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafer, or the like. The semiconductor structure 200 shown in fig. 2A may have undergone some of the necessary processing, such as having formed a common active region, having undergone the necessary cleaning, and so forth.

In some embodiments of the present invention, the semiconductor structure 200 may further include a hard mask layer over the substrate, and the material of the hard mask layer may be selected from a variety of materials, so long as the hard mask layer can be used as an etch stop layer when etching the substrate. In other words, the substrate and the hard mask layer may have different etch selectivities such that the etching process performed on the substrate does not damage (i.e., does not etch through) the hard mask layer. For example, the material of the hard mask layer may include a metal, a metal oxide, a metal nitride, or a non-metal nitride, such as hafnium oxide or aluminum oxide, or the like. The hard mask layer may be formed by deposition such as physical vapor deposition, chemical vapor deposition, and atomic layer deposition. The thickness of the hard mask layer can be adjusted as desired.

In some embodiments of the present invention, the semiconductor structure 200 may further include an anti-reflective coating over the substrate. For example, an anti-reflective coating may be located between the substrate and the hard mask layer. The anti-reflective coating may comprise an oxide, such as silicon oxide or silicon oxycarbide.

In step S120, a first material layer is formed on the semiconductor structure using a first patterning process based on a bilayer photoresist, the first material layer having a first pattern. The right side of fig. 2B shows a top view of the semiconductor structure and the left side shows a cross-sectional view of the semiconductor structure taken along the dashed line in the top view. As shown, a first material layer 210 is formed on the semiconductor structure 200, having a pattern of a plurality of lines extending along a first direction (e.g., x-direction) with a certain interval between the plurality of lines.

The material of the first material layer 210 may be selected from a variety of materials, so long as the first material layer 210 is capable of functioning as an etch stop layer when etching the semiconductor structure 200. In other words, the region to be etched of the semiconductor structure and the first material layer 210 may have different etching selectivities such that the etching process performed on the region to be etched of the semiconductor structure does not damage (i.e., does not etch through) the first material layer 210. For example, the material of the first material layer 210 may include an oxide, a nitride, a metal, or a composite thereof. The manner in which the first material layer 210 is formed may include deposition such as physical vapor deposition, chemical vapor deposition, and atomic layer deposition. The thickness of the first material layer 210 may be adjusted as desired.

In step S130, a second material layer is formed on the semiconductor structure using a second patterning process based on a bilayer photoresist. The right side of fig. 2C shows a top view of the semiconductor structure and the left side shows a cross-sectional view of the semiconductor structure taken along the dashed lines A-A 'and B-B', respectively, in the top view. As shown, a second material layer 220 is formed in the semiconductor structure 200, having a pattern of a plurality of lines extending along a second direction (e.g., y-direction), the plurality of lines having a certain interval therebetween.

The material of the second material layer 220 may be selected from a variety of materials, so long as the second material layer 220 is capable of functioning as an etch stop layer when etching the semiconductor structure 200. In other words, the region of the semiconductor structure to be etched and the second material layer 220 may have different etch selectivities such that the etching process performed on the region of the semiconductor structure to be etched does not damage (i.e., does not etch through) the second material layer 220. For example, the material of the second material layer 220 may include an oxide, a nitride, a metal, or a composite thereof. The manner in which the second material layer 220 is formed may include deposition such as physical vapor deposition, chemical vapor deposition, and atomic layer deposition. The thickness of the second material layer 220 may be adjusted as desired. The first material layer 210 and the second material layer 220 may have the same material, or may have different materials.

The first material layer 210 and the second material layer 220 overlap to define a plurality of separate exposed regions 201 (only one is labeled in fig. 2C for simplicity) of the semiconductor structure 200. The exposed region 201 may be a region of the semiconductor structure 200 to be etched for forming a via. In some embodiments of the invention, the angle between the first direction and the second direction is not 0 °, for example may be between 0 ° and 90 °.

In step S140, the exposed semiconductor structure is etched using the first material layer and the second material layer as an etch-resistant mask to form a plurality of vias in the semiconductor structure. Optionally, the first material layer and the second material layer may also be removed after the formation of the via holes. Fig. 2D shows a top view of semiconductor structure 200 on the right and a cross-sectional view of semiconductor structure 200 taken along a dashed line in the top view on the left. As shown, a plurality of vias 202 are formed in the semiconductor structure 200, and the first material layer 210 and the second material layer 220 are removed.

The patterning process involved in steps S120 and S130 may include a bilayer photoresist-based photolithography method and a deposition technique, and various embodiments of the patterning process will be described hereinafter.

Embodiment 1

< Lithography method based on bilayer Photoresist in combination with deposition technique >

Embodiment 1 of the present invention provides a patterning process, which may include the steps of:

(1) Forming a negative photoresist layer on the semiconductor structure, and forming a positive photoresist layer on the negative photoresist layer by using a positive photoresist;

(2) Patterning the negative adhesive layer and the positive adhesive layer so as to form a positive pattern area and a negative pattern area on the positive adhesive layer and the negative adhesive layer respectively, wherein the positive pattern area is larger than the negative pattern area;

(3) Developing the positive photoresist layer by using positive photoresist developing solution to remove positive photoresist in the positive graph area; and

(4) Developing the negative photoresist layer with a negative photoresist developer to remove negative photoresist located adjacent to the negative pattern region and thereby provide an exposed region associated with the positive pattern region and the negative pattern region in size to expose the semiconductor structure; and

(5) A layer of material is deposited over the semiconductor structure.

Next, embodiment 1 of the patterning process will be described in detail with reference to fig. 3A, 3B, 3C, 3D, 3E, 3F, and 3G. In the drawings, the same or corresponding portions are denoted by the same reference numerals.

Fig. 3A is a schematic diagram showing step 1A of applying a negative photoresist on a substrate in a patterning process according to embodiment 1 of the present invention. Fig. 3B is a schematic diagram showing step 2A of coating positive photoresist on negative photoresist in the patterning process of embodiment 1 of the present invention.

First, as shown in fig. 3A, in step 1A, a layer of negative photoresist 302A (i.e., a negative photoresist layer) is spin-coated on the hard mask layer 301A of the semiconductor structure 300 (note that the hard mask layer 301A is optional, or there may be no hard mask layer 301A or other coating on top of the semiconductor structure 300), and baked; then, as shown in fig. 3B, in step 2A, a positive photoresist 303A (i.e., a positive photoresist layer) is spin-coated on the negative photoresist 302A and baked (corresponding to forming a negative photoresist layer on the semiconductor structure with the negative photoresist and forming a positive photoresist layer on the negative photoresist layer with the positive photoresist).

The negative photoresist includes negative ultraviolet photoresist, negative deep ultraviolet photoresist, negative developing deep ultraviolet photoresist, negative extreme ultraviolet photoresist, negative electron beam photoresist, negative ion beam photoresist or negative X-ray photoresist, including but not limited to NANO ^TM SU-8Series, HSQ, AZ Series photoresist (e.g., AZ N4000, AZ N6000), HNR Series photoresist, SC Series photoresist, ma-N Series photoresist (e.g., ma-N400, ma-N1400),2000Series，/>5500 Photorosis, NR7-PY Series, NR9-PY Series, JSR WPR SERIES, NR Series NR9 Series, and the like.

Positive photoresists include positive uv photoresists, positive deep uv photoresists, positive extreme uv photoresists, positive electron beam photoresists, positive ion beam photoresists, or positive X-ray photoresists, including but not limited to MICROPOSIT S series of photoresists, BCI-3511 photoresists, AZ series of photoresists (e.g., AZ111, AZ 1500,AZ 3300,AZ 4999,AZ 6600,AZ 8112,AZ 3000,AZ 1075,AZ 700,AZ 900), HNR 500 series of photoresists, oiR series of photoresists, TDMR-AR80 HP 6cp, pr1 series of photoresists, ma-P1200 series of photoresists, SPR series of photoresists (e.g., SPR 220,SPR 660,SPR3000, etc.), PMMA series of photoresists, and the like.

In addition, positive and negative photoresists of different models need to confirm the matching degree in advance, and examples of two positive and negative photoresist paired groups are given below. A first group: the positive photoresist model is HTI 751, and the negative photoresist model is SUN 9i; second group: the positive photoresist model is AZ 1500, and the negative photoresist model is AZ nlof 2020.

As an example, the process of spin coating a negative photoresist (for example SUN 9i, az nlof 2020) is: spin-coating at 800-1000 rpm for 5-10 seconds (this step may be omitted), spin-coating at 4000-8000 rpm for 30-40 seconds, and baking at 95-100deg.C for 60-90 seconds.

As an example, a process of spin-coating a positive photoresist (HTI 751, az 1500 is exemplified) is: spin-coating at 800-1000 rpm for 5-10 seconds (this step may be omitted), spin-coating at 2000-5000 rpm for 30-40 seconds, and baking at 90-100deg.C for 30-50 seconds.

In addition, the different rotation speeds determine the film thickness of the photoresist; the temperature and time of the pre-baking, and the exposure amount, exposure time, development time, and the like after that are adjusted according to different film thicknesses.

Fig. 3C is a schematic diagram showing step 3A of exposing two layers of photoresist in the patterning process of embodiment 1 of the present invention.

After step 2A, as shown in fig. 3C, in step 3A, the two layers of photoresist 302A, 303A are exposed to an exposure source using a reticle carrying a template pattern or by focus-direct writing (an example of a reticle 308A is shown in fig. 3C). After exposure, exposure patterns 304A, 305A (i.e., negative pattern areas, positive pattern areas) having different sizes are formed on the negative photoresist 302A and the positive photoresist 303A, respectively, and then baking (corresponding to patterning the negative photoresist layer and the positive photoresist layer, thereby forming positive pattern areas and negative pattern areas on the positive photoresist layer and the negative photoresist layer, respectively, wherein the positive pattern areas are larger than the negative pattern areas).

The exposure source comprises an ultraviolet light source, a deep ultraviolet light source, an extreme ultraviolet light source, an ion beam, an electron beam or X-rays. As an example, the wavelength of the exposure source may be 1-500nm, and the temperature of post-exposure baking may be 30-300 ℃. Further, the wavelength of the exposure source may be 350-400nm, and the temperature of post-exposure baking may be 95-105 ℃.

Focusing direct writing includes ultraviolet direct writing, deep ultraviolet direct writing, extreme ultraviolet direct writing, ion beam direct writing, electron beam direct writing or X-ray direct writing. As an example, the feature line width or feature size of the template pattern may be 2nm-1000 μm. Further, the feature line width or feature size of the template pattern may be 2nm to 1 μm.

As one example, a pre-baked semiconductor structure is secured under a reticle, then placed under an ultraviolet light source, and the ultraviolet light source is turned on for photolithography. The exposure time is adjusted according to the positive and negative photoresist pairing set used. Taking the above mentioned pairing as an example, an exposure flux of 100-200mJ/cm ² at a wavelength of 350-400nm is applicable to the resist pairing group of HTI 751 and SUN 9i, or AZ1500 and AZ nlof 2020. The use of UV wavelengths and exposure flux should take into account the absorption of UV light by positive photoresists of varying thickness (e.g. HTI 751, az 1500) to ensure that sufficient exposure flux is obtained in the underlying negative photoresists (e.g. SUN 9i, az nlof 2020). Because the HTI 751 and SUN 9i, az1500 and AZ nlof2020 photoresist pairs have different exposure flux responses at specific wavelengths, different sized patterns (e.g. 304A, 305A in fig. 3C) based on reticle patterns can be obtained.

As an example, the exposure may be in the form of a single exposure. As an example, the exposure may also be performed in a multiple exposure manner. I.e. a multiple exposure superposition which can also be broken down into multiple shorter times or smaller doses.

Fig. 3D is a schematic diagram showing step 4A of developing the resist in the patterning process of embodiment 1 of the present invention. Fig. 3E is a schematic diagram showing step 5A of developing the negative photoresist in the patterning process of embodiment 1 of the present invention.

After step 3A, as shown in fig. 3D, in step 4A, developing the positive photoresist with a positive photoresist developer (corresponding to developing the positive photoresist layer with a positive photoresist developer to remove the positive photoresist in the positive pattern region); then, as shown in fig. 3E, in step 5A, the negative photoresist is controllably developed with a negative photoresist developer, only an edge portion of the exposure pattern 304A on the negative photoresist is washed away, and the hard mask layer 301A is exposed, thereby converting the template pattern into a contour pattern (corresponding to developing the negative photoresist layer with the negative photoresist developer to remove the negative photoresist located near the negative pattern region, thereby providing an exposed region related to the size of the positive pattern region, the negative pattern region, to expose the semiconductor structure).

The positive photoresist developer is a developer corresponding to the positive photoresist, and the negative photoresist developer is a developer corresponding to the negative photoresist. For example, the positive photoresist developer solution may be TMAH 2.38%, MF-26A, the negative photoresist developer solution may be TMAH 2.38%, SU-8developer, etc.

As one example, the exposed semiconductor structure is placed in a corresponding positive photoresist developer, such as TMAH developer, such that the exposed positive photoresist on the semiconductor structure is rinsed away, creating a pattern opposite the exposed pattern, after which the semiconductor structure is rinsed, developed, and dried to remove residual liquid. Then, the exposed semiconductor structure is placed in a corresponding negative photoresist developer, such as TMAH developer, and the non-exposed negative photoresist on the semiconductor structure is partially (but not completely) washed away by adjusting the development time, and then the semiconductor structure is cleaned, the developer is removed, and the residual liquid is removed, so that the contour pattern of the exposed pattern is generated.

In addition, if the positive and negative photoresist developers are the same, for example, TMAH, the two steps of development, step 4A and step 5A, may be combined without an additional cleaning and drying step therebetween. In addition, the positive and negative photoresist and the corresponding developing solutions should be subjected to a crossover experiment to formulate the most suitable developing process.

Fig. 3F is a schematic diagram showing step 6A of deposition by a deposition technique in the photolithography method of embodiment 1 of the present invention. Fig. 3G is a schematic diagram showing step 7A of removing photoresist after deposition in the photolithography method of embodiment 1 of the present invention.

After step 5A, as shown in fig. 3F, in step 6A, a deposition layer 306A may be formed by a material deposition technique. Then, as shown in fig. 3G, in step 7A, the photoresist is removed, leaving a contour pattern.

Material deposition techniques include electrochemical deposition, electroplating, CVD deposition, laser sputtering, magnetron sputtering, thermal evaporation, electron beam evaporation, or atomic deposition.

In addition, fig. 4 is a schematic view showing a contour pattern obtained based on a mask pattern by a patterning process according to an embodiment of the present invention.

As shown in fig. 4, by adopting embodiment 1 of the present invention, a contour pattern based on a mask pattern can be obtained, the line width of which is smaller than that of the mask pattern, thereby line density multiplication can be achieved, and downsizing for the original mask pattern can be achieved. In addition, in fig. 4, a mask pattern having a plurality of lines is shown, but the present invention is not limited thereto.

In some embodiments of the present invention, the template pattern for the first patterning process may include a plurality of lines as shown in fig. 4, and the template pattern may be positioned such that the plurality of lines extend along a first direction (e.g., the x1 or x2 direction shown in fig. 5). Thus, the first patterning process may form a line pattern of the first material layer 210 on the semiconductor structure 200, where the lines of the first material layer 210 have a certain interval therebetween. In other words, the first patterning process does not cause the first material layer 210 to cover the entire semiconductor structure 200, but exposes the semiconductor structure 200 at the space.

In some embodiments of the present invention, the template pattern for the second patterning process may include a plurality of lines as shown in fig. 4, and the template pattern may be positioned such that the plurality of lines extend along the second direction (e.g., the y1 or y2 direction shown in fig. 5). In this manner, the second patterning process may form a line pattern of the second material layer 220 on the semiconductor structure 200, where the lines of the second material layer 220 have a certain interval therebetween. In other words, the second patterning process does not cause the second material layer 220 to cover the entire semiconductor structure 200, but instead exposes the underlying layers at the spaces. As such, the linear pattern of the first material layer 210 and the linear pattern of the second material layer 220 overlap to define a plurality of independent exposed regions 201 of the semiconductor structure 200. Thereafter, the exposed semiconductor structure (e.g., an optional hard mask layer on top of the semiconductor structure) may be etched using the first material layer 210 and the second material layer 220 as etch-resistant masks to transfer the pattern of the exposed regions 201 to the hard mask layer. In the example of fig. 5, the angle between x1 and y1 is 90 ° and the angle between x2 and y2 is 60 °.

Note that although the plurality of lines in the template pattern shown in fig. 4 or 5 exhibit a straight morphology, the pattern transferred to the photoresist or even the semiconductor structure 200 (or the optional hard mask layer on top thereof) does not necessarily exhibit a straight morphology entirely due to factors such as diffraction of light during exposure. In other words, the edges of the first and second material layers formed do not necessarily take on a straight form, and thus the areas not covered by the first and second material layers are not necessarily square or rectangular, but may be circular, oval or irregular. Steps in the patterning process may be simulated using EDA software so that the template pattern and associated process parameters may be determined from the desired pattern to be formed.

Hereinafter, specific embodiments of the bilayer photoresist-based photolithography method of the present invention will be described in detail.

Example 1a

As an example, the present embodiment 1a specifically includes the following steps:

(1) Coating negative photoresist

The initial semiconductor structure is placed in a spin coater system and held. The negative photoresist SUN 9i or AZ nlof 2020 was spin coated with photoresist at 1000rpm×5s+4000rpm×40s, and then baked at 100-100 ℃ for 60 seconds.

(2) Coating positive photoresist

And placing the cooled semiconductor structure in a spin coating system and fixing. The positive photoresist HTI751 or AZ 1500 was spin-coated at 800rpm×5s+2500rpm×30s, and then baked at 95-100 ℃ for 40 seconds.

(3) Exposure to light

And tightly fixing the semiconductor structure subjected to the steps under the mask, vacuumizing and placing the semiconductor structure under an ultraviolet light source, and turning on the light source to carry out photoetching operation. The exposure time is adjusted according to the type of the photoresist pairing group and the thickness of the photoresist layer. After the exposure is finished, the mask is taken down, the exposed semiconductor structure is moved to a heating table, and baked for 45 seconds at 100 ℃. The exposure flux is, for example, 100mJ/cm ², and can be changed according to the requirements.

(4) Positive photoresist development

The exposed semiconductor structure is placed in a corresponding positive photoresist developer, such as TMAH developer, and the exposed positive photoresist on the semiconductor structure is rinsed away to create a pattern opposite to the exposed pattern, after which the semiconductor structure is rinsed, developed, and dried to remove residual liquid.

(5) Negative photoresist development

The exposed semiconductor structure is placed in a corresponding negative photoresist developer, such as TMAH developer, and the development time is regulated to wash away part (not all) of the unexposed negative photoresist on the semiconductor structure, and then the semiconductor structure is cleaned, the developer is removed and dried to remove residual liquid, thereby generating a contour pattern based on the mask pattern.

Note that if the positive and negative photoresist developers are the same, e.g., both TMAH, the two development steps (4) (5) may be combined without an additional rinse and dry step in between.

(6) Material deposition

Placing the developed semiconductor structure in an evaporation coating apparatus, pumping the molecular pump to 10 ^-6 Pa, usingAndA2 nm chromium film and a 50 nm gold film were thermally evaporated, respectively. A2 nm chromium film was used as an adhesion layer for the gold film.

(7) Photoresist removal

And after the cavity is cooled, releasing the vacuum, and taking out the semiconductor structure after coating. The semiconductor structure was immersed in acetone and ultrasonically cleaned until the photoresist was completely removed, leaving a contoured pattern of gold.

Example 1b

Regarding exposure, in embodiment 1a, an exposure method in which the semiconductor structure is tightly fixed under the mask plate, vacuumized and placed under the ultraviolet light source is used, but the present invention is not limited thereto. For example, positive and negative bilayer photoresist lithography of the present invention may also use projection exposure. In the following, in the present embodiment 1b, an exposure step of the positive and negative double layer resist lithography technique of the present invention will be described by taking a projection type ultraviolet lithography system having an ultraviolet wavelength of less than 400nm as an example (since the remaining steps are similar to embodiment 1a, only the exposure step (3) will be described here, and a repetitive description of the remaining steps will be omitted).

(3) Projection type ultraviolet exposure

The semiconductor structure after the steps is tightly fixed on a sample stage of a projection type photoetching machine, and projection type ultraviolet exposure operation is carried out through a photoetching mask. The exposure time is adjusted according to the type of the photoresist pairing group and the thickness of the photoresist layer. After the exposure was completed, the exposed silicon wafer was transferred to a heating stage and baked at 110℃for 90 seconds. The exposure flux is, for example, 100mJ/cm ², which can be varied as desired.

Example 1c

In example 1a, the exposure method in which the semiconductor structure is tightly fixed under the mask and evacuated and placed under the ultraviolet light source is used, and in example 1b, the projection exposure method is used, but the present invention is not limited thereto. For example, the positive and negative bilayer photoresist lithography of the present invention may also use a uv direct write exposure. Hereinafter, in this example 1c, an exposure step of the positive and negative bilayer resist lithography of the present invention using uv direct-write exposure will be described (since the remaining steps are similar to example 1a, only the exposure step (3) will be described here, and a repetitive description of the remaining steps will be omitted).

(3) Ultraviolet direct writing exposure

And tightly fixing the semiconductor structure subjected to the steps under an exposure source, and opening an ultraviolet direct-writing system to perform direct-writing exposure operation. The exposure time is adjusted according to the type of the photoresist pairing group and the thickness of the photoresist layer. After the exposure is finished, the mask plate is taken down, the exposed silicon wafer is moved to a heating table, and the silicon wafer is baked for 60 seconds at 110 ℃. The exposure flux is, for example, 100mJ/cm ², which can be varied as desired.

Example 1d

In the exposure, in the embodiment 1a, an exposure method in which the semiconductor structure is tightly fixed under the mask plate and vacuumized and placed under the ultraviolet light source is used, in the embodiment 1b, a projection exposure method is used, and in the embodiment 1c, an ultraviolet direct writing exposure method is used, but the present invention is not limited thereto. For example, the positive and negative bilayer photoresist lithography of the present invention may also use electron beam direct write exposure. Hereinafter, in this example 1d, the main steps of the positive and negative bilayer resist lithography of the present invention using electron beam direct-write exposure will be described.

(1) Spin-on negative photoresist

Placing the semiconductor structure after cleaning on a rotator Tu Yi, and fixing in vacuum. And (3) dripping negative electron beam photoresist HSQ, spin-coating the photoresist, and pre-baking.

(2) Spin-on positive photoresist

The cooled semiconductor structure is placed in a screw Tu Yi and held in vacuum. And (3) dripping positive electron beam photoresist PMMA, spin-coating the photoresist, and pre-baking.

(3) Electron beam direct writing exposure

And placing the semiconductor structure subjected to the steps in an electron beam direct writing system to perform electron beam direct writing operation. And adjusting the electron beam exposure dose according to the type of the photoresist pairing group and the thickness of the photoresist layer. After the electron beam direct writing exposure is finished, the exposed semiconductor structure is moved to a heating table for post baking. The exposure flux is, for example, 500. Mu.C/cm ², which can be varied as desired.

(4) Positive photoresist development

After the post baking is finished, after the semiconductor structure is cooled to room temperature, developing respectively, wherein the process is as follows: placing the semiconductor structure after photoetching in positive electron beam photoresist developing solution (MIBK: IPA developing solution) to enable the exposed positive photoresist on the semiconductor structure to be washed away; the semiconductor structure is then removed and rinsed with water and dried with a stream of nitrogen.

(5) Negative photoresist development

Placing the semiconductor structure in negative electron beam photoresist developer (TMAH developer), and partially removing unexposed negative photoresist PMMA below the unexposed positive photoresist; the semiconductor structure is then removed and rinsed with water and dried with a stream of nitrogen. A contour pattern based on the template pattern is prepared.

The material layer protrusion structure can be realized by further combining the steps of material deposition and the like, and the description will not be repeated here because of the similarity to the steps (6) and (7) in embodiment 1 a.

Embodiment 2

< Lithography method based on negative resist+interlayer film+positive resist combined deposition technique >

Embodiment 2 of the present invention provides a patterning process based on negative photoresist, interlayer film and positive photoresist, the method comprising the steps of:

(1) Forming a negative photoresist layer on the semiconductor structure, forming an interlayer on the negative photoresist layer, and forming a positive photoresist layer on the interlayer by using a positive photoresist;

(3) Developing the positive photoresist layer by using positive photoresist developing solution to remove positive photoresist in the positive graph area;

(4) Developing the interlayer by using interlayer developing solution, or etching the interlayer by taking the pattern of the developed positive photoresist layer as an etching-resistant mask so as to enable the pattern of the interlayer to be consistent with the pattern of the developed positive photoresist layer; and

(5) Developing the negative photoresist layer with a negative photoresist developer to remove negative photoresist located adjacent to the negative pattern region and thereby provide an exposed region associated with the positive pattern region and the negative pattern region in size to expose the semiconductor structure; and

(6) A layer of material is deposited over the semiconductor structure.

Next, embodiment 2 of the negative photoresist+interlayer film+positive photoresist patterning process will be described in detail with reference to fig. 6A, 6B, 6C, 6D, 6E, 6F, 6G, 6H, and 6I. In the drawings, the same or corresponding portions are denoted by the same reference numerals. In embodiment 2, similar parts to those of embodiment 1 are omitted from repeated explanation.

Fig. 6A is a schematic diagram showing a step 1B of applying a negative photoresist on a semiconductor structure in a patterning process according to embodiment 2 of the present invention. Fig. 6B is a schematic diagram showing step 2B of coating a negative photoresist with a spacer in the patterning process according to embodiment 2 of the present invention. Fig. 6C is a schematic diagram showing step 3B of applying positive resist on the interlayer in the patterning process of embodiment 2 of the present invention.

First, as shown in fig. 6A, in step 1B, a layer of negative photoresist 302B (i.e., a negative photoresist layer) is spin-coated on the hard mask layer 301B of the semiconductor structure 300 (note that the hard mask layer 301B is optional, or there may be no hard mask layer 301B or other coating on top of the semiconductor structure 300), and baked; then, as shown in fig. 6B, in step 2B, a spacer film 310B is coated on the negative photoresist 302B; then, as shown in fig. 6C, in step 2C, a positive photoresist 303B (i.e., a positive photoresist layer) matching the negative photoresist 302B is spin-coated on the interlayer film 310B, and baked (corresponding to forming a negative photoresist layer on the semiconductor structure, forming an interlayer on the negative photoresist layer, and forming a positive photoresist layer on the interlayer using the positive photoresist layer).

The negative photoresist comprises negative ultraviolet photoresist, negative deep ultraviolet photoresist, negative extreme ultraviolet photoresist, negative electron beam photoresist, negative ion beam photoresist or negative X-ray photoresist. Positive photoresists include positive ultraviolet photoresists, positive deep ultraviolet photoresists, positive extreme ultraviolet photoresists, positive electron beam photoresists, positive ion beam photoresists, or positive X-ray photoresists.

Fig. 6D is a schematic diagram showing step 4B of exposing two layers of photoresist in the patterning process of embodiment 2 of the present invention.

After step 3B, as shown in fig. 6D, in step 4B, the two layers of photoresist 302B, 303B are exposed to an exposure source using a reticle carrying a template pattern or by focus-direct writing (an example of a reticle 308B is shown in fig. 6D). After exposure, exposure patterns 304B, 305B (i.e., negative pattern areas, positive pattern areas) having different sizes are formed on the negative photoresist 302B and the positive photoresist 303B, respectively, and then baking (corresponding to patterning the negative photoresist layer and the positive photoresist layer, thereby forming positive pattern areas and negative pattern areas on the positive photoresist layer and the negative photoresist layer, respectively, wherein the positive pattern areas are larger than the negative pattern areas).

The exposure source comprises an ultraviolet light source, a deep ultraviolet light source, an extreme ultraviolet light source, an ion beam, an electron beam or X-rays. Focusing direct writing includes ultraviolet direct writing, deep ultraviolet direct writing, extreme ultraviolet direct writing, ion beam direct writing, electron beam direct writing or X-ray direct writing. The feature line width or feature size of the template pattern is 2nm-1000 μm.

As one example, a pre-baked semiconductor structure is secured under a reticle, then placed under an ultraviolet light source, and the ultraviolet light source is turned on for photolithography. The exposure time is adjusted according to the positive and negative photoresist pairing set used. Taking the above mentioned pairing as an example, an exposure flux of 100-200mJ/cm ² at a wavelength of 350-400nm is applicable to the resist pairing group of HTI 751 and SUN 9i, or AZ 1500 and AZ nlof 2020. The use of UV wavelengths and exposure flux should take into account the absorption of UV light by positive photoresists of varying thickness (e.g. HTI 751, az 1500) to ensure that sufficient exposure flux is obtained in the underlying negative photoresists (e.g. SUN 9i, az nlof 2020). Because the HTI 751 and SUN 9i, az 1500 and AZ nlof 2020 photoresist pairs have different exposure flux responses at specific wavelengths, different sized patterns (e.g. 304B, 305B in fig. 6D) based on reticle patterns can be obtained.

Fig. 6E is a schematic diagram showing step 5B of developing the resist in the patterning process of embodiment 2 of the present invention. Fig. 6F is a schematic diagram showing step 6B of patterning the spacer layer in the patterning process according to embodiment 2 of the present invention. Fig. 6G is a schematic diagram showing step 7B of developing the negative photoresist in the patterning process of embodiment 2 of the present invention.

After step 4B, as shown in fig. 6E, in step 5B, the positive photoresist is developed with a positive photoresist developer (corresponding to developing the positive photoresist layer with a positive photoresist developer to remove the positive photoresist in the positive pattern region); then, as shown in fig. 6F, in step 6B, developing the interlayer film with an interlayer film developing solution, or etching the interlayer film with the pattern of the developed positive photoresist as an etching resist mask, so that the pattern of the interlayer film is consistent with the pattern of the developed positive photoresist (corresponding to developing the interlayer with the interlayer developing solution, or etching the interlayer with the pattern of the developed positive photoresist layer as an etching resist mask, so that the pattern of the interlayer is consistent with the pattern of the developed positive photoresist layer); then, as shown in fig. 6G, in step 7B, the negative photoresist is controllably developed with a negative photoresist developer, only an edge portion of the exposure pattern 304B on the negative photoresist is washed away, and the hard mask layer is exposed, thereby converting the template pattern into a contour pattern (corresponding to developing the negative photoresist layer with the negative photoresist developer to remove the negative photoresist located near the negative pattern region, thereby providing an exposure region related to the size of the positive pattern region, the negative pattern region to expose the semiconductor structure).

As one example, the exposed semiconductor structure is placed in a corresponding positive photoresist developer, such as TMAH developer, such that the exposed positive photoresist on the semiconductor structure is rinsed away, creating a pattern opposite the exposed pattern, after which the semiconductor structure is rinsed, developed, and dried to remove residual liquid. Then, the exposed semiconductor structure is placed in a corresponding interlayer film developing solution, such as TMAH developing solution, or a dry etching method and other means are adopted, the positive photoresist pattern is used as an etching-resistant mask, the positive photoresist pattern is transferred onto the interlayer film below, and then the semiconductor structure is cleaned and dried according to the situation, so that the interlayer film obtains a pattern consistent with or close to the positive photoresist pattern. Then, the exposed semiconductor structure is placed in a corresponding negative photoresist developer, such as TMAH developer, and the exposed negative photoresist on the semiconductor structure is partially (not completely) washed out by adjusting the development time, and then the semiconductor structure is cleaned, the developer is removed, and the residual liquid is removed, so that the contour pattern of the exposed pattern is obtained.

In addition, if the developing solutions of the positive photoresist, the negative photoresist and the interlayer film are the same, or the developing solutions of the positive photoresist, the negative photoresist and the interlayer film are the same, the corresponding developing steps can be combined according to actual conditions, so that the cleaning and drying steps can be reduced. In addition, the positive photoresist, the negative photoresist, the interlayer film and the corresponding developing solution should be subjected to a crossover experiment to formulate the most suitable developing process.

Fig. 6H is a schematic diagram showing step 8B of deposition by a deposition technique in the photolithography method of embodiment 2 of the present invention. Fig. 6I is a schematic diagram showing step 9B of removing photoresist after deposition in the photolithography method of embodiment 2 of the present invention.

After step 7B, as shown in fig. 6H, in step 8B, a deposition layer 306B may be formed by a material deposition technique. Then, as shown in fig. 6I, in step 9B, the photoresist is removed, leaving a contour pattern.

By adopting the embodiment 2 of the present invention, as shown in fig. 4, a contour pattern based on a mask pattern can be obtained, and the line width of the contour pattern is smaller than that of the mask pattern, so that the line density multiplication can be realized, and the size reduction for the original mask pattern can be realized; and, through coating the interlayer film between two layers of photoresist, can also avoid or reduce the phenomenon that two layers of photoresist dissolve in the coating process.

Example 2a

As an example, the present embodiment 2a specifically includes the following steps:

(1) Coating negative photoresist

(2) Coating interlayer film

The semiconductor structure is placed in a barrier film coating system (doctor blade, spray, spin, etc.) for barrier film coating. The interlayer film comprises an inorganic, polymer or composite material. The interlayer is used for avoiding or reducing the phenomenon that two layers of photoresist are dissolved in the coating process.

(3) Coating positive photoresist

(4) Exposure to light

(5) Positive photoresist development

(6) Interlayer film patterning

And placing the exposed semiconductor structure in a corresponding interlayer film developing solution, such as TMAH developing solution, or adopting dry etching and other means, taking the positive photoresist pattern as an etching-resistant mask, transferring the positive photoresist pattern onto the interlayer film below, and then cleaning and drying the wafer according to the condition, so that the interlayer film obtains a pattern consistent with or close to the positive photoresist pattern.

(7) Negative photoresist development

Note that if the developing solutions of the positive photoresist, the negative photoresist, the interlayer film are the same, or the developing solutions of both are the same, the corresponding developing steps may be combined according to actual conditions, so that the cleaning and drying steps may be reduced.

(8) Material deposition

Placing the developed semiconductor structure in an evaporation coating apparatus, pumping the molecular pump to 10-6Pa, and usingAndA2 nm chromium film and a 50 nm gold film were thermally evaporated, respectively. A2 nm chromium film was used as an adhesion layer for the gold film.

(9) Photoresist removal

And after the cavity is cooled, releasing the vacuum, and taking out the semiconductor structure after coating. The semiconductor structure was immersed in acetone and ultrasonically cleaned until the photoresist was completely removed, leaving a gold profile pattern.

In addition, similarly to the projection exposure of example 1b, the ultraviolet write-through exposure of example 1c, and the electron beam write-through exposure of example 1d described above, in this embodiment 2, example 2a may be modified to obtain example 2b using projection exposure, example 2c using ultraviolet write-through exposure, and example 2d using electron beam write-through exposure. Here, repetitive description of the projection exposure of example 2b, the ultraviolet write-through exposure of example 2c, and the electron beam write-through exposure of example 2d will be omitted.

Embodiment 3

< Photolithography method based on Positive resist+interlayer film+negative resist combined deposition technique >

Embodiment 3 of the present invention provides a patterning process based on positive photoresist, interlayer film and negative photoresist, the method comprising the steps of:

(1) Forming a positive photoresist layer on the semiconductor structure, forming an interlayer on the positive photoresist layer, and forming a negative photoresist layer on the interlayer by using a negative photoresist;

(3) Developing the negative photoresist layer by using a negative photoresist developing solution to remove negative photoresist outside the negative pattern area;

(4) Developing the interlayer by using interlayer developing solution, or etching the interlayer by taking the pattern of the developed negative adhesive layer as an etching-resistant mask so as to enable the pattern of the interlayer to be consistent with the pattern of the developed negative adhesive layer; and

(5) Developing the positive photoresist layer with a positive photoresist developer to remove positive photoresist at an edge portion of the positive pattern region, thereby providing an exposed region associated with the dimensions of the positive pattern region and the negative pattern region to expose the semiconductor structure; and

(6) A layer of material is deposited over the semiconductor structure.

Next, embodiment 3 of the positive resist+spacer film+negative resist patterning process will be described in detail with reference to fig. 7A, 7B, 7C, 7D, 7E, 7F, and 7G. In the drawings, the same or corresponding portions are denoted by the same reference numerals. In embodiment 3, similar parts to those in embodiment 2 are omitted from repeated explanation.

Fig. 7A is a schematic diagram showing step 1C of applying positive photoresist on a semiconductor structure in the patterning process of embodiment 3 of the present invention. Fig. 7B is a schematic diagram showing step 2C of coating a spacer layer on a positive resist in the patterning process of embodiment 3 of the present invention. Fig. 7C is a schematic diagram showing step 3C of applying a negative photoresist on the interlayer in the patterning process of embodiment 3 of the present invention.

First, as shown in fig. 7A, in step 1C, a positive photoresist 303C (i.e., a positive photoresist layer) is spin-coated on the hard mask layer 301C of the semiconductor structure 300 (note that the hard mask layer 301C is optional, or there may be no hard mask layer 301C or other coating on top of the semiconductor structure 300), and baked; then, as shown in fig. 7B, in step 2C, a spacer film 310C is coated on the positive photoresist 303C; then, as shown in fig. 7C, in step 3C, a layer of negative photoresist 302C (i.e., a negative photoresist layer) matching the positive photoresist 303C is spin-coated on the interlayer film 310C, and baked (corresponding to forming a positive photoresist layer on the semiconductor structure, forming an interlayer on the positive photoresist layer, and forming a negative photoresist layer on the interlayer using the negative photoresist layer).

Fig. 7D is a schematic diagram showing step 4C of exposing two layers of photoresist in the patterning process of embodiment 3 of the present invention.

After step 3C, as shown in FIG. 7D, in step 4C, the two layers of photoresist 302C, 303C are exposed using a stencil-patterned reticle or by focus direct writing (an example of a stencil 308C is shown in FIG. 7D) under an exposure source. After exposure, exposure patterns 304C, 305C (i.e., negative pattern areas, positive pattern areas) having different sizes are formed on the negative photoresist 302C and the positive photoresist 303C, respectively, and then baking (corresponding to patterning the negative photoresist layer and the positive photoresist layer, thereby forming positive pattern areas and negative pattern areas on the positive photoresist layer and the negative photoresist layer, respectively, wherein the positive pattern areas are larger than the negative pattern areas).

As one example, a pre-baked semiconductor structure is secured under a reticle, then placed under an ultraviolet light source, and the ultraviolet light source is turned on for photolithography. The exposure time is adjusted according to the positive and negative photoresist pairing set used. Taking the above mentioned pairing as an example, an exposure flux of 100-200mJ/cm ² at a wavelength of 350-400nm is applicable to the resist pairing group of HTI 751 and SUN 9i, or AZ1500 and AZ nlof 2020. The use of UV wavelengths and exposure flux should take into account the absorption of UV light by negative photoresists of different thickness (e.g. SUN 9i, az nlof2020) to ensure that sufficient exposure flux is obtained in the underlying positive photoresist (e.g. HTI 751, az1500). Because the HTI 751 and SUN 9i, az1500 and AZ nlof2020 photoresist pairs have different exposure flux responses at specific wavelengths, different sized patterns (e.g. 304C, 305C in fig. 7D) based on reticle patterns can be obtained.

Fig. 7E is a schematic diagram showing step 5C of developing the negative photoresist in the patterning process of embodiment 3 of the present invention. Fig. 7F is a schematic diagram showing step 6C of patterning the spacer layer in the patterning process of embodiment 3 of the present invention. Fig. 7G is a schematic diagram showing step 7C of developing the resist in the patterning process of embodiment 3 of the present invention.

After step 4C, as shown in fig. 7E, in step 5C, developing the negative photoresist with a negative photoresist developer (corresponding to developing the negative photoresist layer with a negative photoresist developer to remove negative photoresist outside the negative pattern area); then, as shown in fig. 7F, in step 6C, developing the interlayer film with an interlayer film developing solution, or etching the interlayer film with the pattern of the developed positive photoresist as an etching resist mask, so that the pattern of the interlayer film is consistent with the pattern of the developed positive photoresist (corresponding to developing the interlayer with the interlayer developing solution, or etching the interlayer with the pattern of the developed negative photoresist layer as an etching resist mask, so that the pattern of the interlayer is consistent with the pattern of the developed negative photoresist layer); then, as shown in fig. 7G, in step 7C, the positive photoresist is controllably developed with a positive photoresist developer, only the edge portion of the exposure pattern 305C on the positive photoresist is washed away, and the hard mask layer is exposed, thereby converting the template pattern into a contour pattern (corresponding to developing the positive photoresist layer with a positive photoresist developer to remove the positive photoresist at the edge portion of the positive pattern region, thereby providing an exposed region related to the size of the positive pattern region, the negative pattern region, to expose the semiconductor structure).

As one example, the exposed semiconductor structure is placed in a corresponding negative photoresist developer, such as TMAH developer, and the unexposed negative photoresist on the semiconductor structure is rinsed off to create a pattern of exposed patterns, after which the semiconductor structure is rinsed, the developer removed, and dried to remove residual liquid. Then, the exposed semiconductor structure is placed in a corresponding interlayer film developing solution, such as TMAH developing solution, or a dry etching method and other means are adopted, the negative photoresist pattern is used as an etching-resistant mask, the pattern of the negative photoresist is transferred onto the interlayer film below, and then the semiconductor structure is cleaned and dried according to the situation, so that the interlayer film obtains a pattern consistent with or close to the negative photoresist pattern. Then, the exposed semiconductor structure is placed in a corresponding positive photoresist developer, such as TMAH developer, and the exposed positive photoresist on the semiconductor structure is partially (not completely) washed away by adjusting the development time, and then the semiconductor structure is cleaned, the developer is removed, and the residual liquid is removed, so that the contour pattern of the exposed pattern is obtained.

Example 3a

As an example, the present embodiment 3a specifically includes the following steps:

(1) Coating positive photoresist

The initial semiconductor structure is placed into a spin-on system and fixed, a positive photoresist (e.g., HTI751 or AZ 1500), spin-coated at 800rpm x 5s+2500rpm x 30s, and then baked at 95-100 ℃ for 40 seconds.

(2) Coating interlayer film

(3) Coating negative photoresist

The cooled wafer is placed in a spin coater system and fixed, and a negative photoresist (e.g., SUN9i, AZ nlof 2020) is spin coated at 1000rpm×5s+4000rpm×40s, and then baked at 100-110 ℃ for 60 seconds.

(4) Exposure to light

(5) Negative photoresist development

The exposed semiconductor structure is placed in a corresponding negative photoresist developer, such as TMAH developer, so that the unexposed negative photoresist on the semiconductor structure is washed away, thereby creating a pattern of exposed patterns, and then the semiconductor structure is washed, the developer is removed, and then dried to remove residual liquid.

(6) Interlayer film patterning

And placing the exposed semiconductor structure in a corresponding interlayer film developing solution, such as TMAH developing solution, or adopting dry etching and other means, taking the negative photoresist pattern as an etching-resistant mask, transferring the pattern of the negative photoresist to the interlayer film below, and then cleaning and drying the semiconductor structure according to the condition, so that the interlayer film obtains a pattern consistent with or close to the negative photoresist pattern.

(7) Positive photoresist development

And placing the exposed semiconductor structure in a corresponding positive photoresist developer, such as TMAH developer, and adjusting the development time to wash away part (not all) of the exposed positive photoresist on the semiconductor structure, then cleaning the semiconductor structure, removing the developer, drying and removing residual liquid, thereby obtaining the contour pattern of the exposed pattern.

In this embodiment 3a, the deposition step may be further performed in addition to the steps (1) to (7), and the specific content of the deposition step is similar to that in the embodiment 2a, so that a repetitive description thereof is omitted here.

In addition, similarly to the projection exposure of example 1b, the ultraviolet write-through exposure of example 1c, and the electron beam write-through exposure of example 1d described above, in embodiment 3, example 3a may be modified to obtain example 3b using projection exposure, example 3c using ultraviolet write-through exposure, and example 3d using electron beam write-through exposure. Here, repetitive description of the projection exposure of example 3b, the ultraviolet write-through exposure of example 3c, and the electron beam write-through exposure of example 3d will be omitted.

By adopting the embodiment 3 of the present invention, as shown in fig. 4, a contour pattern based on a mask pattern can be obtained, and the line width of the contour pattern is smaller than that of the mask pattern, so that the line density multiplication can be realized, and the size reduction for the original mask pattern can be realized; and, through coating the interlayer film between two layers of photoresist, can also avoid or reduce the phenomenon that two layers of photoresist dissolve in the coating process.

Embodiment 4

< Photolithography method based on Positive and negative gums in combination with deposition technique >

Embodiment 4 of the present invention provides a positive photoresist+negative photoresist-based patterning process, which includes the steps of:

(1) Forming a positive photoresist layer on the semiconductor structure, and forming a negative photoresist layer on the positive photoresist layer by using the negative photoresist;

(3) Developing the negative photoresist layer by using a negative photoresist developing solution to remove negative photoresist in the negative pattern area;

(4) Developing the positive photoresist layer with a positive photoresist developer to remove positive photoresist at an edge portion of the positive pattern region, thereby providing an exposed region associated with the dimensions of the positive pattern region and the negative pattern region to expose the semiconductor structure; and

(5) A layer of material is deposited over the semiconductor structure.

Embodiment 4 differs from embodiment 3 in that the interlayer film is omitted, and thus the processing steps associated with the interlayer film can be omitted, while the other steps are substantially identical to embodiment 3, and thus will not be described again.

In some embodiments of the present invention, in addition to the above-mentioned photolithography mask having the template pattern, photolithography may be performed by using a selective mask (as shown in fig. 9) in a superimposed manner in the exposure step of the patterning process, so as to implement selective via processing.

< System for Forming a Via in a semiconductor Structure >

Next, a structure of a system corresponding to a method for forming a via hole in a semiconductor structure according to an embodiment of the present invention will be described in detail.

Fig. 10 is a block diagram schematically illustrating a system according to the present invention for a method of forming a via in a semiconductor structure.

As shown in fig. 10, a lithography system 1000 corresponding to the method of forming a via in a semiconductor structure of the present invention includes a layer patterning portion 1001 and an etching portion 1002, the system being configured to perform the steps of:

forming a first material layer on the semiconductor structure using a first patterning process based on a bilayer photoresist using the patterning 1001, the first material layer having a first pattern;

Forming a second material layer on the semiconductor structure using a bilayer photoresist-based second patterning process using the patterning 1001, the second material layer having a second pattern, wherein the first material layer and the second material layer overlap to define a plurality of independent exposed regions of the semiconductor structure;

the exposed semiconductor structure is etched using the etching portion 1002 with the first material layer and the second material layer as an etch-resistant mask to form a plurality of vias in the semiconductor structure.

In addition, the invention also provides a system control method for controlling the system to execute each step.

In addition, the present invention also provides a computer device, including: the system comprises a memory, a processor and a computer program stored in the memory and capable of running on the processor, and is characterized in that the processor executes the computer program to realize the system control method.

Furthermore, the present invention provides a computer readable medium having stored thereon a computer program which, when executed by a processor, implements the above-described system control method.

Thus, the method and system of forming a semiconductor structure of the present invention has been described. The invention utilizes the positive photoresist, namely the positive photoresist and the negative photoresist, to obtain the difference of exposure energy in the light source response and the exposure, and utilizes the difference of pattern sizes after the positive photoresist and the negative photoresist which are matched with each other are actually developed to obtain the contour line type pattern based on the characteristics of the original mask pattern, and the line width of the contour line type pattern is smaller than the line width of the characteristics of the original mask pattern, thereby realizing the multiplication of line density, and then the contour line type pattern can be further transferred to a target material by combining a deposition process or an etching process for a semiconductor structure or an optional hard mask layer on the top of the semiconductor structure.

Compared with the prior art, the invention has the following advantages:

(1) A completely different way of forming the through holes from the prior art is provided;

(2) The invention has the characteristics of high efficiency, low cost and simple operation, realizes the size miniaturization of the original mask pattern, and can realize smaller line width than the traditional technology through the pattern contouring;

(3) According to the invention, the interlayer film is coated between the two layers of photoresist, so that the phenomenon that the two layers of photoresist are dissolved in the coating process can be avoided or reduced.

Industrial applicability

The method and the system of the invention can be widely applied to the fields of semiconductor technology, chip manufacturing and the like, and have wide research and application values.

Claims

1. A method for forming a via in a semiconductor structure, the method comprising the steps of:

Providing a semiconductor structure;

Forming a first material layer on the semiconductor structure by using a first patterning process based on a bilayer photoresist, wherein the first material layer has a first pattern;

Forming a second material layer on the semiconductor structure using a bilayer photoresist-based second patterning process, the second material layer having a second pattern, wherein the first material layer and the second material layer overlap to define a plurality of independent exposed regions of the semiconductor structure; and

And etching the exposed semiconductor structure by taking the first material layer and the second material layer as etching-resistant masks so as to form a plurality of through holes in the semiconductor structure.

2. The method of claim 1, wherein at least one of the first patterning process and the second patterning process comprises the steps of:

forming a negative photoresist layer on the semiconductor structure, and forming a positive photoresist layer on the negative photoresist layer by using a positive photoresist;

Patterning the negative adhesive layer and the positive adhesive layer so as to form a positive pattern area and a negative pattern area on the positive adhesive layer and the negative adhesive layer respectively, wherein the positive pattern area is larger than the negative pattern area;

developing the positive photoresist layer by using positive photoresist developing solution to remove positive photoresist in the positive graph area;

Developing the negative photoresist layer with a negative photoresist developer to remove negative photoresist located adjacent to the negative pattern region and thereby provide an exposed region associated with the positive pattern region and the negative pattern region in size to expose the semiconductor structure; and

A layer of material is deposited over the semiconductor structure.

3. The method of claim 1, wherein at least one of the first patterning process and the second patterning process comprises the steps of:

forming a negative photoresist layer on the semiconductor structure, forming an interlayer on the negative photoresist layer, and forming a positive photoresist layer on the interlayer by using a positive photoresist;

Developing the interlayer by using interlayer developing solution, or etching the interlayer by taking the pattern of the developed positive photoresist layer as an etching-resistant mask so as to enable the pattern of the interlayer to be consistent with the pattern of the developed positive photoresist layer; and

A layer of material is deposited over the semiconductor structure.

4. The method of claim 1, wherein at least one of the first patterning process and the second patterning process comprises the steps of:

forming a positive photoresist layer on the semiconductor structure, forming an interlayer on the positive photoresist layer, and forming a negative photoresist layer on the interlayer by using a negative photoresist;

Developing the negative photoresist layer by using a negative photoresist developing solution to remove negative photoresist outside the negative pattern area;

Developing the interlayer by using interlayer developing solution, or etching the interlayer by taking the pattern of the developed negative adhesive layer as an etching-resistant mask so as to enable the pattern of the interlayer to be consistent with the pattern of the developed negative adhesive layer; and

Developing the positive photoresist layer with a positive photoresist developer to remove positive photoresist at an edge portion of the positive pattern region, thereby providing an exposed region associated with the dimensions of the positive pattern region and the negative pattern region to expose the semiconductor structure; and

A layer of material is deposited over the semiconductor structure.

5. The method of claim 1, wherein at least one of the first patterning process and the second patterning process comprises the steps of:

Forming a positive photoresist layer on the semiconductor structure, and forming a negative photoresist layer on the positive photoresist layer by using a negative photoresist;

Developing the negative photoresist layer by using a negative photoresist developing solution to remove negative photoresist in the negative pattern area;

A layer of material is deposited over the semiconductor structure.

6. The method according to any one of claim 2 to 5, wherein,

In the patterning step, under an exposure source, a photoetching mask plate carrying a template pattern is used or through focusing direct writing, the positive photoresist layer and the negative photoresist layer are exposed, so that a positive pattern area and a negative pattern area are respectively formed on the positive photoresist layer and the negative photoresist layer.

7. The method of claim 6, wherein the template pattern for the first patterning process comprises a plurality of lines extending along a first direction and the template pattern for the second patterning process comprises a plurality of lines extending along a second direction.

8. The method of claim 6, wherein the step of providing the first layer comprises,

In the step of the patterning step of the wafer,

Exposing the positive adhesive layer and the negative adhesive layer by using a projection exposure mode under an exposure source through a photoetching mask plate carrying the template pattern; or alternatively

Exposing the positive adhesive layer and the negative adhesive layer by using a shielding exposure mode under an exposure source through a photoetching mask plate carrying the template pattern; or alternatively

And exposing the positive adhesive layer and the negative adhesive layer by reflecting on the photoetching mask plate carrying the template pattern under an exposure source in a reflection type exposure mode.

9. The method of claim 6, wherein the step of providing the first layer comprises,

The focusing direct writing comprises ultraviolet direct writing, deep ultraviolet direct writing, extreme ultraviolet direct writing, ion beam direct writing, electron beam direct writing or X-ray direct writing.

10. The method according to any one of claim 2 to 5, wherein,

Depositing the layer of material includes using electrochemical deposition, electroplating, CVD deposition, laser sputtering, magnetron sputtering, thermal evaporation, electron beam evaporation, or atomic deposition.

11. A system for forming a via in a semiconductor structure, comprising a patterning and etching, the system for performing the steps of:

Forming a first material layer on the semiconductor structure using a double-layer photoresist-based first patterning process using the patterning part, the first material layer having a first pattern;

Forming a second material layer on the semiconductor structure using a bilayer photoresist-based second patterning process using the patterning, the second material layer having a second pattern, wherein the first material layer and the second material layer overlap to define a plurality of independent exposed regions of the semiconductor structure;

And etching the exposed semiconductor structure by using the etching part and taking the first material layer and the second material layer as etching-resistant masks so as to form a plurality of through holes in the semiconductor structure.

12. The system of claim 11, wherein at least one of the first patterning process and the second patterning process comprises the steps of:

A layer of material is deposited over the semiconductor structure.

13. The system of claim 11, wherein at least one of the first patterning process and the second patterning process comprises the steps of:

A layer of material is deposited over the semiconductor structure.

14. The system of claim 11, wherein at least one of the first patterning process and the second patterning process comprises the steps of:

A layer of material is deposited over the semiconductor structure.

15. The system of claim 11, wherein at least one of the first patterning process and the second patterning process comprises the steps of:

A layer of material is deposited over the semiconductor structure.

16. A system control method for controlling the system according to any one of claims 11 to 15 to perform the respective steps.

17. A computer device, comprising: a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the processor implements the system control method of claim 16 when executing the computer program.

18. A computer readable medium having stored thereon a computer program which, when executed by a processor, implements the system control method of claim 16.