CN118171623A - Power supply network analysis method and system based on distributed computing platform - Google Patents
Power supply network analysis method and system based on distributed computing platform Download PDFInfo
- Publication number
- CN118171623A CN118171623A CN202410580704.4A CN202410580704A CN118171623A CN 118171623 A CN118171623 A CN 118171623A CN 202410580704 A CN202410580704 A CN 202410580704A CN 118171623 A CN118171623 A CN 118171623A
- Authority
- CN
- China
- Prior art keywords
- sub
- line
- coupling
- host
- unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 77
- 238000003012 network analysis Methods 0.000 title claims abstract description 39
- 230000008878 coupling Effects 0.000 claims abstract description 103
- 238000010168 coupling process Methods 0.000 claims abstract description 103
- 238000005859 coupling reaction Methods 0.000 claims abstract description 103
- 238000004364 calculation method Methods 0.000 claims abstract description 34
- 238000004458 analytical method Methods 0.000 claims abstract description 31
- 238000012545 processing Methods 0.000 claims abstract description 16
- 230000004044 response Effects 0.000 claims description 17
- 238000013461 design Methods 0.000 abstract description 9
- 239000011159 matrix material Substances 0.000 description 25
- 239000003990 capacitor Substances 0.000 description 22
- 230000008569 process Effects 0.000 description 9
- 238000010586 diagram Methods 0.000 description 7
- 238000013507 mapping Methods 0.000 description 6
- 230000002776 aggregation Effects 0.000 description 4
- 238000004220 aggregation Methods 0.000 description 4
- 230000003993 interaction Effects 0.000 description 4
- 230000007246 mechanism Effects 0.000 description 3
- 238000011156 evaluation Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000008901 benefit Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000011362 coarse particle Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000001808 coupling effect Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000011218 segmentation Effects 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
Landscapes
- Supply And Distribution Of Alternating Current (AREA)
Abstract
A power network analysis method and system based on a distributed computing platform, the method comprising: the method comprises the steps that a host machine performs slice division on a power supply network line to obtain at least two sub-line units; the electrical connection relation between the sub-line units is non-coupling, capacitive coupling and resistive coupling; when capacitive coupling or resistive coupling exists between the sub-line units, decoupling processing is carried out; the slave machine builds a unit model for the corresponding sub-line unit; the host machine merges the unit models corresponding to the sub-line units which are connected in a coupling way, so that the corresponding slave machine builds a merging model; the corresponding slave calculates the working electric parameters of the power supply network line based on the merging model and the unit model outside the merging model in the power supply network line. Therefore, the efficiency and the precision of the power circuit integrity analysis can be effectively improved, the method is suitable for the layout and wiring design scene of the chip, the method is not limited by the calculated amount of the power circuit integrity analysis, and the threshold of calculation resources is low.
Description
Technical Field
The application relates to the technical field of electronic design automation directional power supply integrity analysis, in particular to a power supply network analysis method and system based on a distributed computing platform.
Background
In the Placement & Routing (layout and wiring) stage of chip design, the rapid and accurate power supply network analysis method has great effect. Because the conditions that the circuit design needs to meet influence each other, when the components are rearranged in order to meet the time sequence requirement, the power distribution changes, the voltage value of the components is changed, and the voltage change is fed back to the time sequence again. Thus requiring dual verification of timing and power supply for each adjustment of the circuit.
The traditional power integrity analysis focuses on the Signoff (signing and checking) stage, and is large in calculation task amount and long in time, and is not suitable for the design stage. However, the existing rapid method model is too simplified, so that the problems are difficult to find in time, and the hidden problems are easy to be delayed to the next stage.
Based on this, how to provide a power supply network analysis method, which gives consideration to the efficiency and the accuracy of the analysis, is a problem to be solved.
Disclosure of Invention
In order to solve at least one problem in the prior art, the application aims to provide a power supply network analysis method and system based on a distributed computing platform, which not only can effectively improve the efficiency and the accuracy of power supply circuit integrity analysis, but also are suitable for a chip layout and wiring design scene, are not limited by the calculation amount of power supply integrity analysis, and have low calculation resource threshold.
In order to achieve the above object, the power network analysis method based on a distributed computing platform provided by the present application is applied to a power network analysis system, where the system includes a distributed computing platform, a host computer, and at least two slave computers serving as computing nodes; the method may include the steps of,
The host machine performs slice division on the power supply network line to obtain at least two sub-line units; wherein the electrical connection between the at least two sub-line units includes at least one of no coupling, capacitive coupling, and resistive coupling;
The host determining whether the capacitive coupling and/or the resistive coupling exists between the at least two sub-line units; if yes, decoupling the corresponding coupling;
The host maps the calculation tasks of the at least two sub-line units to corresponding slaves respectively, so that the slaves construct a unit model for the corresponding sub-line units;
the host machine merges the unit models corresponding to the sub-line units which are coupled and connected, so that the corresponding slave machine constructs a merging model; and the corresponding slave machine calculates the working electric parameters of the power supply network line based on the merging model and a unit model outside the merging model in the power supply network line.
Further, the step of slicing and dividing the power network line by the host to obtain at least two sub-line units includes:
the host machine performs one-time slicing division on the power supply network line to obtain at least two uncoupled sub-circuit units; wherein, there is no coupling connection between the said at least two non-coupling sub-circuit units;
The host computer respectively acquires analysis calculated amounts corresponding to the at least two uncoupled sub-circuit units;
Responding to the fact that the analysis calculated amount of the uncoupled sub-circuit unit is larger than the processing capacity of a single computer, the host machine carries out sub-slicing division on the corresponding uncoupled sub-circuit unit to obtain the sub-circuit unit;
In response to the analysis computation of the uncoupled sub-circuit unit being less than or equal to the processing power of the single computer, the host determines the corresponding uncoupled sub-circuit unit as the sub-line unit.
Further, the step of decoupling the respective couplings comprises,
Configuring at least two grounding nodes for the power supply network line;
And replacing the original coupling capacitance connected between the first power line and the second power line with two replacement capacitances with the two capacitance values twice that of the original coupling capacitance, wherein one replacement capacitance is connected between the first power line and one grounding node, and the other replacement capacitance is connected between the second power line and the one grounding node.
Further, the step of decoupling the respective couplings comprises,
The host determines whether the resistor coupled to the resistor has a parallel resistor; if so, combining the parallel resistors; and/or the number of the groups of groups,
The host determines whether the resistance value of the resistor coupled by the current resistor is larger than or equal to a resistor threshold value; if yes, the corresponding resistor is removed.
Further, the method also comprises the steps of,
In response to receiving a client request instruction, the distributed computing platform deploys a computer from the power network analysis system to act as the host.
Further, the method further comprises the step that after the slicing is divided, the host sends a unit calculation request instruction to the distributed computing platform;
In response to receiving the unit calculation request instruction, the distributed computing platform deploys at least two computers from the power network analysis system, acting as slaves in constructing the respective unit models.
Further, the method further comprises the step that after merging, the host sends a merging calculation request instruction to the distributed computing platform;
In response to receiving the merge computation request instruction, the distributed computing platform deploys at least one computer from the power network analysis system as a slave to construct the corresponding merge model.
Further, the method comprises the step that the slave machine constructs the unit model by adopting a Krylov projection method, a moment matching method or a rational fitting method on the corresponding sub-line unit.
Further, the distributed computing platform is a distributed system infrastructure cloud platform.
In order to achieve the above object, the present application further provides a power network analysis system based on a distributed computing platform, which includes the distributed computing platform, a host computer, and at least two slave computers serving as computing nodes; wherein,
The distributed computing platform is used for analyzing and allocating resources for the power supply network;
The host is used for slicing and dividing the power supply network line to obtain at least two sub-line units; wherein the electrical connection between the at least two sub-line units includes at least one of no coupling, capacitive coupling, and resistive coupling; and for determining whether said capacitive coupling and/or said resistive coupling exists between said at least two sub-line elements; if yes, decoupling the corresponding coupling; the computing tasks of the at least two sub-line units are respectively mapped to corresponding slaves;
The slave is used for constructing a unit model for the corresponding sub-line unit;
the host is used for merging the unit models corresponding to the coupled sub-line units;
The slave machine is used for constructing a merging model; and the corresponding slave machine also calculates the working electric parameters of the power supply network line based on the merging model and a unit model outside the merging model in the power supply network line.
According to the power supply network analysis method and system based on the distributed computing platform, a power supply network line is sliced and divided through a host to obtain at least two sub-line units; when the host determines that capacitive coupling or resistive coupling exists between the sub-line units, decoupling is carried out on the corresponding coupling; the calculation tasks of the sub-line units are respectively mapped to the slaves through the master, so that the slaves construct a unit model for the corresponding sub-line units; merging unit models of the sub-line units which are coupled and connected through a host computer so as to enable corresponding slave mechanisms to build a merging model; and calculating the working electric parameters of the power supply network line based on the merging model and a unit model outside the merging model in the power supply network line through the corresponding slave machine.
Therefore, through rapid and reliable voltage drop analysis, the efficiency and the precision of the power circuit integrity analysis can be effectively improved, the method is suitable for a chip layout and wiring design scene, is not limited by the calculation amount of the power circuit integrity analysis, and has low calculation resource threshold.
Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application.
Drawings
The accompanying drawings are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate the application and together with the embodiments of the application, and do not limit the application. In the drawings:
FIG. 1 is a block diagram of a distributed computing platform based power network analysis system in accordance with an embodiment of the present application;
FIG. 2 is a flow chart of a power network analysis method based on a distributed computing platform according to an embodiment of the application;
FIG. 3 is a schematic view of slice division according to an embodiment of the present application;
FIG. 4 is a schematic diagram of a capacitive coupling decoupling process according to an example of the related art;
FIG. 5 is a schematic diagram of a decoupling process of capacitive coupling according to another example of the related art;
FIG. 6 is a schematic diagram of a decoupling process of capacitive coupling according to yet another example of the related art;
FIG. 7 is a schematic diagram of a decoupling process of capacitive coupling according to an embodiment of the application;
FIG. 8 is a schematic diagram of a decoupling process of capacitive coupling according to another embodiment of the application;
fig. 9 is a schematic diagram of a merging process according to an embodiment of the present application.
Detailed Description
Embodiments of the present application will be described in more detail below with reference to the accompanying drawings. While the application is susceptible of embodiment in the drawings, it is to be understood that the application may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but rather are provided to provide a more thorough and complete understanding of the application. It should be understood that the drawings and embodiments of the application are for illustration purposes only and are not intended to limit the scope of the present application.
The term "including" and variations thereof as used herein are intended to be open-ended, i.e., including, but not limited to. The term "based on" is "based at least in part on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments. Related definitions of other terms will be given in the description below.
It should be noted that the concept of "first" and "second" mentioned in the present application is only used to distinguish between different matrices, and is not used to limit the order or interdependence of functions performed by these matrices.
It should be noted that references to "one", "a plurality" and "a plurality" in this disclosure are intended to be illustrative rather than limiting, and those skilled in the art will appreciate that "one or more" is intended to be construed as "one or more" unless the context clearly indicates otherwise. "plurality" is understood to mean two or more.
Hereinafter, embodiments of the present application will be described in detail with reference to the accompanying drawings.
Firstly, it should be noted that the power network analysis method based on the distributed computing platform provided by the application is applied to a power network analysis system based on the distributed computing platform. As shown in fig. 1, a power network analysis system 100 includes a distributed computing platform 101, a host 102, and at least two slaves 103 that act as computing nodes.
It is understood that the distributed computing platform 101 may be a Hadoop (distributed system infrastructure) cloud platform, or may be another suitable cloud platform. The present application is not particularly limited thereto.
Fig. 2 is a flowchart of a power network analysis method based on a distributed computing platform according to an embodiment of the present application, and the power network analysis method of the present application will be described in detail with reference to fig. 2.
In step 201, the host performs slice division on the power network line to obtain at least two sub-line units.
As shown in fig. 3, a dicing technique may be used to slice and divide the large-scale power network line 300 according to the physical characteristics of the power network line, to obtain four sub-line units 301.
In a specific example, the theoretical basis of slice division may be a graph division algorithm (such as metas) in graph theory, and by optimizing circuit nodes near the boundary, the boundary is adjusted to find a better solution, so as to minimize the number of coupling between sub-line units increased by further segmentation. In the implementation process, the graph node may be a circuit node, or may be a combination of a group of circuit nodes, i.e. supernodes. The selection of supernodes may be dependent on known circuit relationships, such as the merging of circuit nodes within a sub-circuit.
It should be noted that, the electrical connection relationship between the at least two sub-line units includes at least one of no coupling, capacitive coupling, and resistive coupling. Wherein, no coupling means no physical electrical connection; capacitive coupling refers to interaction between a power line and a ground line through capacitance; resistive coupling means that after the power network lines with physical connections are sliced, the power network lines are coupled with each other through resistors due to the existence of metal line overlapping parts.
In an embodiment of the present application, step 201 may include the following sub-steps:
In step 2011, the host performs a slice division on the power network line to obtain at least two uncoupled sub-circuit units.
Wherein, the at least two uncoupled sub-circuit units are uncoupled from each other. That is, the power network line may be partitioned based on whether there is a physical connection, and the line having the physical connection may be divided into one uncoupled sub-circuit unit, thereby obtaining the at least two uncoupled sub-circuit units.
In step 2012, the host computer obtains the analysis calculated amounts corresponding to the at least two uncoupled sub-circuit units respectively.
The evaluation calculation may be a calculation evaluation value of the circuit analysis of the corresponding uncoupled sub-circuit unit.
In step 2013, in response to the analysis computation amount of the uncoupled sub-circuit unit being greater than the processing capability of the single computer, the host computer performs sub-slicing division on the corresponding uncoupled sub-circuit unit to obtain a sub-circuit unit.
The processing capability of the computer may be a value determined based on the computer processor, the dominant frequency, and the memory-related parameters.
In response to the analysis computation of the uncoupled sub-circuit unit being less than or equal to the processing power of the single computer, the host determines the corresponding uncoupled sub-circuit unit as a sub-line unit, step 2014.
That is, for a large-scale power network line, on the basis of no coupled sub-circuit units, division may be continued until the circuit scale is suitable for slave (single general computer) processing.
At step 202, the host determines whether there is capacitive coupling and/or resistive coupling between at least two sub-line units; and if the coupling exists, decoupling the corresponding coupling.
For the decoupling treatment of capacitive coupling, the capacitance between the power lines is generally very small, and the coupling capacitance is often decoupled, however, when the conventional capacitive decoupling method is applied to a large-scale power network, errors are easily accumulated, so that the result is greatly deviated.
For example, in the related art, as shown in fig. 4, when the capacitor is decoupled, the original coupling capacitor C is changed into two replacement capacitors 2C (i.e. the size of the replacement capacitors is twice that of the original coupling capacitor), and the coupling capacitors between the power source and the ground are still C by connecting to the ground in series, so as to realize mathematical equivalence. However, this method has a disadvantage in that as the scale of the power network increases, the more power network lines, the larger the error thereof will be.
As another example, as shown in fig. 5, when the capacitors are decoupled, the original coupling capacitors C 1 -Cn are respectively changed into two replacement capacitors 2C 1 -2Cn which are connected in series through the ground, and the interaction between C 1 and Cn is weak due to the shielding of the line resistance. After decoupling, the electrical distance of C 1 from Cn becomes in close proximity due to the presence of common ground, and the interaction is greatly enhanced.
As yet another example, as shown in fig. 6, in the case of a plurality of power network lines, after the decoupling process, the original coupling capacitance C, C A becomes two replacement capacitances 2C, 2C A respectively, which are connected in series through the ground. So that the links between the lines (line VDD and line VDDA, line VSSA) which would not have been affected by each other are formed due to the presence of the common ground.
In the embodiment of the application, the step of decoupling the corresponding coupling comprises the following sub-steps:
at step 2021, at least two ground nodes are configured for the power network line.
In step 2022, the original coupling capacitance connected between the first power line and the second power line is replaced by two replacement capacitances each having a capacitance twice the original coupling capacitance, where one replacement capacitance is connected between the first power line and one ground node, and the other replacement capacitance is connected between the second power line and one ground node.
That is, an aggregation algorithm may be employed to divide the circuit into clusters, the specific number of divisions of which may depend on the accuracy requirements as well as the chip size. And in each cluster range, adding virtual grounding nodes of the circuit according to the coupling condition of the power network lines. Because the clusters are coarse particles compared with the original coupling capacitance, the number of the increased nodes is far lower than that of the original circuit nodes. The coupling of multiple lines inside the cluster only depends on the virtual grounding node, and the capacitive coupling hardly influences the splitting inside the cluster, so that the line splitting is simple and efficient.
As an example, as shown in fig. 7, the power supply network scale increases, and by configuring at least two ground nodes to form a capacitor cluster, the capacitive coupling effects between different sub-line units can be isolated. Specifically, since the replacement capacitor 2Cn at the far end of the replacement capacitor 2C 1 does not belong to the same capacitor cluster, their ground nodes are different, and are respectively GRAD1 and GRAD2, without any influence therebetween. The replacement capacitor 2C 1 only acts with other replacement capacitors in its vicinity, thereby effectively controlling the range of errors, which is limited to the interior of the vicinity.
As another example, as shown in fig. 8, in the case of multiple power network lines, the capacitive cluster decoupling method is adopted, and the original coupling relationship will not be changed due to the difference of the ground nodes of the replacement capacitors 2C, 2C A. That is, there is no coupling between the two lines, and the uncoupled state is maintained. Therefore, the capacitive cluster decoupling method is adopted, error overflow is avoided, and the analysis and calculation precision can be ensured from the global perspective.
For decoupling processing of the resistive coupling, the coupling can be further reduced by an electrical distance algorithm, thereby achieving a reasonable system scale. The method for reducing the resistance coupling is similar to the front-end processing of decoupling of the capacitor clusters, and the effective resistance engine is adopted in a small range through the aggregation algorithm, so that the resistance aggregation is rapidly simulated, and the node with small effective resistance is equivalent to a super node.
In the embodiment of the application, the step of decoupling the corresponding coupling comprises at least one of the following sub-steps:
step 2023, the host determines whether the parallel resistances exist for the resistance coupled resistances; if so, the parallel resistors are combined.
Step 2024, the host determines whether the resistance value of the resistor of the current resistor coupling is greater than or equal to the resistor threshold; if yes, the corresponding resistor is removed.
The resistance threshold may specifically be 1kΩ.
In a specific example, the effective resistance matrix between boundary points in the circuit formed by adjacent clusters can also be calculated by means of an effective resistance solving engine. The main resistor (resistor with smaller resistance) is selected, and the non-main resistor (resistor with larger resistance) is removed or combined to the adjacent main resistor.
It can be appreciated that the host may only perform decoupling processing on capacitive coupling between the sub-line units; or only the resistor coupling between the sub-line units is used for decoupling; the decoupling processing can be performed by capacitive coupling between the sub-line units and by resistive coupling between the sub-line units. The application is not particularly limited in this regard, but the latter is more effective, i.e., the interaction dimension between the scribes is lower, the error is smaller, and the analysis accuracy and efficiency are higher.
In step 203, the host maps the calculation tasks of at least two sub-line units to the corresponding slaves, respectively, so that the slaves construct a unit model for the corresponding sub-line units.
In the embodiment of the application, the slave can adopt a Krylov projection method, a moment matching method or a rational fitting method for the corresponding sub-line units to construct a unit model.
In the embodiment of the application, the method further comprises the following steps:
Step 401, the slave sets up a first network matrix of capacitance and resistance for the corresponding sub-line units by: 。
Wherein, A immittance matrix that is a resistive network of the sub-line units; /(I)A capacitive reactance matrix of a capacitive network of sub-line units; v is the internal voltage of the sub-line unit; /(I)Is the internal voltage vector of the sub-line unit; /(I)An internal current that is a sub-line unit; /(I)Port current for the sub-line unit; e is a topology matrix mapping ports of the sub-line units and all circuit nodes; /(I)Is the port voltage of the sub-line unit.
In step 402, the slave computer builds a unit model of the corresponding sub-line unit based on the first network matrix.
Specifically, since the internal information of the lower layer module is ignored in the upper layer circuit module, the current except the port is [ ]) Voltage (/ >)) The characteristics, other information, can be hidden during modeling to build a compact model that is small enough. The/>, is obtained by a model reduction method such as a Krylov projection method, a moment matching method or a rational fitting methodMatrix,/>The matrix is deformed to obtain a model which is far smaller than the size of the original netlist, and the model size is only related to the port number and the model order.
Further, step 402 may include the sub-steps of:
Step 4021, constructing solution space vector by slave And/>Wherein/>And/>Is an identity matrix due to/>Not square matrix, can be called/>Is/>Is a pseudo-inverse of (a).
In step 4022, the slave machine converts the first network matrix into a second network matrix of capacitance and resistance of the corresponding sub-line unit according to the solution space vector:。
Wherein, A immittance matrix of a resistance network of the sub-line unit; /(I)A capacitive reactance matrix of a capacitive network of the sub-line unit; /(I)Is the port voltage of the sub-line unit.
Specifically, taking Krylov projection as an example, a suitable projection matrix is usedA new solution space vector is formed so that the first network matrix of capacitive resistors can be rewritten into the second network matrix. The immittance matrix/>, of the resulting second network matrixCapacitive reactance matrix/>The dimension of the matrix is far smaller than the immittance matrix/>, of the first network matrixCapacitive reactance matrix/>And the dimension of the model is reduced.
In step 204, the host performs merging on the unit models corresponding to the sub-line units connected in a coupling manner, so that the corresponding slave mechanisms build a merging model; the corresponding slave calculates the working electric parameters of the power supply network line based on the merging model and the unit model outside the merging model in the power supply network line.
The operating electrical parameters may include, among other things, an operating voltage and an operating current of the power network line.
That is, the slave for constructing the merging model may adopt a method corresponding to the construction of the unit model, such as Krylov projection method, moment matching method, or rational fitting method, and perform merging processing with respect to the unit model corresponding to the coupled sub-line units as an object to construct the merging model. And then, the slave computer constructing the merging model is based on the corresponding merging model, and the slave computers constructing the unit models outside the merging model in the power supply network circuit are based on the corresponding unit models, so as to calculate the working electric parameters of the power supply network circuit.
In a specific example, as shown in FIG. 9, taking two of the unit models as an example, for a unit model 501 where there is coupling adjacently, a more compact upper layer model 500 including two unit models 501 can be formed by merging out internal nodes. The method for eliminating the internal node can refer to the modeling process of the unit model, only the characteristics of the necessary ports are reserved, and details are not repeated here. Each merging will eliminate a certain number of circuit nodes, and a sufficiently compact circuit model can be obtained finally, since the size of the model is only related to the number of ports and the model order.
Therefore, through rapid and reliable voltage drop analysis, the efficiency and the precision of the power circuit integrity analysis can be effectively improved, the method is suitable for a chip layout and wiring design scene, is not limited by the calculation amount of the power circuit integrity analysis, and has low calculation resource threshold.
In the embodiment of the application, the method further comprises the following steps: in response to receiving the client request instruction, the distributed computing platform deploys a computer from the power network analysis system to act as a host.
In the embodiment of the application, the method further comprises the step that after slicing and dividing, a host computer sends a unit calculation request instruction to a distributed calculation platform; in response to receiving the cell calculation request instruction, the distributed computing platform deploys at least two computers from the power network analysis system, acting as slaves in constructing the corresponding cell model.
In the embodiment of the application, the method further comprises the step that after merging, the host sends a merging calculation request instruction to the distributed calculation platform; in response to receiving the merge computation request instruction, the distributed computing platform deploys at least one computer from the power network analysis system, acting as a slave to construct a corresponding merge model.
The application will be further illustrated and described by means of a specific example.
In this particular embodiment, a power network analysis method based on a distributed computing platform includes the steps of:
In step 601, a computing request is sent to a Hadoop cloud platform by a client, and the Hadoop cloud platform distributes a computer from a large number of computing nodes as a host computer for computing resource planning and power network line scribing planning.
In step 602, the host adopts an aggregation algorithm, adds a virtual ground node, and implements the division of the power network line.
In step 603, the host requests computing resources required for the mapping stage unit computation from the Hadoop cloud platform.
And step 604, the Hadoop cloud platform allocates the slave machine as a calculation node, so that the slave machine completes calculation of the mapping stage, establishes a circuit matrix and acquires a total model of the diced circuit cluster.
Step 605, the host collects the calculation result of the mapping stage, and releases the calculation resource of the mapping stage.
In step 606, the host applies for computing resources required for the merging computation based on the line coupling.
In step 607, the hadoop cloud platform allocates the slave as a computing node, so that the slave completes the merging computation and the final computation of the working current and the working voltage of the power network line.
In step 608, the host releases the resources and logs off from the Hadoop cloud platform.
In summary, according to the power network analysis method based on the distributed computing platform of the embodiment of the application, the power network line is sliced and divided by the host to obtain at least two sub-line units; determining whether capacitive coupling or resistive coupling exists between the sub-line units through the host; if yes, decoupling the corresponding coupling; the calculation tasks of the sub-line units are respectively mapped to the slaves through the master, so that the slaves construct a unit model for the corresponding sub-line units; merging unit models of the sub-line units which are coupled and connected through a host computer so as to enable corresponding slave mechanisms to build a merging model; and calculating the working electric parameters of the power supply network line based on the merging model and a unit model outside the merging model in the power supply network line through the corresponding slave machine. Therefore, through rapid and reliable voltage drop analysis, the efficiency and the precision of the power circuit integrity analysis can be effectively improved, the method is suitable for a chip layout and wiring design scene, is not limited by the calculation amount of the power circuit integrity analysis, and has low calculation resource threshold.
Referring to fig. 1, a power network analysis system 100 provided by an embodiment of the present application includes a distributed computing platform 101, a host 102, and at least two slaves 103 serving as computing nodes.
A distributed computing platform 101 for allocating resources for power network analysis.
The host 102 is configured to slice and divide a power network line to obtain at least two sub-line units; wherein the electrical connection between the at least two sub-line units comprises at least one of no coupling, capacitive coupling and resistive coupling; and for determining whether there is capacitive coupling and/or resistive coupling between at least two sub-line elements; if yes, decoupling the corresponding coupling; and for mapping the computing tasks of at least two sub-line units onto respective slaves 103, respectively.
The slave 103 is used for constructing a unit model for the corresponding sub-line unit.
And the host 102 is used for merging the unit models corresponding to the coupled and connected sub-line units.
A slave machine 103 for constructing a merging model; the corresponding slave 103 also calculates the operating electrical parameters of the power network line based on the merging model and the element model outside the merging model in the power network line.
In the embodiment of the present application, the host 102 is specifically configured to: carrying out one-time slicing and dividing on a power supply network line to obtain at least two uncoupled sub-circuit units; wherein, there is no coupling connection between at least two non-coupling sub-circuit units; respectively obtaining analysis calculated amounts corresponding to at least two uncoupled sub-circuit units; responding to the analysis calculated amount of the uncoupled sub-circuit unit being larger than the processing capacity of a single computer, performing sub-slicing division on the corresponding uncoupled sub-circuit unit to obtain a sub-circuit unit; in response to the analysis computation of the uncoupled sub-circuit unit being less than or equal to the processing power of the single computer, the corresponding uncoupled sub-circuit unit is determined to be a sub-line unit.
In the embodiment of the present application, the host 102 is specifically configured to: configuring at least two grounding nodes for a power supply network line; and replacing the original coupling capacitor connected between the first power line and the second power line with two replacement capacitors with the two capacitance values twice that of the original coupling capacitor, wherein one replacement capacitor is connected between the first power line and one grounding node, and the other replacement capacitor is connected between the second power line and one grounding node.
In the embodiment of the present application, the host 102 is specifically configured to: the host 102 determines whether the resistance of the resistive coupling is parallel; if so, combining the parallel resistors; determining whether the resistance value of the resistor coupled by the current resistor is larger than or equal to a resistance threshold value; if yes, the corresponding resistor is removed.
In an embodiment of the present application, the distributed computing platform 101 is further configured to: in response to receiving the client request instruction, a computer is deployed from the power network analysis system to serve as the host 102.
In the embodiment of the present application, the host 102 is further configured to: after the slice division, a unit computation request instruction is transmitted to the distributed computing platform 101.
The distributed computing platform 101 is also for: in response to receiving the cell calculation request instruction, at least two computers are deployed from the power network analysis system to serve as slaves 103 that build respective cell models.
In the embodiment of the present application, the host 102 is further configured to: after the merging, a merging calculation request instruction is sent to the distributed computing platform 101.
The distributed computing platform 101 is also for: in response to receiving the merge computation request instruction, at least one computer is deployed from the power network analysis system as a slave 103 that builds a corresponding merge model.
In the embodiment of the present application, the slave 103 is specifically configured to: and constructing a unit model by adopting a Krylov projection method, a moment matching method or a rational fitting method for the corresponding sub-line units.
In the embodiment of the present application, the distributed computing platform 101 is a distributed system infrastructure cloud platform.
It should be noted that, the explanation of the power network analysis method based on the distributed computing platform 101 in the above embodiment is also applicable to the power network analysis system in the above embodiment, and will not be repeated here.
It should be understood that, although the steps in the flowcharts of the specification are shown in order as indicated by the arrows, these steps are not necessarily performed in order as indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly stated herein, and the steps may be executed in other orders. Moreover, at least a portion of the steps in the flowcharts may include a plurality of sub-steps or stages that are not necessarily performed at the same time, but may be performed at different times, the order in which the sub-steps or stages are performed is not necessarily sequential, and may be performed in turn or alternately with at least a portion of the sub-steps or stages of other steps or other steps.
It is noted that the specific values mentioned above are only for the purpose of illustrating the implementation of the present application in detail and should not be construed as limiting the present application. In other examples or embodiments or examples, other values may be selected according to the present application, without specific limitation.
Those of ordinary skill in the art will appreciate that: the above is only a preferred embodiment of the present application, and the present application is not limited thereto, but it is to be understood that the present application is described in detail with reference to the foregoing embodiments, and modifications and equivalents of some of the technical features described in the foregoing embodiments may be made by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.
Claims (10)
1. A power network analysis method based on a distributed computing platform, which is characterized in that the method is applied to a power network analysis system, wherein the system comprises the distributed computing platform, a host computer and at least two slave computers serving as computing nodes; the method may include the steps of,
The host machine performs slice division on the power supply network line to obtain at least two sub-line units; wherein the electrical connection between the at least two sub-line units includes at least one of no coupling, capacitive coupling, and resistive coupling;
The host determining whether the capacitive coupling and/or the resistive coupling exists between the at least two sub-line units; if yes, decoupling the corresponding coupling;
The host maps the calculation tasks of the at least two sub-line units to corresponding slaves respectively, so that the slaves construct a unit model for the corresponding sub-line units;
the host machine merges the unit models corresponding to the sub-line units which are coupled and connected, so that the corresponding slave machine constructs a merging model; and the corresponding slave machine calculates the working electric parameters of the power supply network line based on the merging model and a unit model outside the merging model in the power supply network line.
2. The method of claim 1, wherein the step of slicing the power network line by the host to obtain at least two sub-line units comprises:
the host machine performs one-time slicing division on the power supply network line to obtain at least two uncoupled sub-circuit units; wherein, there is no coupling connection between the said at least two non-coupling sub-circuit units;
The host computer respectively acquires analysis calculated amounts corresponding to the at least two uncoupled sub-circuit units;
Responding to the fact that the analysis calculated amount of the uncoupled sub-circuit unit is larger than the processing capacity of a single computer, the host machine carries out sub-slicing division on the corresponding uncoupled sub-circuit unit to obtain the sub-circuit unit;
In response to the analysis computation of the uncoupled sub-circuit unit being less than or equal to the processing power of the single computer, the host determines the corresponding uncoupled sub-circuit unit as the sub-line unit.
3. The method of claim 1, wherein said step of decoupling the respective couplings comprises,
Configuring at least two grounding nodes for the power supply network line;
And replacing the original coupling capacitance connected between the first power line and the second power line with two replacement capacitances with the two capacitance values twice that of the original coupling capacitance, wherein one replacement capacitance is connected between the first power line and one grounding node, and the other replacement capacitance is connected between the second power line and the one grounding node.
4. The method of claim 1, wherein said step of decoupling the respective couplings comprises,
The host determines whether the resistor coupled to the resistor has a parallel resistor; if so, combining the parallel resistors; and/or the number of the groups of groups,
The host determines whether the resistance value of the resistor coupled by the current resistor is larger than or equal to a resistor threshold value; if yes, the corresponding resistor is removed.
5. The method of claim 1, further comprising,
In response to receiving a client request instruction, the distributed computing platform deploys a computer from the power network analysis system to act as the host.
6. The method of claim 1, further comprising, after the slicing, the host sending a unit computation request instruction to the distributed computing platform;
In response to receiving the unit calculation request instruction, the distributed computing platform deploys at least two computers from the power network analysis system, acting as slaves in constructing the respective unit models.
7. The method of claim 1, further comprising,
After merging, the host sends a merging calculation request instruction to the distributed computing platform;
In response to receiving the merge computation request instruction, the distributed computing platform deploys at least one computer from the power network analysis system as a slave to construct the corresponding merge model.
8. The method of claim 1, wherein the slave machine constructs the cell model by Krylov projection, moment matching, or rational fitting of the corresponding sub-line cells.
9. The method of any of claims 1-8, wherein the distributed computing platform is a distributed system infrastructure cloud platform.
10. A power network analysis system based on a distributed computing platform, the system comprising the distributed computing platform, a master computer and at least two slave computers serving as computing nodes; wherein,
The distributed computing platform is used for analyzing and allocating resources for the power supply network;
The host is used for slicing and dividing the power supply network line to obtain at least two sub-line units; wherein the electrical connection between the at least two sub-line units includes at least one of no coupling, capacitive coupling, and resistive coupling; and for determining whether said capacitive coupling and/or said resistive coupling exists between said at least two sub-line elements; if yes, decoupling the corresponding coupling; the computing tasks of the at least two sub-line units are respectively mapped to corresponding slaves;
The slave is used for constructing a unit model for the corresponding sub-line unit;
the host is used for merging the unit models corresponding to the coupled sub-line units;
The slave machine is used for constructing a merging model; and the corresponding slave machine also calculates the working electric parameters of the power supply network line based on the merging model and a unit model outside the merging model in the power supply network line.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410580704.4A CN118171623A (en) | 2024-05-11 | 2024-05-11 | Power supply network analysis method and system based on distributed computing platform |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410580704.4A CN118171623A (en) | 2024-05-11 | 2024-05-11 | Power supply network analysis method and system based on distributed computing platform |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN118171623A true CN118171623A (en) | 2024-06-11 |
Family
ID=91353454
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202410580704.4A Pending CN118171623A (en) | 2024-05-11 | 2024-05-11 | Power supply network analysis method and system based on distributed computing platform |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN118171623A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5943507A (en) * | 1994-12-22 | 1999-08-24 | Texas Instruments Incorporated | Interrupt routing circuits, systems and methods |
| CN102037528A (en) * | 2008-03-20 | 2011-04-27 | 格瑞巴奇有限公司 | Shielded three-terminal flat-through EMI/energy dissipating filter |
| EP3503180A1 (en) * | 2017-12-22 | 2019-06-26 | Nagravision S.A. | A decoupling capacitor for an integrated circuit |
| US20220067264A1 (en) * | 2020-08-31 | 2022-03-03 | Changxin Memory Technologies, Inc. | Chip design method, design device, computer device and storage medium |
-
2024
- 2024-05-11 CN CN202410580704.4A patent/CN118171623A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5943507A (en) * | 1994-12-22 | 1999-08-24 | Texas Instruments Incorporated | Interrupt routing circuits, systems and methods |
| CN102037528A (en) * | 2008-03-20 | 2011-04-27 | 格瑞巴奇有限公司 | Shielded three-terminal flat-through EMI/energy dissipating filter |
| EP3503180A1 (en) * | 2017-12-22 | 2019-06-26 | Nagravision S.A. | A decoupling capacitor for an integrated circuit |
| US20220067264A1 (en) * | 2020-08-31 | 2022-03-03 | Changxin Memory Technologies, Inc. | Chip design method, design device, computer device and storage medium |
Non-Patent Citations (1)
| Title |
|---|
| 李鹏;丁承第;王成山;高菲;于浩;李海涛;黄小耘;: "基于多核心处理器的分布式发电微网系统暂态并行仿真方法", 中国电机工程学报, no. 16, 5 June 2013 (2013-06-05) * |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102306396B (en) | Three-dimensional entity model surface finite element mesh automatic generation method | |
| WO2003043057A2 (en) | Synthesis strategies based on the appropriate use of inductance effects | |
| CN112183015B (en) | Chip layout planning method for deep neural network | |
| WO2021227418A1 (en) | Task deployment method and device based on multi-board fpga heterogeneous system | |
| CN102637217B (en) | Large-scale integrated circuit wiring system based on cloud computing platform | |
| US8924913B1 (en) | Schematic display of connectivity in an integrated circuit design | |
| Huang et al. | Application-specific network-on-chip synthesis with topology-aware floorplanning | |
| CN112100971A (en) | Method for constructing hierarchical clock tree for integrated circuit | |
| CN115577664A (en) | Method and device for clock signal wiring of programmable logic device | |
| Halavar et al. | Power and performance analysis of 3D network-on-chip architectures | |
| WO2018080735A2 (en) | Method, apparatus and system for automatically performing end-to-end channel mapping for an interconnect | |
| CN114595651A (en) | Circuit dividing method for multi-FPGA simulation verification platform | |
| US20160364908A1 (en) | Analysis Model Creation Assistance System, Analysis Model Creation Assistance Device and Analysis Model Creation Assistance Program | |
| CN102955877B (en) | Method for generating TSV (through-silicon via) interconnection oriented three-dimensional integrated circuit clock topology structure | |
| CN116522854B (en) | Integrated circuit simulation model generation and calculation method and system of multi-power supply system | |
| Shen et al. | On embedding between 2D meshes of the same size | |
| EP4012573A1 (en) | Graph reconstruction method and apparatus | |
| Montone et al. | Wirelength driven floorplacement for FPGA-based partial reconfigurable systems | |
| CN118171623A (en) | Power supply network analysis method and system based on distributed computing platform | |
| CN105824995A (en) | Three-dimensional electromagnetic field model generation method based on physical layout | |
| Bao et al. | A high-performance and cost-efficient interconnection network for high-density servers | |
| CN103347098A (en) | Network enumeration method of Rapid IO bus interconnection system | |
| CN117034851A (en) | Region decomposition method based on pruning and graph segmentation optimization | |
| CN112232010A (en) | Programmable logic device grouping method and device | |
| CN109800468B (en) | Register retiming-based multi-pipeline sequential circuit boxing operation method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination |