CN118170392A - High compression ratio four-state value case grammar skip list realization method, electronic equipment and medium - Google Patents

Abstract

The invention relates to the technical field of computers, in particular to a high compression ratio four-state value case grammar skip list realization method, electronic equipment and a medium, wherein the method comprises the following steps of S1, obtaining a mapping relation set V1, a first identification sequence, a second identification sequence, max and min; s2, generating a case skip list with four-state values; step S3, executing S7 if VA appears 0 or 1 on bit a _i =0, or VA appears x or z on bit B _i =0, otherwise executing S4; s4, obtaining an offset value OF corresponding to the VA in a case jump table OF the four-state value; s5, if OF is more than or equal to 0 and less than or equal to X-1, executing S6, otherwise, executing S7; step S6, executing the jump table entry corresponding to the OF offset position OF the jump table with the four-state value case; step S7, jumping to G _X for execution. The invention reduces the time for realizing the four-state value case grammar and improves the system execution speed.

Description

High compression ratio four-state value case grammar skip list realization method, electronic equipment and medium

Technical Field

The present invention relates to the field of computer technologies, and in particular, to a method for implementing a high compression ratio four-state value case syntax skip list, an electronic device, and a medium.

Background

Hardware Description Languages (HDL) such as Verilog, system Verilog also exist in four-state data structures, namely 0,1, z and x, which also support case syntax. A case grammar will typically have one input value, multiple case matching branches, each matching a value. The program compares with a plurality of case matching branches in sequence according to the input value, when encountering the first matching branch, the program executes the operation sentence under the branch, then exits the case sentence, and executes the next sentence. When all matching branches and input values of the case grammar are in four states, the case sentence is subjected to four-state comparison. Typically case syntax requires that the input values be aligned one by one with the matching branches in order. However, when the number of cases is large and the branches on the match are relatively ordered later, the case grammar implementation is time-consuming, and the system execution speed is slow. Therefore, how to quickly locate the target case matching branch to be skipped, reduce the time for realizing the four-state value case grammar, and improve the system execution speed becomes a technical problem to be solved.

Disclosure of Invention

The invention aims to provide a high compression ratio four-state value case grammar skip list realization method, electronic equipment and medium, which can rapidly position a target case matching branch to be skipped, reduce the time for realizing the four-state value case grammar and improve the system execution speed.

According to a first aspect of the present invention, there is provided a method for implementing a high compression ratio four-state value case syntax skip list, including:

Step S1, traversing a to-be-processed case sentence, and acquiring a mapping relation set V1＝{(S₁,L₁),(S₂,L₂),...,(S_n,L_n),...,(S_N,L_N)}、 corresponding to the to-be-processed case sentence, a first identification sequence (A ₀,A₁,...,A_i,...,A_I), a second identification sequence (B ₀,B₁,...,B_i,...,B_I), a maximum value max of a case comparison item and a minimum value min of the case comparison item;

The method comprises the steps that a to-be-processed case statement comprises an input expression and a matching branch, the matching branch comprises an execution expression and at least one case comparison item, (S _n,L_n) is an nth mapping relation corresponding to the to-be-processed case statement, the value range of N is 1 to N, N is the total number of mapping relations, S _n is the nth execution expression in V1, L _n is a value list of the case comparison item corresponding to S _n, L _n comprises the value of at least one case comparison item, the to-be-processed case statement is a four-state value case statement, the case comparison item does not comprise a non-constant item, A _i is a first identifier corresponding to the ith bit of the case comparison item, B _i is a second identifier corresponding to the ith bit of the case comparison item, the value range of I is 0 to I, and the case comparison item shares I+1 bit; if the i bit of the case comparison item is 0 or 1, a _i =1, and if the i bit of the case comparison item is not 0 or 1, a _i =0; b _i =1 if x or z is present at the i-th bit of the case comparison term, and B _i =0 if x or z is not present at the i-th bit of the case comparison term;

The value of the case comparison item is a decimal value generated based on the case comparison item conversion, if A _i and B _i are equal to 1 in the conversion process, the ith bit is converted according to the quaternary system, otherwise, the ith bit is converted according to the binary system;

S2, generating a four-state value case jump table (G ₁,G₂,...,G_x,...,G_X) based on V1, V3, max and min;

Wherein G _x is the xth jump table item of the case jump table with four states, the value range of X is 1 to X, X is the total number of jump table items, x=max-min+2, if x+min-1 exists in one of L _n, setting G _x to S _n corresponding to L _n where x+min-1 exists, otherwise, if the case statement to be processed has a default statement DF, setting G _x to DF, if there is no DF, setting G _x to the next statement NE of the case statement to be processed;

Step S3, generating an input value VA to be processed based on the input expression of the case sentence to be processed, if VA appears 0 or 1 on the bit with a _i =0, or VA appears x or z on the bit with B _i =0, executing step S7, otherwise, executing step S4;

step S4, obtaining an offset value OF corresponding to the input value VA to be processed in a case skip list OF a four-state value;

step S5, if OF is more than or equal to 0 and less than or equal to X-1, executing step S6, otherwise, executing step S7;

Step S6, executing the jump table entry corresponding to the OF offset position OF the jump table with the four-state value case;

step S7, jumping to G _X for execution.

According to a second aspect of the present invention, there is provided an electronic device comprising: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being arranged to perform the method according to the first aspect of the invention.

According to a third aspect of the present invention there is provided a computer readable storage medium storing computer executable instructions for performing the method of the first aspect of the present invention.

Compared with the prior art, the invention has obvious advantages and beneficial effects. By means of the technical scheme, the high compression ratio four-state value case grammar skip list implementation method, the electronic equipment and the medium can achieve quite technical progress and practicality, and have wide industrial utilization value, and the method has the following beneficial effects:

According to the method, the four-state value case skip list with high compression ratio is constructed based on the mapping relation corresponding to the case statement, the first identification sequence, the second identification sequence, the maximum value max of the case comparison item and the minimum value min of the case comparison item, the target case matching branch to be skipped can be rapidly positioned based on the four-state value case skip list with high compression ratio, time for realizing the four-state value case grammar is shortened, and the system execution speed is improved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a flowchart of a method for implementing a high compression ratio four-state value case syntax skip list according to an embodiment of the present invention.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to fall within the scope of the invention.

The embodiment of the invention provides a high compression ratio four-state value case grammar skip list implementation method, which is shown in figure 1 and comprises the following steps:

Step S1, traversing a to-be-processed case sentence, and obtaining a mapping relation set V1＝{(S₁,L₁),(S₂,L₂),...,(S_n,L_n),...,(S_N,L_N)}、 corresponding to the to-be-processed case sentence, a first identification sequence (A ₀,A₁,...,A_i,...,A_I), a second identification sequence (B ₀,B₁,...,B_i,...,B_I), a maximum value max of a case comparison item and a minimum value min of the case comparison item.

The to-be-processed case statement comprises an input expression and a matching branch, wherein the matching branch comprises an execution expression and at least one case comparison item. (S _n,L_n) is the N-th mapping relation corresponding to the case statement to be processed, the value range of N is 1 to N, and N is the total number of the mapping relations. S _n is the nth execution expression in V1, L _n is a list of values of case comparison items corresponding to S _n, and L _n includes the value of at least one case comparison item.

The case statement to be processed is a four-state value case statement, namely each bit of the case comparison item is 0, 1, x or z, and it should be noted that x and z of the case comparison item respectively represent an x state and a z state and are not wild cards. In addition, the case comparison item does not contain a non-constant item, and if the case comparison item contains a non-constant item, the value of the case comparison item cannot be fixed and cannot be accurately realized by using a skip list, so the case comparison item does not contain a non-constant item.

A _i is a first identifier corresponding to the ith bit of the case comparison item, B _i is a second identifier corresponding to the ith bit of the case comparison item, the value range of I is 0 to I, and the case comparison item has I+1 bits; if the i bit of the case comparison item is 0 or 1, a _i =1, and if the i bit of the case comparison item is not 0 or 1, a _i =0; b _i =1 if x or z is present at the i-th bit of the case comparison term, and B _i =0 if x or z is not present at the i-th bit of the case comparison term; the value of the case comparison term is a decimal value generated based on the case comparison term conversion, if A _i and B _i are equal to 1 in the conversion process, the ith bit is converted into a quaternary value, otherwise, the ith bit is converted into a binary value. It should be noted that if each bit is directly converted according to quaternary system, in general, the value space of the quaternary data is twice that of the binary data in each bit, and when the bit is increased to N, the value space of the quaternary data will increase by 2 ^N times that of the binary data, and the value space of the quaternary data increases exponentially. According to the embodiment of the invention, through the first identification sequence (A ₀,A₁,...,A_i,...,A_I) and the second identification sequence (B ₀,B₁,...,B_i,...,B_I), the A _i and the B _i are equal to 1, the ith bit is converted according to the quaternary system, otherwise, the ith bit is converted according to the binary system, so that the value space compression with high compression ratio is realized, and the efficiency of the subsequent code compiling and running is improved. It should be noted that all the conversions involved in the embodiments of the present invention are performed in an unsigned form.

And S2, generating a four-state value case jump table (G ₁,G₂,...,G_x,...,G_X) based on V1, V3, max and min.

Wherein G _x is the xth jump table item of the case jump table with four states, X is the jump table item sequence number corresponding to G _x, the value range of X is 1 to X, X is the total number of jump table items, x=max-min+2, it should be noted that the jump table is continuous, and the total number of max-min+1 is between min and max, but it is necessary to construct max-min+2 jump table items, because it is necessary to set the corresponding jump table items under the condition that the matching is unsuccessful in the jump table. If x+min-1 exists in one of the L _n, setting G _x to S _n corresponding to L _n where x+min-1 exists, otherwise, if a default sentence DF exists in the case sentence to be processed, setting G _x to DF, and if DF does not exist, setting G _x to the next sentence NE of the case sentence to be processed.

Step S3, generating an input value VA to be processed based on the input expression of the case sentence to be processed, if VA appears 0 or 1 on the bit with a _i =0, or VA appears x or z on the bit with B _i =0, executing step S7, otherwise, executing step S4;

It should be noted that, by judging that VA appears 0 or 1 on the bit with a _i =0 or VA appears x or z on the bit with B _i =0, one layer of filtering can be performed, and some input values that need to jump to the subscript position of G _X can be directly determined, so that the execution of steps S4-S6 is avoided, useless calculation is reduced, and the overall execution efficiency is improved.

Step S4, obtaining an offset value OF corresponding to the input value VA to be processed in the case skip list OF the four-state value.

And S5, if OF is more than or equal to 0 and less than or equal to X-1, executing a step S6, otherwise, executing a step S7.

If the value OF OF is more than or equal to 0 and less than or equal to X-1, the value VA is between min and max, the corresponding jump table item OF the OF offset position OF the jump binary value case jump table is executed, if a corresponding execution statement exists, the corresponding execution statement is executed, and if the corresponding execution statement does not exist, the corresponding execution statement is executed according to an initial value KE. If not, it is indicated that the matching branch capable OF successfully matching cannot exist, and the execution OF the corresponding initial value KE is directly carried out by jumping to G _X.

And S6, executing the jump table entry corresponding to the OF offset position OF the jump table with the four-state value case.

Step S7, jumping to G _X for execution.

It should be noted that, in the embodiment of the invention, the target case matching branch to be skipped is quickly located based on the case skip list with four states, and the input values and the matching branches do not need to be compared one by one according to the sequence, so that the time for realizing the case grammar with four states is reduced, and the execution speed of the system is improved.

As an embodiment, the matching branches of the case statement to be processed include { C ₁,C₂,...,C_m,...,C_M }, where C _m is the M-th matching branch of the case statement to be processed, M has a value range from 1 to M, M is the total number of matching branches, M is greater than or equal to N, and it should be noted that, since the case statement traverses the matching branches sequentially, when the matching is successful, the case statement does not traverse further, and therefore, for the same case comparison term, only a mapping relationship needs to be established with the execution statement corresponding to the matching branch traversed first, and therefore ,M≥N.C_m＝{D₁ ^m,D₂ ^m,...,D_y ^m,...,D_f(m) ^m,E^m},D_y ^m is the y-th comparison term in C _m, y has a value range from 1 to f (M), f (M) is the total number of comparison terms corresponding to C _m, and E ^m is the execution expression corresponding to C _m.

As an embodiment, in the step S1, the obtaining the first identification sequence (a ₀,A₁,...,A_i,...,A_I) and the second identification sequence (B ₀,B₁,...,B_i,...,B_I) includes:

Step S11, setting the initial value of each item in the first identification sequence and the second identification sequence to 0, setting i=0, and executing step S12.

Step S12, if the ith bit is 0 or 1, step S13 is executed, and if the ith bit is x or z, step S14 is executed.

Step S13, if a _i =0, a _i =1 is set, step S15 is executed, and if a _i =1, step S15 is executed directly.

Step S14 is executed by setting B _i =1 if B _i =0, and step S15 is executed directly if B _i =1.

Step S15, if I < I, i=i+1 is set, and the process returns to step S12, and if i=i, (a ₀,A₁,...,A_i,...,A_I) and (B ₀,B₁,...,B_i,...,B_I) are generated.

The generation (a ₀,A₁,...,A_i,...,A_I) and (B ₀,B₁,...,B_i,...,B_I) in step S15 refers to the generation of the current (a ₀,A₁,...,A_i,...,A_I) and (B ₀,B₁,...,B_i,...,B_I) as the first identification sequence (a ₀,A₁,...,A_i,...,A_I) and the second identification sequence (B ₀,B₁,...,B_i,...,B_I) in the subsequent processing.

In step S1, obtaining the maximum value max of the comparison term and the minimum value min of the comparison term of the mapping relation set V1＝{(S₁,L₁),(S₂,L₂),...,(S_n,L_n),...,(S_N,L_N)}、case corresponding to the case statement to be processed includes:

Step C11, initially setting m=1, y=1, n=1, V1 is null, case comparison item set V2 is null, L _n is null, and step C12 is executed.

And C12, if A _i and B _i are equal to 1, converting the ith bit of D _y ^m according to quaternary system, otherwise, converting the ith bit of D _y ^m according to binary system, and generating a decimal number F _y ^m corresponding to D _y ^m.

And step C13, judging whether F _y ^m exists in the current V2, if not, adding F _y ^m into the V2 and L _n, executing the step C14, otherwise, directly executing the step C14.

Note that, if F _y ^m exists in V2, it is explained that the mapping relationship has been established based on F _y ^m, and it is not necessary to establish the mapping relationship for F _y ^m.

Step C14, if y < f (m), set y=y+1, return to step C12, if y=f (m) and current L _n is not empty, step C15 is performed, and if y=f (m) and current L _n is empty, step C16 is performed.

Step C15, based on the current L _n, generates (S _n,L_n), where S _n＝E^m, adds (S _n,L_n) to V1, then sets n=n+1, sets L _n to be empty, and performs step C16.

Step C16, if M < M, set m=m+1, y=1, return to step C12, and if m=m, determine the maximum value in the current V2 as max, and the minimum value as min, and generate V1.

The generation of V1 in step C16 refers to the generation of the current V1 as V1 in the subsequent process.

As an example ,D_y ^m＝(d_I ^ym,d_I-1 ^ym,....,d_i ^ym,...,d₀ ^ym),d_i ^ym is the value of bit I of D _y ^m, I ranges from 0 to I, D _y ^m shares bit i+1, said step C12 includes:

Step C121, initial setting i= 0,F _y ^m =0.

Step C122, setting F _y ^m＝F_y ^m+t×Qⁱ, wherein Q is the advance number corresponding to the i-1 th bit, ,Q＝w₀ ^ym×w₁ ^ym×...×w_j ^ym×...w_i ^ym,w_j ^ym is the system corresponding to the j-th bit of D _y ^m, and the value range of j is 1 to i; if a _i and B _i are equal to 1, when d _i ^ym is equal to 0 or 1, t=d _i ^ym,d_i ^ym =z, t=2, d _i ^ym =x, t=3; if A _i＝1,B_i is not equal to 1; if a _i＝1,B_i is not equal to 1, t=d _i ^ym; if a _i≠1,B_i =1, then when d _i ^ym =z, t=0, and when d _i ^ym =x, t=1;

Step C123, if I < I, set i=i+1, return to step C122, and if i=i, generate F _y ^m.

As an embodiment ,L_n＝{LU₁ ⁿ,LU₂ ⁿ,...,LU_z ⁿ,...,LU_g(n) ⁿ},LU_z ⁿ is the value of the z-th comparison term in L _n, the value of z ranges from 1 to g (n), and g (n) is the total number of comparison terms in L _n, and the step S2 includes:

step S21, determining X based on V1, max and min, x=max-min+2.

Step S22, if a default statement DF exists in the case statement to be processed, setting a default kf=df of the case jump table with four-state values, otherwise, obtaining a next statement NE of the case statement to be processed, setting kf=ne, initially setting each item of the case jump table with four-state values as KF, and initially setting n=1, z=1, and executing step S23.

It should be noted that, when the input value of the default statement DF is not successfully matched with the matching branch in the case statement to be processed, the statement needs to be executed. However, default sentences exist in some to-be-processed case sentences, default sentences do not exist in some to-be-processed case sentences, and when the default sentences do not exist, if an input value is not successfully matched with a matched branch in the to-be-processed case sentences, the next sentence of the to-be-processed case sentences needs to be executed.

Step S23, obtaining the corresponding item sequence number LG _z ⁿ,LG_z ⁿ＝LU_z ⁿ -min+1 of the LU _z ⁿ in the four-state value case skip list, and updating the LG _z ⁿ item in the four-state value case skip list to S _n.

It should be noted that, through step S23, a mapping relationship between each LU _z ⁿ and an entry sequence number in the case skip list with four-state values can be established, and the execution statement corresponding to LU _z ⁿ is updated to the corresponding skip list entry, so that the target case matching branch based on skip list skip can be implemented.

Step S24, if z < g (n), setting z=z+1, returning to step S23, and if z=g (n), executing step S35;

Step S25, if N < N, set n=n+1, and z=1, return to step S23, and if n=n, generate the case skip list with four state values.

It should be noted that if the number of case comparison terms is small, the efficiency of directly traversing to determine the target matching branch may be higher than the efficiency of first establishing the four-state value case skip table and then determining the target matching branch based on the four-state value case skip table. If the value distribution of the case comparison items is too sparse, the building of the four-state value case jump table consumes too much memory, so that resource waste is caused, that is, the advantage of building the jump table is not great under the condition that the number of the case comparison items is small or the value distribution of the case comparison items is too sparse. Therefore, before the four-state value case skip list is built, it may be determined whether to build the four-state value case skip list better than not, as an embodiment, the step S21 includes:

step S01, obtaining the number VC of case comparison items in V2, if VC is larger than a preset comparison item number threshold, executing step S02, otherwise, ending the flow.

Step S02, acquiring a value interval gn=max+min-1, acquiring sparsity r=gn/VC based on VC and GN, if R is smaller than a preset sparsity threshold, executing step S21, otherwise, ending the flow.

The comparison term number threshold and the sparseness threshold are specifically set according to specific application requirements.

As an embodiment, the step S4 includes:

Step S41, if A _i and B _i are equal to 1, converting the ith bit of VA according to quaternary system, otherwise, converting the ith bit of VA according to binary system, and generating a decimal number VB corresponding to VA;

It should be noted that, the step S41 is directly implemented in the same manner as the step C121-step C126, and will not be described herein.

Step S42, obtaining an offset value of=vb-min corresponding to VA in the case jump table pair.

It should be noted that some exemplary embodiments are described as a process or a method depicted as a flowchart. Although a flowchart depicts steps as a sequential process, many of the steps may be implemented in parallel, concurrently, or with other steps. Furthermore, the order of the steps may be rearranged. The process may be terminated when its operations are completed, but may have additional steps not included in the figures. The processes may correspond to methods, functions, procedures, subroutines, and the like.

The embodiment of the invention also provides electronic equipment, which comprises: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to perform the methods of embodiments of the present invention.

The embodiment of the invention also provides a computer readable storage medium, which stores computer executable instructions for executing the method according to the embodiment of the invention.

According to the method, the four-state value case skip list with high compression ratio is constructed based on the mapping relation corresponding to the case statement, the first identification sequence, the second identification sequence, the maximum value max of the case comparison item and the minimum value min of the case comparison item, the target case matching branch to be skipped can be rapidly positioned based on the four-state value case skip list with high compression ratio, time for realizing the four-state value case grammar is shortened, and the system execution speed is improved.

The present invention is not limited to the above-mentioned embodiments, but is intended to be limited to the following embodiments, and any modifications, equivalents and modifications can be made to the above-mentioned embodiments without departing from the scope of the invention.

Claims (8)

1. The method for realizing the high compression ratio four-state value case grammar skip list is characterized by comprising the following steps of:

Step S1, traversing a to-be-processed case sentence, and acquiring a mapping relation set V1＝{(S₁,L₁),(S₂,L₂),...,(S_n,L_n),...,(S_N,L_N)}、 corresponding to the to-be-processed case sentence, a first identification sequence (A ₀,A₁,...,A_i,...,A_I), a second identification sequence (B ₀,B₁,...,B_i,...,B_I), a maximum value max of a case comparison item and a minimum value min of the case comparison item;

The method comprises the steps that a to-be-processed case statement comprises an input expression and a matching branch, the matching branch comprises an execution expression and at least one case comparison item, (S _n,L_n) is an nth mapping relation corresponding to the to-be-processed case statement, the value range of N is 1 to N, N is the total number of mapping relations, S _n is the nth execution expression in V1, L _n is a value list of the case comparison item corresponding to S _n, L _n comprises the value of at least one case comparison item, the to-be-processed case statement is a four-state value case statement, the case comparison item does not comprise a non-constant item, A _i is a first identifier corresponding to the ith bit of the case comparison item, B _i is a second identifier corresponding to the ith bit of the case comparison item, the value range of I is 0 to I, and the case comparison item shares I+1 bit; if the i bit of the case comparison item is 0 or 1, a _i =1, and if the i bit of the case comparison item is not 0 or 1, a _i =0; b _i =1 if x or z is present at the i-th bit of the case comparison term, and B _i =0 if x or z is not present at the i-th bit of the case comparison term;

The value of the case comparison item is a decimal value generated based on the case comparison item conversion, if A _i and B _i are equal to 1 in the conversion process, the ith bit is converted according to the quaternary system, otherwise, the ith bit is converted according to the binary system;

S2, generating a four-state value case jump table (G ₁,G₂,...,G_x,...,G_X) based on V1, V3, max and min;

Wherein G _x is the xth jump table item of the case jump table with four states, the value range of X is 1 to X, X is the total number of jump table items, x=max-min+2, if x+min-1 exists in one of L _n, setting G _x to S _n corresponding to L _n where x+min-1 exists, otherwise, if the case statement to be processed has a default statement DF, setting G _x to DF, if there is no DF, setting G _x to the next statement NE of the case statement to be processed;

Step S3, generating an input value VA to be processed based on the input expression of the case sentence to be processed, if VA appears 0 or 1 on the bit with a _i =0, or VA appears x or z on the bit with B _i =0, executing step S7, otherwise, executing step S4;

step S4, obtaining an offset value OF corresponding to the input value VA to be processed in a case skip list OF a four-state value;

step S5, if OF is more than or equal to 0 and less than or equal to X-1, executing step S6, otherwise, executing step S7;

Step S6, executing the jump table entry corresponding to the OF offset position OF the jump table with the four-state value case;

step S7, jumping to G _X for execution.

2. The method of claim 1, wherein the step of determining the position of the substrate comprises,

The matching branches of the case statement to be processed comprise { C ₁,C₂,...,C_m,...,C_M }, wherein C _m is the M-th matching branch of the case statement to be processed, the value range of M is 1 to M, M is the total number ,M≥N,C_m＝{D₁ ^m,D₂ ^m,...,D_y ^m,...,D_f(m) ^m,E^m},D_y ^m of the matching branches and is the y-th comparison item in C _m, the value range of y is 1 to f (M), f (M) is the total number of comparison items corresponding to C _m, and E ^m is the execution expression corresponding to C _m.

3. The method of claim 2, wherein the step of determining the position of the substrate comprises,

In the step S1, a first identification sequence (a ₀,A₁,...,A_i,...,A_I) and a second identification sequence (B ₀,B₁,...,B_i,...,B_I) are acquired, including:

Step S11, setting the initial value of each item in the first identification sequence and the second identification sequence to 0, setting i=0, and executing step S12;

Step S12, if the ith bit is 0 or 1, executing step S13, and if the ith bit is x or z, executing step S14;

Step S13, if a _i =0, a _i =1 is set, step S15 is executed, and if a _i =1, step S15 is directly executed;

step S14, if B _i =0, setting B _i =1, executing step S15, and if B _i =1, directly executing step S15;

Step S15, if I < I, i=i+1 is set, and the process returns to step S12, and if i=i, (a ₀,A₁,...,A_i,...,A_I) and (B ₀,B₁,...,B_i,...,B_I) are generated.

4. The method of claim 2, wherein the step of determining the position of the substrate comprises,

In the step S1, obtaining a maximum value max of a comparison term and a minimum value min of a comparison term of the mapping relation set V1＝{(S₁,L₁),(S₂,L₂),...,(S_n,L_n),...,(S_N,L_N)}、case corresponding to the case statement to be processed, including:

step C11, initially setting m=1, y=1, n=1, V1 is empty, the case comparison item set V2 is empty, and L _n is empty, and executing step C12;

Step C12, if A _i and B _i are equal to 1, converting the ith bit of D _y ^m according to quaternary system, otherwise converting the ith bit of D _y ^m according to binary system, and generating a decimal number F _y ^m corresponding to D _y ^m;

Step C13, judging whether F _y ^m exists in the current V2, if not, adding F _y ^m into the V2 and L _n, executing the step C14, otherwise, directly executing the step C14;

Step C14, if y < f (m), setting y=y+1, returning to step C12, if y=f (m) and current L _n is not empty, step C15 is performed, and if y=f (m) and current L _n is empty, step C16 is performed;

Step C15, generating (S _n,L_n) based on the current L _n, wherein S _n＝E^m, adding (S _n,L_n) to V1, then setting n=n+1, setting L _n to be empty, and executing step C16;

step C16, if M < M, set m=m+1, y=1, return to step C12, and if m=m, determine the maximum value in the current V2 as max, and the minimum value as min, and generate V1.

5. The method of claim 4, wherein the step of determining the position of the first electrode is performed,

D_y ^m＝(d_I ^ym,d_I-1 ^ym,....,d_i ^ym,...,d₀ ^ym),d_i ^ym For the value of the ith bit of D _y ^m, the value range of I is 0 to I, D _y ^m shares the i+1 bits, and the step C12 includes:

Step C121, initially setting i= 0,F _y ^m =0;

Step C122, setting F _y ^m＝F_y ^m+t×Qⁱ, wherein Q is the advance number corresponding to the i-1 th bit, ,Q＝w₀ ^ym×w₁ ^ym×...×w_j ^ym×...w_i ^ym,w_j ^ym is the system corresponding to the j-th bit of D _y ^m, and the value range of j is 1 to i; if a _i and B _i are equal to 1, when d _i ^ym is equal to 0 or 1, t=d _i ^ym,d_i ^ym =z, t=2, d _i ^ym =x, t=3; if A _i＝1,B_i is not equal to 1; if a _i＝1,B_i is not equal to 1, t=d _i ^ym; if a _i≠1,B_i =1, then when d _i ^ym =z, t=0, and when d _i ^ym =x, t=1;

Step C123, if I < I, set i=i+1, return to step C122, and if i=i, generate F _y ^m.

6. The method of claim 2, wherein the step of determining the position of the substrate comprises,

The step S4 includes:

Step S41, if A _i and B _i are equal to 1, converting the ith bit of VA according to quaternary system, otherwise, converting the ith bit of VA according to binary system, and generating a decimal number VB corresponding to VA;

Step S42, obtaining an offset value of=vb-min corresponding to VA in the case jump table pair.

7. An electronic device, comprising:

At least one processor;

And a memory communicatively coupled to the at least one processor;

wherein the memory stores instructions executable by the at least one processor, the instructions being arranged to perform the method of any of the preceding claims 1-6.

8. A computer readable storage medium, characterized in that computer executable instructions are stored for performing the method of any of the preceding claims 1-6.