CN118160027A

CN118160027A - Display device and electronic apparatus

Info

Publication number: CN118160027A
Application number: CN202280067164.9A
Authority: CN
Inventors: 木村肇; 井上达则
Original assignee: Semiconductor Energy Laboratory Co Ltd
Current assignee: Semiconductor Energy Laboratory Co Ltd
Priority date: 2021-10-27
Filing date: 2022-10-14
Publication date: 2024-06-07

Abstract

Provided is a display device with high display quality. One embodiment of the present invention is a display device including pixels and a circuit. The pixel includes a light emitting device, a driving transistor, first to fourth switches, and a first capacitor. In addition, the circuit includes a fifth switch, a sixth switch, and a second capacitor. The gate of the driving transistor is electrically connected to the first terminal of the first switch, the first terminal of the second switch, and the first terminal of the first capacitor, one of the source and the drain of the driving transistor is electrically connected to the second terminal of the first capacitor, the first terminal of the fourth switch, and the anode of the light emitting device, and the other of the source and the drain of the driving transistor is electrically connected to the second terminal of the second switch and the first terminal of the third switch. The second terminal of the first switch is electrically connected to the first terminal of the second capacitor, and the first terminal of the fifth switch is electrically connected to the first terminal of the sixth switch and the second terminal of the second capacitor.

Description

Display device and electronic apparatus

Technical Field

One embodiment of the present invention relates to a display device and an electronic apparatus.

One embodiment of the present invention is not limited to the above-described technical field. The technical field of the invention disclosed in the present specification and the like relates to an object, a driving method, or a manufacturing method. Furthermore, one embodiment of the present invention relates to a process, machine, product, or composition (composition of matter). Specifically, examples of the technical field of one embodiment of the present invention disclosed in the present specification include a semiconductor device, a display device, a liquid crystal display device, a light emitting device, a power storage device, an image pickup device, a storage device, a signal processing device, a processor, an electronic device, a system, a driving method thereof, a manufacturing method thereof, and an inspection method thereof.

Background

In recent years, various improvements have been made in display devices including electronic devices for XR (Extended reality) such as VR (virtual reality) and AR (augmented reality) or Cross reality, mobile phones such as smartphones, tablet information terminals, and notebook PCs (personal computers). For example, a display device having high screen resolution, high color reproducibility (NTSC ratio), small driving circuit, and low power consumption has been developed.

In particular, by increasing the pixel density (sharpness) and color reproducibility of the display device, the display image can be made clear, and the sense of reality can be improved. Further, patent document 1 discloses a display device having a high-definition display device with a high number of pixels including a light-emitting device made of an organic EL (Electroluminescence) material.

[ Prior Art literature ]

[ Patent literature ]

[ Patent document 1] International patent application publication No. 2019/220278

Disclosure of Invention

Technical problem to be solved by the invention

In particular, by improving the definition of a display device including a light-emitting device including an organic EL material, the area of a region (light-emitting surface) where the light-emitting device is formed becomes small. When the area of the region (light emitting surface) of the light emitting device becomes small, the amount of current required for light emission of the light emitting device becomes small, but the allowable amount of current also becomes small. That is, when the definition of the display apparatus of the light emitting device is improved, the range of the amount of current that can flow through the light emitting device is narrowed, so that fine control of the amount of current is required when adjusting the luminance of the light emitting device.

An object of one embodiment of the present invention is to provide a display apparatus capable of finely controlling an amount of current flowing through a light emitting device. Another object of one embodiment of the present invention is to provide a display device with high definition. Another object of one embodiment of the present invention is to provide a display device with high display quality. Another object of one embodiment of the present invention is to provide a novel display device. Another object of one embodiment of the present invention is to provide an electronic apparatus including the display device.

Note that the object of one embodiment of the present invention is not limited to the above object. The above objects do not prevent the existence of other objects. Other objects refer to objects not mentioned in this section which will be described later. Those skilled in the art can derive and appropriately extract the objects not mentioned in this section from the description of the specification, drawings, and the like. One embodiment of the present invention achieves at least one of the above objects and other objects. Moreover, an embodiment of the present invention does not necessarily need to achieve all of the above objects and other objects.

Means for solving the technical problems

(1)

One embodiment of the present invention is a display device including a pixel and a circuit. The pixel includes a light emitting device, a driving transistor, a first switch, a second switch, a third switch, a fourth switch, and a first capacitor. In addition, the circuit includes a fifth switch, a sixth switch, and a second capacitor. The gate of the driving transistor is electrically connected to the first terminal of the first switch, the first terminal of the second switch, and the first terminal of the first capacitor, one of the source and the drain of the driving transistor is electrically connected to the second terminal of the first capacitor, the first terminal of the fourth switch, and the anode of the light emitting device, and the other of the source and the drain of the driving transistor is electrically connected to the second terminal of the second switch and the first terminal of the third switch. In addition, the second terminal of the first switch is electrically connected to the first terminal of the second capacitor. The first terminal of the fifth switch is electrically connected to the first terminal of the sixth switch and the second terminal of the second capacitor.

(2)

In the above (1), one embodiment of the present invention may have the following structure: the first switch includes an n-channel type first transistor, the second switch includes an n-channel type second transistor, the third switch includes an n-channel type third transistor, and the fourth switch includes an n-channel type fourth transistor. It is particularly preferred that one of the source and the drain of the first transistor is electrically connected to the first terminal of the first switch and the other of the source and the drain of the first transistor is electrically connected to the second terminal of the first switch. In addition, it is preferable that one of a source and a drain of the second transistor is electrically connected to the first terminal of the second switch, and the other of the source and the drain of the second transistor is electrically connected to the second terminal of the second switch. In addition, it is preferable that one of a source and a drain of the third transistor is electrically connected to a first terminal of the third switch, and the other of the source and the drain of the third transistor is electrically connected to a second terminal of the third switch. In addition, it is preferable that one of a source and a drain of the fourth transistor is electrically connected to the first terminal of the fourth switch, and the other of the source and the drain of the fourth transistor is electrically connected to the second terminal of the fourth switch.

(3)

Further, one embodiment of the present invention is a display device including pixels and circuits and having a structure different from the structure (1) described above. The pixel includes a light emitting device, a driving transistor, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a first capacitor, and a third capacitor. In addition, the circuit includes a sixth switch, a seventh switch, an eighth switch, and a second capacitor. In addition, the driving transistor comprises a first grid electrode and a second grid electrode. The first gate of the driving transistor is electrically connected to the first terminal of the first switch, the first terminal of the second switch, and the first terminal of the first capacitor, and one of the source and the drain of the driving transistor is electrically connected to the second terminal of the first capacitor, the first terminal of the third capacitor, the second terminal of the second switch, the first terminal of the third switch, and the first terminal of the fourth switch, and the second gate of the driving transistor is electrically connected to the second terminal of the third capacitor and the first terminal of the fifth switch. In addition, a second terminal of the third switch is electrically connected to an anode of the light emitting device. The second terminal of the first switch is electrically connected to the first terminal of the second capacitor and the first terminal of the eighth switch. The first terminal of the sixth switch is electrically connected to the first terminal of the seventh switch and the second terminal of the second capacitor.

(4)

In the above (3), one embodiment of the present invention may have the following structure: the first switch includes an n-channel type first transistor, the second switch includes an n-channel type second transistor, the third switch includes an n-channel type third transistor, the fourth switch includes an n-channel type fourth transistor, and the fifth switch includes an n-channel type fifth transistor. It is particularly preferred that one of the source and the drain of the first transistor is electrically connected to the first terminal of the first switch and the other of the source and the drain of the first transistor is electrically connected to the second terminal of the first switch. In addition, it is preferable that one of a source and a drain of the second transistor is electrically connected to the first terminal of the second switch, and the other of the source and the drain of the second transistor is electrically connected to the second terminal of the second switch. In addition, it is preferable that one of a source and a drain of the third transistor is electrically connected to a first terminal of the third switch, and the other of the source and the drain of the third transistor is electrically connected to a second terminal of the third switch. In addition, it is preferable that one of a source and a drain of the fourth transistor is electrically connected to the first terminal of the fourth switch, and the other of the source and the drain of the fourth transistor is electrically connected to the second terminal of the fourth switch. In addition, it is preferable that one of a source and a drain of the fifth transistor is electrically connected to the first terminal of the fifth switch, and the other of the source and the drain of the fifth transistor is electrically connected to the second terminal of the fifth switch.

(5)

Further, one embodiment of the present invention is a display device including pixels and circuits and having a structure different from the structures (1) and (3). The pixel includes a light emitting device, a driving transistor, a first switch, a third switch, a fourth switch, a fifth switch, a first capacitor, and a third capacitor. In addition, the circuit includes a sixth switch, a seventh switch, an eighth switch, and a second capacitor. In addition, the driving transistor comprises a first grid electrode and a second grid electrode. The first gate of the driving transistor is electrically connected to the first terminal of the first switch and the first terminal of the first capacitor, one of the source and the drain of the driving transistor is electrically connected to the second terminal of the first capacitor, the first terminal of the third switch and the first terminal of the fourth switch, and the second gate of the driving transistor is electrically connected to the second terminal of the third capacitor and the first terminal of the fifth switch. In addition, a second terminal of the third switch is electrically connected to an anode of the light emitting device. The second terminal of the first switch is electrically connected to the first terminal of the second capacitor and the first terminal of the eighth switch. The first terminal of the sixth switch is electrically connected to the first terminal of the seventh switch and the second terminal of the second capacitor.

(6)

In the above (5), one embodiment of the present invention may have the following structure: the first switch includes an n-channel type first transistor, the third switch includes an n-channel type third transistor, the fourth switch includes an n-channel type fourth transistor, and the fifth switch includes an n-channel type fifth transistor. It is particularly preferred that one of the source and the drain of the first transistor is electrically connected to the first terminal of the first switch and the other of the source and the drain of the first transistor is electrically connected to the second terminal of the first switch. In addition, it is preferable that one of a source and a drain of the third transistor is electrically connected to a first terminal of the third switch, and the other of the source and the drain of the third transistor is electrically connected to a second terminal of the third switch. In addition, it is preferable that one of a source and a drain of the fourth transistor is electrically connected to the first terminal of the fourth switch, and the other of the source and the drain of the fourth transistor is electrically connected to the second terminal of the fourth switch. In addition, it is preferable that one of a source and a drain of the fifth transistor is electrically connected to the first terminal of the fifth switch, and the other of the source and the drain of the fifth transistor is electrically connected to the second terminal of the fifth switch.

(7)

One embodiment of the present invention is a display device including a pixel and a circuit. The pixel includes a light emitting device, a driving transistor, a first switch, a second switch, a third switch, a fourth switch, a first capacitor, and a second capacitor. In addition, the circuit comprises a fifth switch and a sixth switch. The gate of the driving transistor is electrically connected to the first terminal of the first switch, the first terminal of the second switch, and the first terminal of the first capacitor, one of the source and the drain of the driving transistor is electrically connected to the second terminal of the first capacitor, the first terminal of the fourth switch, and the anode of the light emitting device, and the other of the source and the drain of the driving transistor is electrically connected to the second terminal of the second switch and the first terminal of the third switch. In addition, the second terminal of the first switch is electrically connected to the first terminal of the second capacitor. The first terminal of the fifth switch is electrically connected to the first terminal of the sixth switch and the second terminal of the second capacitor.

(8)

Further, one embodiment of the present invention is a display device including pixels and a circuit and having a structure different from the structure (7). The pixel includes a light emitting device, a driving transistor, a first switch, a second switch, a third switch, a fourth switch, a first capacitor, and a second capacitor. In addition, the circuit comprises a fifth switch and a sixth switch. The gate of the driving transistor is electrically connected to the first terminal of the second switch, the first terminal of the first capacitor, and the first terminal of the second capacitor, one of the source and the drain of the driving transistor is electrically connected to the second terminal of the first capacitor, the first terminal of the fourth switch, and the anode of the light emitting device, and the other of the source and the drain of the driving transistor is electrically connected to the second terminal of the second switch and the first terminal of the third switch. In addition, a second terminal of the second capacitor is electrically connected to the first terminal of the first switch. The first terminal of the fifth switch is electrically connected to the first terminal of the sixth switch and the second terminal of the first switch.

(9)

Further, one embodiment of the present invention is a display device including pixels and circuits and having a structure different from the structures (7) and (8). The pixel includes a light emitting device, a driving transistor, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a first capacitor, and a second capacitor. In addition, the circuit includes a sixth switch. The gate of the driving transistor is electrically connected to the first terminal of the second switch, the first terminal of the first capacitor, and the first terminal of the second capacitor, one of the source and the drain of the driving transistor is electrically connected to the second terminal of the first capacitor, the first terminal of the fourth switch, and the anode of the light emitting device, and the other of the source and the drain of the driving transistor is electrically connected to the second terminal of the second switch and the first terminal of the third switch. The second terminal of the second capacitor is electrically connected to the first terminal of the first switch and the first terminal of the fifth switch. In addition, the first terminal of the sixth switch is electrically connected to the second terminal of the first switch.

(10)

Further, one embodiment of the present invention is a display device including a pixel and a driver circuit. The pixel includes a light emitting device, a driving transistor, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a first capacitor, and a second capacitor. The gate of the driving transistor is electrically connected to the first terminal of the second switch, the first terminal of the first capacitor, and the first terminal of the second capacitor, one of the source and the drain of the driving transistor is electrically connected to the second terminal of the first capacitor, the first terminal of the fourth switch, and the anode of the light emitting device, and the other of the source and the drain of the driving transistor is electrically connected to the second terminal of the second switch and the first terminal of the third switch. The second terminal of the second capacitor is electrically connected to the first terminal of the first switch and the first terminal of the fifth switch. In addition, the driving circuit is electrically connected to the second terminal of the first switch. In addition, the driving circuit has a function of transmitting an image signal to the second terminal of the first switch.

(11)

In addition, in any one of the above (7) to (10), one embodiment of the present invention may have the following structure: the first switch includes an n-channel type first transistor, the second switch includes an n-channel type second transistor, the third switch includes an n-channel type third transistor, and the fourth switch includes an n-channel type fourth transistor. It is particularly preferred that one of the source and the drain of the first transistor is electrically connected to the first terminal of the first switch and the other of the source and the drain of the first transistor is electrically connected to the second terminal of the first switch. In addition, it is preferable that one of a source and a drain of the second transistor is electrically connected to the first terminal of the second switch, and the other of the source and the drain of the second transistor is electrically connected to the second terminal of the second switch. In addition, it is preferable that one of a source and a drain of the third transistor is electrically connected to a first terminal of the third switch, and the other of the source and the drain of the third transistor is electrically connected to a second terminal of the third switch. In addition, it is preferable that one of a source and a drain of the fourth transistor is electrically connected to the first terminal of the fourth switch, and the other of the source and the drain of the fourth transistor is electrically connected to the second terminal of the fourth switch.

(12)

Further, one embodiment of the present invention is a display device including pixels and circuits and having a structure different from the structures (7) to (9) described above. The pixel includes a light emitting device, a driving transistor, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, an eighth switch, a first capacitor, a second capacitor, and a third capacitor. In addition, the circuit includes a sixth switch and a seventh switch. In addition, the driving transistor comprises a first grid electrode and a second grid electrode. The first gate of the driving transistor is electrically connected to the first terminal of the first switch, the first terminal of the second switch, the first terminal of the eighth switch, and the first terminal of the first capacitor, and one of the source and the drain of the driving transistor is electrically connected to the second terminal of the first capacitor, the first terminal of the third capacitor, the second terminal of the second switch, the first terminal of the third switch, and the first terminal of the fourth switch, and the second gate of the driving transistor is electrically connected to the second terminal of the third capacitor and the first terminal of the fifth switch. In addition, a second terminal of the third switch is electrically connected to an anode of the light emitting device. In addition, the second terminal of the first switch is electrically connected to the first terminal of the second capacitor. The second terminal of the second capacitor is electrically connected to the first terminal of the sixth switch and the first terminal of the seventh switch.

(13)

Further, one embodiment of the present invention is a display device including pixels and circuits and having a structure different from the structures (7) to (9) and (12) described above. The pixel includes a light emitting device, a driving transistor, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, an eighth switch, a first capacitor, a second capacitor, and a third capacitor. In addition, the circuit includes a sixth switch and a seventh switch. In addition, the driving transistor comprises a first grid electrode and a second grid electrode. The first gate of the driving transistor is electrically connected to the first terminal of the second switch, the first terminal of the eighth switch, the first terminal of the first capacitor, and the first terminal of the second capacitor, and one of the source and the drain of the driving transistor is electrically connected to the second terminal of the first capacitor, the first terminal of the third capacitor, the second terminal of the second switch, the first terminal of the third switch, and the first terminal of the fourth switch, and the second gate of the driving transistor is electrically connected to the second terminal of the third capacitor and the first terminal of the fifth switch. In addition, a second terminal of the third switch is electrically connected to an anode of the light emitting device. In addition, a second terminal of the second capacitor is electrically connected to the first terminal of the first switch. The second terminal of the first switch is electrically connected to the first terminal of the sixth switch and the first terminal of the seventh switch.

(14)

Further, one embodiment of the present invention is a display device including pixels and circuits and having a structure different from the structures (7) to (9), (12) and (13). The pixel includes a light emitting device, a driving transistor, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, an eighth switch, a first capacitor, a second capacitor, and a third capacitor. In addition, the circuit includes a seventh switch. In addition, the driving transistor comprises a first grid electrode and a second grid electrode. The first gate of the driving transistor is electrically connected to the first terminal of the second switch, the first terminal of the eighth switch, the first terminal of the first capacitor, and the first terminal of the second capacitor, and one of the source and the drain of the driving transistor is electrically connected to the second terminal of the first capacitor, the first terminal of the third capacitor, the second terminal of the second switch, the first terminal of the third switch, and the first terminal of the fourth switch, and the second gate of the driving transistor is electrically connected to the second terminal of the third capacitor and the first terminal of the fifth switch. In addition, a second terminal of the third switch is electrically connected to an anode of the light emitting device. The second terminal of the second capacitor is electrically connected to the first terminal of the first switch and the first terminal of the sixth switch. In addition, the second terminal of the first switch is electrically connected to the first terminal of the seventh switch.

(15)

Further, one embodiment of the present invention is a display device including a pixel and a driver circuit and having a structure different from the structure (10) described above. The pixel includes a light emitting device, a driving transistor, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, an eighth switch, a first capacitor, a second capacitor, and a third capacitor. In addition, the driving transistor comprises a first grid electrode and a second grid electrode. The first gate of the driving transistor is electrically connected to the first terminal of the second switch, the first terminal of the eighth switch, the first terminal of the first capacitor, and the first terminal of the second capacitor, and one of the source and the drain of the driving transistor is electrically connected to the second terminal of the first capacitor, the first terminal of the third capacitor, the second terminal of the second switch, the first terminal of the third switch, and the first terminal of the fourth switch, and the second gate of the driving transistor is electrically connected to the second terminal of the third capacitor and the first terminal of the fifth switch. In addition, a second terminal of the third switch is electrically connected to an anode of the light emitting device. The second terminal of the second capacitor is electrically connected to the first terminal of the first switch and the first terminal of the sixth switch. In addition, the driving circuit is electrically connected to the second terminal of the first switch. In addition, the driving circuit has a function of transmitting an image signal to the second terminal of the first switch.

(16)

In addition, in any one of the above (12) to (15), one embodiment of the present invention may have the following structure: the first switch includes an n-channel type first transistor, the second switch includes an n-channel type second transistor, the third switch includes an n-channel type third transistor, the fourth switch includes an n-channel type fourth transistor, and the fifth switch includes an n-channel type fifth transistor. It is particularly preferred that one of the source and the drain of the first transistor is electrically connected to the first terminal of the first switch and the other of the source and the drain of the first transistor is electrically connected to the second terminal of the first switch. In addition, it is preferable that one of a source and a drain of the second transistor is electrically connected to the first terminal of the second switch, and the other of the source and the drain of the second transistor is electrically connected to the second terminal of the second switch. In addition, it is preferable that one of a source and a drain of the third transistor is electrically connected to a first terminal of the third switch, and the other of the source and the drain of the third transistor is electrically connected to a second terminal of the third switch. In addition, it is preferable that one of a source and a drain of the fourth transistor is electrically connected to the first terminal of the fourth switch, and the other of the source and the drain of the fourth transistor is electrically connected to the second terminal of the fourth switch. In addition, it is preferable that one of a source and a drain of the fifth transistor is electrically connected to the first terminal of the fifth switch, and the other of the source and the drain of the fifth transistor is electrically connected to the second terminal of the fifth switch.

(17)

In addition, in the above (1) to (16), one embodiment of the present invention may have a structure in which the light-emitting device includes an organic EL device.

(18)

Further, one embodiment of the present invention is an electronic device including the display device of (17) and a housing.

Effects of the invention

According to one embodiment of the present invention, a display apparatus capable of finely controlling an amount of current flowing through a light emitting device can be provided. Further, according to one embodiment of the present invention, a display device with high definition can be provided. Further, according to one embodiment of the present invention, a display device with high display quality can be provided. Further, according to an embodiment of the present invention, a novel display device can be provided. Further, according to an embodiment of the present invention, an electronic apparatus including the display device described above can be provided.

Note that the effect of one embodiment of the present invention is not limited to the above-described effect. The above effects do not prevent the presence of other effects. Other effects refer to effects not mentioned in this section, which will be described later. Those skilled in the art can derive and appropriately extract effects not mentioned in this section from the descriptions of the specification, drawings, and the like. In addition, one embodiment of the present invention has at least one of the above effects and other effects. Therefore, according to the embodiment of the present invention, the above-described effects may not be achieved in some cases.

Drawings

Fig. 1 is a block diagram showing a structural example of a display device.

Fig. 2 is a circuit diagram showing a structural example of the display device.

Fig. 3A and 3B are timing charts showing an operation example of the display device.

Fig. 4A to 4C are diagrams showing a relationship between an image data signal input to a circuit and a potential of an image data signal output from the circuit.

Fig. 5 is a timing chart showing an operation example of the display device.

Fig. 6A and 6B are plan views showing layout examples of circuits.

Fig. 7 is a plan view showing an example of the layout of the circuit.

Fig. 8A to 8C are circuit diagrams showing a structural example of a pixel included in the display device.

Fig. 9 is a circuit diagram showing a structural example of the display device.

Fig. 10 is a circuit diagram showing a structural example of the display device.

Fig. 11 is a circuit diagram showing a structural example of the display device.

Fig. 12 is a circuit diagram showing a structural example of the display device.

Fig. 13 is a circuit diagram showing a configuration example of the display device.

Fig. 14 is a circuit diagram showing a structural example of the display device.

Fig. 15 is a circuit diagram showing a configuration example of the display device.

Fig. 16 is a timing chart showing an operation example of the display device.

Fig. 17 is a circuit diagram showing a configuration example of the display device.

Fig. 18A to 18C are timing charts showing operation examples of the display device.

Fig. 19A to 19C are diagrams showing a relationship between an image data signal input to a circuit and a potential of an image data signal output from the circuit.

Fig. 20 is a plan view showing an example of the layout of the circuit.

Fig. 21 is a circuit diagram showing a configuration example of the display device.

Fig. 22 is a circuit diagram showing a configuration example of the display device.

Fig. 23A to 23D are circuit diagrams showing structural examples of circuits included in the display device.

Fig. 24 is a circuit diagram showing a configuration example of the display device.

Fig. 25 is a circuit diagram showing a configuration example of the display device.

Fig. 26 is a circuit diagram showing a configuration example of the display device.

Fig. 27 is a circuit diagram showing a configuration example of the display device.

Fig. 28 is a circuit diagram showing a configuration example of the display device.

Fig. 29 is a circuit diagram showing a configuration example of the display device.

Fig. 30 is a circuit diagram showing a structural example of the display device.

Fig. 31 is a timing chart showing an operation example of the display device.

Fig. 32A to 32C are schematic sectional views showing structural examples of the display device.

Fig. 33A is a schematic plan view showing an example of a display portion of the display device, and fig. 33B is a schematic plan view showing an example of a driving circuit region of the display device.

Fig. 34A and 34B are schematic plan views showing examples of the structure of the display device.

Fig. 35A and 35B are block diagrams showing a configuration example of the display device.

Fig. 36 is a schematic sectional view showing a structural example of the display device.

Fig. 37A to 37C are schematic sectional views showing regions of a part of a structural example of the display device.

Fig. 38 is a schematic sectional view showing a structural example of the display device.

Fig. 39 is a schematic sectional view showing a structural example of the display device.

Fig. 40 is a schematic sectional view showing a structural example of the display device.

Fig. 41 is a schematic cross-sectional view showing a structural example of the display device.

Fig. 42 is a schematic cross-sectional view showing a structural example of the display device.

Fig. 43A is a schematic cross-sectional view showing a structural example of the display device, and fig. 43B and 43C are cross-sectional views showing structural examples of the transistor.

Fig. 44 is a schematic sectional view showing a structural example of the display device.

Fig. 45 is a schematic sectional view showing a structural example of the display device.

Fig. 46 is a schematic sectional view showing a structural example of the display device.

Fig. 47A is a schematic sectional view showing a structural example of the display device, and fig. 47B is a schematic sectional view showing a structural example of the light emitting device.

Fig. 48 is a schematic sectional view showing a structural example of the display device.

Fig. 49A to 49D are schematic sectional views showing structural examples of the LED package.

Fig. 50A and 50B are schematic plan views showing structural examples of the LED package.

Fig. 51A is a schematic cross-sectional view showing a structural example of a display device, and fig. 51B is a schematic cross-sectional view showing a substrate included in the display device and a structural example of a light-emitting diode on the substrate.

Fig. 52A to 52F are diagrams showing structural examples of the light emitting device.

Fig. 53A to 53C are diagrams showing structural examples of the light emitting device.

Fig. 54A is a circuit diagram showing a structural example of a pixel circuit included in the display device, and fig. 54B is a perspective view showing a structural example of a pixel circuit included in the display device.

Fig. 55A to 55G are plan views showing one example of a pixel.

Fig. 56A to 56F are plan views showing one example of a pixel.

Fig. 57A to 57H are plan views showing one example of a pixel.

Fig. 58A to 58D are plan views showing one example of a pixel.

Fig. 59A to 59G are plan views showing one example of a pixel.

Fig. 60A is a schematic plan view showing a structural example of a transistor, and fig. 60B and 60C are schematic sectional views showing a structural example of a transistor.

Fig. 61A and 61B are diagrams showing examples of the structure of the display module.

Fig. 62A to 62F are diagrams showing structural examples of the electronic apparatus.

Fig. 63A to 63D are diagrams showing structural examples of the electronic apparatus.

Fig. 64A to 64C are diagrams showing structural examples of the electronic apparatus.

Fig. 65A to 65H are diagrams showing structural examples of the electronic apparatus.

Detailed Description

In this specification and the like, a semiconductor device refers to a device using semiconductor characteristics, a circuit including semiconductor elements (e.g., a transistor, a diode, and a photodiode), and a device including the circuit. The semiconductor device refers to all devices that can function by utilizing semiconductor characteristics. Examples of the semiconductor device include an integrated circuit, a chip including the integrated circuit, and an electronic component in which the chip is housed in a package. Further, for example, a memory device, a display device, a light emitting device, a lighting device, and an electronic apparatus are semiconductor devices themselves or include semiconductor devices.

Note that, in the present specification and the like, when the description is "X and Y are connected", it means that the following is disclosed in the present specification and the like: the X is electrically connected with Y; the case where X and Y are functionally linked; and the case where X is directly connected to Y. Accordingly, the connection relationships shown in the drawings and the description are not limited, and other connection relationships are also described in the drawings and the description. X, Y are objects (e.g., devices, elements, circuits, wires, electrodes, terminals, conductive films, or layers).

As an example of the case where X and Y are electrically connected, one or more elements capable of electrically connecting X and Y (for example, a switch, a transistor, a capacitive element, an inductor, a resistor, a diode, a display device, a light emitting device, and a load) may be connected between X and Y. In addition, the switch has a function of controlling on or off. In other words, whether or not to flow the current is controlled by placing the switch in a conductive state (on state) or a nonconductive state (off state).

In the case where both the element and the power supply line (for example, VDD (high power supply potential), VSS (low power supply potential), GND (ground potential), or wiring to which a desired potential is applied) are arranged between X and Y, it cannot be said that X and Y are electrically connected. In the case where only the power supply line is arranged between X and Y, there is no other element between X and Y, and thus it can be said that X and Y are directly connected. Therefore, when only the power supply line is arranged between X and Y, it can be said that "X and Y are electrically connected". However, in the case where both the element and the power supply line are arranged between X and Y, it can be said that X is electrically connected to the power supply line (through the element) and Y is electrically connected to the power supply line, and it cannot be said that X is electrically connected to Y. In addition, in the case where the gate and the source of the transistor are interposed between X and Y, it cannot be said that X and Y are electrically connected. In addition, in the case where the gate and the drain of the transistor are interposed between X and Y, it cannot be said that X and Y are electrically connected. That is, in the case of a transistor, in which the drain and the source of the transistor are interposed between X and Y, it can be said that X and Y are electrically connected. In the case where a capacitive element is arranged between X and Y, it may be said that X and Y are electrically connected, or it may be said that X and Y are electrically connected. For example, in the configuration of a digital circuit or a logic circuit, when a capacitive element is arranged between X and Y, it may not be said that X and Y are electrically connected. On the other hand, for example, in the case where a capacitive element is arranged between X and Y in the structure of an analog circuit, X and Y may be electrically connected.

As an example of the case where X and Y are functionally connected, for example, one or more circuits (for example, a logic circuit (for example, an inverter, a NAND circuit, a NOR circuit), a signal conversion circuit (for example, a digital-analog conversion circuit, an analog-digital conversion circuit, a gamma correction circuit), a potential level conversion circuit (for example, a power supply circuit such as a voltage boosting circuit, a voltage reducing circuit, or a level shift circuit that changes the potential level of a signal), a voltage source, a current source, a switching circuit, an amplifying circuit (for example, a circuit that can increase the amplitude or the current amount of a signal, an operational amplifier, a differential amplifying circuit, a source follower circuit, a buffer circuit), a signal generation circuit, a memory circuit, or a control circuit) that can functionally connect X and Y may be connected between X and Y. Note that, for example, even if another circuit is interposed between X and Y, when a signal output from X is transmitted to Y, it can be said that X and Y are functionally connected.

Further, when explicitly stated as "X and Y are electrically connected", the following is included: the case where X and Y are electrically connected (in other words, the case where X and Y are connected with other elements or other circuits interposed therebetween); and the case where X and Y are directly connected (in other words, the case where X and Y are connected without other elements or other circuits interposed therebetween).

For example, "X, Y" may be expressed as that the source of the transistor (which may be referred to as one of the first terminal and the second terminal) and the drain of the transistor (which may be referred to as the other of the first terminal and the second terminal) are electrically connected to each other, and X, the source of the transistor, and the drain of the transistor are electrically connected to Y in this order. Or it may be expressed as "the source of the transistor is electrically connected to X, the drain of the transistor is electrically connected to Y, and X, the source of the transistor, and the drain of the transistor are electrically connected in turn to Y". Or "X is electrically connected to Y through the source and drain of the transistor, and X, the source of the transistor, the drain of the transistor, and Y are sequentially connected to each other". By defining the connection order in the circuit configuration using the same expression method as those of these examples, the source and drain of the transistor can be distinguished and the technical range can be determined. Note that this expression method is an example, and is not limited to the above expression method. Here, X and Y are objects (e.g., devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, or the like).

In addition, even if the individual components are electrically connected to each other in the circuit diagram, one component may have functions of a plurality of components. For example, when a part of the wiring is used as an electrode, one conductive film functions as both the wiring and the electrode. Accordingly, the term "electrically connected" in the present specification also includes a case where such a single conductive film has functions of a plurality of constituent elements.

In this specification and the like, the "resistor" may be, for example, a circuit element having a resistance value higher than 0Ω or a wiring having a resistance value higher than 0Ω. Therefore, in this specification and the like, the "resistor" includes a wiring having a resistance value, a transistor, a diode, or a coil in which a current flows between a source and a drain. Thus, a "resistor" may sometimes be referred to as a "resistance," load, "or" region having a resistance value. In contrast, the "resistance", "load" or "region having a resistance value" may be sometimes referred to as a "resistor". The resistance value is, for example, preferably 1mΩ to 10Ω, more preferably 5mΩ to 5Ω, and still more preferably 10mΩ to 1Ω. For example, it may be 1 Ω or more and 1×10 ⁹ Ω or less.

In this specification and the like, the "capacitance element" may be, for example, a circuit element having a capacitance value higher than 0F, a region of a wiring having a capacitance value higher than 0F, a parasitic capacitance, or a gate capacitance of a transistor. In addition, the "capacitive element", "parasitic capacitance", or "gate capacitance" or the like may be sometimes referred to as "capacitance". In contrast, the "capacitance" may be sometimes referred to as a "capacitive element", "parasitic capacitance", or "gate capacitance". Further, the "capacitor" (including a three-terminal or more "capacitor") has a structure including an insulator and a pair of conductors sandwiching the insulator. Thus, a "pair of conductors" of a "capacitor" may be interchangeably referred to as a "pair of electrodes", "a" pair of conductive regions "," a "pair of regions" or a "pair of terminals". Further, "one of the pair of terminals" and "the other of the pair of terminals" are sometimes referred to as a first terminal and a second terminal, respectively. The capacitance value may be, for example, 0.05fF or more and 10pF or less. For example, the temperature may be 1pF or more and 10. Mu.F or less.

In this specification and the like, a transistor includes three terminals of a gate, a source, and a drain. The gate is used as a control terminal to control the on state of the transistor. The two terminals serving as the source or the drain are input-output terminals of the transistor. Depending on the conductivity type of the transistor (n-channel type or p-channel type) and the level of the potential applied to the three terminals of the transistor, one of the two input-output terminals serves as a source and the other serves as a drain. Therefore, in this specification and the like, the source and the drain may be exchanged with each other. In this specification and the like, when describing a connection relation of a transistor, expressions of "one of a source and a drain" (a first electrode or a first terminal), "the other of the source and the drain" (a second electrode or a second terminal) are used. In addition, depending on the structure of the transistor, a back gate may be included in addition to the three terminals. In this case, in this specification or the like, one of the gate and the back gate of the transistor is sometimes referred to as a first gate, and the other of the gate and the back gate of the transistor is sometimes referred to as a second gate. In the same transistor, the "gate" and the "back gate" may be exchanged with each other. In the case where the transistor includes three or more gates, each gate may be referred to as a first gate, a second gate, a third gate, or the like in this specification.

For example, in this specification or the like, a transistor having a multi-gate structure with two or more gate electrodes can be used as an example of the transistor. When the multi-gate structure is adopted, the channel formation regions are connected in series, so that a plurality of transistors are connected in series. Therefore, by adopting the multi-gate structure, off-state current can be reduced, and the voltage resistance of the transistor can be improved (reliability is improved). Or by using a multi-gate structure, when the transistor is operated in a saturation region, even if the drain-source voltage is changed, the drain-source current is not changed much, so that a voltage-current characteristic with a flat inclination angle can be obtained. When the voltage-current characteristic of the flat inclination angle is utilized, an ideal current source circuit or an active load having an extremely high resistance value can be realized. As a result, a differential circuit, a current mirror circuit, or the like having good characteristics can be realized.

In the present specification and the like, circuit elements such as a "light emitting device" and a "light receiving device" may have polarities called an "anode" and a "cathode". With regard to the "light emitting device", the "light emitting device" may sometimes be caused to emit light by applying a forward bias (positive potential with respect to the "cathode" is applied to the "anode"). In addition, regarding the "light receiving device", a current is sometimes generated between the "anode" - "cathode" by applying a zero bias or a reverse bias (negative potential with respect to the "cathode" is applied to the "anode") and irradiating light to the "light receiving device". As described above, the "anode" and the "cathode" may be used as input/output terminals in circuit elements such as the "light emitting device" and the "light receiving device". In this specification and the like, the "anode" and the "cathode" in the circuit element such as the "light emitting device" and the "light receiving device" are sometimes referred to as terminals (first terminal, second terminal, and the like), respectively. For example, one of the "anode" and the "cathode" is sometimes referred to as a first terminal, and the other of the "anode" and the "cathode" is sometimes referred to as a second terminal.

Further, the circuit diagram shows a case of one circuit element, sometimes including a case where the circuit element has a plurality of circuit elements. For example, the circuit diagram shows a case where one resistor includes a case where two or more resistors are electrically connected in series. Further, for example, the circuit diagram shows a case where one capacitor includes a case where two or more capacitors are electrically connected in parallel. Further, for example, the circuit diagram shows a case where one transistor includes a case where two or more transistors are electrically connected in series and gates of the respective transistors are electrically connected to each other. Also, for example, the circuit diagram shows a case of one switch including a case where the switch has two or more transistors, the two or more transistors are electrically connected in series or in parallel, and gates of the respective transistors are electrically connected to each other.

In this specification, the node may be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, or the like depending on a circuit configuration, a device configuration, or the like. In addition, terminals, wirings, and the like may also be referred to as nodes.

In this specification and the like, the "voltage" and the "potential" may be appropriately exchanged. The "voltage" refers to a potential difference from a reference potential, and may be referred to as a "potential" when the reference potential is a ground potential (ground potential), for example. The ground potential does not necessarily mean 0V. The potential is relatively, and the potential applied to the wiring, the potential applied to the circuit, or the like, the potential output from the circuit, or the like also changes according to the change in the reference potential.

In this specification, the "high-level potential" and the "low-level potential" do not mean specific potentials. For example, in the case where both wirings are denoted as "wirings for applying high-level potentials", the high-level potentials applied by the two wirings may be different from each other. Also, in the case where both wirings are denoted as "wirings for applying low-level potentials", the low-level potentials applied by the two wirings may be different from each other.

The "current" refers to a movement phenomenon (conduction) of electric charges, and for example, the description of "conduction of a positively charged body" may be replaced with the description of "conduction of a negatively charged body in the opposite direction. Therefore, in the present specification and the like, unless otherwise specified, "current" refers to a phenomenon of movement (conduction) of charge when carriers move. Examples of carriers include electrons, holes, anions, cations, and complex ions, and the carriers vary depending on the system (for example, semiconductor, metal, electrolyte, and vacuum) through which the current flows. The "direction of current" in the wiring and the like is a direction in which positively charged carriers move, and is described as a positive current amount. In other words, the direction of movement of the negatively charged carriers is opposite to the current direction, and is described as a negative current flow. Therefore, in the present specification and the like, unless otherwise specified, the description of "current flowing from element a to element B" may be replaced with the description of "current flowing from element B to element a" with respect to the positive and negative of the current (or the direction of the current). Note that the description of "input current to element a" may be replaced with the description of "output current from element a".

In the present specification and the like, ordinal numbers such as "first", "second", "third", and the like are added to avoid confusion of constituent elements. Therefore, the ordinal words do not limit the number of constituent elements. The ordinal words do not limit the order of the constituent elements. For example, a constituent element to which "first" is attached in one of the embodiments of the present specification and the like may be attached "second" in other embodiments or claims. For example, in the present specification and the like, the constituent element referred to as "first" in one embodiment may be omitted in other embodiments or claims.

In this specification and the like, for convenience, terms such as "upper" and "lower" are used to indicate arrangement, and positional relationships of constituent elements are sometimes described with reference to the drawings. In addition, the positional relationship of the constituent elements is appropriately changed according to the direction in which the respective structures are described. Therefore, the words and phrases described in the specification and the like are not limited, and words and phrases may be appropriately replaced according to circumstances. For example, in the expression "an insulator located on the top surface of an electrical conductor", the direction of the drawing shown is rotated 180 degrees, and may also be referred to as "an insulator located on the bottom surface of an electrical conductor".

The term "upper" or "lower" is not limited to the case where the positional relationship of the constituent elements is "directly above" or "directly below" and is in direct contact. For example, in the expression "electrode B on insulating layer a", electrode B is not necessarily formed in direct contact with insulating layer a, and other components may be included between insulating layer a and electrode B. In addition, for example, in the case of the expression "electrode B above insulating layer a", electrode B is not necessarily formed in direct contact with insulating layer a, and other components may be included between insulating layer a and electrode B. In addition, for example, in the case of the expression "electrode B under the insulating layer a", the electrode B is not necessarily formed in direct contact with the insulating layer a, and other components may be included between the insulating layer a and the electrode B.

In the present specification and the like, terms such as "row" and "column" may be used to describe components arranged in a matrix and their positional relationship. In addition, the positional relationship of the constituent elements is appropriately changed according to the direction in which the respective structures are described. Therefore, the words and phrases described in the specification and the like are not limited, and words and phrases may be appropriately replaced according to circumstances. For example, in the expression of "row direction", the direction of the drawing shown is rotated by 90 degrees, and may be referred to as "column direction".

In the present specification and the like, wirings electrically connecting components arranged in a matrix may be provided so as to extend in the row direction or the column direction. For example, in the present specification and the like, when the description is given of "the wiring a extends in the row direction", the wiring a may extend in the column direction. In the case where the description of "the wiring a extends in the column direction" or the like is given, the wiring a may extend in the row direction. That is, the direction in which the wirings electrically connected to the components arranged in a matrix extend is not limited to the direction described in the specification or the like, and may be a row direction or a column direction.

In this specification and the like, words such as "film" and "layer" may be exchanged with each other according to circumstances. For example, the "conductive layer" may be replaced with the "conductive film" in some cases. In addition, the "insulating film" may be converted into an "insulating layer" in some cases. In addition, other words and phrases may be used instead of words and phrases such as "film" and "layer" depending on the situation or situation. For example, a "conductive layer" or a "conductive film" may be sometimes converted into a "conductor". In addition, for example, the "insulating layer" and the "insulating film" may be sometimes converted into "insulator".

Note that, in this specification and the like, the expressions of "electrode", "wiring", and "terminal" do not functionally define the constituent elements thereof. For example, an "electrode" is sometimes used as part of a "wiring" and vice versa. The term "electrode" or "wiring" includes a case where a plurality of "electrodes" or "wirings" are integrally formed. Further, for example, a "terminal" is sometimes used as a part of a "wiring" or an "electrode", and vice versa. The term "terminal" includes a case where one or more selected from the group consisting of "electrode", "wiring" and "terminal" are integrally formed. Thus, for example, an "electrode" may be part of a "wiring" or "terminal", e.g., a "terminal" may be part of a "wiring" or "electrode". The words such as "electrode", "wiring", and "terminal" may be replaced with words such as "region" in some cases.

In this specification and the like, words such as "wiring", "signal line", and "power line" may be exchanged with each other according to circumstances or conditions. For example, the "wiring" may be sometimes converted into the "signal line". In addition, for example, the "wiring" may be sometimes converted into the "power line" or the like. Vice versa, it is sometimes possible to convert "signal lines" or "power lines" or the like into "wirings". The "power line" and the like may be sometimes converted into a "signal line". Vice versa, it is sometimes possible to convert "signal lines" or the like into "power lines". In addition, depending on the situation or the state, the "potential" applied to the wirings may be converted into a "signal" from each other. Vice versa, it is sometimes possible to transform a "signal" into a "potential".

In this specification and the like, a method of operating a semiconductor device may be described with reference to a timing chart. The timing chart used in the present specification and the like shows an ideal operation example, and is not limited to the period shown in the timing chart, the magnitude of a signal (e.g., potential or current), and the timing unless otherwise specified. In the timing chart of the present specification or the like, the magnitude and timing of a signal (e.g., potential or current) input to each wiring (including a node) in the timing chart may be changed according to the situation. For example, even if two periods of equal intervals are shown in the timing chart, the lengths of the two periods are sometimes different. For example, even if one of the two periods is shown to be long and the other period is shown to be short, the lengths of the two periods may be the same, or one of the two periods may be made short and the other period may be made long.

In the present specification and the like, metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), and oxide semiconductors (Oxide Semiconductor, which may also be simply referred to as OS), and the like. For example, in the case where a channel formation region of a transistor includes a metal oxide, the metal oxide is sometimes referred to as an oxide semiconductor. In other words, when a metal oxide can form a channel formation region of a transistor having at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide can be referred to as a metal oxide semiconductor (metal oxide semiconductor). Further, an OS transistor may also be referred to as a transistor including a metal oxide or an oxide semiconductor.

In this specification and the like, a metal oxide containing nitrogen is sometimes referred to as a metal oxide (metal oxide). In addition, the metal oxide containing nitrogen may also be referred to as metal oxynitride (metal oxynitride).

In this specification and the like, the impurities of the semiconductor refer to substances other than the main component constituting the semiconductor layer. For example, an element having a concentration of less than 0.1 atomic% is an impurity. When impurities are contained, for example, one or both of an increase in defect state density, a decrease in carrier mobility, and a decrease in crystallinity in a semiconductor may occur. When the semiconductor is an oxide semiconductor, examples of impurities that change the characteristics of the semiconductor include group 1 elements, group 2 elements, group 13 elements, group 14 elements, group 15 elements, and transition metals other than the main component, and particularly, examples thereof include hydrogen (contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Specifically, when the semiconductor is a silicon layer, examples of impurities that change the characteristics of the semiconductor include group 1 elements, group 2 elements, group 13 elements, and group 15 elements (note that oxygen and hydrogen are not included).

In this specification and the like, a switch means an element having a function of controlling whether or not to flow a current by changing to a conductive state (on state) or a nonconductive state (off state). Or a switch refers to an element having a function of selecting and switching a current path. Therefore, the switch may include two or three or more terminals through which current flows in addition to the control terminal. As an example of the switch, an electric switch, a mechanical switch, or the like may be used. In other words, the switch is not limited to a specific element as long as the current can be controlled.

Examples of the electric switch include a transistor (e.g., a bipolar transistor or a MOS transistor), a diode (e.g., a PN diode, a PIN diode, a schottky diode, a MIM (metal-insulator-metal) diode, a MIS (metal-insulator-semiconductor) diode, and a diode-connected transistor), a logic circuit combining these elements, or the like. When a transistor is used as a switch, the "on state" of the transistor refers to, for example, a state in which a source electrode and a drain electrode of the transistor are electrically shorted, a state in which a current can flow between the source electrode and the drain electrode, or the like. The "non-conductive state" of the transistor means a state in which the source electrode and the drain electrode of the transistor are electrically disconnected. When only a transistor is used as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

As an example of the mechanical switch, a switch using MEMS (micro electro mechanical system) technology can be given. The switch has a mechanically movable electrode and operates by moving the electrode to control conduction and non-conduction.

In addition, in this specification and the like, a device manufactured using a metal mask or FMM (FINE METAL MASK, high-definition metal mask) is sometimes referred to as a MM (Metal Mask) -structured device. In this specification and the like, a device manufactured without using a metal mask or an FMM is sometimes referred to as a device having a MML (Metal Mask Less) structure.

In this specification and the like, a structure in which light-emitting layers are formed or applied to light-emitting devices of respective colors (here, blue (B), green (G), and red (R)) is sometimes referred to as a SBS (Side By Side) structure. In this specification and the like, a light-emitting device that can emit white light is sometimes referred to as a white light-emitting device. The white light emitting device can realize a display device that displays in full color by combining with a colored layer (e.g., a color filter).

Further, the light emitting device can be roughly classified into a single structure and a series structure. The single structure device preferably has the following structure: a light emitting unit is included between a pair of electrodes, and the light emitting unit includes one or more light emitting layers. When white light emission is obtained by using two light-emitting layers, the light-emitting layers may be selected so that the respective light-emitting colors of the two light-emitting layers are in a complementary relationship. For example, by placing the light emission color of the first light emission layer and the light emission color of the second light emission layer in a complementary relationship, a structure that emits light in white on the whole light emitting device can be obtained. In the case where white light emission is obtained by using three or more light-emitting layers, the light-emitting colors of the three or more light-emitting layers may be combined to obtain a structure in which the light-emitting device emits white light as a whole.

The device of the tandem structure preferably has the following structure: two or more light emitting units are included between a pair of electrodes, and each light emitting unit includes one or more light emitting layers. In order to obtain white light emission, a structure may be employed in which light emitted from the light-emitting layers of the plurality of light-emitting units is combined to obtain white light emission. Note that the structure to obtain white light emission is the same as that in the single structure. In the device having the tandem structure, an intermediate layer such as a charge generation layer is preferably provided between the plurality of light emitting cells.

Further, in the case of comparing the above-described white light emitting device (single structure or tandem structure) and the light emitting device of the SBS structure, the power consumption of the light emitting device of the SBS structure can be made lower than that of the white light emitting device. A light emitting device employing an SBS structure is preferable in the case where power consumption reduction is desired. On the other hand, a manufacturing process of the white light emitting device is simpler than that of the SBS structure light emitting device, whereby manufacturing cost can be reduced or manufacturing yield can be improved, so that it is preferable.

In the present specification, "parallel" refers to a state in which two straight lines form an angle of-10 ° or more and 10 ° or less. Therefore, the state in which the angle is-5 ° or more and 5 ° or less is also included. "substantially parallel" means a state in which two straight lines form an angle of-30 DEG or more and 30 DEG or less. The term "vertical" refers to a state in which an angle formed by two straight lines is 80 ° or more and 100 ° or less. Therefore, the state in which the angle is 85 ° or more and 95 ° or less is also included. The term "substantially perpendicular" means a state in which an angle formed by two straight lines is 60 ° or more and 120 ° or less.

In this specification and the like, the configuration shown in each embodiment may be appropriately combined with the configuration shown in the other embodiment to constitute one embodiment of the present invention. Further, when a plurality of structural examples are shown in one embodiment, these structural examples may be appropriately combined.

Furthermore, the content (or a part thereof) described in one embodiment may be applied/combined/replaced with at least one of the other content (or a part thereof) described in the embodiment and the content (or a part thereof) described in another embodiment or embodiments.

Note that the content described in the embodiments refers to the content described in the various drawings or the content described in the specification.

Further, by combining a drawing (or a part thereof) shown in a certain embodiment with at least one drawing among other parts of the drawing, other drawings (or a part thereof) shown in the embodiment, and drawings (or a part thereof) shown in another or more other embodiments, more drawings can be constituted.

Embodiments described in the present specification are described with reference to the drawings. It is noted that one of ordinary skill in the art can easily understand the fact that the embodiments may be implemented in a plurality of different forms, and that the manner and details thereof may be changed into various forms without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments. Note that in the structure of the invention in the embodiment, the same reference numerals are commonly used in different drawings to denote the same parts or parts having the same functions, and repetitive description thereof may be omitted. In the perspective view and the like, some of the constituent elements may be omitted for clarity.

In the drawings of the present specification, the structure according to each embodiment is sometimes described with reference to a plan view. The top view is a view showing a state where the surface (cross section) of the structure is cut in the parallel direction. In addition, by using hidden lines (for example, broken lines) in a plan view, a positional relationship of a plurality of components included in the structure or a relationship in which the plurality of components are superimposed can be shown. In this specification and the like, the "top view" may also be referred to as a "projection view", "plan view" or "bottom view". In addition, a plane (cross section) other than a plane (cross section) when the structure is cut in the parallel direction when the structure is cut in a direction different from the parallel direction may be referred to as a plan view, depending on the situation.

In the drawings of the present specification, a structure according to each embodiment is sometimes described with reference to a cross-sectional view. The cross-sectional illustration is, for example, a view showing a state where the surface (cross section) of the structure is cut in the vertical direction. In this specification and the like, the "cross-sectional view" may also be referred to as a "front view" or a "side view". In addition, a plane (cross section) other than a plane (cross section) when the structure is cut in the vertical direction when the structure is cut in a direction different from the vertical direction may be referred to as a cross section according to circumstances.

In this specification and the like, when the same symbol is used for a plurality of elements and it is necessary to distinguish them, a symbol for identification such as "_1", "[ n ]," [ m, n ] "may be added to the symbol. In the drawings, when symbols for identification such as "_1", "[ n ]," [ m, n ] "are added to the symbols, if it is not necessary to distinguish them in the present specification, the symbols for identification may not be added.

In the drawings of the present specification, the size, thickness of layers, or regions are sometimes exaggerated for clarity of illustration. Accordingly, the present invention is not limited to the dimensions in the drawings. In addition, in the drawings, ideal examples are schematically shown, and therefore the present invention is not limited to the shapes, numerical values, and the like shown in the drawings. For example, unevenness of signals, voltages, or currents due to noise, timing deviation, or the like may be included.

(Embodiment 1)

In this embodiment, a display device according to an embodiment of the present invention is described.

< Structural example of display device 1>

Fig. 1 shows a display device according to an embodiment of the present invention. The display device DSP0 includes, for example, a pixel array ALP, a row driving circuit RWD, and a column driving circuit CLM.

The pixel array ALP includes, for example, m×n (m is an integer of 1 or more, and n is an integer of 1 or more) pixels PX. In particular, each pixel PX is arranged in a matrix of m rows and n columns in the pixel array ALP. In fig. 1, as a plurality of pixels PX, pixels PX [1,1], pixels PX [ m,1], pixels PX [1, n ], pixels PX [ m, n ], and pixels PX [ i, j ] (i is an integer of 1 to m inclusive, and j is an integer of 1 to n inclusive) are selectively shown.

The pixel PX is used as a display pixel. The display pixel may be, for example, a pixel using one or both of a liquid crystal display device and a light emitting device. Examples of the light-emitting device include a light-emitting device including an Organic EL element (OLED (Organic LIGHT EMITTING Diode)), an inorganic EL element, an LED (including Micro LED), a QLED (Quantum-dot LIGHT EMITTING Diode), and a semiconductor laser. Note that in this embodiment mode, a light-emitting device including an organic EL material is used for the pixel PX. In particular, the luminance of light emitted from a light-emitting device capable of emitting light with high luminance may be, for example, 500cd/m ² or more, preferably 1000cd/m ² or more and 10000cd/m ² or less, more preferably 2000cd/m ² or more and 5000cd/m ² or less.

Further, as an example, in the pixel array ALP, the wiring GL [1] to the wiring GL [ m ] are all provided to extend in the row direction. Further, as an example, in the pixel array ALP, the wiring SL [1] to the wiring SL [ n ] are all provided to extend in the column direction.

The pixel PX [ i, j ] is electrically connected to, for example, the wiring GL [ i ] and the wiring SL [ j ].

The wiring SL [ j ] is used, for example, as a wiring for transmitting an image data signal to the pixel PX [ i, j ].

Note that fig. 1 shows a case where one wiring SL is provided extending for each column in the pixel array, but the number of wirings SL provided extending for one column is not limited to one. That is, the number of wirings SL extending on one column of the pixel array ALP may be two or more.

As an example, the wiring GL [ i ] is used as a wiring that transmits a selection signal for selecting the pixel PX [ i, j ] to which the image data signal is supplied. Further, as an example, the wiring GL [ i ] may also be used as a wiring that transmits a selection signal for selecting the pixel PX [ i, j ] to correct the threshold voltage of the driving transistor included in the pixel PX [ i, j ]. Further, the wiring GL [ i ] may also be used as a wiring that transmits a control signal (digital potential) that switches the on state and the off state of a switch included in the pixel PX [ i, j ].

Note that fig. 1 shows a case where one wiring GL is provided extending for each row in the pixel array, but the number of wirings GL provided extending on a row is not limited to one. That is, the number of the wirings GL extending in one row of the pixel array ALP may be two or more. For example, the number of the wirings GL extending in one row may be determined according to the circuit configuration of the pixel PX, or the number of the wirings GL may be two or more according to the circuit configuration of the pixel PX.

As one example, the row driving circuit RWD includes a driving circuit GD.

As an example, the driving circuit GD is electrically connected to each of the wirings GL [1] to GL [ m ].

As an example, the driving circuit GD has the following functions: one or more lines to be supplied with the image data signals are selected from the first to mth lines of the pixel array ALP, and a selection signal is transmitted to a plurality of pixels PX arranged in the selected line. Accordingly, the driving circuit GD may also include a demultiplexer. The selection signal may be, for example, an analog potential, a digital potential (high level potential or low level potential), or a pulse potential. The drive circuit GD may have a function of selecting not only the pixel PX to be the supply target of the image data signal but also the pixel PX for the purpose of correcting the threshold voltage of the transistor included in the pixel PX. That is, the driving circuit GD may also have a function of transmitting a selection signal for correcting the threshold voltage of the transistor included in the pixel PX.

The column driving circuit CLM includes, for example, a driving circuit SD and circuits CD [1] to CD [ n ].

In addition, the circuits CD [1] to CD [ j ] are all electrically connected to the driving circuit SD. The circuit CD [ j ] is electrically connected to the wiring SL [ j ], for example.

The driving circuit SD has, for example, a function of transmitting an image data signal to the pixels PX included in the pixel array ALP. In addition, the driving circuit SD may include a demultiplexer according to a transmission method of the image data signal. The image data signal may be, for example, an analog potential, a digital potential (high level potential or low level potential), or a pulse potential.

The circuit CD [ j ] has, for example, a function of level-converting an image data signal input from the drive circuit SD and transmitting the level-converted image data signal to the wiring SL [ j ].

Next, a structural example of the pixel PX and the circuit CD will be described. The display device DSP1A shown in fig. 2 is an example of the display device DSP0 of fig. 1, and in fig. 2, one of a plurality of pixels PX included in the pixel array ALP, a driving circuit GD of a row driving circuit RWD electrically connected to the pixel PX, and a circuit CD and a driving circuit SD of a column driving circuit CLM are selectively shown.

In the display device DSP1A of fig. 2, as an example, the pixel PX includes a transistor M2, a switch SW1, a switch SW3, a switch SW5, a switch SW6, a capacitor C1, and a light emitting device LD. The circuit CD includes a switch SW11, a switch SW12 and a capacitor C2. In particular, the transistor M2 is used as a driving transistor in the pixel PX.

As an example, the transistor M2 is preferably an OS transistor. In particular, examples of the metal oxide included in the channel formation region of the OS transistor include indium oxide, gallium oxide, and zinc oxide. In addition, the metal oxide preferably contains one or more selected from indium, element M, and zinc. Note that the element M is one or more selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, and magnesium. In particular, the element M is preferably one or more selected from aluminum, gallium, yttrium, and tin.

In particular, as a metal oxide used for the semiconductor layer, an oxide containing indium (In), gallium (Ga), and zinc (Zn) (also referred to as IGZO) is preferably used. Or preferably an oxide containing indium, tin, and zinc (also referred to as ITZO (registered trademark)). Or preferably oxides containing indium, gallium, tin and zinc are used. Alternatively, an oxide containing indium (In), aluminum (Al), and zinc (Zn) (also referred to as IAZO) is preferably used. Alternatively, an oxide (also referred to as IAGZO) containing indium (In), aluminum (Al), gallium (Ga), and zinc (Zn) is preferably used. Note that the OS transistor is described in detail in embodiment mode 5.

Note that a transistor other than an OS transistor may be used for the transistor M2. For example, as the transistor M2, a transistor including silicon in a channel formation region (hereinafter, referred to as a Si transistor) can be used. As the silicon, for example, single crystal silicon, amorphous silicon (sometimes referred to as hydrogenated amorphous silicon), microcrystalline silicon, or polycrystalline silicon (including low-temperature polycrystalline silicon) can be used.

In addition to the OS transistor and the Si transistor, the transistor M2 may be, for example, a transistor including germanium or the like in a channel formation region, a transistor including a compound semiconductor such as zinc selenide, cadmium sulfide, gallium arsenide, indium phosphide, gallium nitride, or silicon germanium in a channel formation region, a transistor including a carbon nanotube in a channel formation region, or a transistor including an organic semiconductor in a channel formation region.

Note that, although the transistor M2 shown in fig. 2 is an n-channel type transistor, it may be a p-channel type transistor according to circumstances or situations. In addition, in the case of replacing the n-channel type transistor with the p-channel type transistor, the potential or the like input to the pixel PX needs to be appropriately changed to make the pixel PX operate normally. The same applies to the transistor described in other parts of the specification and the transistor shown in other drawings except fig. 2. In this embodiment, the structure and operation of the pixel PX will be described on the premise that the transistor M2 is an n-channel transistor.

In addition, the transistor M2 preferably operates as follows: a current corresponding to a voltage between the gate and the source is caused to flow between the source and the drain, and a current according to the voltage between the source and the drain is not caused to flow. That is, the transistor M2 preferably operates in the saturation region when in the on state. By operating the transistor M2 in the saturation region, the amount of current flowing through the transistor M2 can be determined according to the voltage between the gate and the source. In addition, by operating the transistor M2 in the saturation region, even if the voltage between the source and the drain of the transistor M2 changes, the change in drain current is not large. That is, by determining the amount of current flowing through the transistor M2 according to the voltage between the gate and the source, the transistor M2 can flow a stable current between the anode and the cathode of the light emitting device LD. In addition, the transistor M2 may also operate in the linear region when in the on state, as the case may be. In addition, the transistor M2 may also operate in a subthreshold region.

Note that the above description of the transistor can be applied not only to the transistor M2 but also to a transistor described in other parts of the specification and a transistor shown in the drawings.

As each of the switches SW1, SW3, SW5, SW6, SW11 and SW12, for example, an electric switch such as an analog switch or a transistor can be used. In particular, the above-described transistors as the electric switches are preferably used as the switches SW1, SW3, SW5, SW6, SW11, and SW12, and more preferably the OS transistors are used. Note that when electric switches are used as the switches SW1, SW3, SW5, SW6, SW11 and SW12, transistors usable for the transistor M2 may be used as the electric switches in addition to the OS transistors. Specifically, the transistor may be a Si transistor. Further, mechanical switches may be used as the switches SW1, SW3, SW5, SW6, SW11 and SW12, for example.

In the present specification and the like, the switches SW1, SW3, SW5, SW6, SW11 and SW12 shown in fig. 2 are all in an on state when a high-level potential is applied to their control terminals, and in an off state when a low-level potential is applied to their control terminals.

In fig. 2, as an example, the light emitting device LD is a self-luminous light emitting device including an organic EL element (OLED). Note that the structure of the light emitting device LD usable for the pixel PX will be described in detail in embodiment 4.

In the pixel PX, a first terminal of the switch SW1 is electrically connected to the gate of the transistor M2, a first terminal of the switch SW3, and a first terminal of the capacitor C1, a second terminal of the switch SW1 is electrically connected to the wiring SL, and a control terminal of the switch SW1 is electrically connected to the wiring GL 1. The first terminal of the transistor M2 is electrically connected to the second terminal of the capacitor C1, the first terminal of the switch SW6, and the anode of the light emitting device LD, and the second terminal of the transistor M2 is electrically connected to the second terminal of the switch SW3 and the first terminal of the switch SW 5. The control terminal of the switch SW3 is electrically connected to the wiring GL 3. The second terminal of the switch SW5 is electrically connected to the wiring VE2, and the control terminal of the switch SW5 is electrically connected to the wiring GL 5. The second terminal of the switch SW6 is electrically connected to the wiring VE1, and the control terminal of the switch SW6 is electrically connected to the wiring GL 6. Further, the cathode of the light emitting device LD is electrically connected to the wiring VE 0.

Note that in this embodiment, an electrical connection point of the first terminal of the switch SW1, the first terminal of the switch SW3, the gate of the transistor M2, and the first terminal of the capacitor C1 is referred to as a node N1. The electrical connection point of the first terminal of the transistor M2, the second terminal of the capacitor C1, the first terminal of the switch SW6, and the anode of the light emitting device LD is referred to as a node N2.

In the circuit CD, a first terminal of the capacitor C2 is electrically connected to the wiring SL, and a second terminal of the capacitor C2 is electrically connected to a first terminal of the switch SW11 and a first terminal of the switch SW 12. The second terminal of the switch SW11 is electrically connected to the wiring VE3, and the control terminal of the switch SW11 is electrically connected to the wiring SWL 11. A second terminal of the switch SW12 is electrically connected to the driving circuit SD, and a control terminal of the switch SW12 is electrically connected to the wiring SWL 12.

Note that in this embodiment, an electrical connection point of the first terminal of the switch SW11, the first terminal of the switch SW12, and the second terminal of the capacitor C2 is referred to as a node N3.

The wirings VE0 to VE3 are each used as a wiring for applying a constant potential, for example. The constant potentials applied to each of the wirings VE0 to VE3 may be equal to or different from each other. Or in the potentials applied to each of the wirings VE0 to VE3, a part may be equal and the rest may be different. Further, one or more wirings selected from the wirings VE0 to VE3 may be used as wirings to which a pulse potential is applied without applying a constant potential.

In particular, in the pixel PX of fig. 2, the wiring VE0 is preferably used as a wiring for applying a potential to the cathode of the light emitting device LD. Further, the wiring VE2 is preferably used as a wiring for applying a potential to the anode of the light emitting device LD.

Note that in the pixel PX of fig. 2, the cathode of the light emitting device LD is electrically connected to the wiring VE0 and the anode of the light emitting device LD is electrically connected to the wiring VE2 through the transistor M2 and the switch SW5, but a structure may be adopted in which the anode of the light emitting device LD is electrically connected to the wiring VE0 and the cathode of the light emitting device LD is electrically connected to the wiring VE 2. That is, in the case where the structure of the light emitting device LD as the former adopts a front-up structure, the light emitting device of the pixel of the display device according to one embodiment of the present invention may also adopt an inverted structure. In this case, the wiring VE0 is used as a wiring for applying a potential to the anode of the light emitting device LD, and the wiring VE2 is used as a wiring for applying a potential to the cathode of the light emitting device LD.

The wirings GL1, GL3, GL5, and GL6 correspond to one of the wirings GL [1] to GL [ m ] of fig. 1. That is, in the case of adopting the circuit configuration of the pixel PX shown in fig. 2, the number of wirings GL extending on one row of the pixel array ALP is 4.

The wiring SWL11 is used as a wiring for transmitting a control signal (digital potential) for switching the on state and the off state of the switch SW 11. In addition, similarly, the wiring SWL12 is used as a wiring that transmits a control signal (digital potential) that switches the on state and the off state of the switch SW 12.

Working method of display device example 1

Next, an example of an operation method of the display device DSP1A of fig. 2 is described.

Fig. 3A and 3B are timing charts showing an example of an operation method of the display device DSP 1A. Specifically, the timing chart of fig. 3A shows potential changes of the wirings GL1, GL3, GL5, GL6, SWL11, SWL12, and the node N3 in each of the periods T11 to T17. Fig. 3B shows the potential changes of the node N1 and the node N2 in each of the period T11 to the period T17. In fig. 3B, the potential change of the node N1 is shown by a solid line, and the potential change of the node N2 is shown by a chain line. Note that the timing chart of fig. 3B shows a case where the threshold voltage of the transistor M2 is greater than 0V.

In fig. 3A, high represents a High-level potential, and Low represents a Low-level potential.

The wiring VE1 is applied with V _N as a constant potential. Further, the wiring VE3 is applied with V _ref as a constant potential. Note that V _N and V _ref may be equal potentials to each other.

Further, the wiring VE2 is applied with V _AN as a constant potential. Further, the wiring VE0 is applied with V _CT as a constant potential. In addition, V _AN is a potential higher than V _CT.

In addition, V _AN is a potential higher than V _N. Further, the voltage of V _N-V_CT is a voltage that does not cause the light emitting device LD to emit light (current does not flow between the anode and the cathode of the light emitting device LD). Therefore, V _N is preferably a potential equal to or lower than V _CT.

In addition, the threshold voltage of the transistor M2 is set to V _th. Note that V _th is a voltage lower than V _AN-V_N.

[ Period T11 before ]

Before the period T11, the low-level potential is applied to all of the wirings GL1, GL3, GL5, GL6, SWL11, and SWL 12. Thus, the control terminals of the switches SW1, SW3, SW5, SW6, SW11 and SW12 are applied with low-level potential, so that these switches are all in an off state.

Before the period T11, the potentials of the node N1 and the node N2 are not particularly limited. For example, although fig. 3B shows an example in which the potential of the node N1 rises in the period T11 described later, the potential of the node N1 before the period T11 may be a potential that falls in the period T11. For example, fig. 3B shows an example in which the potential of the node N2 decreases in the period T11 described later, but the potential of the node N2 before the period T11 may be the potential that increases in the period T11.

Before the period T11, the potential of the node N3 is indefinite. Therefore, the potential of the node N3 before the period T11 of the timing chart of fig. 3A is shown in hatching.

Period T11

In the period T11, the high-level potential is applied to the wirings GL1, GL3, GL5, GL6, and SWL 11. Thus, the control terminals of the switches SW1, SW3, SW5, SW6 and SW11 are applied with a high-level potential, so that these switches are all in an on state.

Since the switch SW1, the switch SW3 and the switch SW5 are all in an on state, each of the gate of the transistor M2, the first terminal of the capacitor C1 and the first terminal of the capacitor C2 is in an on state with the wiring VE 2. Accordingly, the potential V _AN from the wiring VE2 is applied to the first terminal of the capacitor C2, the gate of the transistor M2, and the first terminal of the capacitor C1 (the node N1) (see fig. 3B).

Further, since the switch SW6 is in an on state, each of the first terminal of the transistor M2, the second terminal of the capacitor C1, and the anode of the light emitting device LD is in an on state with the wiring VE 1. Accordingly, the potential V _N (see fig. 3B) from the wiring VE1 is applied to the first terminal of the transistor M2, the second terminal of the capacitor C1, and the anode (node N2) of the light-emitting device LD.

At this time, the voltage between the anode and the cathode of the light emitting device LD is V _N-V_CT. As described above, when the voltage between the anode and the cathode of the light emitting device LD is V _N-V_CT, the light emitting device LD does not emit light (current does not flow between the anode and the cathode of the light emitting device LD).

The potential of the gate and the second terminal of the transistor M2 is V _AN, the potential of the first terminal of the transistor M2 is V _N, and thus the voltage between the gate and the source of the transistor M2 is V _AN-V_N. Since the voltage V _AN-V_N between the gate and the source is a voltage higher than V _th, the transistor M2 is in an on state. In addition, when it is assumed that a current does not flow between the anode and the cathode of the light emitting device LD, a current flows between the wiring VE1 and the wiring VE2 through the switch SW5, the transistor M2, and the switch SW 6.

In addition, since the switch SW11 is in an on state, each of the second terminal of the capacitor C2 and the first terminal of the switch SW12 is in an on state with the wiring VE 3. Therefore, the second terminal of the capacitor C2 and the first terminal (node N3) of the switch SW12 are applied with the potential V _ref from the wiring VE3 (see fig. 3A).

Note that, in the period T11 of the timing chart of fig. 3A, the high-level potential is input to each of the wirings GL1, GL3, GL5, GL6, and SWL11 at the same timing, but the timings at which the high-level potential is input to each of the wirings GL1, GL3, GL5, GL6, and SWL11 may be different from each other as long as the period T11 is provided.

Period T12

In the period T12, the low-level potential is applied to the wiring GL 5. Thereby, the control terminal of the switch SW5 is applied with a low-level potential, so the switch SW5 is in an off state. Therefore, the second terminal of the transistor M2 is in a non-conductive state with the wiring VE 2.

Immediately before the switch SW5 is in the off state, the voltage V _AN-V_N between the gate and the source of the transistor M2 is greater than the threshold voltage V _th of the transistor M2, so the transistor M2 is in the on state. When the switch SW5 is in the off state, the potential V _AN is not applied from the wiring VE2 to the second terminal of the transistor M2 and the gate of the transistor M2, so positive charge supplied to the node N1 is discharged to the wiring VE1 through between the first terminal and the second terminal of the transistor M2 and the switch SW 6. Thereby, the potential of the node N1 decreases.

When the potential of the node N1 decreases, the voltage between the gate and the source of the transistor M2 also decreases. When the voltage between the gate and the source of the transistor M2 drops to the threshold voltage V _th of the transistor M2, the transistor M2 is in an off state, and the release of positive charge from the node N1 is stopped. That is, when the potential of the node N1 reaches V _N+V_th from V _AN, the transistor M2 is in an off state. Since the transistor M2 is in an off state, the potential of the node N1 does not change from V _N+V_th (refer to fig. 3B). In addition, since the transistor M2 is in an off state, the node N1 and the wiring SL are in a floating state.

Period T13

In the period T13, the low-level potential is applied to both the wiring GL3 and the wiring SWL 11. Thus, the control terminals of the switch SW3 and the switch SW11 are applied with a low-level potential, and thus both the switch SW3 and the switch SW11 are in an off state.

Since the switch SW3 is in the off state, each of the first terminal of the capacitor C2, the gate of the transistor M2, and the first terminal of the capacitor C1 is in a non-conductive state with the second terminal of the transistor M2.

In addition, since the switch SW11 is in the off state, each of the second terminal of the capacitor C2 and the first terminal of the switch SW12 is in a non-conductive state with the wiring VE 3. At this time, the node N3 is in a floating state.

Period T14

In the period T14, the wiring SWL12 is applied with a high-level potential. Thereby, the control terminal of the switch SW12 is applied with a high-level potential, so the switch SW12 is in an on state.

In particular, when the switch SW12 is in the on state, the driving circuit SD transmits an image data signal corresponding to the image displayed on the pixel PX to the second terminal (node N3) of the capacitor C2 through the switch SW 12. Note that the image data signal is at the potential V _data.

Therefore, the potential of the node N3 changes from V _ref to V _data. Further, since the wiring SL and the node N1 are in a floating state, the potential of the wiring SL and the node N1 also changes with the potential change of the node N3 due to the capacitive coupling of the capacitor C2. The amounts of change in the potentials of the wiring SL and the node N1 depend on, for example, the capacitance of the capacitor C1, the capacitance of the capacitor C2, the gate capacitance of the transistor M2, the parasitic capacitance related to the switch SW1, the parasitic capacitance related to the switch SW3, and the parasitic capacitance related to the wiring SL. In this working example, for simplicity of explanation, it is assumed that the amounts of change in the potential of the wiring SL and the node N1 depend on the capacitance of the capacitor C1 and the capacitance of the capacitor C2.

When the capacitance of the capacitor C1 is C ₁, the capacitance of the capacitor C2 is C ₂, and the potential of the node N3 is changed from V _ref to V _data, the potentials of the wiring SL and the node N1 are applied with Δv _data＝(V_data-V_ref)×C₂/(C₁+C₂ as a change amount. Therefore, the potential of the wiring SL and the node N1 becomes V _N+V_th+ΔV_data (see fig. 3B).

On the other hand, since the potential V _N from the wiring VE1 is applied to the second terminal (node N2) of the capacitor C1 from before the period T14, the potential of the second terminal (node N2) of the capacitor C1 remains V _N without change even when the potential of the node N3 changes from V _ref to V _data.

Thus, when the voltage between the gate and the source of the transistor M2 in the period T14 is V _drv, V _drv = (potential of the node N1) - (potential of the node N2) =v _th+ΔV_data holds. That is, in the period T14, the voltage V _drv held between the first terminal and the second terminal of the capacitor C1 is set to the sum of the potential Δv _data corresponding to the image displayed by the pixel PX and the threshold voltage V _th of the transistor M2.

In addition, the voltage V _drv between the gate and the source of the transistor M2 is greater than the threshold voltage V _th of the transistor M2, so the transistor M2 is in an on state. However, since the switch SW3 and the switch SW5 are both in the off state, the second terminal of the transistor M2 and the node N1 and the second terminal of the transistor M2 and the wiring VE2 are both in the non-conductive state. Therefore, current does not flow between the first terminal and the second terminal of the transistor M2.

Period T15

In the period T15, the low-level potential is applied to the wiring GL 1. Thereby, the control terminal of the switch SW1 is applied with a low-level potential, so the switch SW1 is in an off state.

When the switch SW1 is turned off, the gate of the transistor M2 and the first terminal of the capacitor C1 are in a non-conductive state with the wiring SL. Since the switch SW3 is turned off from the period T13, the first terminal (node N1) of the capacitor C1 is kept at the potential V _N+V_th+ΔV_data.

Period T16

In the period T16, the high-level potential is applied to the line GL5, and the low-level potential is applied to the line GL 6. Thereby, the control terminal of the switch SW5 is applied with a high-level potential, so the switch SW5 is in an on state. In addition, the control terminal of the switch SW6 is applied with a low-level potential, whereby the switch SW6 is in an off state.

Since the switch SW5 is in an on state, the second terminal of the transistor M2 is in an on state with the wiring VE 2. Further, since the switch SW6 is in an off state, the first terminal of the transistor M2 and the second terminal of the capacitor C1 are each in a non-conductive state with the wiring VE 1. Since the switch SW3 is turned off from the period T13, the second terminal of the transistor M2 and the gate (node N1) of the transistor M2 are in a non-conductive state.

In addition, the voltage between the gate and the source of the transistor M2 is V _drv＝V_th+ΔV_data, which is greater than the threshold voltage V _th of the transistor M2, so the transistor M2 is in an on state.

Accordingly, a current flows between the wiring VE0 and the wiring VE2 through the switch SW5, the transistor M2 and the light emitting device LD.

At this time, the voltage V _AN-V_CT between the wiring VE0 and the wiring VE2 is divided by the transistor M2, the light-emitting device LD, and the switch SW 5. In this working example, the potential of the first terminal (the second terminal of the capacitor C1 and the node N2) of the transistor M2 is boosted from V _N to V _S by the operation in the period T16 (see fig. 3B).

In addition, the potential of the first terminal (the second terminal of the capacitor C1 and the node N2) of the transistor M2 is boosted from V _N to V _S, whereby the potential of the gate (the first terminal of the capacitor C1 and the node N1) of the transistor M2 also changes due to the capacitive coupling of the capacitor C1. In this working example, the potential of the gate (the first terminal of the capacitor C1 and the node N1) of the transistor M2 is boosted from V _N+V_th+ΔV_data to V _G by the operation in the period T16 (see fig. 3B).

Note that the amount of change in the potential of the node N1 occurring due to the capacitive coupling of the capacitor C1 described above depends on the electrostatic capacitance of the capacitor C1, the gate capacitance of the transistor M2, the parasitic capacitance related to the switch SW1, and the parasitic capacitance related to the switch SW 3. Note that in this working example, for simplicity of explanation, the amount of change in the potential of the node N1 is equal to the amount of change in the potential of the node N2. That is, when the amount of change in the potential of the node N2 is Δv _c(＝V_S-V_N), the amount of change in the potential of the node N1 is Δv _c. This corresponds to the case where the capacitive coupling coefficient around the node N1 is 1.

Note that since Δv _c＝V_G-(V_N+V_th+ΔV_data) is satisfied in the node N1, V _G-V_S＝V_th+ΔV_data＝V_drv can be obtained by substituting the amount of change Δv _c＝V_S-V_N in the potential of the node N2 into the expression. That is, the voltage between the gate and the source of the transistor M2 in the period T16 does not change after the image data signal is input to the circuit CD in the period T14.

Here, consider a case where the transistor M2 operates in a saturation region. The amount of current flowing between the first terminal and the second terminal of the transistor M2 is determined according to the voltage V _drv between the gate and the source of the transistor M2. Specifically, the amount I of current flowing between the source and the drain of the transistor operating in the saturation region is proportional to the square of the difference between the voltage V _GS between the gate and the source of the transistor and the threshold voltage V _th of the transistor, so i=k (V _GS-V_th)² holds, note that k is a proportionality constant depending on the structure of the transistor by substituting the voltage V _drv between the gate and the source of the transistor M2 into V _GS,I＝k(ΔV_data)² of the above expression holds, the amount I of current flowing through the transistor M2 does not depend on the threshold voltage V _th but depends on Δv _data.

As described above, by performing the operations from the period T11 to the period T16, the transistor M2 can generate a current independent of the threshold voltage V _th of the transistor M2.

In addition, since the potential of the anode of the light emitting device LD is V _S, the potential between the anode and the cathode of the light emitting device LD is V _S-V_CT. In addition, a current (i=k (Δv _data)²) flowing between the source and the drain of the transistor M2 flows between the anode and the cathode of the light emitting device LD, so the light emitting device LD emits light.

The image data signal V _data output from the drive circuit SD passes through the circuit CD to become V _AN+K×(V_data-V_ref). That is, V _AN+K×(V_data-V_ref) is input to the pixel PX. Note that, set to k=c ₂/(C₁+C₂). Here, consider the following case: the minimum value of the gray level of the pixel is V _{data_min}, the maximum value of the gray level of the pixel is V _{data_max}, and the image data signal V _data takes any one of a plurality of potentials of V _{data_min} to V _{data_max}. Each of the plurality of potentials of V _{data_min} to V _{data_max} becomes V _AN+K×(V_{data_min}-V_ref) to V _AN+K×(V_{data_max}-V_ref when input to the pixel PX through the circuit CD).

In the case where V _ref is lower than V _AN, the relationship of each of the image data signals V _{data_min} to V _{data_max} output from the driving circuit SD and V _AN+K×(V_{data_min}-V_ref) to V _AN+K×(V_{data_max}-V_ref input to the pixel PX through the circuit CD) is shown in fig. 4A. That is, when the image data signal output from the driving circuit SD is input to the pixel PX through the circuit CD, the potential range of the image data signal becomes narrow, and the step size of the potential of the image data signal also becomes small. Thus, the potential of the image data signal input to the pixel PX can be finely changed, so that the amount of current flowing between the source and the drain of the transistor M2 can be finely changed.

In addition, in the case where V _ref is higher than V _AN, the relationship of each of the image data signals V _{data_min} to V _{data_max} output from the driving circuit SD and V _AN+K×(V_{data_min}-V_ref) to V _AN+K×(V_{data_max}-V_ref input to the pixel PX through the circuit CD) is shown in fig. 4B. In addition, as in fig. 4A, by reducing the step size of the potential of the image data signal, the amount of current flowing between the source and the drain of the transistor M2 can be finely changed.

In addition, in the case where V _ref is equal to V _AN, the relationship of each of the image data signals V _{data_min} to V _{data_max} output from the driving circuit SD and V _AN+K×(V_{data_min}-V_ref) to V _AN+K×(V_{data_max}-V_ref input to the pixel PX through the circuit CD) is shown in fig. 4C. In addition, as in fig. 4A and 4B, by reducing the step size of the potential of the image data signal, the amount of current flowing between the source and the drain of the transistor M2 can be finely changed.

Note that in the period T16 of the timing chart of fig. 3A, the high-level potential and the low-level potential are input to the wiring GL5 and the wiring GL6 at the same timing, but the timings of inputting the potentials to the wiring GL5 and the wiring GL6 may be different from each other as long as in the period T16.

Period T17

In the period T17, the low-level potential is applied to both the wiring GL5 and the wiring SWL12, and the high-level potential is applied to the wiring GL 6. Thus, the control terminals of the switch SW5 and the switch SW12 are applied with a low-level potential, and thus both the switch SW5 and the switch SW12 are in an off state. In addition, the control terminal of the switch SW6 is applied with a high-level potential, whereby the switch SW6 is in an on state.

Since the switch SW5 is in the off state, the second terminal of the transistor M2 is in a non-conductive state with the wiring VE 2. Further, since the switch SW6 is in an on state, each of the first terminal of the transistor M2, the second terminal of the capacitor C1, and the anode of the light emitting device LD is in an on state with the wiring VE 1. Accordingly, the potential V _N (see fig. 3B) from the wiring VE1 is applied to the first terminal of the transistor M2, the second terminal of the capacitor C1, and the anode (node N2) of the light-emitting device LD.

That is, by performing the operation for the period T17, the light emission of the light emitting device LD can be stopped.

By performing the operations of the above-described period T11 to period T17, the transistor M2 of the pixel PX can generate a current independent of the threshold voltage V _th of the transistor M2, and the current can be supplied to the light emitting device LD.

The threshold voltages of the driving transistors of a plurality of pixels included in the pixel array of the display device may fluctuate depending on the manufacturing process and the manufacturing environment of the display device. That is, when the same image data signal is supplied to different pixels and the threshold voltages of the transistors of the respective pixels are different, the amounts of currents flowing through the respective transistors are also sometimes different, and the light-emitting luminance of the light-emitting devices of the respective pixels is also different. As a result, the light emitting device emits light with uneven brightness, and the display quality of an image of the display device is degraded.

On the other hand, by using the display device DSP1A as one embodiment of the present invention, the transistor M2 of the pixel PX can generate a current independent of the threshold voltage V _th of the transistor M2, whereby the occurrence of the non-uniformity of the light emission luminance of the light emitting device included in each pixel PX of the pixel array ALP can be prevented. Therefore, by using the display device DSP1A, the display quality of the display device DSP1A can be improved.

Further, by performing the operations of the above-described period T11 to period T17, the amount of current flowing through the light emitting device LD of the pixel PX of the display device DSP1A can be more finely controlled.

When the definition of the display device is high, the area of the region (light emitting surface) of the light emitting device in which the plurality of pixels are formed, which is included in the pixel array, is small. When the area of the region (light emitting surface) of the light emitting device becomes smaller, the amount of current required for light emission of the light emitting device becomes smaller, but the allowable amount of current also becomes smaller. Therefore, in order to accurately adjust the light emission luminance of the light emitting device, it is necessary to finely control the current.

By using the display device DSP1A as one embodiment of the present invention, the amount of current flowing through the light emitting device LD can be finely controlled, so that the light emitting luminance of the light emitting device LD of the pixel PX can be finely adjusted. Therefore, by using the display device DSP1A, the gradation of an image can be finely set, whereby the display quality of the display device DSP1A can be improved. Further, by using the display device DSP1A, the amount of current flowing through the light emitting device LD can be reduced, whereby damage to the light emitting device LD due to an overcurrent can be prevented.

Working method of display device example 2

In fig. 3A and 3B, the operation of one pixel PX included in the pixel array ALP of the display device DSP1A is described. Here, the operation of the entire pixel array ALP in the display device DSP0 using the display device DSP1A will be described.

Note that, since the display device DSP0 employs the display device DSP1A, the circuits CD [1] to CD [ n ] of the display device DSP0 employ the circuit CD of fig. 2. In addition, the pixels PX [1,1] to PX [ m, n ] are all pixels PX of fig. 2.

Fig. 5 is a timing chart showing an example of a method of writing image data to a plurality of pixels PX included in the pixel array ALP of the display device DSP 0.

The timing chart of fig. 5 shows the potential changes of the node N3[1], the node N3[2], the node N3[ N ], the wiring GL1[1], the wiring GL6[1], the wiring GL1[2], the wiring GL6[2], the wiring GL1[ m ], and the wiring GL6[ m ] and the changes of the image data held between the first terminal and the second terminal of each of the capacitors C1[1,1], the capacitors C1[1,2], the capacitors C1[1, N ], the capacitors C1[2, the capacitors C1[2, N ], the capacitors C1[ m,1], the capacitors C1[ m,2], and the capacitors C1[ m, N ] in the periods U1 to U7 and the vicinity thereof.

Node N3[1] corresponds to node N3 comprised by circuit CD [1] in display device DSP 0. Similarly, the node N3[2] corresponds to the node N3 included in the circuit CD [2] (not shown in fig. 1) in the display device DSP0, and the node N3[ N ] corresponds to the node N3 included in the circuit CD [ N ] in the display device DSP 0.

The line GL1[1] corresponds to the line GL1 of fig. 2 extending in the first row in the pixel array ALP of the display device DSP 0. Similarly, the wiring GL1[2] corresponds to the wiring GL1 of fig. 2 extending in the second row in the pixel array ALP of the display device DSP0, and the wiring GL1[ m ] corresponds to the wiring GL1 of fig. 2 extending in the m-th row in the pixel array ALP of the display device DSP 0.

The capacitor C1[1,1] corresponds to the capacitor C1 of fig. 2 in the pixel PX [1,1] included in the pixel array ALP of the display device DSP 0. Similarly, the capacitor C1[1,2] corresponds to the capacitor C1 of fig. 2 in the pixel PX [1,2] (not shown in fig. 1) included in the pixel array ALP of the display device DSP0, and the capacitor C1[1, n ] corresponds to the capacitor C1 of fig. 2 in the pixel PX [1, n ] included in the pixel array ALP of the display device DSP 0. Hereinafter, the description of "capacitor C1[ i, j ]" is regarded as the capacitor C1 of fig. 2 corresponding to the pixel PX [ i, j ] included in the pixel array ALP of the display device DSP 0.

In each of the periods U1, U3, and U6 in the timing chart of fig. 5, the plurality of pixels PX in the predetermined row are operated from the period T11 to the period T13 in the timing chart of fig. 3. In each of the periods U2, U4, and U7 in the timing chart of fig. 5, the plurality of pixels PX in the predetermined row are operated from the period T14 to the period T17 in the timing chart of fig. 3A.

Before the period U1, the voltage V _drv [1,1] 0 is held in the capacitor C1[1,1], the voltage V _drv [1,2] 0 is held in the capacitor C1[1,2], the voltage V _drv [1, n ] 0 is held in the capacitor C1[1, n ], the voltage V _drv [2,1] 0 is held in the capacitor C1[2,1], the voltage V _drv [2,2] 0 is held in the capacitor C1[2, n ], the voltage V _drv [2, n ] 0 is held in the capacitor C1[2,1], the voltage V _drv [ m,1] 0 is held in the capacitor C1[ m,2], the voltage V _drv [ m,2] is held in the capacitor C1[ m,2], and the voltage V _drv [ m, n ] 0 is held in the capacitor C1[2, n ]. Note that V _drv [ i, j ] corresponds to V _drv in the timing chart of fig. 3B of the pixel PX [ i, j ].

Before the period U1, the low-level potential is input to all of the wirings GL1[1] to GL1[ m ]. Thereby, the control terminals of the switches SW1 of all the pixels PX of the pixel array ALP are applied with the low-level potential, so the switches SW1 of all the pixels PX are in the off state. Further, due to the above-described operation, a current flows between the anode and the cathode of the light emitting device LD of all the pixels PX of the pixel array ALP, whereby the light emitting device LD emits light.

In the period U1, operations from the period T11 to the period T13 of the timing chart of fig. 3A are performed in the pixels PX [1,1] to PX [1, n ] on the first row of the pixel array ALP. Thus, the potentials of the nodes N3[1] to N3[ N ] all become V _ref.

In addition, in the period U1, the high-level potential is input to the wiring GL1[1 ]. Thereby, the control terminals of the switches SW1 of the pixels PX [1,1] to PX [1, n ] arranged on the first row of the pixel array ALP are all applied with the high-level potential, so the switches SW1 of the pixels PX [1,1] to PX [1, n ] are all in an on state.

In addition, in the period U1, the high-level potential is input to the wiring GL6[1 ]. Thereby, the control terminals of the switches SW6 of the pixels PX [1,1] to PX [1, n ] arranged on the first row of the pixel array ALP are all applied with the high-level potential, so the switches SW6 of the pixels PX [1,1] to PX [1, n ] are all in an on state. Further, due to this operation, current does not flow between the anode and the cathode of each light emitting device LD of the pixels PX [1,1] to PX [1, n ], so that these light emitting devices LD do not emit light.

In addition, due to the operations of the period T11 to the period T13 of the timing chart of fig. 3A, the voltages V _drv [1,1] _0 to V _drv [1, n ] _0 held by the capacitors C1[1,1] to C1[1, n ] in the pixels PX [1,1] to the pixels PX [1, n ] before the period U1 are initialized, and the correction voltages of the threshold voltages of the transistors M2 are written to the capacitors C1[1,1] to C1[1, n ]. Note that the correction voltage is not shown in the capacitors C1[1,1], C1[1,2] and C1[1, n ] of the period U1 in fig. 5.

In the period U2, operations from the period T14 to the period T17 of the timing chart of fig. 3A are performed in the pixels PX [1,1] to PX [1, n ] on the first row of the pixel array ALP. At this time, as an example, potentials V _d [1,1] 1 to V _d [1, N ] 1 are input to each of the nodes N3[1] to N3[ N ] as signals corresponding to image data written to the pixels PX [1,1] to PX [1, N ], respectively. Note that V _d [1,1] _1 to V _d [1, n ] _1 correspond to V _data of the description of fig. 3A and 3B.

In addition, due to the operations of the period T14 to the period T17 of the timing chart of fig. 3A, the potentials obtained by converting the levels of the first terminals of the capacitors C1[1,1] to C1[1, n ] in the pixels PX [1,1] to PX [1, n ] are input to V _d [1,1] 1 to V _d [1, n ] 1. Thus, each of the capacitors C1[1,1] to C1[1, n ] holds V _drv [1,1] _1 to V _drv [1, n ] _1, respectively, as a potential corresponding to image data.

Then, the wiring GL1[1] is inputted with a low-level potential. Thereby, the control terminals of the switches SW1 of the pixels PX [1,1] to PX [1, n ] arranged on the first row of the pixel array ALP are all applied with the low-level potential, so the switches SW1 of the pixels PX [1,1] to PX [1, n ] are in the off state.

In addition, in the period U2, after the low-level potential is applied to the wiring GL1[1], the low-level potential is input to the wiring GL6[1 ]. Thereby, the control terminals of the switches SW6 of the pixels PX [1,1] to PX [1, n ] arranged on the first row of the pixel array ALP are all applied with the low-level potential, so the switches SW6 of the pixels PX [1,1] to PX [1, n ] are all in the off state. Further, due to the above-described operation, a current flows between the anode and the cathode of the light emitting devices LD of each of the pixels PX [1,1] to PX [1, n ], so that these light emitting devices LD emit light of a luminance corresponding to the amount of the current. Note that, as illustrated in fig. 3A and 3B, the amount of the current is determined according to the voltage between the gate and the source of the transistor M2, that is, the voltage held in the capacitor C1. That is, the light emitting device LD of the pixel PX [1,1] emits light of the luminance corresponding to the voltage V _drv [1,1] _1, the light emitting device LD of the pixel PX [1,2] emits light of the luminance corresponding to the voltage V _drv [1,2] _1, and the light emitting device LD of the pixel PX [1, n ] emits light of the luminance corresponding to the voltage V _drv [1, n ] _1.

In the period U3, operations from the period T11 to the period T13 of the timing chart of fig. 3A are performed in the pixels PX [2,1] to PX [2, n ] (not shown in fig. 1) on the second row of the pixel array ALP. Thus, the potentials of the nodes N3[1] to N3[ N ] all become V _ref.

In addition, in the period U3, the high-level potential is input to the wiring GL1[ 2]. Thereby, the control terminals of the switches SW1 of the pixels PX [2,1] to PX [2, n ] arranged on the second row of the pixel array ALP are all applied with the high-level potential, so that the switches SW1 of the pixels PX [2,1] to PX [2, n ] are all in the on state.

In addition, in the period U3, the high-level potential is input to the wiring GL6[2 ]. Thereby, the control terminals of the switches SW6 of the pixels PX [2,1] to PX [2, n ] arranged on the second row of the pixel array ALP are all applied with the high-level potential, so that the switches SW6 of the pixels PX [2,1] to PX [2, n ] are all in the on state. Further, due to this operation, current does not flow between the anode and the cathode of each light emitting device LD of the pixels PX [2,1] to PX [2, n ], so that these light emitting devices LD do not emit light.

In addition, due to the operations of the period T11 to the period T13 of the timing chart of fig. 3A, the voltages V _drv [2,1] _0 to V _drv [2, n ] _0 held by the capacitors C1[2,1] to C1[2, n ] in the pixels PX [2,1] to the pixels PX [2, n ] before the period U3 are initialized, and the correction voltages of the threshold voltages of the transistors M2 are written to the capacitors C1[2,1] to C1[2, n ]. Note that the correction voltage is not shown in the capacitors C1[2,1], C1[2,2] and C1[2, n ] in the period U3 of fig. 5.

In the period U4, operations from the period T14 to the period T17 of the timing chart of fig. 3A are performed in the pixels PX [2,1] to PX [2, n ] on the second row of the pixel array ALP. At this time, as an example, potentials V _d [2,1] 1 to V _d [2, N ] 1 are input to each of the nodes N3[1] to N3[ N ] as signals corresponding to image data written to the pixels PX [2,1] to PX [2, N ], respectively. Note that V _d [2,1] _1 to V _d [2, n ] _1 correspond to V _data of the description of fig. 3A and 3B.

In addition, due to the operations of the period T14 to the period T17 of the timing chart of fig. 3A, the potentials obtained by converting the levels of the first terminals of the capacitors C1[2,1] to C1[2, n ] in the pixels PX [2,1] to PX [2, n ] are input to V _d [2,1] 1 to V _d [2, n ] 1. Thus, each of the capacitors C1[2,1] to C1[2, n ] holds V _drv [2,1] _1 to V _drv [2, n ] _1, respectively, as a potential corresponding to image data.

Then, the low-level potential is inputted to the wiring GL1[2 ]. Thereby, the control terminals of the switches SW1 of the pixels PX [2,1] to PX [2, n ] arranged on the second row of the pixel array ALP are all applied with the low-level potential, so the switches SW1 of the pixels PX [2,1] to PX [2, n ] are in the off state.

In addition, in the period U4, after the low-level potential is applied to the wiring GL1[2], the low-level potential is input to the wiring GL6[2 ]. Thereby, the control terminals of the switches SW6 of the pixels PX [2,1] to PX [2, n ] arranged on the second row of the pixel array ALP are all applied with the low-level potential, so the switches SW6 of the pixels PX [2,1] to PX [2, n ] are all in the off state. Further, due to the above-described operation, a current flows between the anode and the cathode of the light emitting devices LD of each of the pixels PX [2,1] to PX [2, n ], so that these light emitting devices LD emit light of a luminance corresponding to the amount of the current. Note that, as illustrated in fig. 3A and 3B, the amount of the current is determined according to the voltage between the gate and the source of the transistor M2, that is, the voltage held in the capacitor C1. That is, the light emitting device LD of the pixel PX [2,1] emits light of the luminance corresponding to the voltage V _drv [2,1] _1, the light emitting device LD of the pixel PX [2,2] emits light of the luminance corresponding to the voltage V _drv [2,2] _1, and the light emitting device LD of the pixel PX [2, n ] emits light of the luminance corresponding to the voltage V _drv [2, n ] _1.

In the period U5, like the periods U1 and U2 (the periods U3 and U4), the image data is written to the pixels PX in each of the third to m-1 th rows. Note that, in the period U5, image data is written successively to the pixels PX of each row.

In the period U6, operations from the period T11 to the period T13 of the timing chart of fig. 3A are performed in the pixels PX [ m,1] to PX [ m, n ] on the m-th row of the pixel array ALP. Thus, the potentials of the nodes N3[1] to N3[ N ] all become V _ref.

In addition, in the period U6, the high-level potential is input to the wiring GL1[ m ]. Thereby, the control terminals of the switches SW1 of the pixels PX [ m,1] to PX [ m, n ] arranged on the m-th row of the pixel array ALP are all applied with the high-level potential, so that the switches SW1 of the pixels PX [ m,1] to PX [ m, n ] are all in an on state.

In addition, in the period U6, the high-level potential is input to the wiring GL6[ m ]. Thereby, the control terminals of the switches SW6 of the pixels PX [ m,1] to PX [ m, n ] arranged on the m-th row of the pixel array ALP are all applied with the high-level potential, so that the switches SW6 of the pixels PX [ m,1] to PX [ m, n ] are all in an on state. Further, due to this operation, current does not flow between the anode and the cathode of each light emitting device LD of the pixels PX [ m,1] to PX [ m, n ], so that these light emitting devices LD do not emit light.

In addition, due to the operations of the period T11 to the period T13 of the timing chart of fig. 3A, the voltages V _drv [ M, 1_0 to V _drv [ M, n ] 0 held by the capacitors C1[ M,1] to C1[ M, n ] in the pixels PX [ M,1] to the pixels PX [ M, n ] before the period U6 are initialized, and the correction voltages of the threshold voltages of the transistors M2 are written to the capacitors C1[1,1] to C1[1, n ]. Note that, in the capacitor C1[ m,1], the capacitor C1[ m,2], and the capacitor C1[ m, n ] of the period U6 in fig. 5, the correction voltage is not described.

In the period U7, operations from the period T14 to the period T17 of the timing chart of fig. 3A are performed in the pixels PX [ m,1] to PX [ m, n ] on the m-th row of the pixel array ALP. At this time, as an example, potentials V _d [ m,1] _1 to V _d [ m, N ] _1 are input to each of the nodes N3[1] to N3[ N ] as signals corresponding to image data written to the pixels PX [ m,1] to PX [ m, N ], respectively. Note that V _d [ m,1] _1 to V _d [ m, n ] _1 correspond to V _data of the description of fig. 3A and 3B.

In addition, due to the operations of the period T14 to the period T17 of the timing chart of fig. 3A, the potentials obtained by converting the levels of the first terminals of the capacitors C1[ m,1] to C1[ m, n ] in the pixels PX [ m,1] to PX [ m, n ] are input V _d [ m,1] _1 to V _d [ m, n ] _1. Thus, each of the capacitors C1[ m,1] to C1[ m, n ] holds V _drv [ m,1] _1 to V _drv [ m, n ] _1, respectively, as a potential corresponding to the image data.

Then, the low-level potential is inputted to the wiring GL1[ m ]. Thereby, the control terminals of the switches SW1 of the pixels PX [ m,1] to PX [ m, n ] arranged on the m-th row of the pixel array ALP are all applied with the low-level potential, so the switches SW1 of the pixels PX [ m,1] to PX [ m, n ] are in the off state.

In addition, in the period U7, after the low-level potential is applied to the wiring GL1[3], the low-level potential is input to the wiring GL6[ m ]. Thereby, the control terminals of the switches SW6 of the pixels PX [ m,1] to PX [ m, n ] arranged on the m-th row of the pixel array ALP are all applied with the low-level potential, so the switches SW6 of the pixels PX [ m,1] to PX [ m, n ] are all in the off state. Further, due to the above-described operation, a current flows between the anode and the cathode of the light emitting device LD of each of the pixels PX [ m,1] to PX [ m, n ], so that these light emitting devices LD emit light of a luminance corresponding to the amount of the current. Note that, as illustrated in fig. 3A and 3B, the amount of the current is determined according to the voltage between the gate and the source of the transistor M2, that is, the voltage held in the capacitor C1. That is, the light emitting device LD of the pixel PX [ m,1] emits light of a luminance corresponding to the voltage V _drv [ m,1] _1, the light emitting device LD of the pixel PX [ m,2] (not shown in fig. 1) emits light of a luminance corresponding to the voltage V _drv [ m,2] _1, and the light emitting device LD of the pixel PX [ m, n ] emits light of a luminance corresponding to the voltage V _drv [ m, n ] _1.

As described above, by performing the operations of the periods U1 to U7, the display device DSP0 using the display device DSP1A can display an image. The image displayed on the display device DSP0 may be updated every time the operations of the periods U1 to U7 are repeated.

The operation method of the display device DSP0 is not limited to the operation method of the display device according to one embodiment of the present invention. For example, the operation method of the display device according to one embodiment of the present invention may be a method in which the display device DSP0 of fig. 1 displays an image by performing one or both of on/off state control of a switch included in the pixel PX and control of a voltage supplied to the pixel PX to cause a light emitting device of the pixel PX to emit light in a pulse shape during one frame. In contrast, in a period other than the light emitting device of the pixel PX in one frame period, the light emitting device of the pixel PX may not be caused to emit light in the display device DSP0 of fig. 1. That is, the display device DSP0 can perform an operation of image display and black display during one frame (referred to as Duty driving).

In the case where the display device DSP0 of fig. 1 is caused to display a moving image, the frame rate of the display device DSP0 may be 30Hz or more, 60Hz or more, 120Hz or more, 165Hz or more, or 240Hz or more. In the case where the display device DSP0 of fig. 1 is caused to display a still image, the frame rate of the display device DSP0 may be 10Hz or less, 5Hz or less, 1Hz or less, 0.5Hz or less, or 0.1Hz or less.

Layout example of display device

Fig. 6A and 6B are layout diagrams (plan views) each showing an example of a circuit configuration of a part of the display device DSP1A of fig. 2. Fig. 6A shows a layout of the circuit CD, and fig. 6B shows a layout of the pixels PX.

In the layout diagram of fig. 6A, a transistor M11 is used as the switch SW11 included in the circuit CD of fig. 1, and a transistor M12 is used as the switch SW12 included in the circuit CD of fig. 1. In the layout diagram of fig. 6B, the transistor M1 is used as the switch SW1 included in the pixel PX of fig. 1, the transistor M3 is used as the switch SW3 included in the pixel PX of fig. 1, the transistor M5 is used as the switch SW5 included in the pixel PX of fig. 1, and the transistor M6 is used as the switch SW6 included in the pixel PX of fig. 1.

In each of fig. 6A and 6B, the display device DSP1A includes a conductor GEM, a conductor SDMB, a conductor SDMT, a semiconductor SMC, and a conductor PLG. Note that fig. 6A and 6B do not show an insulator included in the display device DSP 1A.

As an example, the semiconductor SMC is located below the conductor GEM. Further, as an example, the conductor GEM is located below the conductor SDMB. Further, as an example, conductor SDMB is located below conductor SDMT. That is, in fig. 6A and 6B, the circuit CD and the pixel PX are sequentially formed with a semiconductor SMC, a conductor GEM, a conductor SDMB, and a conductor SDMT.

As an example, a part of the conductor GEM is used as the gate (sometimes referred to as a first gate) of each of the transistors M1, M2, M3, M5, M6, M11, and M12.

The semiconductor SMC, the conductor GEM, the conductor SDMB, and the conductor SDMT may be formed by photolithography, for example. Specifically, for example, when forming the conductor GEM, a conductive material to be the conductor GEM may be formed by one or more methods selected from a sputtering method, a chemical vapor deposition (CVD: chemical Vapor Deposition) method, a pulsed laser deposition (PLD: pulsed Laser Deposition) method, and an atomic layer deposition (ALD: atomic Layer Deposition) method, and then a desired pattern may be formed by photolithography. The semiconductor SMC, the conductor SDMB, and the conductor SDMT may be formed by the same method as described above.

Further, insulators may be provided between the semiconductor SMC and the conductor GEM, between the conductor GEM and the conductor SDMB, and between the conductor SDMB and the conductor SDMT, respectively. In particular, an insulator provided between the semiconductor SMC and the conductor GEM is sometimes used as a gate insulating film (sometimes referred to as a first gate insulating film, a front gate insulating film).

Further, conductors PLG serving as wirings or plugs are provided between the semiconductor SMC and the conductors SDMB, between the semiconductor SMC and the conductors SDMT, and between the conductors GEM and the conductors SDMT, respectively. For example, an opening is formed in the insulator, and the opening is filled with a conductive material to be the conductor PLG, thereby forming the conductor PLG. After the formation of the conductor PLG, the surface of each film of the conductor PLG and the insulator in the vicinity thereof may be planarized by a planarization process such as a chemical mechanical polishing process so as to make the heights uniform.

As an example, the transistors M1, M2, M3, M5, M6, M11, and M12 shown in fig. 6A and 6B each include a part of each of the semiconductor SMC, the conductor GEM, the insulator, and the conductor PLG.

The capacitor C1 and the capacitor C2 shown in fig. 6A and 6B include a part of each of the conductors SDMB and SDMT. Specifically, each of the capacitors C1 and C2 has a region where a part of each of the conductors SDMB and SDMT overlaps. In other words, in each of the capacitor C1 and the capacitor C2, a part of the conductor SDMB is used as one of the pair of electrodes, and a part of the conductor SDMT is used as the other of the pair of electrodes. Further, it is preferable that an insulator having a high dielectric constant is provided between the conductors SDMB and SDMT in the capacitors C1 and C2.

Further, as an example, the conductor EC shown in fig. 6B is formed on the conductor SDMB. The conductor EC is used as a wiring or plug electrically connected to the anode of the light emitting device LD (not shown in fig. 6B) located above the conductor SDMT.

Note that the layout of the display device according to one embodiment of the present invention is not limited to fig. 6A and 6B. The layout of the display device according to one embodiment of the present invention may be a layout obtained by appropriately changing fig. 6A or 6B.

Fig. 7 shows a modification example of fig. 6B. The layout of the pixels PX shown in fig. 7 is different from the layout of the pixels PX of fig. 6B in that: the semiconductor SMC included in the transistor M3 and the semiconductor SMC included in the transistor M5 are formed as continuous semiconductor films without being separated.

In fig. 7, since the semiconductor SMC included in the transistor M3 and the semiconductor SMC included in the transistor M5 are formed as continuous semiconductor films, one conductor PLG is formed in a region including one of the source and the drain of the transistor M3 corresponding to the second terminal of the switch SW3 and one of the source and the drain of the transistor M5 corresponding to the first terminal of the switch SW 5.

As shown in fig. 7, by forming a continuous semiconductor film without separating the semiconductor film, the distance of a current flowing between one of the source and the drain of the transistor M3 and one of the source and the drain of the transistor M5 can be shortened. Thereby, the resistance value between one of the source and the drain of the transistor M3 and one of the source and the drain of the transistor M5 can be reduced, and thus power consumption can be reduced.

In addition to the processed pattern of the semiconductor, the processed pattern of each film such as the conductor and the insulator is finer, and the processing failure of the film is more likely to occur. As shown in fig. 7, by not separating the semiconductor SMC between one of the source and the drain of the transistor M3 and one of the source and the drain of the transistor M5, processing failure caused when separating the semiconductor SMC between one of the source and the drain of the transistor M3 and one of the source and the drain of the transistor M5 can be prevented in some cases.

Modified example of display device 1

Note that the pixel of the display device according to one embodiment of the present invention described above is not limited to the pixel PX shown in fig. 2. The display device according to one embodiment of the present invention may be configured by appropriately changing the pixel PX shown in fig. 2.

Fig. 8A shows a modification example of the pixel PX of fig. 2. The pixel PX shown in fig. 8A is different from the pixel PX of fig. 2 in that the transistor M2 includes a back gate.

Specifically, as an example, the transistor M2 shown in fig. 8A has a structure including a gate above and below a channel, and the transistor M2 includes a first gate and a second gate. As an example, for convenience, the first gate is referred to as a gate (sometimes referred to as a front gate) and the second gate is referred to as a back gate, but the first gate and the second gate may be interchanged. Therefore, in this specification and the like, the "gate" may be exchanged for the "back gate". Likewise, a "back gate" may be exchanged for a "gate". Specifically, the connection structure of "the gate is electrically connected to the first wiring and the back gate is electrically connected to the second wiring" may be replaced with a connection structure of "the back gate is electrically connected to the first wiring and the gate is electrically connected to the second wiring".

In addition, the pixel PX of the display device according to one embodiment of the present invention does not depend on the connection structure of the back gate of the transistor. The back gate is shown in the transistor M2 shown in fig. 8A without showing the connection structure of the back gate, but the electrical connection point of the back gate may be decided at the time of design. For example, in a transistor including a back gate, the gate may be electrically connected to the back gate in order to increase the on-state current of the transistor. That is, the gate and the back gate of the transistor M2 may be electrically connected. For example, in a transistor including a back gate, a wiring electrically connected to an external circuit or the like is provided to change the threshold voltage or the like of the transistor or reduce the off-state current of the transistor, and a fixed potential or a variable potential is applied to the back gate of the transistor by the external circuit or the like. The same applies to the transistor described in other portions of the specification and the transistor shown in other drawings except fig. 8A.

In the pixel PX of fig. 8A, the gate of the transistor M2 is electrically connected to the first terminal of the switch SW3, the first terminal of the switch SW1, and the first terminal of the capacitor C1, but as shown in fig. 8B, in the pixel PX, the back gate of the transistor M2 may be electrically connected to the first terminal of the switch SW3, the first terminal of the switch SW1, and the first terminal of the capacitor C1, but may not be electrically connected to the gate of the transistor M2.

As described above, as the switches SW1, SW3, SW5, and SW6 included in the pixel PX shown in fig. 2, electrical switches such as transistors may be used. Specifically, as shown in fig. 8C, in the pixel PX, a transistor M1, a transistor M3, a transistor M5, and a transistor M6 may be included as the switch SW1, the switch SW3, the switch SW5, and the switch SW6, respectively. Note that as the transistor M1, the transistor M3, the transistor M5, and the transistor M6, each of the transistors usable for the transistor M2 can be used.

As described above, the display device DSP1A of fig. 2 performs potential conversion of the image data signal by using the capacitor C1 in the pixel PX and the capacitor C2 outside the pixel PX. For example, when the voltage for correcting the threshold voltage of the transistor M2 is written to the capacitor C1, since the potential obtained by multiplying the potential change of the node N2 by C ₁/(C₁+C₂) is added to the potential of the node N1 by the potential change of the node N2, the voltage for correcting the threshold voltage of the transistor M2 written to the capacitor C1 may be shifted (when the potential change of the node N2 is the same as the potential change of the node N1, the voltage for correcting the threshold voltage of the transistor M2 written to the capacitor C1 may not be shifted). However, according to the timing charts of fig. 3A and 3B, in the display device DSP1A of fig. 2, the potential of the node N2 does not change in a period other than the period T11, the period T16, and the period T17, and the node N1 and the first terminal of the capacitor C2 are in a non-conductive state, so that the potential change of the node N1 due to the potential change of the node N2 is not affected by the capacitor C2. That is, when the potential of the node N2 changes, the amount of change in the potential of the node N1 is substantially the same as the amount of change in the potential of the node N2.

Modified example of display device 2

Next, fig. 9 shows an example of the display device DSP0 of fig. 1, which is different from the display device DSP 1A. The display device DSP1B shown in fig. 9 is a modified example of the display device DSP1A of fig. 2, and is different from the display device DSP1A in that: a capacitor C2I is provided in the pixel PX; and the capacitor C2 is not provided in the circuit CD.

Therefore, in the description of the display device DSP1B, the description of the display device DSP1A is referred to for a portion common to the content of the display device DSP 1A.

In the display device DSP1B, a first terminal of the capacitor C2I is electrically connected to a second terminal of the switch SW 1. In addition, a second terminal of the capacitor C2I is electrically connected to the wiring SL.

The first terminal of the switch SW11 is electrically connected to the wiring SL and the first terminal of the switch SW 12.

In the display device DSP1B, an electrical connection point of the first terminal of the switch SW11, the first terminal of the switch SW12 and the capacitor C2I is referred to as a node N3. Note that in the display device DSP1B of the present configuration example, the node N3 may be replaced with the wiring SL in some cases.

In the display device DSP1B, the capacitor C2I corresponds to the capacitor C2 of the display device DSP 1A. That is, the display device DSP1B has a structure in which a capacitor C2 included in the circuit CD in the display device DSP1A is provided as a capacitor C2I in the pixel PX. Therefore, the operation method of the display device DSP1B may be described by replacing the capacitor C2 with the capacitor C2I in the operation method of the display device DSP 1A.

In the display device DSP1B, an image can be displayed on the pixel PX by correcting the threshold voltage of the transistor M2 of the pixel PX by performing the same operation method as in the display device DSP 1A.

Note that the display device according to one embodiment of the present invention is not limited to the structure of the display device DSP 1B. The display device according to one embodiment of the present invention may have a structure in which the display device DSP1B is appropriately changed.

Fig. 10 shows a modification of the display device DSP1B of fig. 9. The display device DSP1C shown in fig. 10 is different from the display device DSP1B of fig. 9 in that: a second terminal of the switch SW1 is electrically connected to the wiring SL but not to the first terminal of the capacitor C2I; a first terminal of the switch SW1 is electrically connected to the second terminal of the capacitor C2I without being electrically connected to the gate of the transistor M2, the first terminal of the switch SW3 and the first terminal of the capacitor C1; and a first terminal of the capacitor C2I is electrically connected to the gate of the transistor M2, the first terminal of the switch SW3, and the first terminal of the capacitor C1.

That is, the capacitor C2I, the switch SW1, the capacitor C1, and the light emitting device LD are sequentially provided on the electrical path from the wiring SL to the wiring VE0 in the display device DSP1B, and the switch SW1, the capacitor C2I, the capacitor C1, and the light emitting device LD are sequentially provided on the electrical path from the wiring SL to the wiring VE0 in the display device DSP 1C.

Note that in this specification and the like, an electrical connection point between the first terminal of the switch SW1 and the second terminal of the capacitor C2I is referred to as a node N4.

In the display device DSP1C, the capacitor C2I corresponds to the capacitor C2 of the display device DSP 1A. In the display device DSP1C, the node N4 corresponds to the node N3 of the display device DSP 1A. That is, the display device DSP1C has a structure in which a capacitor C2 included in the circuit CD in the display device DSP1A is provided as a capacitor C2I in the pixel PX. Therefore, in some cases, the operation method of the display device DSP1C may be described by replacing the capacitor C2 with the capacitor C2I and replacing the node N3 with the node N4 in the operation method of the display device DSP 1A.

In the display device DSP1C, an image may be displayed on the pixel PX by correcting the threshold voltage of the transistor M2 of the pixel PX by the same operation method as in the display device DSP 1A.

Fig. 11 shows another modification of the display device DSP1A different from the display device DSP1C shown in fig. 10. The display device DSP1D shown in fig. 11 is an example of further changing the display device DSP1C of fig. 10, and is different from the display device DSP1C in that: the pixel PX is provided with a switch SW11I; and the switch SW11 is not provided in the circuit CD. That is, the display device DSP1D shown in fig. 11 is different from the display device DSP1A in that: the pixel PX is provided with a switch SW11I and a capacitor C2I; and the switch SW11 and the capacitor C2 are not provided in the circuit CD.

In the display device DSP1D, a first terminal of the switch SW11I is electrically connected to a first terminal of the switch SW1 and a second terminal of the capacitor C2I. In addition, a second terminal of the switch SW11I is electrically connected to the wiring VE 3. The control terminal of the switch SW11I is electrically connected to the wiring GL 11.

The first terminal of the capacitor C2I is electrically connected to the first terminal of the switch SW3, the first terminal of the capacitor C1, and the gate of the transistor M2. In addition, a second terminal of the switch SW1 is electrically connected to the wiring SL.

In addition, a first terminal of the switch SW12 is electrically connected to the wiring SL.

Like the wirings GL1, GL3, GL5, and GL6, the wiring GL11 corresponds to one of the wirings GL [1] to GL [ m ] of fig. 1. That is, in the case of adopting the circuit configuration of the pixel PX shown in fig. 11, the number of wirings GL extending on one row of the pixel array ALP is 5.

In the display device DSP1D, the capacitor C2I corresponds to the capacitor C2 of the display device DSP 1A. The switch SW11I corresponds to the switch SW11 of the display device DSP 1A. The line GL11 corresponds to the line SWL11 of the display device DSP 1A. The node N4 corresponds to the node N3 of the display device DSP 1A. That is, the display device DSP1D has a structure in which the switch SW11 and the capacitor C2 included in the circuit CD in the display device DSP1A are provided as the switch SW11I and the capacitor C2I in the pixel PX, respectively. Therefore, in the operation method of the display device DSP1A, the switch SW11 may be replaced with the switch SW11I, the capacitor C2 may be replaced with the capacitor C2I, the node N3 may be replaced with the node N4, and the wiring SWL11 may be replaced with the wiring GL11, whereby the operation method of the display device DSP1D may be described.

In the display device DSP1D, an image can be displayed on the pixel PX by correcting the threshold voltage of the transistor M2 of the pixel PX by performing the same operation method as in the display device DSP 1A.

In addition, as described in the operation method of the display device DSP1A, the potentials applied to the wiring VE2 and the wiring VE3, respectively, can be made equal to each other. In this case, the wiring VE2 and the wiring VE3 may be combined into one wiring. As an example, fig. 12 shows a display device DSP1DA in which a wiring VE2 and a wiring VE3 in the display device DSP1D are combined into one wiring VE3.

In addition, as described in the operation method of the display device DSP1A, the potentials applied to the wiring VE1 and the wiring VE3, respectively, can be made equal to each other. In this case, the wiring VE1 and the wiring VE3 may be combined into one wiring. As an example, fig. 13 shows a display device DSP1DB in which a wiring VE1 and a wiring VE3 in the display device DSP1D are combined into one wiring VE1.

Fig. 14 shows another modification of the display device DSP1A different from the display device DSP1B of fig. 9, the display device DSP1C of fig. 10, the display device DSP1D of fig. 11, the display device DSP1DA of fig. 12, and the display device DSP1DB of fig. 13. The display device DSP1E shown in fig. 14 is an example of further changing the display device DSP1D of fig. 11, and is different from the display device DSP1D in that the switch SW12 is not provided in the circuit CD. That is, the display device DSP1E shown in fig. 14 is different from the display device DSP1A in that: the pixel PX is provided with a switch SW11I, a switch SW12I, and a capacitor C2I; and no circuit CD is provided.

Note that, in the display device DSP1E, the switch SW1 of the display device DSP1D is referred to as a switch SW12I, and the wiring GL1 of the display device DSP1D is referred to as a wiring GL12 for convenience.

In the display device DSP1E, the driving circuit SD is electrically connected to the wiring SL, and the wiring SL is electrically connected to the second terminal of the switch SW 12I.

The switch SW12I provided in the display device DSP1E may also serve as the switch SW1 provided in the pixel PX in the display device DSP 1D. Therefore, the structure of the display device DSP1D can be changed to a structure in which the switch SW12 is not provided in the circuit CD as shown in the display device DSP1E of fig. 14.

Therefore, in the operation method of the display device DSP1A, the switch SW11 may be replaced with the switch SW11I, the capacitor C2 may be replaced with the capacitor C2I, the node N3 may be replaced with the node N4, the wiring SWL11 may be replaced with the wiring GL11, and the wiring SWL12 may be replaced with the wiring GL12, whereby the operation method of the display device DSP1E may be described. Note that the signal supplied from the wiring GL1 of the display device DSP1A may not be considered in the display device DSP 1E.

Modified example of display device 3

Next, fig. 15 shows an example of the display device DSP0 of fig. 1, which is different from the display devices DSP1A to DSP 1E. The display device DSP1F shown in fig. 15 is a modified example of the display device DSP1A of fig. 2, and is different from the display device DSP1A in that: a switch SW4 is provided in series electrical connection between the second terminal of the capacitor C1, the first terminal of the transistor M2, and the first terminal of the switch SW6 and the light emitting device LD; a switch SW9 is provided in parallel electrical connection with the light emitting device LD.

As the switch SW4 and the switch SW9, for example, a switch usable for the switch SW1, the switch SW3, the switch SW5, the switch SW6, the switch SW11, or the switch SW12 can be used. The switch SW4 and the switch SW9 are both in an on state when a high-level potential is applied to their control terminals, and in an off state when a low-level potential is applied to their control terminals.

A first terminal of the switch SW4 is electrically connected to the second terminal of the capacitor C1, the first terminal of the transistor M2, and the first terminal of the switch SW 6. In addition, a second terminal of the switch SW4 is electrically connected to the anode of the light emitting device LD and a first terminal of the switch SW 9. The control terminal of the switch SW4 is electrically connected to the wiring GL 4.

A second terminal of the switch SW9 is electrically connected to the cathode of the light emitting device LD and the wiring VE 0. The control terminal of the switch SW9 is electrically connected to the wiring GL 9.

In the display device DSP1F of fig. 15, like the wirings GL1, GL3, GL5, and GL6, the wirings GL4 and GL9 correspond to one of the wirings GL [1] to GL [ m ] of fig. 1. That is, in the case of adopting the circuit configuration of the pixel PX shown in fig. 15, the number of wirings GL extending on one row of the pixel array ALP is 6.

Next, an example of an operation method of the display device DSP1F of fig. 15 is described.

Fig. 16 is a timing chart showing an example of an operation method of the display device DSP 1F. Specifically, the timing chart of fig. 16 is a modified example of the timing chart of fig. 3A, in which potential changes of the wiring GL4 and the wiring GL9 are added to the timing chart of fig. 3A. Therefore, operations other than the potential change of the wirings GL4 and GL9 of the display device DSP1F are described with reference to the timing chart of fig. 3A.

In the period T16, the high-level potential is applied to the line GL4, and the low-level potential is applied to the line GL 9. Thereby, the control terminal of the switch SW4 is applied with a high-level potential, so the switch SW4 is in an on state. In addition, the control terminal of the switch SW9 is applied with a low-level potential, whereby the switch SW9 is in an off state.

That is, in the period T16, each of the wiring VE0 and the cathode of the light emitting device LD is in a non-conductive state with the anode of the light emitting device LD, so the anode of the light emitting device LD is not applied with the potential V _CT from the wiring VE0 through the switch SW 9. On the other hand, during the period T16, both the switch SW5 and the switch SW4 are in the on state, so that the current from the wiring VE2 flows through the anode of the light emitting device LD. Accordingly, the light emitting device LD emits light.

In the period T11 to the period T15 and the period T17, the low-level potential is applied to the wiring GL4, and the high-level potential is applied to the wiring GL 9. Thereby, the control terminal of the switch SW4 is applied with a low-level potential, so the switch SW4 is in an off state. In addition, the control terminal of the switch SW9 is applied with a high-level potential, so the switch SW9 is in an on state.

That is, in the period T11 to the period T15 and the period T17, each of the wiring VE0 and the cathode of the light emitting device LD is in a conductive state with the anode of the light emitting device LD, whereby the voltage between the anode and the cathode of the light emitting device LD becomes 0V. In addition, since the switch SW4 is in the off state, a current flows between the node N2 and the anode of the light emitting device LD without passing through the switch SW 4.

In particular, although the periods T11 to T15 and T17 are periods in which the light emitting device LD does not emit light, the charge stored in the anode of the light emitting device LD can be discharged to the wiring VE0 through the switch SW9 by turning on the switch SW9 during these periods. That is, during the period in which the light emitting device LD does not emit light, the discharge rate of the electric charges stored in the anode of the light emitting device LD of the display device DSP1F can be faster than that of the display devices (for example, the display devices DSP1A to DSP 1E) in which the switch SW9 is not provided. Thereby, the light emitting state of the light emitting device LD can be more quickly shifted to the quenching state.

Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification.

(Embodiment 2)

In this embodiment, a display device according to an embodiment of the present invention different from the display device DSP1A described above will be described.

< Structural example of display device 1>

Fig. 17 shows examples of the respective structures of pixels PX and circuits CD that can be used in the display device DSP0 of fig. 1 described in embodiment 1. As in fig. 2, the display device DSP2A shown in fig. 17 selectively shows one of the plurality of pixels PX included in the pixel array ALP, the driving circuit GD of the row driving circuit RWD electrically connected to the pixel PX, the circuit CD of the column driving circuit CLM, and the driving circuit SD.

In the display device DSP2A of fig. 17, as an example, the pixel PX includes a transistor M2, a switch SW1, a switch SW4, a switch SW6, a switch SW7, a switch SW8, a capacitor C1, a capacitor C3, and a light emitting device LD. The circuit CD includes a switch SW11, a switch SW12, a switch SW13 and a capacitor C2.

Note that the transistor M2 shown in fig. 17 may use a transistor usable for the transistor M2 shown in fig. 2. Note that the transistor M2 of fig. 17 includes a back gate, which differs from the transistor M2 of fig. 2 in this point.

As the switches SW1, SW4, SW6, SW7, SW8, SW11, SW12 and SW13 shown in fig. 17, switches usable for the switches SW1, SW3, SW5, SW6, SW11 and SW12 shown in fig. 2 can be used.

In the present specification and the like, the switches SW1, SW4, SW6, SW7, SW8, SW11, SW12 and SW13 shown in fig. 17 are all in an on state when a high-level potential is applied to their control terminals, and in an off state when a low-level potential is applied to their control terminals.

The description of the light emitting device LD described in embodiment 1 is referred to.

In the pixel PX, a first terminal of the switch SW1 is electrically connected to the gate of the transistor M2, a first terminal of the switch SW8, and a first terminal of the capacitor C1, a second terminal of the switch SW1 is electrically connected to the wiring SL, and a control terminal of the switch SW1 is electrically connected to the wiring GL 1. The first terminal of the transistor M2 is electrically connected to the first terminal of the switch SW4, the first terminal of the switch SW6, the second terminal of the switch SW8, the second terminal of the capacitor C1 and the first terminal of the capacitor C3, the second terminal of the transistor M2 is electrically connected to the wiring VE2, and the back gate of the transistor M2 is electrically connected to the second terminal of the capacitor C3 and the first terminal of the switch SW 7. In addition, a second terminal of the switch SW4 is electrically connected to the anode of the light emitting device LD, and a control terminal of the switch SW4 is electrically connected to the wiring GL 4. The second terminal of the switch SW6 is electrically connected to the wiring VE1, and the control terminal of the switch SW6 is electrically connected to the wiring GL 6. The second terminal of the switch SW7 is electrically connected to the wiring VE5, and the control terminal of the switch SW7 is electrically connected to the wiring GL 7. Further, the cathode of the light emitting device LD is electrically connected to the wiring VE 0.

Note that in this embodiment, an electrical connection point of the first terminal of the switch SW1, the first terminal of the switch SW8, the gate of the transistor M2, and the first terminal of the capacitor C1 is referred to as a node N1. The electrical connection point of the first terminal of the transistor M2, the second terminal of the capacitor C1, the first terminal of the capacitor C3, the first terminal of the switch SW4, the first terminal of the switch SW6, and the second terminal of the switch SW8 is referred to as a node N2. The electrical connection point between the back gate of the transistor M2, the second terminal of the capacitor C3, and the first terminal of the switch SW7 is referred to as a node NB.

In the circuit CD, a first terminal of the capacitor C2 is electrically connected to the wiring SL and a first terminal of the switch SW13, and a second terminal of the capacitor C2 is electrically connected to a first terminal of the switch SW11 and a first terminal of the switch SW 12. The second terminal of the switch SW11 is electrically connected to the wiring VE3, and the control terminal of the switch SW11 is electrically connected to the wiring SWL 11. A second terminal of the switch SW12 is electrically connected to the driving circuit SD, and a control terminal of the switch SW12 is electrically connected to the wiring SWL 12. The second terminal of the switch SW13 is electrically connected to the wiring VE4, and the control terminal of the switch SW13 is electrically connected to the wiring SWL 13.

The wirings VE0 to VE5 are each used as a wiring for applying a constant potential, for example. The constant potentials applied to each of the wirings VE0 to VE5 may be equal to or different from each other. Or in the potentials applied to each of the wirings VE0 to VE5, a part may be equal and the rest may be different. Further, one or more wirings selected from the wirings VE0 to VE5 may be used as wirings to which a pulse potential is applied without applying a constant potential.

In particular, in the pixel PX of fig. 17, the wiring VE0 is preferably used as a wiring for applying a potential to the cathode of the light emitting device LD. Further, the wiring VE2 is preferably used as a wiring for applying a potential to the anode of the light emitting device LD.

Note that in the case where the light emitting device LD included in the pixel PX of fig. 17 adopts a positive structure, the light emitting device LD of fig. 17 may also adopt an inverted structure. In this case, the wiring VE0 is used as a wiring for applying a potential to the anode of the light emitting device LD, and the wiring VE2 is used as a wiring for applying a potential to the cathode of the light emitting device LD.

The wirings GL1, GL4, GL6, and GL7 correspond to one of the wirings GL [1] to GL [ m ] of fig. 1. That is, in the case of adopting the circuit configuration of the pixel PX shown in fig. 17, the number of wirings GL extending on one row of the pixel array ALP is 4.

The wiring SWL11 and the wiring SWL12 are described with reference to the wiring SWL11 and the wiring SWL12 shown in fig. 2. In addition, the wiring SWL13 is used as a wiring for transmitting a control signal (digital potential) for switching the on state and the off state of the switch SW 13.

Working method of display device example 1

Next, an example of an operation method of the display device DSP2A of fig. 17 is described.

Fig. 18A to 18C are timing charts showing one example of the operation method of the display device DSP 1A. Specifically, the timing chart of fig. 18A shows potential changes of the wirings GL1, GL4, GL6, GL7, SWL11, SWL12, SWL13, and the node N3 in each of the periods T21 to T30. Fig. 18B shows the potential changes of the node N1 and the node N2 in each of the periods T21 to T30, and fig. 18C shows the potential changes of the node N2 and the node NB in each of the periods T21 to T30. In fig. 18B and 18C, the potential change of the node N1 is shown by a solid line, the potential change of the node N2 is shown by a chain line, and the potential change of the node NB is shown by a two-dot chain line.

In fig. 18A, high represents a High-level potential, and Low represents a Low-level potential.

The wiring VE1 is applied with V _N1 as a constant potential. Further, the wiring VE3 is applied with V _ref as a constant potential. Further, the wiring VE5 is applied with V _N5 as a constant potential. Note that although V _N1 is a potential lower than V _N5 in fig. 18C, V _N1 may be a potential equal to V _N5 or a potential lower than V _N5.

In addition, V _N5 preferably has a potential that makes the threshold voltage of the transistor M2 lower than 0V when the voltage between the back gate and the source of the transistor M2 is V _N5-V_N1.

In addition, V _AN is a potential higher than V _N1. Further, the voltage of V _N1-V_CT is a voltage that does not cause the light emitting device LD to emit light (current does not flow between the anode and the cathode of the light emitting device LD). Therefore, V _N1 is preferably a potential equal to or lower than V _CT.

[ Before period T21 ]

Before the period T21, the low-level potential is applied to all of the wirings GL1, GL6, GL7, SWL11, SWL12, and SWL 13. Therefore, the control terminals of the switches SW1, SW6, SW7, SW8, SW11, SW12 and SW13 are applied with low-level potential, so that these switches are all in an off state.

In addition, a high-level potential is applied to the wiring GL4 before the period T21. Therefore, the control terminal of the switch SW4 is applied with a high-level potential, so the switch SW4 is in an on state.

Before the period T21, the potential of the node N3 is indefinite. Therefore, the potential of the node N3 before the period T21 of the timing chart of fig. 18A is shown in hatching.

In addition, since the switch SW4 is in an on state, when the voltage between the gate and the source of the transistor M2 is higher than the threshold voltage of the transistor M2, a current flows between the wiring VE2 and the wiring VE0 through the transistor M2, the switch SW4, and the light emitting device LD. Therefore, the light emitting device LD may emit light before the period T21.

Period T21

In the period T21, the high-level potential is applied to the wirings GL6, GL7, and SWL 11. Thus, the control terminals of the switches SW6, SW7, SW8 and SW11 are applied with a high-level potential, so that these switches are all in an on state.

Since the switch SW6 and the switch SW8 are both in an on state, each of the gate of the transistor M2, the first terminal of the capacitor C1, the second terminal of the capacitor C1, and the first terminal of the capacitor C3 is in an on state with the wiring VE 1. Accordingly, the potential V _N1 from the wiring VE1 is applied to the gate of the transistor M2 and the first terminal of the capacitor C1 (the node N1), the first terminal of the transistor M2, the second terminal of the capacitor C1, and the first terminal of the capacitor C3 (the node N2) (see fig. 18B and 18C).

In addition, since the switch SW7 is in an on state, each of the back gate of the transistor M2 and the second terminal of the capacitor C3 is in an on state with the wiring VE 5. Accordingly, the potential V _N5 from the wiring VE5 is applied to the back gate of the transistor M2 and the second terminal (node NB) of the capacitor C3 (see fig. 18C).

At this time, since the switch SW4 is in an on state, the potential V _N1 from the wiring VE1 is applied to the anode of the light emitting device. Therefore, the voltage between the anode and the cathode of the light emitting device LD is V _N1-V_CT. As described above, when the voltage between the anode and the cathode of the light emitting device LD is V _N1-V_CT, the light emitting device LD does not emit light (current does not flow between the anode and the cathode of the light emitting device LD). When the transistor M2 is turned on, a current flows from the wiring VE2 to the wiring VE1 through the transistor M2 and the switch SW 6.

In addition, since the switch SW11 is in an on state, each of the second terminal of the capacitor C2 and the first terminal of the switch SW12 is in an on state with the wiring VE 3. Therefore, the second terminal of the capacitor C2 and the first terminal (node N3) of the switch SW12 are applied with the potential V _ref from the wiring VE3 (see fig. 18A).

Note that, in the period T21 of the timing chart of fig. 18A, the high-level potential is inputted to each of the wirings GL6, GL7, and SWL11 at the same timing, but the timings at which the high-level potential is inputted to each of the wirings GL6, GL7, and SWL11 may be different from each other as long as the period T21 is provided.

Period T22

In the period T22, the low-level potential is applied to the wiring GL 4. Thereby, the control terminal of the switch SW4 is applied with a low-level potential, so the switch SW4 is in an off state. Accordingly, the first terminal of the transistor M2, the second terminal of the capacitor C1, and the first terminal of the capacitor C3 are each in a non-conductive state with the anode of the light emitting device LD.

Period T23

In the period T23, the low-level potential is applied to the wiring GL 6. Thereby, the control terminal of the switch SW6 is applied with a low-level potential, so the switch SW6 is in an off state.

The potential of the gate of the transistor M2 and the first terminal of the transistor M2 is V _N1, so the voltage between the gate and the source of the transistor M2 is 0V. When the threshold voltage of the transistor M2 is 0V or less, the transistor M2 is in an on state.

In addition, the voltage between the back gate and the source of the transistor M2 is V _N5-V_N1 immediately before the switch SW6 is in the off state. When the switch SW6 is in the off state, the wiring VE1 does not apply the potential V _N1 to the first terminal of the transistor M2 and the gate of the transistor M2, whereby positive charges are stored from the wiring VE2 through between the first terminal and the second terminal of the transistor M2 and the switch SW8 in the node N1 and the node N2. Thereby, the potentials of the node N1 and the node N2 rise.

When the potential of the node N1 and the node N2 rises, the voltage between the back gate and the source of the transistor M2 decreases. When the threshold voltage V _th of the transistor M2 reaches 0V of the voltage between the gate and the source of the transistor M2 due to the decrease in the voltage between the back gate and the source of the transistor M2, the transistor M2 is in the off state, and positive charge storage from the wiring VE2 is stopped. The voltage between the back gate and the source at this time is Δv _B. In addition, since the switch SW7 is turned on and the potential of the node NB is V _N5, the potentials of the node N1 and the node N2 at this time are V _N5-ΔV_B. When the transistor M2 is in the off state, the positive charge storage from the wiring VE2 is stopped, and thus the potentials of the node N1 and the node N2 do not change from V _N5-ΔV_B (see fig. 18B and 18C). In addition, since the transistor M2 is in the off state, the nodes N1 and N2 are in the floating state.

Period T24

In the period T24, the low-level potential is applied to the wiring GL 7. Thus, the control terminals of the switch SW7 and the switch SW8 are applied with a low-level potential, and thus both the switch SW7 and the switch SW8 are in an off state.

Since the switch SW7 is in the off state, each of the second terminal of the capacitor C3 and the back gate of the transistor M2 is in a non-conductive state with the wiring VE 5. At this time, the node NB is in a floating state. Thereby, the voltage Δv _B between the first terminal and the second terminal of the capacitor C3 can be maintained.

Further, since the switch SW8 is in the off state, the first terminal of the capacitor C1 and the gate of the transistor M2 are in a non-conductive state with the second terminal of the capacitor C1, the first terminal of the transistor M2 and the first terminal of the capacitor C3. At this time, the nodes N1 and N2 are in a floating state.

Period T25

In the period T25, the high-level potential is applied to each of the wirings GL1, GL6, and SWL 13. Accordingly, the control terminals of the switches SW1, SW6 and SW13 are applied with high-level potential, so that the switches SW1, SW6 and SW12 are in an on state.

Since the switch SW1 and the switch SW13 are both in an on state, each of the gate of the transistor M2, the first terminal of the capacitor C1, and the wiring SL is in an on state with the wiring VE 4. Therefore, the potential V _init from the wiring VE4 is applied to the gate of the transistor M2, the first terminal (node N1) of the capacitor C1, and the wiring SL (see fig. 18B).

In addition, since the switch SW6 is in an on state, each of the first terminal of the transistor M2, the second terminal of the capacitor C1, and the first terminal of the capacitor C3 is in an on state with the wiring VE 1. Accordingly, the potential V _N1 from the wiring VE1 is applied to the first terminal of the transistor M2, the second terminal of the capacitor C1, and the first terminal of the capacitor C3 (the node N2) (see fig. 18B and 18C).

At this time, the potential of the first terminal of the transistor M2, the second terminal of the capacitor C1, and the first terminal of the capacitor C3 (node N2) changes from V _N5-ΔV_B to V _N1, and thus the potential of the back gate of the transistor M2 (the second terminal of the capacitor C3 and the node NB) also changes due to the capacitive coupling of the capacitor C3. In this working example, the potential of the back gate (the second terminal of the capacitor C3 and the node NB) of the transistor M2 is reduced from V _N5 to V _N1+ΔV_B due to the operation in the period T25 (see fig. 18C). This corresponds to the case where the capacitive coupling coefficient near the node NB is 1.

Period T26

In the period T26, the low-level potential is applied to the wiring SWL 13. Thereby, the control terminal of the switch SW13 is applied with a low-level potential, so the switch SW13 is in an off state.

Since the switch SW13 is in an off state, each of the gate of the transistor M2, the first terminal (node N1) of the capacitor C1, and the wiring SL is in a non-conductive state with the wiring VE 4. At this time, the gate of the transistor M2, the first terminal (node N1) of the capacitor C1, and the wiring SL are in a floating state.

Period T27

In the period T27, the low-level potential is applied to the wiring SWL11, and the high-level potential is applied to the wiring SWL 12. Thereby, the control terminal of the switch SW11 is applied with a low-level potential, so the switch SW11 is in an off state. In addition, the control terminal of the switch SW12 is applied with a high-level potential, so the switch SW12 is in an on state.

Therefore, the potential of the node N3 changes from V _ref to V _data. Further, since the wiring SL and the node N1 are in a floating state, the potential of the wiring SL and the node N1 also changes with the potential change of the node N3 due to the capacitive coupling of the capacitor C2. The amounts of change in the potentials of the wiring SL and the node N1 depend on, for example, the capacitance of the capacitor C1, the capacitance of the capacitor C2, the gate capacitance of the transistor M2, the parasitic capacitance related to the switch SW1, the parasitic capacitance related to the switch SW8, and the parasitic capacitance related to the wiring SL. In this working example, for simplicity of explanation, it is assumed that the amounts of change in the potential of the wiring SL and the node N1 depend on the capacitance of the capacitor C1 and the capacitance of the capacitor C2.

When the capacitance of the capacitor C1 is C ₁, the capacitance of the capacitor C2 is C ₂, and the potential of the node N3 is changed from V _ref to V _data, the potentials of the wiring SL and the node N1 are applied with Δv _data＝(V_data-V_ref)×C₂/(C₁+C₂ as a change amount. Therefore, the potential of the wiring SL and the node N1 becomes V _init+ΔV_data (see fig. 18B).

On the other hand, since the potential V _N1 from the wiring VE1 is applied to the second terminal (node N2) of the capacitor C1 from before the period T27, the potential of the second terminal (node N2) of the capacitor C1 remains V _N1 without change even when the potential of the node N3 changes from V _ref to V _data.

Thus, when the voltage between the gate and the source of the transistor M2 in the period T27 is V _drv, V _drv = (potential of the node N1) - (potential of the node N2) =v _init+ΔV_data-V_N1 holds. Therefore, during the period T27, the voltage held between the first terminal and the second terminal of the capacitor C1 is V _drv＝V_init+ΔV_data-V_N1.

In addition, the voltage V _drv between the gate and the source of the transistor M2 is greater than the threshold voltage (0V) of the transistor M2, so the transistor M2 is in an on state. However, since the switch SW4 and the switch SW8 are in an off state and the switch SW6 is in an on state, a current flows between the wiring VE2 and the wiring VE1 through the transistor M2 and the switch SW 6.

Period T28

In the period T28, the low-level potential is applied to the wiring GL 1. Thereby, the control terminal of the switch SW1 is applied with a low-level potential, so the switch SW1 is in an off state.

When the switch SW1 is turned off, the gate of the transistor M2 and the first terminal of the capacitor C1 are in a non-conductive state with the wiring SL. Since the switch SW8 is turned off from the period T24, the first terminal (node N1) of the capacitor C1 is kept at the potential V _init+ΔV_data.

Period T29

In the period T29, the high-level potential is applied to the line GL4, and the low-level potential is applied to the line GL 6. Thereby, the control terminal of the switch SW4 is applied with a high-level potential, so the switch SW4 is in an on state. In addition, the control terminal of the switch SW6 is applied with a low-level potential, whereby the switch SW6 is in an off state.

Since the switch SW4 is in an on state, a first terminal of the transistor M2 is in an on state with the anode of the light emitting device LD. Further, since the switch SW6 is in an off state, the first terminal of the transistor M2, the second terminal of the capacitor C1, and the first terminal of the capacitor C3 are each in a non-conductive state with the wiring VE 1. Since the switch SW8 is turned off from the period T24, the first terminal (node N2) of the transistor M2 and the gate (node N1) of the transistor M2 are in a non-conductive state.

In addition, the voltage between the gate and the source of the transistor M2 is V _drv＝V_init+ΔV_data. In addition, since V _drv is larger than the threshold voltage (0V) of the transistor M2, the transistor M2 is in an on state.

Accordingly, a current flows between the wiring VE0 and the wiring VE2 through the transistor M2, the switch SW4, and the light emitting device LD.

At this time, the voltage V _AN-V_CT between the wiring VE0 and the wiring VE2 is divided by the transistor M2, the light-emitting device LD, and the switch SW 4. In this working example, the potential of the first terminal of the transistor M2 (the second terminal of the capacitor C1, the first terminal of the capacitor C3, and the node N2) is boosted from V _N1 to V _S by the operation in the period T29 (see fig. 18B and 18C).

The potential of the first terminal of the transistor M2 (the second terminal of the capacitor C1 and the node N2) is boosted from V _N1 to V _S, whereby the potential of the gate of the transistor M2 (the first terminal of the capacitor C1 and the node N1) also changes due to the capacitive coupling of the capacitor C1. In this working example, the potential of the gate (the first terminal of the capacitor C1 and the node N1) of the transistor M2 is boosted from V _init+ΔV_data to V _G by the operation in the period T29 (see fig. 18B).

Note that the amount of change in the potential of the node N1 occurring due to the capacitive coupling of the capacitor C1 described above depends on the electrostatic capacitance of the capacitor C1, the gate capacitance of the transistor M2, and the parasitic capacitance related to the switch SW 1. Note that in this working example, for simplicity of explanation, the amount of change in the potential of the node N1 is equal to the amount of change in the potential of the node N2. That is, when the amount of change in the potential of the node N2 is Δvc1 (=v _S-V_N1), the amount of change in the potential of the node N1 is also Δvc1. This corresponds to the case where the capacitive coupling coefficient around the node N1 is 1.

Note that since Δv _c1＝V_G-(V_init+ΔV_data) is satisfied in the node N1, V _G-V_S＝V_init+ΔV_data-V_N1＝V_drv can be obtained by substituting the amount of change Δv _c1＝V_S-V_N1 in the potential of the node N2 into the expression. That is, the voltage between the gate and the source of the transistor M2 in the period T29 does not change after the image data signal is input to the circuit CD in the period T27.

In addition, the potential of the first terminal of the transistor M2 (the second terminal of the capacitor C1 and the node N2) is boosted from V _N1 to V _S, whereby the potential of the back gate of the transistor M2 (the second terminal of the capacitor C3 and the node NB) also changes due to the capacitive coupling of the capacitor C3. In this working example, when the capacitive coupling coefficient in the vicinity of the node N3 is 1 by the operation of the period T29, the potential of the back gate of the transistor M2 (the second terminal of the capacitor C3 and the node NB) is boosted from V _N1+ΔV_B to V _N1+ΔV_B+ΔV_c1 (see fig. 18℃ Note that V _BG＝V_N1+ΔV_B+ΔV_C1 in fig. 18C). Note that at this time, the voltage between the back gate and the source of the transistor M2 remains Δv _B unchanged, and thus the threshold voltage of the transistor M2 remains 0V.

Here, consider a case where the transistor M2 operates in a saturation region. The amount of current flowing between the first terminal and the second terminal of the transistor M2 is determined according to the voltage V _drv between the gate and the source of the transistor M2. Specifically, the amount I of current flowing between the source and the drain of the transistor operating in the saturation region is proportional to the square of the difference between the voltage V _GS between the gate and the source of the transistor and the threshold voltage V _th of the transistor, so i=k (V _GS-V_th)² holds, note that k is a proportionality constant depending on the structure of the transistor by substituting the voltage V _drv between the gate and the source of the transistor M2 into V _GS of the above expression and into V _th＝0,I＝k(V_init+ΔV_data)² holds, the amount I of current flowing through the transistor M2 does not depend on the threshold voltage V _th but depends on V _init+ΔV_data.

As described above, by performing the operations from the period T21 to the period T30, the transistor M2 can generate a current independent of the threshold voltage V _th of the transistor M2.

In addition, since the potential of the anode of the light emitting device LD is V _S, the potential between the anode and the cathode of the light emitting device LD is V _S-V_CT. Further, a current (i=k (vinit+Δvdata) ²) flowing between the source and the drain of the transistor M2 flows between the anode and the cathode of the light emitting device LD, so the light emitting device LD emits light. In the case where the light emitting device LD is an organic EL element, the light emitting luminance of the light emitting device LD depends on the amount of current flowing between the anode and the cathode of the light emitting device LD. Since Vinit is a constant potential, the light emission luminance of the light emitting device LD depends on the image data signal Vdata input from the driving circuit SD.

In addition, as in the description of the potential change shown in fig. 4A to 4C, when the minimum value of the gray level of the pixel is vdata_min and the maximum value of the gray level of the pixel is vdata_max, since the image data signal Vdata output from the driving circuit SD passes through the circuit CD, the pixel PX is input to any one of vinit+k× (vdata_min-Vref) to vinit+k× (vdata_max-Vref). Note that k=c ₂/(C₁+C₂).

In the case where Vref is lower than Vinit, the relationship of each of the image data signals vdata_min to vdata_max output from the driving circuit SD and vinit+k× (vdata_min-Vref) to vinit+k× (vdata_max-Vref) input to the pixel PX through the circuit CD is as shown in fig. 19A. In addition, in the case where Vref is higher than Vinit, the relationship of each of the image data signals vdata_min to vdata_max output from the driving circuit SD and vinit+k× (vdata_min-Vref) to vinit+k× (vdata_max-Vref) input to the pixel PX through the circuit CD is shown in fig. 19B. Further, in the case where Vref is equal to Vinit, the relationship of each of the image data signals vdata_min to vdata_max output from the driving circuit SD and vinit+k× (vdata_min-Vref) to vinit+k× (vdata_max-Vref) input to the pixel PX through the circuit CD is shown in fig. 19C.

That is, as in fig. 4A to 4C, when the image data signal output from the driving circuit SD is input to the pixel PX via the circuit CD, the potential range of the image data signal becomes narrow, and the step size of the potential of the image data signal also becomes small. Thus, the potential of the image data signal input to the pixel PX can be finely changed, so that the amount of current flowing between the source and the drain of the transistor M2 can be finely changed.

Note that in the period T29 of the timing chart of fig. 18A, the high-level potential and the low-level potential are input to the wiring GL4 and the wiring GL6 at the same timing, but the timings of inputting the potentials to the wiring GL4 and the wiring GL6 may be different from each other as long as in the period T29.

Period T30

In the period T30, the low-level potential is applied to both the wiring GL4 and the wiring SWL12, and the high-level potential is applied to the wiring GL 6. Thus, the control terminals of the switch SW4 and the switch SW12 are applied with a low-level potential, and thus both the switch SW4 and the switch SW12 are in an off state. In addition, the control terminal of the switch SW6 is applied with a high-level potential, whereby the switch SW6 is in an on state.

Since the switch SW4 is in the off state, the second terminal of the transistor M2 is in a non-conductive state with the light emitting device LD. Further, since the switch SW6 is in an on state, each of the first terminal of the transistor M2, the second terminal of the capacitor C1, the first terminal of the capacitor C3, and the anode of the light emitting device LD is in an on state with the wiring VE 1. Accordingly, the potential V _N1 from the wiring VE1 is applied to the first terminal of the transistor M2, the second terminal of the capacitor C1, and the anode (node N2) of the light-emitting device LD (see fig. 18B and 18C).

At this time, the voltage between the anode and the cathode of the light emitting device LD is V _N1-V_CT. As described above, when the voltage between the anode and the cathode of the light emitting device LD is V _N1-V_CT, the light emitting device LD does not emit light (current does not flow between the anode and the cathode of the light emitting device LD).

That is, by performing the operation for the period T30, the light emission of the light emitting device LD can be stopped.

By performing the operations from the period T21 to the period T30, the transistor M2 of the pixel PX can generate a current independent of the threshold voltage V _th of the transistor M2, and the current can be supplied to the light emitting device LD, as in the display device DSP1A of embodiment 1.

Further, by performing the operations from the period T21 to the period T30, the amount of current flowing through the light emitting device LD of the pixel PX of the display device DSP2A can be controlled more finely, as in the display device DSP1A of embodiment 1.

Working method of display device example 2

In fig. 18A to 18C, the operation of one pixel PX included in the pixel array ALP of the display device DSP2A is described. Here, the operation of the entire pixel array ALP in the display device DSP0 using the display device DSP2A will be described.

The operation of the entire pixel array ALP in the display device DSP0 using the display device DSP2A can be the same as the operation of the entire pixel array ALP in the display device DSP0 using the display device DSP1A described in embodiment 1. That is, as an example of the operation of the entire pixel array ALP in the display device DSP0 using the display device DSP2A, the timing chart of fig. 5 can be used. Next, regarding this operation, a portion different from the operation of the entire pixel array ALP in the display device DSP0 using the display device DSP1A described in embodiment 1 will be described, and for the other portion, reference will be made to the description of embodiment 1.

The line GL1[1] corresponds to the line GL1 of fig. 17 extending in the first row in the pixel array ALP of the display device DSP 0. Similarly, the wiring GL1[2] corresponds to the wiring GL1 of fig. 17 extending in the second row in the pixel array ALP of the display device DSP0, and the wiring GL1[ m ] corresponds to the wiring GL1 of fig. 17 extending in the m-th row in the pixel array ALP of the display device DSP 0.

The line GL6[1] corresponds to the line GL6 of fig. 17 extending in the first row in the pixel array ALP of the display device DSP 0. Similarly, the line GL6[2] corresponds to the line GL6 of fig. 17 extending in the second row in the pixel array ALP of the display device DSP0, and the line GL1[ m ] corresponds to the line GL6 of fig. 17 extending in the m-th row in the pixel array ALP of the display device DSP 0.

The capacitor C1[1,1] corresponds to the capacitor C1 of fig. 17 in the pixel PX [1,1] included in the pixel array ALP of the display device DSP 0. Similarly, the capacitor C1[1,2] corresponds to the capacitor C1 of fig. 17 in the pixel PX [1,2] (not shown in fig. 1) included in the pixel array ALP of the display device DSP0, and the capacitor C1[1, n ] corresponds to the capacitor C1 of fig. 17 in the pixel PX [1, n ] included in the pixel array ALP of the display device DSP 0. Hereinafter, the description of "capacitor C1[ i, j ]" is regarded as the capacitor C1 of fig. 17 corresponding to the pixel PX [ i, j ] included in the pixel array ALP of the display device DSP 0.

In each of the periods U1, U3, and U6 in the timing chart of fig. 5, the plurality of pixels PX in the predetermined row are operated from the period T21 to the period T26 in the timing chart of fig. 18A. In each of the periods U2, U4, and U7 in the timing chart of fig. 5, the plurality of pixels PX in the predetermined row are operated from the period T27 to the period T30 in the timing chart of fig. 18A.

As described above, by performing the operations of the periods U1 to U7, the display device DSP0 using the display device DSP2A can display an image. The image displayed on the display device DSP0 may be updated every time the operations of the periods U1 to U7 are repeated.

Layout example of display device

Fig. 20 is a layout diagram (plan view) showing an example of a partial circuit configuration of the display device DSP2A of fig. 17. Specifically, fig. 20 shows a layout diagram of the pixels PX. Note that, as an example, the layout of the circuit CD of the display device DSP2A refers to the layout of fig. 6A.

In the layout diagram of fig. 20, the transistor M1 is used as the switch SW1 included in the pixel PX of fig. 17, the transistor M4 is used as the switch SW4 included in the pixel PX of fig. 17, the transistor M6 is used as the switch SW6 included in the pixel PX of fig. 17, the transistor M7 is used as the switch SW7 included in the pixel PX of fig. 17, and the transistor M8 is used as the switch SW 8.

In fig. 20, the pixel PX includes a conductor BGM, a conductor GEM, a conductor SDMB, a conductor SDMT, a semiconductor SMC, and a conductor PLG. Note that fig. 20 does not illustrate an insulator included in the display device DSP 2A.

As an example, the electrical conductor BGM is located below the semiconductor SMC. Further, as an example, the semiconductor SMC is located below the conductor GEM. Further, as an example, the conductor GEM is located below the conductor SDMB. Further, as an example, conductor SDMB is located below conductor SDMT. That is, in fig. 20, the circuit CD and the pixel PX are sequentially formed with the conductor BGM, the semiconductor SMC, the conductor GEM, the conductor SDMB, and the conductor SDMT.

As an example, a part of the conductor GEM is used as the gate (sometimes referred to as a first gate) of each of the transistors M1, M2, M4, M6, M7, and M8. Further, a part of the electric conductor BGM is used as, for example, a back gate (sometimes referred to as a second gate) of the transistor M2.

The conductors BGM, SMC, GEM, SDMB, SDMT may be formed by photolithography, for example. Specifically, for example, when forming the conductor GEM, a conductive material to be the conductor GEM may be formed by one or more methods selected from the group consisting of a sputtering method, a CVD method, a PLD method, and an ALD method, and then a desired pattern may be formed by photolithography. The conductor BGM, the semiconductor SMC, the conductor SDMB, and the conductor SDMT may be formed by the same method as described above.

Further, insulators may be provided between the conductor BGM and the semiconductor SMC, between the semiconductor SMC and the conductor GEM, between the conductor GEM and the conductor SDMB, and between the conductor SDMB and the conductor SDMT, respectively. In particular, an insulator provided between the semiconductor SMC and the conductor GEM is sometimes used as a first gate insulating film (sometimes referred to as a front gate insulating film). Further, an insulator provided between the electric conductor BGM and the semiconductor SMC is sometimes used as a second gate insulating film (sometimes referred to as a back gate insulating film).

Further, between the conductor BGM and the conductor SDMT, between the semiconductor SMC and the conductor SDMB, between the semiconductor SMC and the conductor SDMT, and between the conductor GEM and the conductor SDMT, respectively, a conductor PLG serving as a wiring or a plug is provided. For example, an opening is formed in the insulator, and the opening is filled with a conductive material to be the conductor PLG, thereby forming the conductor PLG. After the formation of the conductor PLG, the surface of each film of the conductor PLG and the insulator in the vicinity thereof may be planarized by a planarization process such as a chemical mechanical polishing process so as to make the heights uniform.

As an example, the transistors M1, M2, M4, M6, M7, and M8 shown in fig. 20 each include a part of each of the semiconductor SMC, the conductor GEM, the insulator, and the conductor PLG. Further, as an example, the transistor M2 includes a part of the electric conductor BGM.

The capacitors C1 and C3 shown in fig. 20 include a part of each of the conductors SDMB and SDMT. Specifically, each of the capacitors C1 and C3 has a region where a part of each of the conductors SDMB and SDMT overlaps. In other words, in each of the capacitor C1 and the capacitor C3, a part of the conductor SDMB is used as one of the pair of electrodes, and a part of the conductor SDMT is used as the other of the pair of electrodes. Further, it is preferable that an insulator having a high dielectric constant is provided between the conductors SDMB and SDMT in the capacitors C1 and C3.

Further, as an example, the conductor EC shown in fig. 20 is formed on the conductor SDMT. The conductor EC is used as a wiring or a plug electrically connected to the anode of the light emitting device LD (not illustrated in fig. 20) located above the conductor SDMT.

Modified example of display device 1

Note that the pixel of the display device according to one embodiment of the present invention described above is not limited to the pixel PX shown in fig. 17. The pixel of the display device according to one embodiment of the present invention may be configured by appropriately changing the pixel PX of fig. 17.

Fig. 21 shows a modification example of the pixel PX of fig. 17. In the pixel PX of the display device DSP2AA shown in fig. 21, the anode of the light emitting device LD is electrically connected to the first terminal of the switch SW6, the second terminal of the switch SW8, the first terminal of the transistor M2, the second terminal of the capacitor C1, and the first terminal of the capacitor C3, the cathode of the light emitting device LD is electrically connected to the first terminal of the switch SW4, and the second terminal of the switch SW4 is electrically connected to the wiring VE0, which is different from the pixel PX of the display device DSP2A of fig. 17 at these points. That is, the pixel PX of the display device DSP2AA shown in fig. 21 has a structure in which the switch SW4 and the light emitting device LD are replaced in the pixel PX of fig. 17.

As for the operation method of the display device DSP2AA of fig. 21, the same operation method as the display device DSP2A of fig. 17 is referred to. The display device DSP2AA can obtain the same effects as the display device DSP2A by performing the same operation method as the display device DSP2A of fig. 17.

Fig. 22 shows a modification example of the pixel PX of fig. 17, which is different from the pixel PX of fig. 21. The pixel PX of the display device DSP2B shown in fig. 22 is different from the pixel PX of the display device DSP2A of fig. 17 in that the switch SW8 is not provided.

Therefore, the operation method of the display device DSP2B of fig. 22 is different from a part of the operation method of the display device DSP 2A. The following description is different from the operation method of the display device DSP 2A.

The switch SW1 of the display device DSP2B is turned on during the period T21 in fig. 18A and turned off during the period T23. In addition, the switch SW13 of the display device DSP2B is turned on during the period T21 in fig. 18A and turned off during the period T24. Note that the switch SW13 of the display device DSP2B may be turned on until the period T25.

Note that when the display device DSP2B is operated, the potential V _init applied to the wiring VE4 is equal to the potential V _N1 applied to the wiring VE 1.

The period after the period T25 may be substantially the same as the operation of the display device DSP2A of fig. 18A.

As described above, by operating the display device DSP2B, the display device DSP2B can obtain the same effect as the display device DSP2A when V _init and V _N1 are equal.

Modified example of display device 2

The circuit CD of the display device according to the embodiment of the present invention described above is not limited to the circuit CD shown in fig. 17. The circuit CD of the display device according to one embodiment of the present invention may be configured by appropriately changing the circuit CD of fig. 17.

For example, in the display device DSP2A of fig. 17, when the potential V _ref applied to the wiring VE3 is equal to the potential V _init applied to the wiring VE4, the structure of the circuit CD of the display device DSP2A of fig. 17 may be changed to the structure of the circuit CD shown in fig. 23A.

The circuit CD shown in fig. 23A is different from the display device DSP2A shown in fig. 17 in that the second terminal of the switch SW11 is not electrically connected to the wiring VE3 but is electrically connected to the wiring VE 4. Although not shown, the display device DSP2A may have a structure in which the second terminal of the switch SW11 and the second terminal of the switch SW13 are electrically connected to the wiring VE 3.

The display device DSP2A using the circuit CD of fig. 23A can operate in the same manner as the operation of the timing chart of fig. 18A.

The structure of the circuit CD of fig. 23A may be changed to the structure of the circuit CD of fig. 23B. The circuit CD of fig. 23B is different from the circuit CD of fig. 23A in that: the second terminal of the switch SW11 is not electrically connected to the wiring VE4 but is electrically connected to the first terminal of the switch SW13, the first terminal of the capacitor C2 and the wiring SL.

Note that, as the operation of the circuit CD of fig. 23B, for example, in a period (period T21 to period T26 in the timing chart of fig. 18A) in which the threshold voltage of the transistor M2 is corrected, the switch SW11 and the switch SW13 may be turned on to change the potential of the node N3 and the wiring SL to V _init(＝V_ref, and then, before the image data signal is input from the driving circuit SD to the circuit CD (period T27 and thereafter in the timing chart of fig. 18A), the switch SW11 and the switch SW13 may be turned off.

For example, a capacitor may be added to the circuit CD shown in fig. 23A. Specifically, as shown in the circuit CD of fig. 23C, a capacitor C4 is provided in the circuit CD, and the first terminal of the capacitor C4 may be electrically connected to the first terminal of the switch SW13, the first terminal of the capacitor C2, and the wiring SL. Further, a second terminal of the capacitor C4 is electrically connected to the wiring VE 6.

The wiring VE6 is used, for example, as a wiring to which a constant potential is applied. In addition, the constant potential applied by the wiring VE6 may be equal to or different from the constant potential applied by any one of the wirings VE0 to VE 5.

As shown in fig. 23C, by adding the capacitor C4 to the circuit CD, the wiring SL due to the potential change of the node N3 and the amount of change in the potential of the node in the period T27 of the timing chart of fig. 18A can be further reduced. Specifically, when the capacitance of the capacitor C4 is C ₄, the wiring SL due to the potential change of the node N3 and the amount of change in the potential of the node are the value of the potential change of the node N3 multiplied by C ₂/(C₁+C₂+C₄).

In addition, in fig. 23C, the capacitor C4 is provided inside the circuit CD, but the capacitor C4 may be provided outside the circuit CD. Specifically, for example, as in the display device DSP2C shown in fig. 24, the wiring SL may be electrically connected to the first terminal of the capacitor C4, and the wiring VE6 may be electrically connected to the second terminal of the capacitor C4.

Although not shown, as with the capacitor C4 and the wiring VE6 shown in fig. 24, in all the circuits CD described in the present specification, the drawings, and the like, a part of the plurality of switches and the capacitor included in the circuits CD may be provided outside the circuits CD. That is, one embodiment of the present invention is not limited to the structure of the circuit CD shown in the present specification, the drawings, and the like, and for example, a part of the circuit elements included in the circuit CD shown in the present specification, the drawings, and the like may be provided outside the circuit CD.

For example, the configuration of the circuit CD of the display device DSP2A of fig. 17 may be changed to the circuit CD of fig. 23D. The circuit CD of fig. 23D is different from the circuit CD of fig. 23A in that: comprises an inverter circuit INV; the control terminal of the switch SW12 is not electrically connected to the wiring SWL12 but is electrically connected to the wiring SWL 11.

By using the circuit CD shown in fig. 23D for the display device DSP2A of fig. 17, the wiring SWL12 does not need to be provided, and thus the circuit area of the display device DSP2A can be reduced.

Although not shown, when a switch is used as the switch SW12, the switch is turned off when a high-level potential is input to the control terminal thereof and turned on when a low-level potential is input to the control terminal thereof, the control terminal of the switch SW12 may not be electrically connected to the wiring SWL11 through the inverter circuit INV.

Modified example of display device 3

Next, fig. 25 shows an example of the display device DSP0 of fig. 1, which is different from the display devices DSP2A to DSP 2C. The display device DSP2D shown in fig. 25 is a modified example of the display device DSP2A of fig. 17, and is different from the display device DSP2A in that: the pixel PX is provided with a capacitor C2I and a switch SW13I; and the capacitor C2 and the switch SW13 are not provided in the circuit CD.

Therefore, in the description of the display device DSP2D, the description of the display device DSP2A is referred to for a portion common to the content of the display device DSP 2A.

The switch SW13I may use, for example, a switch usable for the switch SW 13. In addition, the switch SW13I is in an on state when a high-level potential is applied to its control terminal, and is in an off state when a low-level potential is applied to its control terminal.

In the display device DSP2D, a first terminal of the capacitor C2I is electrically connected to a second terminal of the switch SW 1. In addition, a second terminal of the capacitor C2I is electrically connected to the wiring SL. In addition, a first terminal of the switch SW13I is electrically connected to a first terminal of the switch SW1, a first terminal of the switch SW8, a first terminal of the capacitor C1 and a gate of the transistor M2. The second terminal of the switch SW13I is electrically connected to the wiring VE4, and the control terminal of the switch SW13I is electrically connected to the wiring GL 13.

In the display device DSP2D, an electrical connection point of the first terminal of the switch SW11, the first terminal of the switch SW12 and the capacitor C2I is referred to as a node N3. Note that in the display device DSP2D of the present configuration example, the node N3 may be replaced with the wiring SL in some cases.

Similarly to the lines GL1, GL4, GL6, and GL7, the line GL13 corresponds to one of the lines GL [1] to GL [ m ] in fig. 1. That is, in the case of adopting the circuit configuration of the pixel PX shown in fig. 25, the number of wirings GL extending on one row of the pixel array ALP is 5.

In the display device DSP2D, the capacitor C2I corresponds to the capacitor C2 of the display device DSP 2A. In the display device DSP2D, the switch SW13I corresponds to the switch SW13 of the display device DSP 2A. In addition, in the display device DSP2D, the wiring GL13 corresponds to the wiring SWL13 of the display device DSP 2A. That is, the display device DSP2D has a structure in which the switch SW13 and the capacitor C2 included in the circuit CD in the display device DSP2A are provided as the switch SW13I and the capacitor C2I in the pixel PX, respectively. Therefore, in the operation method of the display device DSP2A, the capacitor C2 is sometimes replaced with the capacitor C2I, the switch SW13 is replaced with the switch SW13I, and the wiring SWL13 is replaced with the wiring GL13, whereby the operation method of the display device DSP2D can be explained.

In the display device DSP2D, an image can be displayed on the pixel PX by correcting the threshold voltage of the transistor M2 of the pixel PX by performing the same operation method as the display device DSP 1A.

Note that the display device according to one embodiment of the present invention is not limited to the structure of the display device DSP 2D. The display device according to one embodiment of the present invention may have a structure in which the display device DSP2D is appropriately changed.

Fig. 26 shows a modification example of the display device DSP2D of fig. 25. The display device DSP2DA shown in fig. 26 is different from the display device DSP2D of fig. 25 in that: the first terminal of the switch SW13I is not electrically connected to the first terminal of the switch SW1, the first terminal of the switch SW8, the first terminal of the capacitor C1 and the gate of the transistor M2, but is electrically connected to the second terminal of the switch SW1 and the first terminal of the capacitor C2I.

As in the display device DSP2DA of fig. 26, even if the configuration of the display device DSP2D is changed, the display device DSP2DA can correct the threshold voltage of the transistor M2 of the pixel PX by performing the same operation method as the display device DSP1A, and display an image on the pixel PX.

Fig. 27 shows a modification of the display device DSP2D of fig. 25, which is different from the display device DSP2DA of fig. 26. The display device DSP2E shown in fig. 27 is different from the display device DSP2D of fig. 25 in that: a second terminal of the switch SW1 is electrically connected to the wiring SL but not to the first terminal of the capacitor C2I; a first terminal of the switch SW1 is electrically connected to the second terminal of the capacitor C2I and is not electrically connected to the gate of the transistor M2, the first terminal of the switch SW13I, the first terminal of the switch SW8 and the first terminal of the capacitor C1; and a first terminal of the capacitor C2I is electrically connected to the gate of the transistor M2, the first terminal of the switch SW13I, the first terminal of the switch SW8, and the first terminal of the capacitor C1.

That is, the capacitor C2I, the switch SW1, the capacitor C1 (or the switch SW 8), the switch SW4, and the light emitting device LD are sequentially provided on the electrical path from the wiring SL to the wiring VE0 in the display device DSP2D, and the switch SW1, the capacitor C2I, the capacitor C1 (or the switch SW 8), the switch SW4, and the light emitting device LD are sequentially provided on the electrical path from the wiring SL to the wiring VE0 in the display device DSP 2E.

In the display device DSP2E, the capacitor C2I corresponds to the capacitor C2 of the display device DSP 2A. In the display device DSP2E, the switch SW13I corresponds to the switch SW13 of the display device DSP 2A. In the display device DSP2E, the wiring GL13 corresponds to the wiring SWL13. In the display device DSP2E, the node N4 corresponds to the node N3 of the display device DSP 2A. That is, the display device DSP2E has a structure in which the switch SW13 and the capacitor C2 included in the circuit CD in the display device DSP2A are provided as the switch SW13I and the capacitor C2I in the pixel PX, respectively. Therefore, in the operation method of the display device DSP2A, the capacitor C2 is replaced with the capacitor C2I, the switch SW13 is replaced with the switch SW13I, the wiring SWL13 is replaced with the wiring GL13, and the node N3 is replaced with the node N4, whereby the operation method of the display device DSP2E can be explained.

In the display device DSP2E, an image may be displayed on the pixel PX by correcting the threshold voltage of the transistor M2 of the pixel PX by the same operation method as in the display device DSP 1A.

Fig. 28 shows another modification of the display device DSP2D different from the display device DSP2DA of fig. 26 and the display device DSP2E of fig. 27. The display device DSP2F shown in fig. 28 is an example of further changing the display device DSP2E of fig. 27, and is different from the display device DSP2E in that: the pixel PX is provided with a switch SW11I; and the switch SW11 is not provided in the circuit CD. That is, the display device DSP2F shown in fig. 28 is different from the display device DSP2A in that: the pixel PX is provided with a switch SW11I, a switch SW13I, and a capacitor C2I; and the switch SW11, the switch SW13 and the capacitor C2 are not provided in the circuit CD.

In the display device DSP2F, the first terminal of the switch SW11I is electrically connected to the first terminal of the switch SW1 and the second terminal of the capacitor C2I. In addition, a second terminal of the switch SW11I is electrically connected to the wiring VE 3. The control terminal of the switch SW11I is electrically connected to the wiring GL 11.

The first terminal of the capacitor C2I is electrically connected to the first terminal of the switch SW8, the first terminal of the switch SW13I, the first terminal of the capacitor C1 and the gate of the transistor M2. In addition, a second terminal of the switch SW1 is electrically connected to the wiring SL.

Like the wirings GL1, GL4, GL6, GL7, and GL13, the wiring GL11 corresponds to one of the wirings GL [1] to GL [ m ] of fig. 1. That is, in the case of adopting the circuit configuration of the pixel PX shown in fig. 28, the number of wirings GL extending on one row of the pixel array ALP is 6.

In the display device DSP2F, the capacitor C2I corresponds to the capacitor C2 of the display device DSP 2A. The switch SW11I corresponds to the switch SW11 of the display device DSP 2A. The line GL11 corresponds to the line SWL11 of the display device DSP 2A. The switch SW13I corresponds to the switch SW13 of the display device DSP 2A. The line GL13 corresponds to the line SWL13 of the display device DSP 2A. The node N4 corresponds to the node N3 of the display device DSP 2A. That is, the display device DSP2F has a structure in which the switch SW11, the switch SW13, and the capacitor C2 included in the circuit CD in the display device DSP2A are provided as the switch SW11I, the switch SW13I, and the capacitor C2I, respectively, in the pixel PX. Therefore, in the operation method of the display device DSP2A, the operation method of the display device DSP2F may be described by replacing the switch SW11 with the switch SW11I, replacing the switch SW13 with the switch SW13I, replacing the capacitor C2 with the capacitor C2I, replacing the node N3 with the node N4, replacing the wiring SWL11 with the wiring GL11, and replacing the wiring SWL13 with the wiring GL 13.

In the display device DSP2F, an image can be displayed on the pixel PX by correcting the threshold voltage of the transistor M2 of the pixel PX by performing the same operation method as the display device DSP 2A.

Further, as described in the operation method of the display device DSP2A, the potentials applied by two or more wirings selected from the wirings VE1 to VE5 may be made equal to each other. In this case, the selected wirings may be combined into one wiring.

Fig. 29 shows another modification of the display device DSP2A different from the display device DSP2B of fig. 22, the display device DSP2C of fig. 24, the display device DSP2D of fig. 25, the display device DSP2DA of fig. 26, the display device DSP2E of fig. 27, and the display device DSP2F of fig. 28. The display device DSP2G shown in fig. 29 is an example of further changing the display device DSP2F of fig. 28, and is different from the display device DSP2F in that the switch SW12 is not provided in the circuit CD. That is, the display device DSP2G shown in fig. 29 is different from the display device DSP2A in that: the pixel PX is provided with a switch SW11I, a switch SW12I, a switch SW13I, and a capacitor C2I; and no circuit CD is provided.

Note that, in the display device DSP2G, the switch SW1 of the display device DSP1F is referred to as a switch SW12I, and the wiring GL1 of the display device DSP1F is referred to as a wiring GL12 for convenience.

In the display device DSP2G, the driving circuit SD is electrically connected to the wiring SL, and the wiring SL is electrically connected to the second terminal of the switch SW 12I.

The switch SW12I provided in the display device DSP2G may also serve as the switch SW1 provided in the pixel PX in the display device DSP 2D. Therefore, the structure of the display device DSP2D can be changed to a structure shown in the display device DSP2G of fig. 29 in which the switch SW12 is not provided in the circuit CD.

Therefore, in the operation method of the display device DSP2A, the switch SW11 may be replaced with the switch SW11I, the switch SW13 may be replaced with the switch SW13I, the capacitor C2 may be replaced with the capacitor C2I, the node N3 may be replaced with the node N4, the wiring SWL11 may be replaced with the wiring GL11, the wiring SWL12 may be replaced with the wiring GL12, and the wiring SWL13 may be replaced with the wiring GL13, whereby the operation method of the display device DSP2G may be described. Note that the signal supplied from the wiring GL1 of the display device DSP2A may not be considered in the display device DSP 2G.

Modified example of display device 4

Next, fig. 30 shows an example of the display device DSP0 of fig. 1, which is different from the display devices DSP2A to DSP 2G. The display device DSP2H shown in fig. 30 is a modified example of the display device DSP2A of fig. 17, and is different from the display device DSP2A in that a switch SW9 is provided in parallel electrical connection with the light emitting device LD.

As the switch SW9, for example, switches usable for the switch SW1, the switch SW4, the switch SW6, the switch SW7 and the switch SW8 can be used. In addition, the switch SW9 is in an on state when a high-level potential is applied to its control terminal, and is in an off state when a low-level potential is applied to its control terminal.

A first terminal of the switch SW9 is electrically connected to a second terminal of the switch SW4 and an anode of the light emitting device LD. A second terminal of the switch SW9 is electrically connected to the cathode of the light emitting device LD and the wiring VE 0. The control terminal of the switch SW9 is electrically connected to the wiring GL 9.

In the display device DSP2H of fig. 30, the wiring GL9 corresponds to one of the wirings GL [1] to GL [ m ] of fig. 1, similarly to the wirings GL1, GL4, GL6, and GL 7. That is, in the case of adopting the circuit configuration of the pixel PX shown in fig. 30, the number of wirings GL extending on one row of the pixel array ALP is 5.

Next, an example of an operation method of the display device DSP2H of fig. 30 will be described.

Fig. 31 is a timing chart showing an example of an operation method of the display device DSP 2H. Specifically, the timing chart of fig. 31 is a modified example of the timing chart of fig. 18A, in which the potential change of the wiring GL9 is added to the timing chart of fig. 18A. In addition, the potential change of the wiring GL4 in the timing chart of fig. 31 is different from the potential change of the wiring GL4 in the timing chart of fig. 18A. Therefore, operations other than the potential change of the wirings GL4 and GL9 of the display device DSP2H are described with reference to the timing chart of fig. 18A.

In the period T29, the high-level potential is applied to the line GL4, and the low-level potential is applied to the line GL 9. Thereby, the control terminal of the switch SW4 is applied with a high-level potential, so the switch SW4 is in an on state. In addition, the control terminal of the switch SW9 is applied with a low-level potential, whereby the switch SW9 is in an off state.

That is, in the period T29, each of the wiring VE0 and the cathode of the light emitting device LD is in a non-conductive state with the anode of the light emitting device LD, so the anode of the light emitting device LD is not applied with the potential V _CT from the wiring VE0 through the switch SW 9. On the other hand, during the period T29, the switch SW4 is in an on state, so that the current from the wiring VE2 flows through the anode of the light emitting device LD. Accordingly, the light emitting device LD emits light.

In the period T21 to the period T28 and the period T30, the low-level potential is applied to the wiring GL4, and the high-level potential is applied to the wiring GL 9. Thereby, the control terminal of the switch SW4 is applied with a low-level potential, so the switch SW4 is in an off state. In addition, the control terminal of the switch SW9 is applied with a high-level potential, so the switch SW9 is in an on state.

That is, in the period T21 to the period T28 and the period T30, each of the wiring VE0, the cathode of the light emitting device LD, and the anode of the light emitting device LD are in an on state, whereby the voltage between the anode and the cathode of the light emitting device LD becomes 0V. In addition, since the switch SW4 is in the off state, a current flows between the node N2 and the anode of the light emitting device LD without passing through the switch SW 4.

In particular, although the periods T21 to T28 and T30 are periods in which the light emitting device LD does not emit light, the charge stored in the anode of the light emitting device LD can be discharged to the wiring VE0 through the switch SW9 by turning on the switch SW9 during these periods. That is, during the period in which the light emitting device LD does not emit light, the discharge rate of the electric charges stored in the anode of the light emitting device LD of the display device DSP1F can be faster than that of the display devices (for example, the display devices DSP2A to DSP 2G) in which the switch SW9 is not provided. Thereby, the light emitting state of the light emitting device LD can be more quickly shifted to the quenching state.

Note that, although the wiring GL4 in the period T21 of the timing chart of fig. 18A is applied with a high-level potential, the wiring GL4 in the period T21 of the timing chart of fig. 31 is applied with a low-level potential. They differ in their operation in that: in a period T21 of the timing chart in fig. 18A, a potential from the wiring VE1 is applied to the anode of the light emitting device LD so that the light emitting device LD does not emit light, and in a period T21 of the timing chart in fig. 31, a potential from the wiring VE0 is applied to the anode of the light emitting device LD so that the light emitting device LD does not emit light.

As described above, the display device DSP2A of fig. 17 and the display device DSP2B of fig. 22 perform potential conversion of the image data signal by using the capacitor C1 in the pixel PX and the capacitor C2 outside the pixel PX. For example, when the voltage for correcting the threshold voltage of the transistor M2 is written to the capacitor C1, since the potential obtained by multiplying the potential change of the node N2 by C ₁/(C₁+C₂) is added to the potential of the node N1 by the potential change of the node N2, the voltage for correcting the threshold voltage of the transistor M2 written to the capacitor C1 may be shifted (when the potential change of the node N2 is the same as the potential change of the node N1, the voltage for correcting the threshold voltage of the transistor M2 written to the capacitor C1 may not be shifted). On the other hand, as shown in the display device DSP2A of fig. 17 and the display device DSP2B of fig. 22, when the configuration is provided in which the voltage for correcting the threshold voltage of the transistor M2 is written to the capacitor C3, the amount of change in the potential of the node N1 due to the potential change of the node N2 can be made substantially equal to the amount of change in the potential of the node N2, so that the voltage deviation for correcting the threshold voltage of the transistor M2 written to the capacitor C3 can be suppressed.

In this embodiment, a configuration example of the display device DSP2A having a configuration different from that of the pixel PX and the circuit CD described in embodiment 1 will be described. As described above, in the display device according to one embodiment of the present invention, the structures of the pixels PX and the circuits CD may be appropriately changed.

Embodiment 3

In this embodiment, an example of the structure of the display device described in the above embodiment will be described. Fig. 32A is a schematic cross-sectional view of an example of the display device described in the above embodiment. The display device DSP includes, for example, a pixel layer PXAL, a wiring layer LINL, and a circuit layer SICL.

The wiring layer LINL is provided over the circuit layer SICL, and the pixel layer PXAL is provided over the wiring layer LINL. Note that the pixel layer PXAL overlaps with a region including a driving circuit region DRV described later.

The circuit layer SICL includes a substrate BS and a driving circuit region DRV.

As the substrate BS, for example, a single crystal substrate (for example, a semiconductor substrate made of silicon or germanium) can be used, and as the substrate BS, besides a single crystal substrate, for example, an SOI (Silicon On Insulator: silicon on insulator) substrate, a glass substrate, a quartz substrate, a plastic substrate, a sapphire glass substrate, a metal substrate, a stainless steel substrate, a substrate containing a stainless steel foil, a tungsten substrate, a substrate containing a tungsten foil, a flexible substrate, a bonding film, paper containing a fibrous material, or a base material film can be used. Examples of the glass substrate include barium borosilicate glass, aluminoborosilicate glass, and soda lime glass. Examples of the flexible substrate, the adhesive film, and the base film are as follows. Examples thereof include plastics typified by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyether sulfone (PES), and Polytetrafluoroethylene (PTFE). Further, as an example, a synthetic resin such as an acrylic resin is given. Further, polypropylene, polyester, polyfluorinated ethylene, or polyvinyl chloride may be mentioned as examples. Examples of the polymer include polyamide, polyimide, aromatic polyamide, epoxy resin, inorganic vapor deposition film, and paper. When the manufacturing process of the display device DSP includes heat treatment, a substrate having high heat resistance is preferably selected as the substrate BS.

In this embodiment mode, a case where the substrate BS is a semiconductor substrate containing silicon as a material will be described. Thus, the transistor in the driving circuit region DRV may be a transistor containing silicon in a channel formation region (hereinafter referred to as a Si transistor).

The driving circuit region DRV is provided on the substrate BS.

As an example, the driving circuit region DRV includes a driving circuit for driving pixels included in a pixel layer PXAL described later. Note that a specific structural example of the driving circuit region DRV will be described later.

The wiring layer LINL is provided over the circuit layer SICL.

As one example, the wiring is provided in the wiring layer LINL. Further, the wiring included in the wiring layer LINL is used, for example, as a wiring for electrically connecting a driving circuit included in the driving circuit region DRV provided below and a circuit included in the pixel layer PXAL provided above.

As one example, the pixel layer PXAL includes a plurality of pixels (e.g., pixel PX [1,1] to pixel PX [ m, n ] of fig. 1).

Fig. 33A is an example of a plan view of the display device DSP, and shows only the display portion DIS. The display portion DIS may be a top view of the pixel layer PXAL.

In the display device DSP of fig. 33A, the display unit DIS is divided into, for example, p rows and q columns (p is an integer of 1 or more, and q is an integer of 1 or more). Therefore, the display section DIS includes the display area ARA [1,1] to the display area ARA [ p, q ]. Note that, as an example, a display area ARA [1,1], a display area ARA [2,1], a display area ARA [ p-1,1], a display area ARA [ p,1], a display area ARA [1,2], a display area ARA [2,2], a display area ARA [ p-1,2], a display area ARA [ p,2], a display area ARA [1, q-1], a display area ARA [2, q-1], a display area ARA [ p-1, q-1], a display area ARA [ p, q-1], a display area ARA [1, q ], a display area ARA [2, q ], a display area ARA [ p-1, q ], and a display area ARA [ p, q ] are selectively shown in fig. 33A.

For example, when the display unit DIS is to be divided into 32 areas, p=4 and q=8 may be applied to fig. 33A. In the case where the resolution of the display device DSP is 8K4K, the number of display pixels is 7680×4320px. In the case where the subpixels of the display section DIS are three colors of red (R), green (G), and blue (B), the total number of subpixels is 7680x4320×3. Here, when the pixel array of the display unit DIS having the resolution of 8K4K is divided into 32 regions, the number of display pixels per region is 960×1080px, and when the subpixels of the display device DSP are three colors of red (R), green (G), and blue (B), the number of subpixels per region is 960×1080×3.

Here, consider a driving circuit region DRV included in the circuit layer SICL when the display portion DIS is divided into p rows and q columns in the display device DSP of fig. 33A.

Fig. 33B is an example of a top view of the display device DSP, and only the driving circuit region DRV included in the circuit layer SICL is shown.

In the display device DSP of fig. 33A, the display unit DIS is divided into p rows and q columns, and thus the divided display regions ARA [1,1] to ARA [ p, q ] each require a corresponding driving circuit. Specifically, the driving circuit region DRV may be divided into p rows and q columns, and the driving circuits may be provided in the divided regions.

The display device DSP of fig. 33B shows a structure in which the driving circuit region DRV is divided into p rows and q columns. Thus, the driving circuit region DRV includes circuit regions ARD [1,1] to ARD [ p, q ]. Note that, as an example, a circuit region ARD [1,1], a circuit region ARD [2,1], a circuit region ARD [ p-1,1], a circuit region ARD [ p,1], a circuit region ARD [1,2], a circuit region ARD [2,2], a circuit region ARD [ p-1,2], a circuit region ARD [ p,2], a circuit region ARD [1, q-1], a circuit region ARD [2, q-1], a circuit region ARD [ p-1, q-1], a circuit region ARD [ p, q-1], a circuit region ARD [1, q ], a circuit region ARD [2, q ], a circuit region ARD [ p-1, q ], and a circuit region ARD [ p, q ] are selectively shown in fig. 33B.

The circuit region ARD [1,1] to the circuit region ARD [ p, q ] each include a column driving circuit CLM and a row driving circuit RWD. For example, the column driving circuit CLM and the row driving circuit RWD in the circuit region ARD [ h, k ] (not shown in fig. 33B) located in the h-th and k-th columns (h is an integer of 1 to p, k is an integer of 1 to q), can drive a plurality of pixels in the display region ARA [ h, k ] (not shown in fig. 33A) located in the h-th and k-th columns of the display section DIS.

The column driving circuit CLM includes, for example, a source driving circuit that transmits an image signal to a plurality of pixels included in the corresponding display region ARA. Therefore, like the display device DSP0 of fig. 1, the display device DSP of fig. 32A or 33A preferably has a structure in which the column driver circuit CLM is electrically connected to the wirings SL [1] to SL [ n ]. The column driving circuit CLM may also include a digital-to-analog conversion circuit that converts an image signal of digital data into analog data.

The row driving circuit RWD includes, for example, a gate driving circuit that selects a plurality of display pixels that are transmission targets of image signals in the corresponding display area ARA. Therefore, like the display device DSP0 of fig. 1, the display device DSP of fig. 32A or 33A preferably has a structure in which the row driving circuit RWD is electrically connected to the wiring GL [1] to the wiring GL [ m ].

Note that the display device DSP shown in fig. 32A, 33A, and 33B has a structure in which the display regions ARA [ h, k ] and the circuit regions ARD [ h, k ] of the display section DIS overlap each other, but the display device of one embodiment of the present invention is not limited to this. The display region ARA [ h, k ] and the circuit region ARD [ h, k ] in the display device according to the embodiment of the present invention may not necessarily overlap each other.

For example, as shown in fig. 32B, the display device DSP may be provided with a region LIA on the substrate BS in addition to the driving circuit region DRV.

As an example, a wiring is provided in the region LIA. Further, the wiring in the region LIA may be electrically connected to the wiring in the wiring layer LINL. In this case, in the display device DSP, a circuit included in the driving circuit region DRV may be electrically connected to a circuit included in the pixel layer PXAL by a wiring included in the region LIA and a wiring included in the wiring layer LINL. In the display device DSP, a circuit included in the driving circuit region DRV and a wiring or a circuit included in the region LIA may be electrically connected to each other through a wiring included in the wiring layer LINL.

Furthermore, as an example, the region LIA may also include a GPU (Graphics Processing Unit: image processor). In addition, when the display device DSP includes a touch panel, the area LIA may also include a sensor controller that controls a touch sensor in the touch panel. In addition, in the case of using a liquid crystal element as a display element of the display device DSP, a gamma correction circuit may be included. The area LIA may include a controller having a function of processing an input signal from the outside of the display device DSP. The region LIA may include a voltage generating circuit for generating a voltage to be supplied to the circuit and the driving circuit included in the circuit region ARD.

In addition, in the case of employing a light-emitting device using an organic EL material as a display element of the display device DSP, the region LIA may also include an EL correction circuit. The EL correction circuit has, for example, a function of appropriately adjusting the amount of current input to a light emitting device including an organic EL material. Since the luminance of a light emitting device including an organic EL material is proportional to the amount of current, when the characteristics of a driving transistor electrically connected to the light emitting device are poor, the luminance of light emitted from the light emitting device may be lower than desired. The EL correction circuit may monitor, for example, the amount of current flowing through the light emitting device and increase the amount of current flowing through the light emitting device when the amount of current is less than a desired amount of current to increase the brightness of light emitted by the light emitting device. In contrast, when the amount of current is larger than the desired amount of current, the amount of current flowing through the light emitting device may be adjusted to be small.

Fig. 34A is an example of a top view of the display device DSP shown in fig. 32B, and shows a drive circuit region DRV indicated by a solid line and a display portion DIS indicated by a broken line. As an example, the display device DSP of fig. 34A has a structure in which the driving circuit region DRV is surrounded by the region LIA (fig. 34B is an example of a top view of the display device DSP showing only the circuit layer SICL). Therefore, as shown in fig. 34A, the driving circuit region DRV is arranged so as to overlap the inside of the display portion DIS in a plan view.

In the display device DSP shown in fig. 34A, the display portion DIS is divided into the display regions ARA [1,1] to ARA [ p, q ], and the driving circuit region DRV is also divided into the circuit regions ARD [1,1] to ARD [ p, q ], as in fig. 33A.

As shown in fig. 34A, as an example, a correspondence relationship between a display region ARA and a circuit region ARD including a driving circuit that drives pixels in the display region ARA is shown with a thick arrow. Specifically, the driving circuit in the circuit area ARD [1,1] drives the pixels in the display area ARA [1,1], and the driving circuit in the circuit area ARD [2,1] drives the pixels in the display area ARA [2,1 ]. In addition, the driving circuit in the circuit region ARD [ p-1,1] drives the pixels in the display region ARA [ p-1,1], and the driving circuit in the circuit region ARD [ p,1] drives the pixels in the display region ARA [ p,1 ]. In addition, the driving circuits in the circuit areas ARD [1, q ] drive the pixels in the display areas ARA [1, q ], and the driving circuits in the circuit areas ARD [2, q ] drive the pixels in the display areas ARA [2, q ]. In addition, the driving circuit in the circuit region ARD [ p-1, q ] drives the pixels in the display region ARA [ p-1, q ], and the driving circuit in the circuit region ARD [ p, q ] drives the pixels in the display region ARA [ p, q ]. That is, although not shown in fig. 34A, the driving circuits located in the circuit regions ARD [ h, k ] of h rows and k columns drive the pixels in the display regions ARA [ h, k ].

In fig. 32B, a driver circuit included in the circuit region ARD in the circuit layer SICL is electrically connected to a pixel included in the display region ARA in the pixel layer PXAL through a wiring included in the wiring layer LINL, and the display device DSP may have a structure in which the display region ARA [ h, k ] and the circuit region ARD [ h, k ] do not necessarily overlap each other. Therefore, the positional relationship between the driving circuit region DRV and the display unit DIS is not limited to the top view of the display device DSP shown in fig. 34A, and the arrangement of the driving circuit region DRV can be freely determined.

Note that the display device DSP shown in fig. 32A and 32B has a structure provided with the wiring layer LINL, but one embodiment of the present invention is not limited thereto. As shown in fig. 32C, a display device according to an embodiment of the present invention may have a structure in which a pixel layer PXAL is disposed over a circuit layer SICL, for example.

The arrangement of the column driver circuit CLM and the row driver circuit RWD in each of the circuit regions ARD [1,1] to ARD [ p, q ] shown in fig. 33B and 34A is not limited to the configuration of the display device according to one embodiment of the present invention. In fig. 33B and 34A, the column driver circuit CLM and the row driver circuit RWD are arranged so as to intersect each other (so as to be cross-shaped), but in one circuit region ARD, the column driver circuit CLM and the row driver circuit RWD may be arranged in various shapes.

As shown in fig. 33A to 34B, by dividing the display section DIS into a plurality of display areas ARA and providing driving circuits corresponding to the respective display areas ARA, circuits included in the plurality of display areas ARA can be driven independently. For example, the display region ARA having a high rewriting frequency of image data may be driven by increasing the frame rate of the column driver circuit CLM and the row driver circuit RWD included in the corresponding circuit region ARD, and the display region ARA having a low rewriting frequency of image data may be driven by decreasing the frame rate of the column driver circuit CLM and the row driver circuit RWD included in the corresponding circuit region ARD. Specifically, the column driver circuit CLM and the row driver circuit RWD corresponding to the display region ARA in which the rewriting frequency of image data such as a moving image is high may operate at a high frame rate of 60Hz or more, 120Hz or more, 165Hz or more, or 240Hz or more. The column driver circuit CLM and the row driver circuit RWD corresponding to the display region ARA in which the rewriting frequency of image data such as still images is low may operate at a low frame rate of 5Hz or less, 1Hz or less, 0.5Hz or less, or 0.1Hz or less. In this way, by dividing the display section DIS of the display device DSP into the display areas ARA [1,1] to ARA [ p, q ], the rewriting frequency (frame rate) can be changed according to the image displayed on the display area ARA. That is, the display device DSP may display images at different frame rates from each other in at least two of the display areas ARA [1,1] to ARA [ p, q ] in the display section DIS.

Next, examples of the respective components included in the display device DSP will be described. Fig. 35A is a block diagram showing an example of the display device DSP of fig. 32A or 32B. The display device DSP shown in fig. 35A includes a display portion DIS and a peripheral circuit PRPH.

Peripheral circuitry PRPH includes: a circuit GDS including a plurality of row driving circuits RWD; a circuit SDS including a plurality of column driving circuits CLM; a distribution circuit DMG; a distribution circuit DMS; a control unit CTR; a storage device MD; a voltage generation circuit PG; a timing controller TMC; a clock signal generation circuit CKS; an image processing unit GPS; interface INT. Note that, as an example, the peripheral circuit PRPH may be a circuit included in the circuit layer SICL in fig. 32A and 32B.

Note that in the display device DSP, as shown in fig. 32A to 34A, the driving circuit region DRV including each of the plurality of row driving circuits RWD overlaps the pixel layer PXAL including the plurality of display regions ARA, but for convenience, it is illustrated in fig. 35A that the plurality of row driving circuits RWD are arranged on one column outside the display portion DIS. Likewise, the driving circuit region DRV including each of the plurality of column driving circuits CLM overlaps the pixel layer PXAL including the plurality of display regions ARA, but is illustrated in fig. 35A as a plurality of column driving circuits CLM arranged on one line outside the display portion DIS for convenience.

The peripheral circuit PRPH is included in the circuit layer SICL shown in fig. 32A and 32B, for example. The circuit GDS and the circuit SDS in the peripheral circuit PRPH are included in the driving circuit region DRV shown in fig. 32A and 32B, for example.

In the display device DSP of fig. 32B, one or more selected from the group consisting of the distribution circuit DMG, the distribution circuit DMS, the control unit CTR, the memory device MD, the voltage generation circuit PG, the timing controller TMC, the clock signal generation circuit CKS, the image processing unit GPS, and the interface INT may be included in the area LIA. Further, the circuit not included in the region LIA among the circuits described above may be electrically connected to one or both of the circuit included in the region LIA and the circuit included in the driving circuit region DRV as an external circuit.

The distribution circuit DMG, the distribution circuit DMS, the control section CTR, the memory device MD, the voltage generation circuit PG, the timing controller TMC, the clock signal generation circuit CKS, the image processing section GPS, and the interface INT all transmit and receive various signals to and from each other via the bus BW.

The interface INT is used, for example, as a circuit that introduces image information output from an external device for displaying an image on the display device DSP into the peripheral circuit PRPH. Examples of the external device include a playback device for a recording medium, a nonvolatile storage device such as an HDD (HARD DISK DRIVE: hard disk drive) and an SSD (Solid STATE DRIVE: solid state drive). The interface INT may be a circuit for outputting a signal from a circuit in the peripheral circuit PRPH to a device outside the display device DSP.

In addition, in the case where image information is input to the interface INT from an external device by wireless communication, the interface INT may include one or more selected from an antenna, a mixer, an amplifying circuit, and an analog-digital conversion circuit that receive the image information, as an example.

The control unit CTR has a function of controlling various circuits included in the peripheral circuit PRPH by processing various control signals transmitted from the external device through the interface INT.

The memory device MD has a function of temporarily holding information and image signals. At this time, the storage device MD is used as a frame memory (sometimes referred to as a frame buffer), for example. The storage device MD may have a function of temporarily holding one or both of the information transmitted from the external device via the interface INT and the information processed by the control unit CTR. Note that, as the memory device MD, for example, one or both of SRAM (Static Random Access Memory: static random access memory) and DRAM (Dynamic Random Access Memory: dynamic random access memory) may be used.

The voltage generation circuit PG has a function of generating a power supply voltage to be supplied to each of the pixel circuit included in the display portion DIS and the circuit included in the peripheral circuit PRPH. Note that the voltage generation circuit PG may have a function of a circuit for selecting a supply voltage. For example, the voltage generation circuit PG can reduce power consumption of the entire display device DSP by stopping supply of one or more voltages selected from the group consisting of the circuit GDS, the circuit SDS, the image processing unit GPS, the timing controller TMC, and the clock signal generation circuit CKS while the still image is displayed on the display unit DIS.

The timing controller TMC has a function of generating timing signals used by a plurality of row driving circuits RWD included in the circuit GDS and timing signals used by a plurality of column driving circuits CLM included in the circuit SDS. In addition, the clock signal generated by the clock signal generation circuit CKS may be used for the generation of the timing signal.

The image processing unit GPS has a function of performing processing for drawing an image on the display unit DIS. For example, the image processing unit GPS may include a GPU. In particular, since the image processing unit GPS has a structure for performing parallel pipeline processing, it is possible to process the image data displayed on the display unit DIS at a high speed. The image processing unit GPS may be used as a decoder for restoring the encoded image.

The image processing unit GPS may have a function of correcting the color tone of the image displayed on the display unit DIS. In this case, the image processing unit GPS is preferably provided with one or both of a dimming circuit and a toning circuit. In addition, in the case where the display pixel circuit included in the display section DIS includes an organic EL element, the image processing section GPS may be provided with an EL correction circuit.

In addition, the image correction described above may also utilize artificial intelligence. For example, the current (or voltage) flowing through the display device included in the pixel (or the voltage applied to the display device) may be monitored and acquired, the image displayed on the display unit DIS may be acquired by the image sensor, and the current (or voltage) and the image may be used as input data for an artificial intelligence operation (for example, an artificial neural network or the like), and whether or not the image is corrected may be determined based on the output result.

In addition, the operation of artificial intelligence can be applied not only to image correction but also to up-conversion processing of image data. Thus, by up-converting the image data having a low resolution according to the resolution of the display section DIS, an image having a high display quality can be displayed on the display section DIS.

Note that the above-described artificial intelligence operation may be performed using, for example, a GPU included in the image processing unit GPS. That is, the GPU may be used to perform operations for various corrections (e.g., color non-uniformity correction or up-conversion).

Note that in this specification and the like, a GPU that performs an operation of artificial intelligence is referred to as an AI accelerator. That is, in the present specification and the like, the GPU may be replaced with an AI accelerator.

The clock signal generation circuit CKS has a function of generating a clock signal. For example, the clock signal generation circuit CKS may change the frame rate of the clock signal according to the image displayed on the display unit DIS.

The distribution circuit DMG has a function of transmitting a signal received from the bus BW to the row drive circuit RWD which drives pixels included in one of the plurality of display areas ARA in accordance with the content of the signal.

The distribution circuit DMS has a function of transmitting a signal received from the bus BW to the column driving circuit CLM which drives pixels included in one of the plurality of display areas ARA, in accordance with the content of the signal.

In the display device DSP shown in fig. 35A, LVDS (Low Voltage DIFFERENTIAL SIGNALING: low Voltage differential signal) may be used as a technique for transmitting a digital signal. Or eDP (embedded DisplayPort) or iDP (internal DisplayPort) may be used.

Although not shown in fig. 35A, the peripheral circuit PRPH may include a level shifter. The level shifter has a function of converting a signal input to each circuit into an appropriate level as an example.

Note that the structure of the peripheral circuit PRPH of the display device DSP shown in fig. 35A is only an example, and the circuit structure in the peripheral circuit PRPH may be changed according to circumstances. For example, in the case where the display device DSP receives the drive voltage of each circuit from the outside, the drive voltage does not need to be generated in the display device DSP, and therefore the display device DSP may not include the voltage generation circuit PG at this time.

For example, in the display device DSP of fig. 35A, the distribution circuit DMG, the distribution circuit DMS, the control unit CTR, the memory device MD, the voltage generation circuit PG, the timing controller TMC, the clock signal generation circuit CKS, the image processing unit GPS, and the interface INT may not be included in the display device DSP. Specifically, as shown in fig. 35B, the peripheral circuit PRPH may include a distribution circuit DMG, a distribution circuit DMS, a control unit CTR, a memory device MD, a voltage generation circuit PG, a timing controller TMC, a clock signal generation circuit CKS, an image processing unit GPS, and an interface INT, and be provided outside the display device DSP. In addition, although fig. 35B shows a case where signals are transmitted and received between the circuit GDS and the distribution circuit DMG and between the circuit SDS and the distribution circuit DMS, signals may be transmitted and received between the circuit GDS and the distribution circuit DMG and between the circuit SDS and the distribution circuit DMS through the interface INT. The structure of the display device DSP shown in fig. 35B can be applied to the display device DSP of fig. 32C, for example. Fig. 35B shows an example in which the configuration including the distribution circuit DMG, the distribution circuit DMS, the control unit CTR, the memory device MD, the voltage generation circuit PG, the timing controller TMC, the clock signal generation circuit CKS, the image processing unit GPS, and the interface INT is arranged outside the display device DSP, but one or more selected from the distribution circuit DMG, the distribution circuit DMS, the control unit CTR, the memory device MD, the voltage generation circuit PG, the timing controller TMC, the clock signal generation circuit CKS, the image processing unit GPS, and the interface INT are electrically connected as peripheral circuits to other circuits in the drive circuit region DRV.

Embodiment 4

In this embodiment, a configuration example of a display device according to an embodiment of the present invention will be described.

< Structural example of display device 1>

Fig. 36 is a cross-sectional view showing an example of a display device according to an embodiment of the present invention. As an example, the display device 1000 shown in fig. 36 has a structure in which a pixel circuit, a driver circuit, or the like is provided over a substrate 310. The configuration of the display device DSP0 and the like of fig. 1 according to the above-described embodiment may be the configuration of the display device 1000 of fig. 36. The pixel circuit described in this embodiment mode may be the display pixel circuit described in the above embodiment mode.

For example, the circuit layer SICL, the wiring layer LINL, and the pixel layer PXAL shown in the display device DSP of fig. 32A and 32B can be configured as in the display device 1000 of fig. 36. As one example, the circuit layer SICL includes a substrate 310, and the transistor 300 is formed over the substrate 310. A wiring layer LINL is provided over the transistor 300, and a wiring layer LINL is provided to electrically connect the transistor 300, a transistor 500 described later, a light emitting device 130R described later, a light emitting device 130G, and a light emitting device 130B. Further, a pixel layer PXAL is provided over the wiring layer LINL, and the pixel layer PXAL includes, for example, a transistor 500, the light-emitting device 130 (the light-emitting device 130R, the light-emitting device 130G, and the light-emitting device 130B in fig. 36), and the like.

Accordingly, the transistor 500 may be a transistor included in the pixel PX described in embodiment mode 1 and embodiment mode 2. Specifically, for example, the transistor 500 may be the transistor M2 included in the pixel PX shown in fig. 2 or 17. Further, for example, the transistor 500 may be a transistor in a switch included in the display device DSP1A of fig. 2 or a transistor in a switch included in the display device DSP1B of fig. 17.

Further, the light emitting device 130 may be a light emitting device LD included in the pixel PX described in embodiment mode 1 and embodiment mode 2.

Note that the circuit CD shown in fig. 2 or 17 may be included in the pixel layer PXAL, for example. That is, the transistor included in the circuit CD may have the structure of the transistor 500. In addition, the circuit CD shown in fig. 2 or 17 may be included in the circuit layer SICL, for example. That is, the transistor included in the circuit CD may have the structure of the transistor 300.

As the substrate 310, for example, a substrate usable as the substrate BS described in embodiment mode 3 can be used. When the manufacturing process of the display device 1000 includes heat treatment, a substrate having high heat resistance is preferably selected as the substrate 310.

The diagonal dimension of the display device may be determined according to the kind and size of the substrate 310, for example. For example, when a display device having a diagonal dimension of 30 inches or more, 50 inches or more, 70 inches or more, or 100 inches or more, which is supposed to be used in a television device or an electronic device for digital signage, a glass substrate may be used as the substrate 310. For example, when a diagonal display device having a diagonal dimension of 10 inches or less, 5 inches or less, 1.5 inches or less, or 1 inch or less, which is used for XR equipment or a portable information terminal, is manufactured, a semiconductor substrate may be used as the substrate 310.

In addition, the screen ratio (aspect ratio) of the display device 1000 is not particularly limited. For example, the display device 1000 may correspond to 1:1 (square), 4: 3. 16: 9. 16: 10. 21:9 or 32:9, etc.

In this embodiment mode, a case where the substrate 310 is a semiconductor substrate containing silicon as a material will be described.

The transistor 300 is provided over a substrate 310, and includes an element separation layer 312, a conductor 316, an insulator 315, an insulator 317, a semiconductor region 313 formed over a portion of the substrate 310, a low-resistance region 314a functioning as a source region or a drain region, and a low-resistance region 314b. Thus, the transistor 300 is a Si transistor. Note that fig. 36 shows a structure in which one of a source and a drain of the transistor 300 is electrically connected to a conductor 330 and a conductor 356 described later through a conductor 328 described later, but the electrical connection structure of the display device according to one embodiment of the present invention is not limited to this. For example, the display device according to one embodiment of the present invention may be configured such that the gate of the transistor 300 is electrically connected to the conductor 330 and the conductor 356 via the conductor 328.

The transistor 300 may have a Fin-type structure by, for example, covering the conductor 316 with an insulator 315 serving as a gate insulating film on the top surface and the channel width direction side surface of the semiconductor region 313. By providing the transistor 300 with a Fin-type structure, the effective channel width increases, so that the on-state characteristics of the transistor 300 can be improved. In addition, since the influence of the electric field of the gate electrode can be increased, the off-state characteristics of the transistor 300 can be improved.

In addition, the transistor 300 may be a p-channel type transistor or an n-channel type transistor. Further, a plurality of transistors 300 may be provided, and both of a p-channel transistor and an n-channel transistor may be used.

The region forming the channel of the semiconductor region 313, the region in the vicinity thereof, the low-resistance region 314a serving as a source region or a drain region, and the low-resistance region 314b preferably include a silicon semiconductor, and more specifically, preferably include single crystal silicon. The regions may be formed using germanium, silicon germanium, gallium arsenide, aluminum gallium arsenide, or gallium nitride, for example. In addition, silicon that stresses the crystal lattice to change the interplanar spacing to control the effective mass may also be used. The transistor 300 may be, for example, a HEMT (High Electron Mobility Transistor: high electron mobility transistor) using gallium arsenide or aluminum gallium arsenide.

As the conductor 316 used as the gate electrode, a semiconductor material such as silicon containing an element imparting n-type conductivity such as arsenic or phosphorus, or an element imparting p-type conductivity such as boron or aluminum can be used. Alternatively, as the conductor 316, a conductive material such as a metal material, an alloy material, or a metal oxide material can be used.

Further, since the material of the conductor determines the work function, the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, one or both of titanium nitride and tantalum nitride is preferably used as the conductor. For both conductivity and embeddability, a laminate of a metal material of one or both of tungsten and aluminum is preferably used as the conductor, and tungsten is particularly preferably used in terms of heat resistance.

An element separation layer 312 is provided to separate a plurality of transistors formed over the substrate 310 from each other. The element separation layer can be formed using, for example, a LOCOS (Local Oxidation of Silicon: local oxidation of silicon), STI (Shallow Trench Isolation: shallow trench isolation), mesa isolation, or the like.

Note that the structure of the transistor 300 shown in fig. 36 is only an example, and is not limited to the above-described structure, and an appropriate transistor may be used depending on a circuit structure, a driving method, or the like. For example, the transistor 300 may have a planar structure instead of the Fin-type structure.

The transistor 300 shown in fig. 36 includes an insulator 320, an insulator 322, an insulator 324, and an insulator 326 stacked in this order from the substrate 310 side.

As the insulator 320, the insulator 322, and the insulator 326, for example, one or more selected from silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, and aluminum nitride can be used.

In this specification and the like, oxynitride refers to a material having a greater oxygen content than nitrogen content in its composition, and oxynitride refers to a material having a greater nitrogen content than oxygen content in its composition. For example, when referred to as "silicon oxynitride" it refers to a material having a greater oxygen content than nitrogen in its composition, and when referred to as "silicon oxynitride" it refers to a material having a greater nitrogen content than oxygen in its composition.

The insulator 322 can also be used as a planarizing film for planarizing a step generated by the transistor 300 or the like covered with the insulator 320 and the insulator 322. For example, in order to improve the flatness of the top surface of the insulator 322, the top surface thereof may also be planarized by a planarization process using a chemical mechanical Polishing (CMP: CHEMICAL MECHANICAL Polishing) method.

The insulator 324 is preferably an insulating film (also referred to as a block insulating film) having barrier properties, which prevents diffusion of impurities such as water and hydrogen from the substrate 310 or the transistor 300 to a region above the insulator 324 (for example, a region where the transistor 500, the light-emitting device 130R, the light-emitting device 130G, the light-emitting device 130B, or the like is provided). Accordingly, the insulator 324 is preferably made of an insulating material having a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, and water molecules (the impurities are not easily transmitted). In addition, as the insulator 324, an insulating material having a function of suppressing diffusion of impurities such as nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (for example, N ₂ O, NO and NO ₂), copper atoms, and the like (which is not easy to permeate the oxygen) is preferably used. Or preferably has a function of suppressing diffusion of oxygen (for example, one or both of an oxygen atom and an oxygen molecule).

For example, as an example of a film having a barrier property against hydrogen, silicon nitride formed by a CVD method can be used.

The amount of hydrogen released can be analyzed by, for example, thermal desorption spectroscopy (TDS: thermal Desorption Spectroscopy). For example, in the range of 50 ℃ to 500 ℃ of the film surface temperature in the TDS analysis, when the amount of the hydrogen atoms released is converted into the amount per unit area of the insulator 324, the amount of the hydrogen released in the insulator 324 may be 10×10 ¹⁵atoms/cm² or less, preferably 5×10 ¹⁵atoms/cm² or less.

Note that the dielectric constant of insulator 326 is preferably lower than that of insulator 324. For example, the relative dielectric constant of insulator 326 is preferably less than 4, more preferably less than 3. For example, the relative dielectric constant of the insulator 326 is preferably 0.7 times or less, more preferably 0.6 times or less the relative dielectric constant of the insulator 324. By using a material having a low dielectric constant for the interlayer film, parasitic capacitance generated between wirings can be reduced.

Further, the insulators 320, 322, 324, and 326 are embedded with a conductor 328 and a conductor 330 connected to a light emitting device or the like provided above the insulator 326. The conductors 328 and 330 have a plug or wiring function. Note that the same reference numeral is sometimes used to denote a plurality of conductors used as plugs or wirings. In this specification, the wiring and the plug connected to the wiring may be one component. That is, a part of the electric conductor is sometimes used as a wiring, and a part of the electric conductor is sometimes used as a plug.

As a material of each plug and each wiring (for example, the conductor 328 and the conductor 330), a single layer or a stacked layer of one or more conductive materials selected from a metal material, an alloy material, a metal nitride material, and a metal oxide material can be used. It is preferable to use a high melting point material such as tungsten or molybdenum having both heat resistance and conductivity, and for example, tungsten is preferable. Or preferably using a low resistance conductive material such as aluminum or copper. The wiring resistance can be reduced by using a low-resistance conductive material.

Further, a wiring layer may be formed over the insulator 326 and the conductor 330. For example, in fig. 36, an insulator 350, an insulator 352, and an insulator 354 are stacked in this order over an insulator 326 and a conductor 330. Further, conductors 356 are formed in the insulators 350, 352, and 354. The conductor 356 has a function of a plug or a wiring connected to the transistor 300. The conductor 356 may be formed using the same material as the conductor 328 and the conductor 330.

Further, as with the insulator 324, for example, an insulator having a barrier property against one or more selected from hydrogen, oxygen, and water is preferably used for the insulator 350. In addition, as with the insulator 326, the insulator 352 and the insulator 354 are preferably insulators having a low relative dielectric constant so as to reduce parasitic capacitance generated between wirings. The insulators 352 and 354 are used as an interlayer insulating film and a planarizing film. Further, the conductor 356 preferably includes a conductor having a barrier property against one or more selected from hydrogen, oxygen, and water.

As the conductor having hydrogen blocking property, for example, tantalum nitride is preferably used. Further, by stacking tantalum nitride and tungsten having high conductivity, diffusion of hydrogen from the transistor 300 can be suppressed while maintaining conductivity as a wiring. At this time, the tantalum nitride layer having hydrogen blocking property is preferably in contact with the insulator 350 having hydrogen blocking property.

Further, an insulator 512 is provided above the insulator 354 and the conductor 356.

In fig. 36, transistor 500 is disposed on insulator 512. The insulator 512 is preferably made of a material having a barrier property against one or more selected from oxygen and hydrogen. Specifically, for example, one or more selected from silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, and aluminum nitride may be used for the insulator 512.

As an example of the film having hydrogen blocking property, silicon nitride formed by a CVD method can be used. Here, hydrogen may diffuse into a semiconductor element having an oxide semiconductor such as the transistor 500, and the characteristics of the semiconductor element may be degraded. Therefore, a film that suppresses diffusion of hydrogen is preferably provided between the transistor 300 and the transistor 500. Specifically, the film that suppresses diffusion of hydrogen refers to a film that has a small amount of hydrogen desorption.

For example, the same material as that of the insulator 320 can be used as the insulator 512. In addition, by using a material having a low dielectric constant for the insulator, parasitic capacitance generated between wirings can be reduced. For example, a silicon oxide film or a silicon oxynitride film may be used for the insulator 512.

Further, an insulator 514 is provided over the insulator 512, and the transistor 500 is provided over the insulator 514. Further, an insulator 574 is formed over the transistor 500, and an insulator 581 is formed over the insulator 574.

The insulator 574 and the insulator 581 will be described in detail in embodiment 5.

The insulator 514 preferably uses a film (a film having barrier properties) that suppresses diffusion of impurities such as water and hydrogen from the substrate 310, a region where a circuit element or the like is provided below the insulator 512, or the like to a region where the transistor 500 is provided. Therefore, for example, silicon nitride formed by CVD can be used for the insulator 514.

As described above, the transistor 500 shown in fig. 36 is an OS transistor including a metal oxide in a channel formation region. Note that the OS transistor is described in detail in embodiment mode 5.

An insulator 592 and an insulator 594 are sequentially formed on the insulator 581. Further, the conductor 596 is buried in the insulator 592 and the insulator 594. The conductor 596 is used as a plug or wiring connected to the transistor 300. The conductor 596 may be formed using the same material as the conductors 328 and 330.

Further, as with the insulator 324, for example, an insulator having a barrier property against one or more selected from hydrogen, oxygen, and water is preferably used as the insulator 592. In addition, as with the insulator 326, the insulator 594 is preferably an insulator having a low relative dielectric constant so as to reduce parasitic capacitance generated between wirings. In addition, the insulator 594 is used as an interlayer insulating film and a planarizing film. Further, the conductor 596 preferably includes a conductor having a barrier property against one or more selected from hydrogen, oxygen, and water.

Insulator 598 and insulator 599 are formed on insulator 594 and conductor 596.

Further, as with the insulator 324, for example, an insulator having a barrier property against one or more selected from hydrogen, oxygen, and water is preferably used for the insulator 598. In addition, as with the insulator 326, the insulator 599 is preferably an insulator having a low relative dielectric constant to reduce parasitic capacitance generated between wirings. In addition, the insulator 599 is used as an interlayer insulating film and a planarizing film.

The insulator 599 has the light emitting devices 130R, 130G, 130B, and the connection portions 140 formed thereon.

The connection portion 140 is sometimes referred to as a cathode contact portion, and is electrically connected to a cathode electrode of each of the light emitting devices 130R, 130G, and 130B. In fig. 36, the connection part 140 includes: one or more conductors selected from the conductors 112a to 112c to be described later; a conductor of at least one of the conductors 126a to 126c to be described later; one or more conductors selected from the conductors 129a to 129c to be described later; a common layer 114 to be described later; and a common electrode 115 to be described later.

The connection part 140 may be provided around four sides of the display part, or may be provided in the display part (e.g., between adjacent light emitting devices 130).

The light emitting device 130R includes the conductor 112a, the conductor 126a on the conductor 112a, and the conductor 129a on the conductor 126 a. The conductors 112a, 126a, 129a may be referred to as pixel electrodes, or some of the conductors 112a, 126a, 129a may be referred to as pixel electrodes.

Light emitting device 130G includes conductor 112b, conductor 126b on conductor 112b, and conductor 129b on conductor 126 b. As in the case of the light-emitting device 130R, the conductor 112b, the conductor 126b, and the conductor 129b may be referred to as pixel electrodes, or some of the conductor 112b, the conductor 126b, and the conductor 129b may be referred to as pixel electrodes.

Light emitting device 130B includes conductor 112c, conductor 126c on conductor 112c, and conductor 129c on conductor 126 c. As in the case of the light-emitting devices 130R and 130G, the conductors 112c, 126c, and 129c may be referred to as pixel electrodes, or some of the conductors 112c, 126c, and 129c may be referred to as pixel electrodes.

As the conductors 112a to 112c and the conductors 126a to 126c, for example, conductive layers serving as reflective electrodes can be used. As the conductive layer used as the reflective electrode, for example, a conductive body having a high reflectance to visible light such as silver, aluminum, an alloy film (ag—pd—cu (APC) film) composed of silver (Ag), palladium (Pd), and copper (Cu) is used. For example, a stacked film of aluminum sandwiched between a pair of titanium (a film of Ti, al, and Ti in this order), or a stacked film of silver sandwiched between a pair of indium tin oxide (a film of ITO, ag, ITO in this order) may be used for the conductors 112a to 112c and the conductors 126a to 126 c.

For example, a conductive layer serving as a reflective electrode may be used as the conductors 112a to 112c, and a conductor having high light transmittance may be used as the conductors 126a to 126 c. Examples of the high-light-transmittance conductor include: alloys of silver and magnesium; and indium tin oxide (sometimes referred to as ITO).

As the conductors 129a to 129c, for example, a conductive layer functioning as a transparent electrode can be used. As the conductive layer used as the transparent electrode, for example, the above-mentioned conductive body having high light transmittance can be used.

In addition, the light emitting device 130, which will be described in detail later, may also employ a microcavity structure (a micro resonator structure). The microcavity structure refers to a structure in which the thickness of the wavelength according to the color of light emitted from the light-emitting layer is the distance between the bottom surface of the light-emitting layer and the top surface of the lower electrode. In this case, it is preferable that a conductive material having light transmittance and light reflectivity is used for the conductors 129a to 129c of the upper electrode (common electrode), and a conductive material having light reflectivity is used for the conductors 112a to 112c and the conductors 126a to 126c of the lower electrode (pixel electrode).

The microcavity structure is a structure in which the optical distance between the lower electrode and the light-emitting layer is adjusted to (2 n-1) λ/4 (note that n is a natural number of 1 or more, and λ is the wavelength of light emission to be amplified). Therefore, light reflected by the lower electrode (reflected light) largely interferes with light directly incident on the upper electrode from the light-emitting layer (incident light). Thus, the phases of the reflected light and the incident light of the wavelength λ are matched, and the light emitted from the light-emitting layer can be further amplified. On the other hand, when the reflected light and the incident light are other than the wavelength λ, the phases are not uniform, which causes attenuation without resonance.

The conductor 112a is connected to the conductor 596 embedded in the insulator 594 through an opening provided in the insulator 599. In addition, the end of the conductor 126a is located outside the end of the conductor 112 a. The end of electrical conductor 126a is aligned or substantially aligned with the end of electrical conductor 129 a.

The conductors 112B, 126B, 129B in the light emitting device 130G and the conductors 112c, 126c, 129c in the light emitting device 130B are the same as the conductors 112a, 126a, 129a in the light emitting device 130R, so detailed description thereof is omitted.

The conductors 112a, 112b, and 112c have recesses formed therein to cover openings provided in the insulator 599. In addition, the recess is embedded with a layer 128.

The layer 128 has a function of planarizing the concave portions of the conductors 112a, 112b, and 112 c. Conductors 112a, 112b, 112c, and layer 128 are provided with conductors 126a, 126b, and 126c electrically connected to conductors 112a, 112b, and 112 c. Therefore, the region overlapping with the concave portions of the conductors 112a, 112b, and 112c can also be used as a light-emitting region, whereby the aperture ratio of the pixel can be improved.

Layer 128 may be an insulating layer or a conductive layer. For example, various inorganic insulating materials, organic insulating materials, and conductive materials can be used for the layer 128. In particular, the layer 128 is preferably formed using an insulating material.

As the layer 128, an insulating layer containing an organic material can be suitably used. For example, an acrylic resin, a polyimide resin, an epoxy resin, a polyamide resin, a polyimide amide resin, a silicone resin, a benzocyclobutene resin, a phenol resin, and a precursor of the above resin can be used for the layer 128. Further, as the layer 128, a photosensitive resin may be used. The photosensitive resin may be a positive type material or a negative type material.

By using the photosensitive resin, the layer 128 can be manufactured only by the exposure and development process, and the influence of dry etching or wet etching on the surfaces of the conductors 112a, 112b, and 112c can be reduced. Further, by using the negative type photosensitive resin forming layer 128, the same photomask forming layer 128 as a photomask (exposure mask) used to form the opening of the insulator 599 may be used in some cases.

Although fig. 36 shows an example in which the top surface of the layer 128 has a flat portion, the shape of the layer 128 is not particularly limited. Fig. 37A to 37C show modified examples of the layer 128.

As shown in fig. 37A and 37C, the top surface of the layer 128 may have a concave shape in the center and the vicinity thereof in plan view, that is, a concave curved surface shape.

Further, as shown in fig. 37B, the top surface of the layer 128 may have a shape in which the center and the vicinity thereof expand in plan view, that is, a shape having a convex curved surface.

In addition, the top surface of the layer 128 may have one or both of a convex curved surface and a concave curved surface. The number of the convex curved surfaces and the concave curved surfaces on the top surface of the layer 128 is not limited, and may be one or more.

The height of the top surface of the layer 128 may be equal to or substantially equal to the height of the top surface of the conductor 112a, or may be different from each other. For example, the height of the top surface of layer 128 may be lower or higher than the height of the top surface of electrical conductor 112 a.

Fig. 37A can also be said to be an example in which the layer 128 is accommodated in the recess formed in the conductor 112 a. On the other hand, as shown in fig. 37C, the layer 128 may also exist outside the recess formed in the conductor 112a, that is, the layer 128 may also be formed in such a manner that its top surface width is larger than that of the recess.

The light emitting device 130R includes a first layer 113a, a common layer 114 on the first layer 113a, and a common electrode 115 on the common layer 114. In addition, the light emitting device 130G includes the second layer 113b, the common layer 114 on the second layer 113b, and the common electrode 115 on the common layer 114. In addition, the light emitting device 130B includes a third layer 113c, a common layer 114 on the third layer 113c, and a common electrode 115 on the common layer 114.

The first layer 113a is formed so as to cover the top and side surfaces of the conductor 126a and the top and side surfaces of the conductor 129 a. Similarly, the second layer 113b is formed so as to cover the top and side surfaces of the conductor 126b and the top and side surfaces of the conductor 129 b. Similarly, the third layer 113c is formed so as to cover the top and side surfaces of the conductor 126c and the top and side surfaces of the conductor 129 c. Accordingly, the entire region where the conductors 126a, 126B, and 126c are provided can be used as the light-emitting regions of the light-emitting devices 130R, 130G, and 130B, so that the aperture ratio of the pixel can be improved.

In the light emitting device 130R, the first layer 113a and the common layer 114 may be collectively referred to as an EL layer. In addition, in the light emitting device 130G as well, the second layer 113b and the common layer 114 may be collectively referred to as an EL layer. In addition, in the light-emitting device 130B, the third layer 113c and the common layer 114 may be collectively referred to as an EL layer.

The structure of the light emitting device of the present embodiment is not particularly limited, and a single structure or a series structure may be employed.

The first layer 113a, the second layer 113b, and the third layer 113c are processed into islands by photolithography. Thus, the first layer 113a, the second layer 113b, and the third layer 113c form an angle of approximately 90 degrees with the top surface and the side surface at each end. On the other hand, for example, the thickness of the organic film formed using FMM (Fine Metal Mask) tends to be thinner as it gets closer to the end, and for example, the top surface is formed in a slope shape in a range of 1 μm or more and 10 μm or less, so that it is difficult to distinguish the top surface from the side surface.

In the first layer 113a, the second layer 113b, and the third layer 113c, the top surface and the side surface are clearly distinguished. Therefore, in the adjacent first layer 113a and second layer 113b, one side surface of the first layer 113a and one side surface of the second layer 113b are opposed to each other. Any combination of the first layer 113a, the second layer 113b, and the third layer 113c is the same as that.

The first layer 113a, the second layer 113b, and the third layer 113c include at least a light-emitting layer. For example, the first layer 113a, the second layer 113b, and the third layer 113c preferably have a structure including a light-emitting layer that emits red light, a light-emitting layer that emits green light, and a light-emitting layer that emits blue light, respectively. In addition, colors other than the above-described colors of the respective light-emitting layers may be cyan, magenta, yellow, or white.

The first layer 113a, the second layer 113b, and the third layer 113c may each include one or more of a hole injection layer, a hole transport layer, a hole blocking layer, a charge generation layer, an electron blocking layer, an electron transport layer, and an electron injection layer.

For example, the first layer 113a, the second layer 113b, and the third layer 113c may include a hole injection layer, a hole transport layer, a light emitting layer, and an electron transport layer. In addition, an electron blocking layer may be included between the hole transport layer and the light emitting layer. Further, an electron injection layer may be included on the electron transport layer.

For example, the first layer 113a, the second layer 113b, and the third layer 113c may be sequentially stacked with an electron injection layer, an electron transport layer, a light emitting layer, and a hole transport layer. In addition, a hole blocking layer may be included between the electron transport layer and the light emitting layer. Further, a hole injection layer may be included on the hole transport layer.

The first layer 113a, the second layer 113b, and the third layer 113c preferably include a light-emitting layer and a carrier-transporting layer (an electron-transporting layer or a hole-transporting layer) over the light-emitting layer. Since the surfaces of the first layer 113a, the second layer 113b, and the third layer 113c are exposed in some cases in the manufacturing process of the display device, the carrier transport layer is provided over the light-emitting layer, so that the light-emitting layer can be prevented from being exposed to the outermost surface, and damage to the light-emitting layer can be reduced. Thus, the reliability of the light emitting device and the light receiving device can be improved.

The first layer 113a, the second layer 113b, and the third layer 113c may include, for example, a first light-emitting unit, a charge generation layer, and a second light-emitting unit. For example, it is preferable to have the following structure: the first layer 113a includes two or more light emitting units emitting red light, the second layer 113b includes two or more light emitting units emitting green light, and the third layer 113c includes two or more light emitting units emitting blue light.

The second light emitting unit preferably includes a light emitting layer and a carrier transport layer (electron transport layer or hole transport layer) on the light emitting layer. Since the surface of the second light emitting element is exposed in the manufacturing process of the display device, the carrier transport layer is provided over the light emitting layer, so that the light emitting layer is prevented from being exposed to the outermost surface, and damage to the light emitting layer can be reduced. Thereby, the reliability of the light emitting device can be improved.

The common layer 114 includes, for example, an electron injection layer or a hole injection layer. Or the common layer 114 may have a stack of an electron transport layer and an electron injection layer, or may have a stack of a hole transport layer and a hole injection layer. The light emitting devices 130R, 130G, 130B collectively include a common layer 114.

The light emitting device 130R, the light emitting device 130G, and the light emitting device 130B commonly include the common electrode 115. In addition, as shown in fig. 36, the common electrode 115 included in common in the plurality of light emitting devices is electrically connected to the electric conductor in the connection portion 140.

The side surfaces of the first layer 113a, the second layer 113b, and the third layer 113c are covered with the insulator 125 and the insulator 127. The mask layer 118a is located between the first layer 113a and the insulator 125. In addition, a mask layer 118a is located between the second layer 113b and the insulator 125, and the mask layer 118a is located between the third layer 113c and the insulator 125. The first layer 113a, the second layer 113b, the third layer 113c, the insulator 125, and the insulator 127 are provided with a common layer 114, and the common layer 114 is provided with a common electrode 115. The common layer 114 and the common electrode 115 are continuous films commonly provided in a plurality of light emitting devices.

The insulator 125 may be an insulating layer containing an inorganic material. As the insulator 125, for example, one or more inorganic insulating films selected from an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and an oxynitride insulating film can be used. The insulator 125 may have a single-layer structure or a stacked-layer structure. Examples of the oxide insulating film include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, an indium gallium zinc oxide film, a gallium oxide film, a germanium oxide film, a yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, and a tantalum oxide film. Examples of the nitride insulating film include a silicon nitride film and an aluminum nitride film. Examples of the oxynitride insulating film include a silicon oxynitride film and an aluminum oxynitride film. Examples of the oxynitride insulating film include a silicon oxynitride film and an aluminum oxynitride film. In particular, an aluminum oxide film is preferable because it has a high selectivity to an EL layer in an etching step and has a function of protecting the EL layer in the formation of an insulator 127 to be described later. In particular, by using an inorganic insulating film such as an aluminum oxide film, a hafnium oxide film, or a silicon oxide film formed by an ALD method for the insulator 125, the insulator 125 having few pinholes and excellent function of protecting the EL layer can be formed. The insulator 125 may have a stacked structure of a film formed by an ALD method and a film formed by a sputtering method. The insulator 125 may have a stacked structure of an aluminum oxide film formed by an ALD method and a silicon nitride film formed by a sputtering method, for example.

Insulator 125 is preferably used as a barrier insulating layer for one or both of water and oxygen. The insulator 125 preferably has a function of suppressing diffusion of one or both of water and oxygen. The insulator 125 preferably has a function of trapping or fixing (also referred to as gettering) one or both of water and oxygen.

When the insulator 125 is used as a blocking insulating layer or has a gettering function, it may have a structure to suppress entry of impurities (typically, one or both of water and oxygen) which may be diffused to each light emitting device from the outside. By adopting this structure, a light emitting device with high reliability can be provided, and a display panel with high reliability can be provided.

In addition, the impurity concentration of the insulator 125 is preferably low. This can suppress the contamination of impurities from the insulator 125 into the EL layer, thereby suppressing deterioration of the EL layer. In addition, by reducing the impurity concentration in the insulator 125, the barrier properties against one or both of water and oxygen can be improved. For example, one of the hydrogen concentration and the carbon concentration in the insulator 125 is preferably sufficiently low, and both of the hydrogen concentration and the carbon concentration are preferably sufficiently low.

As the insulator 127, an insulating layer containing an organic material can be appropriately used. As the organic material, a photosensitive organic resin is preferably used, and for example, a photosensitive resin composition containing an acrylic resin is preferably used. The viscosity of the material of the insulator 127 may be 1cP to 1500cP, and preferably 1cP to 12 cP. By setting the viscosity of the material of the insulator 127 to be in the above range, the insulator 127 having a tapered shape described later can be formed relatively easily. Note that in this specification and the like, the acrylic resin does not refer to only a polymethacrylate or a methacrylic resin, and may refer to the entire acrylic polymer in a broad sense.

Note that, as described later, the insulator 127 may have a tapered shape on the side, and the organic material that can be used for the insulator 127 is not limited to the above-described material. For example, an acrylic resin, a polyimide resin, an epoxy resin, an imide resin, a polyamide resin, a polyimide amide resin, a silicone resin, a siloxane resin, a benzocyclobutene resin, a phenol resin, and a precursor of the above resins may be used as the insulator 127. As the insulator 127, an organic material such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinylpyrrolidone, polyethylene glycol, polyglycerol, pullulan, water-soluble cellulose, or alcohol-soluble polyamide resin may be used. Further, as the insulator 127, a photoresist may be used as the photosensitive resin in some cases. The photosensitive resin may be a positive type material or a negative type material.

As the insulator 127, a material that absorbs visible light can be used. By absorbing light emission from the light emitting device by the insulator 127, light leakage from the light emitting device to an adjacent light emitting device (stray light) through the insulator 127 can be suppressed. Thereby, the display quality of the display panel can be improved. In addition, since the display quality can be improved without using a polarizing plate in the display panel, the weight and thickness of the display panel can be reduced.

As the material absorbing visible light, a material including a pigment of black or the like, a material including a dye, a resin material including light absorbability (for example, polyimide), and a resin material (color filter material) usable for a color filter can be given. In particular, a resin material obtained by mixing or laminating color filter materials of two colors or three or more colors is preferable because the effect of shielding visible light can be improved. In particular, by mixing color filter materials of three or more colors, a black or near-black resin layer can be realized.

The insulator 127 can be formed by a wet deposition method such as spin coating, dipping, spraying, ink-jet, dispenser, screen printing, offset printing, doctor blade, slit coating, roll coating, curtain coating, or doctor blade coating. In particular, the organic insulating film to be the insulator 127 is preferably formed by spin coating.

Further, the insulator 127 is formed at a temperature lower than the heat-resistant temperature of the EL layer. The substrate temperature at the time of forming the insulator 127 is typically 200 ℃ or less, preferably 180 ℃ or less, more preferably 160 ℃ or less, further preferably 150 ℃ or less, and still further preferably 140 ℃ or less.

Hereinafter, the structure of the insulator 127 and the like between the light emitting device 130R and the light emitting device 130G will be described as an example. The same applies to the insulator 127 between the light emitting device 130G and the light emitting device 130B, the insulator 127 between the light emitting device 130B and the light emitting device 130R, and the like. In the following, an end portion of the insulator 127 on the second layer 113b is described as an example, and the end portion of the insulator 127 on the first layer 113a and the end portion of the insulator 127 on the third layer 113c are similar to each other.

Preferably, the insulator 127 has a tapered shape with a taper angle θ1 on the side surface when the display device is cut. The taper angle θ1 is the angle formed by the side surface of the insulator 127 and the substrate surface. Note that, not limited to the substrate surface, the taper angle θ1 may be an angle formed by the top surface of the flat portion of the insulator 125 or the top surface of the flat portion of the second layer 113b and the side surface of the insulator 127. In addition, by having a tapered shape on the side surface of the insulator 127, the side surface of the insulator 125 and the side surface of the mask layer 118a may have a tapered shape.

The taper angle θ1 of the insulator 127 is smaller than 90 °, preferably 60 ° or smaller, and more preferably 45 ° or smaller. By providing the side edge portion of the insulator 127 with the tapered shape, the common layer 114 and the common electrode 115 provided on the side edge portion of the insulator 127 can be deposited with high coverage without causing disconnection, localized thinning, or the like. This improves the in-plane uniformity of the common layer 114 and the common electrode 115, thereby improving the display quality of the display device.

In addition, the top surface of the insulator 127 preferably has a convex curved surface shape when the display device is cut. The convex curved surface shape of the top surface of the insulator 127 is preferably a shape gently protruding toward the center. In addition, the shape is preferably such that the convex curved surface portion of the center portion of the top surface of the insulator 127 is smoothly connected to the tapered portion of the side surface end portion. By adopting the above-described shape as the insulator 127, the common layer 114 and the common electrode 115 can be deposited with high coverage over the entire top surface of the insulator 127.

In addition, an insulator 127 is formed in a region between the two EL layers (for example, a region between the first layer 113a and the second layer 113 b). At this time, a part of the insulator 127 is sandwiched between the side end portion of one EL layer (for example, the first layer 113 a) and the side end portion of the other EL layer (for example, the second layer 113 b).

Further, it is preferable that one end portion of the insulator 127 overlaps with the conductor 126a serving as the pixel electrode, and the other end portion of the insulator 127 overlaps with the conductor 126b serving as the pixel electrode. By adopting the above structure, the end portion of the insulator 127 can be formed on a substantially flat region of the first layer 113a (the second layer 113 b). Therefore, the insulator 127 is relatively easily processed into the tapered shape described above.

As described above, by providing the insulator 127 or the like, it is possible to prevent the generation of a disconnected portion and a portion in which the thickness is locally reduced in the common layer 114 and the common electrode 115 from the substantially flat region of the first layer 113a to the substantially flat region of the second layer 113 b. Therefore, it is possible to suppress an increase in resistance due to a connection failure at the disconnection portion and a partial thickness reduction in the common layer 114 and the common electrode 115 between the light emitting devices.

In the display device of the present embodiment, the distance between the light emitting devices can be reduced. Specifically, the distance between light emitting devices, the distance between EL layers, or the distance between pixel electrodes can be reduced to less than 10 μm, 8 μm or less, 5 μm or less, 3 μm or less, 2 μm or less, 1 μm or less, 500nm or less, 200nm or less, 100nm or less, 90nm or less, 70nm or less, 50nm or less, 30nm or less, 20nm or less, 15nm or less, or 10nm or less. In other words, the display device of the present embodiment has a region in which the interval between two adjacent island-like EL layers is 1 μm or less, preferably a region in which the interval is 0.5 μm (500 nm) or less, and more preferably a region in which the interval is 100nm or less. By reducing the distance between the light emitting devices as described above, a display device with high definition and high aperture ratio can be provided.

The light emitting devices 130R, 130G, and 130B are provided with a protective layer 131. The protective layer 131 is used as a passivation film for protecting the light emitting device 130. By forming the protective layer 131 covering the light emitting device, entry of impurities such as water and oxygen into the light emitting device can be suppressed, whereby the reliability of the light emitting device 130 can be improved.

As the protective layer 131, for example, aluminum oxide, silicon nitride, or silicon oxynitride can be used.

The protective layer 131 and the substrate 110 are bonded by the adhesive layer 107. As the sealing of the light emitting device, a solid sealing structure, a hollow sealing structure, or the like may be employed. In fig. 36, a space between the substrate 310 and the substrate 110 is filled with the adhesive layer 107, that is, a solid sealing structure is adopted. Alternatively, a hollow sealing structure may be employed in which the space is filled with an inert gas (nitrogen, argon, or the like). At this time, the adhesive layer 107 may be provided so as not to overlap with the light emitting device. In addition, the space may be filled with a resin different from the adhesive layer 107 provided in a frame shape.

As the adhesive layer 107, various kinds of cured adhesives such as a photo-cured adhesive such as an ultraviolet-cured adhesive, a reaction-cured adhesive, a heat-cured adhesive, and an anaerobic adhesive can be used. Examples of the binder include epoxy resin, acrylic resin, silicone resin, phenol resin, polyimide resin, imide resin, PVC (polyvinyl chloride) resin, PVB (polyvinyl butyral) resin, and EVA (ethylene vinyl acetate) resin. In particular, a material having low moisture permeability such as epoxy resin is preferably used. In addition, a two-liquid mixed type resin may be used. In addition, an adhesive sheet may be used.

The display device 1000 has a top emission type structure. The light emitting device emits light to one side of the substrate 110. Therefore, a material having high visible light transmittance is preferably used for the substrate 110. For example, as the substrate 110, a substrate having high visible light transmittance, which can be applied to the substrate 310 and the substrate BS, can be selected. The pixel electrode includes a material that reflects visible light, and the counter electrode (common electrode 115) includes a material that transmits visible light.

By applying the above-described configuration example to a display device, a display device having high resolution and high definition can be realized. Specifically, for example, a display device having a resolution of HD (1280×720 in pixel number), FHD (1920×1080 in pixel number), WQHD (2560×1440 in pixel number), WQXGA (2560×1600 in pixel number), 4K (3840×2160 in pixel number), or 8K (7680×4320 in pixel number) may be realized. Specifically, for example, a display device having a definition of 100ppi or more, 300ppi or more, 500ppi or more, 1000ppi or more, 2000ppi or more, 3000ppi or more, or 5000ppi or more may be realized.

Note that the display device according to one embodiment of the present invention is not limited to the structure of the display device 1000 shown in fig. 36. The display device according to one embodiment of the present invention may have a structure in which the display device 1000 shown in fig. 36 is appropriately changed. A modified example of the display device of fig. 36 of the display device according to an embodiment of the present invention will be described below.

< Structural example of display device 2>

For example, the pixel layer PXAL of the display device 1000 shown in fig. 36 may have a structure in which two or more layers of the transistors 500 are stacked. The display device 1000A shown in fig. 38 is a structural example in which two layers of transistors 500 are stacked, and the transistors 500 are included in the pixel layer PXAL of the display device 1000 in fig. 36. Note that only the pixel layer PXAL is shown in the display device 1000A shown in fig. 38, and the structure of the display device 1000 in fig. 36 is referred to as the circuit layer SICL and the wiring layer LINL.

When the number of transistors included in a pixel in the display device 1000 is to be increased, the structure shown in the display device 1000A of fig. 38 may be employed.

< Structural example of display device 3>

For example, the circuit layer SICL of the display device 1000 shown in fig. 36 may have a structure in which an OS transistor is stacked over the transistor 300. The display device 1000B1 shown in fig. 39 is a structural example in which a transistor 300OS as an OS transistor is stacked over the transistor 300 in the circuit layer SICL of the display device 1000 of fig. 36. Note that only the layer including the transistor 500, out of the circuit layer SICL, the wiring layer LINL, and the pixel layer PXAL, the layer including the light-emitting device, out of the pixel layer PXAL, is shown in the display device 1000B1 shown in fig. 39, and the structure of the display device 1000 in fig. 36 is referred to.

From the viewpoints of mobility and reliability, it is difficult to manufacture a p-type semiconductor using a metal oxide, and thus a circuit formed of an OS transistor is an n-channel type unipolar circuit in many cases. Then, when the transistor 300OS is set to an n-type transistor and the transistor 300 is set to a p-type transistor in the display device 1000B1 of fig. 39, a circuit included in the circuit layer SICL of fig. 39 can be configured as a CMOS circuit. In particular, a circuit in which an OS transistor is set to an n-type transistor and an Si transistor is set to a p-type transistor is sometimes referred to as LTPO.

For example, the circuit layer SICL of the display device 1000 shown in fig. 36 may have a structure in which an OS transistor is formed instead of the transistor 300. The display device 1000B2 shown in fig. 40 is a structural example in which a transistor 300OS as an OS transistor is formed in the circuit layer SICL of the display device 1000 of fig. 36 instead of the transistor 300.

In the display device 1000B2 shown in fig. 40, a substrate other than a semiconductor substrate can be used as the substrate 310. For example, as the substrate 310, a glass substrate, a quartz substrate, a plastic substrate, a sapphire glass substrate, a metal substrate, a stainless steel substrate, a substrate including a stainless steel foil, a tungsten substrate, a substrate including a tungsten foil, a flexible substrate, a bonding film, paper including a fibrous material, or a base film can be used. In addition, when the manufacturing process of the display device includes heat treatment, a material having high heat resistance is preferably selected for the substrate 310.

For example, the circuit layer SICL of the display device 1000 shown in fig. 36 may have a structure in which a transistor including low-temperature polysilicon in a channel formation region (hereinafter referred to as an LTPS transistor) is formed instead of the transistor 300. The display device 1000B3 shown in fig. 41 is a structural example in which a transistor 300LT as an LTPS transistor is formed in the circuit layer SICL of the display device 1000 of fig. 36 instead of the transistor 300.

The transistor 300LT is disposed on the substrate 310. The transistor 300LT includes an insulator 361, an insulator 362, an insulator 363, an insulator 364, a conductor 366, a conductor 367, a low-resistance region 368p, a semiconductor region 368i, and a conductor 369. Here, the same hatching lines are attached to a plurality of layers obtained by processing the same conductive film. In this specification and the like, the low-resistance region 368p and the semiconductor region 368i are collectively referred to as a semiconductor layer 368. In particular, when low-temperature polysilicon is used as a semiconductor material included in the semiconductor layer 368, for example, the transistor 300LT may be an LTPS transistor. LTPS transistors have high field effect mobility and good frequency characteristics.

Further, in fig. 41, a conductor 367 is used as a first gate (sometimes referred to as one of a gate and a back gate) of the transistor 300 LT. Further, the conductor 366 is used as a second gate (sometimes referred to as the other of the gate and the back gate) of the transistor 300 LT. Further, one of a pair of low-resistance regions 368p of the semiconductor layer 368 is used as one of a source and a drain of the transistor 300LT, and the other of the pair of low-resistance regions 368p of the semiconductor layer 368 is used as the other of the source and the drain of the transistor 300 LT. Further, the insulator 363 is used as a first gate insulating film of the transistor 300LT, and the insulator 362 is used as a second gate insulating film of the transistor 300 LT.

In fig. 41, an insulator 361 is formed over a substrate 310. Further, a conductor 366 is formed in a partial region on the insulator 361. Further, an insulator 362 is formed so as to cover the insulator 361 and the conductor 366. Further, the semiconductor layer 368 overlaps with the conductor 366 and the insulator 362 and is formed in a partial region on the insulator 362. Further, an insulator 363 is formed so as to cover the insulator 362 and the semiconductor layer 368. Further, the conductor 367 overlaps with the conductor 366, the insulator 362, the semiconductor layer 368, and the insulator 363 and is formed in a region of a part of the insulator 363. Further, an insulator 364 is formed so as to cover the insulator 363 and the conductor 367. In addition, openings are provided in regions of the insulator 363 and the insulator 364 which overlap with the low-resistance region 368p, and a conductor 369 is formed on the insulator 364 so as to fit into the openings.

As the insulator 361, the insulator 362, the insulator 363, and the insulator 364, for example, one or more selected from silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, and aluminum nitride can be used.

In particular, as the insulator 361, a barrier insulating film which prevents diffusion of impurities (for example, metal ions, metal atoms, oxygen molecules, hydrogen atoms, hydrogen molecules, and water molecules) from an area below the insulator 361 (for example, the substrate 310) is preferably used.

The low-resistance region 368p is a region containing an impurity element. For example, when the transistor 300LT is an n-channel transistor, phosphorus or arsenic may be added to the low-resistance region 368 p. On the other hand, when the transistor 300LT is a p-channel transistor, boron or aluminum may be added to the low-resistance region 368 p. In addition, in order to control the threshold voltage of the transistor 300LT, the impurity described above may be added to the semiconductor region 368i.

Further, the transistor 300LT may be a p-channel type transistor or an n-channel type transistor. Alternatively, a plurality of transistors 300LT may be provided in the circuit layer SICL, and both of a p-channel transistor and an n-channel transistor may be used.

Examples of the conductors 366 and 367 include metals such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, and tungsten. Alternatively, an alloy containing two or more metals selected from the above metals as the main component may be used as the conductors 366 and 367. Alternatively, as the conductor 366 and the conductor 367, a light-transmitting conductive material such as indium oxide, indium Tin Oxide (ITO), indium oxide containing tungsten, indium zinc oxide containing tungsten, indium oxide containing titanium, ITO containing titanium, indium zinc oxide, zinc oxide (ZnO), znO containing gallium, or indium tin oxide containing silicon can be used. Alternatively, as the conductor 366 and the conductor 367, a semiconductor having a low resistance (e.g., polysilicon or an oxide semiconductor) or a silicide (e.g., nickel silicide) may be used by including an impurity element or the like. Alternatively, a film containing graphene may be used for the conductors 366 and 367. The film containing graphene can be formed by, for example, reducing a film containing graphene oxide. Or may be formed using a conductive paste (e.g., a conductive paste containing silver, carbon, or copper) or a conductive polymer (e.g., polythiophene). Conductive pastes are inexpensive and are preferred. Conductive polymers are easy to apply and are therefore preferred. Further, one or both of the conductors 366 and 367 may have a single-layer structure or a stacked-layer structure.

The conductor 369 is used as a wiring electrically connected to the low-resistance region 368p of the transistor 300 LT. In other words, the conductor 369 is used as a source or a drain of the transistor 300 LT. As the conductor 369, a material usable for the conductor 366 and the conductor 367 can be used.

For example, the circuit layer SICL of the display device 1000 shown in fig. 36 may be formed by bonding a plurality of substrates. The circuit layer SICL of the display device 1000B4 shown in fig. 42 includes a substrate 310 and a substrate 310A, and has a structure in which a surface on the upper side of the substrate 310 and a surface on the lower side of the substrate 310A are bonded. Note that fig. 42 shows only the structure of the display device 1000 of fig. 36 with reference to the layer including the transistor 500, the wiring layer LINL, and the layer including the light-emitting device, among the circuit layer SICL and the pixel layer PXAL.

In the display device 1000B4 of fig. 42, the structures of the substrate 310 to the insulator 326 and the conductor 330 are described with reference to the display device 1000 of fig. 36.

As in the display device 1000 of fig. 36, an insulator 350 and an insulator 352 are sequentially formed on the insulator 326 and the conductor 330.

Further, an opening is formed in a region overlapping with a part of the conductor 330 in each of the insulator 350 and the insulator 352, and a conductor 358 is provided so as to fit into the opening. Further, an electrical conductor 358 is also formed on the insulator 352. Then, the conductor 358 is patterned into a shape of a wiring, a terminal, or a pad by an etching process or the like.

As the conductor 358, copper, aluminum, tin, zinc, tungsten, silver, platinum, or gold, for example, can be used. The conductor 358 is preferably formed using the same components as those used for the conductor 319A described later.

Next, an insulator 380 is deposited so as to cover the insulator 352 and the conductor 358, and then, a planarization treatment by, for example, a Chemical Mechanical Polishing (CMP) method is performed until the conductor 358 is exposed. Thus, the electric conductor 358 can be formed on the substrate 310 as a wiring, a terminal, or a pad.

The insulator 380 preferably uses a film (a film having barrier properties) that suppresses diffusion of impurities such as water and hydrogen. In other words, the insulator 380 preferably uses a material that can be used for the insulator 324. Alternatively, for example, as with the insulator 326, an insulator having a low relative dielectric constant may be used for the insulator 380 to reduce parasitic capacitance generated between wirings. In other words, the insulator 380 may also use materials that are useful for the insulator 326. The insulator 380 is preferably formed using the same components as those used for the insulator 382 described later.

Next, the substrate 310A is described. The substrate 310A may use, for example, a semiconductor substrate usable for the substrate 310.

In addition, a transistor, an insulator, and a conductor are formed over the substrate 310A similarly to the substrate 310. Specifically, the transistor 300A is formed over the substrate 310A, the insulator 320A is formed so as to cover the transistor 300A, and the insulator 322A, the insulator 324A, the insulator 326A, and the insulator 350A are sequentially formed over the insulator 320A. Note that the insulator 320A may use a material usable for the insulator 320. Likewise, insulator 322A may use a material that is useful for insulator 322, insulator 324A may use a material that is useful for insulator 324, insulator 326A may use a material that is useful for insulator 326, and insulator 350A may use a material that is useful for insulator 350.

Further, like the conductor 328, the conductor 328A serving as a plug or a wiring is embedded in the insulator 320A and the insulator 322A. Further, as with the conductor 330, the conductor 330A serving as a plug or a wiring is embedded in the insulator 324A and the insulator 326A. In addition, the conductor 328A may use a material usable for the conductor 328, and the conductor 330A may use a material usable for the conductor 330.

For the structure above the insulator 350A of the display device 1000B4, reference is made to the description of the display device 1000.

Further, an insulator 382 is formed on a surface of the substrate 310A opposite to the surface on which the transistor 300A is formed. As described above, the insulator 382 may use a material usable for the insulator 380.

In addition, an opening in a region overlapping with the conductor 358 is provided in addition to an opening in which the conductor 328A is formed in the insulator 320A and the insulator 322A. Further, an insulator 318A is formed on a side surface of an opening formed in a region overlapping with the conductor 358, and a conductor 319A is formed in the remaining opening. In particular, the electrical conductor 319A is sometimes referred to as a TSV (Through Silicon Via: through silicon via).

As described above, the conductor 319A can use a material usable for the conductor 358. The insulator 318A has a function of insulating between the substrate 310A and the conductor 319A, for example. As the insulator 318A, for example, a material usable for the insulator 320 or the insulator 324 is preferably used.

Insulator 380 and conductor 358 are used as a bonding layer on the side of substrate 310, and insulator 382 and conductor 319A are used as a bonding layer on the side of substrate 310A. That is, the insulator 380 and the conductor 358 formed on the substrate 310 and the insulator 382 and the conductor 319A formed on the substrate 310A can be bonded together by, for example, a bonding process.

As a step before the bonding step, for example, a planarization process is performed on the substrate 310 side to make the heights of the respective surfaces of the insulator 380 and the conductor 358 uniform. In the same manner, planarization processing is performed on the substrate 310A side to make the heights of the insulator 382 and the conductor 319A uniform.

When bonding the insulator 380 and the insulator 382, that is, bonding the insulating layers to each other in the bonding step, for example, hydrophilic bonding may be used, in which, after high flatness is obtained by polishing (for example, chemical Mechanical Polishing (CMP)) method, surfaces subjected to hydrophilic treatment by oxygen plasma or the like are brought into contact for temporary bonding, and dehydration is performed by heat treatment, thereby performing main bonding. Hydrophilic bonding also occurs at the atomic level, and therefore mechanically excellent bonding can be obtained.

When the conductor 358 and the conductor 319A are bonded, even when the conductors are bonded to each other, a surface activation bonding method may be used in which an oxide film and an impurity adsorbing layer on the surface are removed by sputtering or the like and the cleaned and activated surface is brought into contact for bonding. Or diffusion bonding may be used in which surfaces are bonded using a combination of temperature and pressure. The above methods all involve atomic bonding, and therefore, excellent bonding both electrically and mechanically can be obtained.

By performing the bonding step, the conductor 358 on the substrate 310 side and the conductor 319A on the substrate 310A side can be electrically connected. In addition, the insulator 380 on the substrate 310 side can be connected to the insulator 382 on the substrate 310A side with sufficient mechanical strength.

In the case of bonding the substrate 310 and the substrate 310A, the insulating layer and the metal layer are mixed at each bonding surface, and thus, for example, a combination of a surface activation bonding method and a hydrophilic bonding method may be used. For example, a method of cleaning the surface after polishing, performing an oxygen-preventing treatment on the surface of the metal layer, and then performing a hydrophilic treatment to bond the metal layer may be used. Further, a difficult-to-oxidize metal such as gold may be used as the surface of the metal layer, and hydrophilic treatment may be performed.

In addition, a bonding method other than the above method may be used when the substrate 310 and the substrate 310A are bonded. For example, as a method for bonding the substrate 310 and the substrate 310A, a flip-chip bonding method may be used. In the case of using flip-chip bonding, a connection terminal such as a bump may be provided above the conductor 358 on the substrate 310 side or below the conductor 319A on the substrate 310A side. Examples of flip-chip bonding include: a method of bonding by injecting a resin including anisotropic conductive particles between insulator 380 and insulator 382 and between conductor 358 and conductor 319A: or a method of bonding using silver-tin soldering. In addition, when both the bump and the conductor connected to the bump are gold, an ultrasonic welding method may be used. In order to reduce physical stress such as impact or thermal stress, an underfill may be injected between the insulator 380 and the insulator 382 and between the conductor 358 and the conductor 319A, in addition to the flip-chip bonding method described above. For example, a die bonding film may be used when the substrate 310 and the substrate 310A are bonded.

< Structural example of display device 4>

Further, for example, the transistor 500 in the pixel layer PXAL of the display device 1000 shown in fig. 36 may be a transistor having another structure. The display device 1000C shown in fig. 43A is a structural example in which a transistor 200 is used as a BGTC (Bottom-Gate Top-Contact) transistor in the display device 1000 of fig. 36 instead of the transistor 500. Note that only the pixel layer PXAL is shown in the display device 1000C shown in fig. 43A, and the structure of the display device 1000 in fig. 36 is referred to as the circuit layer SICL and the wiring layer LINL.

In the display device 1000C of fig. 43A, an insulator 322 is provided over the wiring layer LINL.

The insulator 322 may use materials that may be used for the insulator 320.

A plurality of transistors 200 are formed on the insulator 322. The plurality of transistors 200 can be formed using the same material and the same process, for example.

Insulator 211, insulator 213, insulator 215, and insulator 214 are provided in this order on insulator 322. A portion of the insulator 211 is used as a gate insulating layer of each transistor. A portion of the insulator 213 is used as a gate insulating layer of each transistor. The insulator 215 is provided so as to cover the transistor. The insulator 214 is provided in such a manner as to cover the transistor, and is used as a planarizing layer. The number of gate insulating layers and the number of insulating layers covering the transistor are not particularly limited, and may be one or two or more stacked layers.

Preferably, a material which is not easily diffused by impurities such as water and hydrogen is used for at least one of insulating layers covering the transistor. Thereby, the insulating layer can be used as a barrier layer. By adopting such a structure, diffusion of impurities into the transistor from the outside can be effectively suppressed, so that the reliability of the display device can be improved.

An inorganic insulating film is preferably used for the insulator 211, the insulator 213, and the insulator 215. Examples of the inorganic insulating film include a silicon nitride film, a silicon oxynitride film, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, and an aluminum nitride film. Further, as the insulator 211, the insulator 213, and the insulator 215, for example, a hafnium oxide film, an yttrium oxide film, a zirconium oxide film, a gallium oxide film, a tantalum oxide film, a magnesium oxide film, a lanthanum oxide film, a cerium oxide film, and a neodymium oxide film can be used. The insulator 211, the insulator 213, and the insulator 215 may have a single-layer structure, or may have a structure (stacked structure) in which two or more of the insulating films are stacked.

The insulator 214 used as the planarizing layer preferably uses an organic insulating layer. Examples of the material that can be used for the organic insulating layer include acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimide amide resin, silicone resin, benzocyclobutene resin, phenol resin, and precursors of these resins. The insulator 214 may have a stacked structure of an organic insulating layer and an inorganic insulating layer. The outermost layer of insulator 214 is preferably used as an etch protection layer. Thus, formation of a recess in the insulator 214 during processing of the conductor 112a, the conductor 126a, or the conductor 129a described later can be suppressed. Alternatively, a concave portion may be provided in the insulator 214 when the conductor 112a, the conductor 126a, or the conductor 129a is processed.

Note that the insulator 214 corresponds to the insulator 599 in the display device 1000 of fig. 36. Accordingly, the method of forming the insulator or the conductor on the insulator 214 of the display device 1000C of fig. 43 may be described by replacing the insulator 599 with the insulator 214 in the method of forming the insulator or the conductor on the insulator 599 of the display device 1000 of fig. 36.

The plurality of transistors 200 includes: a conductor 221 serving as a gate; an insulator 211 serving as a gate insulating layer; conductors 222a and 222b serving as source and drain electrodes; a semiconductor layer 231; an insulator 213 serving as a gate insulating layer; and a conductor 223 serving as a gate. Here, as in the transistor 300, a plurality of layers formed by processing the same conductive film are hatched in the same manner. The insulator 211 is located between the conductor 221 and the semiconductor layer 231. Insulator 213 is located between conductor 223 and semiconductor layer 231.

The structure of the transistor included in the display device of this embodiment is not particularly limited. For example, a planar transistor, an interleaved transistor, an inverted interleaved transistor, or the like may be used. In addition, a top gate type or bottom gate type transistor structure may be employed. Alternatively, a gate electrode may be provided above and below the semiconductor layer forming the channel.

Each of the plurality of transistors 200 has a structure in which two gates sandwich a semiconductor layer forming a channel. Further, two gates may be connected to each other, and the same signal may be supplied to the two gates to drive the transistor. Alternatively, the threshold voltage of the transistor can be controlled by applying a potential for controlling the threshold voltage to one of the two gates and applying a potential for driving the other gate.

Further, the structure of the transistor 200 is not limited to that shown in fig. 43A. For example, the transistor 200 of the display device 1000C of fig. 43A may have a TGSA (Top GATE SELF ALIGN: top gate self-aligned) transistor structure shown in fig. 43B and 43C.

The transistor 200A and the transistor 200B include: a conductor 221 serving as a gate; an insulator 211 serving as a gate insulating layer; a semiconductor layer 231 including a channel formation region 231i and a pair of low-resistance regions 231 n; a conductor 222a connected to one of the pair of low-resistance regions 231 n; a conductor 222b connected to the other of the pair of low-resistance regions 231 n; an insulator 225 serving as a gate insulating layer; a conductor 223 serving as a gate; and an insulator 215 covering the conductor 223. The insulator 211 is located between the conductor 221 and the channel formation region 231 i. Insulator 225 is located at least between conductor 223 and channel formation region 231 i. Furthermore, an insulator 218 covering the transistor may be provided.

In the example shown in fig. 43B, the insulator 225 covers the top surface and the side surface of the semiconductor layer 231 in the transistor 200A. The conductors 222a and 222b are connected to the low-resistance region 231n through openings provided in the insulators 225 and 215. One of the conductor 222a and the conductor 222b is used as a source, and the other is used as a drain.

On the other hand, in the transistor 200B shown in fig. 43C, the insulator 225 overlaps with the channel formation region 231i of the semiconductor layer 231 and does not overlap with the low-resistance region 231 n. For example, the structure shown in fig. 43C can be formed by processing the insulator 225 using the conductor 223 as a mask. In fig. 43C, the insulator 215 is provided so as to cover the insulator 225 and the conductor 223, and the conductor 222a and the conductor 222b are connected to the low-resistance region 231n through the opening of the insulator 215, respectively.

< Structural example of display device 5>

For example, a panel having a touch sensor function (sometimes referred to as a touch panel) may be provided in the display device 1000 shown in fig. 36. In the display device 1000D shown in fig. 44, as an example, the resin layer 147, the insulator 103, the conductor 104, the insulator 105, and the conductor 106 are sequentially formed on the protective layer 131.

The resin layer 147 preferably contains an organic insulating material. Examples of the organic insulating material include acrylic resins, polyimide resins, epoxy resins, polyamide resins, polyimide amide resins, silicone resins, benzocyclobutene resins, phenolic resins, and precursors of these resins.

The insulator 103 preferably comprises an inorganic insulating material. Examples of the inorganic insulating material include oxides and nitrides such as silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, and hafnium oxide.

The conductors 104 and 106 are used as electrodes of a touch sensor. In the case where a mutual capacitance type is used as the touch sensor, for example, the following configuration may be adopted: a pulse potential is applied to one of the conductor 104 and the conductor 106, and a detection circuit such as an analog-digital (a-D) conversion circuit or a sense amplifier is electrically connected to the other. At this time, a capacitance is formed between the conductor 104 and the conductor 106. When a finger or the like approaches, the capacitance changes in magnitude (specifically, the capacitance decreases). When a pulse potential is applied to one of the conductor 104 and the conductor 106, the change in capacitance appears as a change in magnitude of the amplitude of the signal generated in the other. Thus, contact and proximity of a finger or the like can be sensed.

As the insulator 105, for example, an inorganic insulating film or an organic insulating film can be used. Specifically, as the insulator 105, for example, a resin such as an acrylic resin or an epoxy resin can be used. Alternatively, as the insulator 105, an inorganic insulating material such as silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, or aluminum oxide can be used. The insulator 105 may have a single-layer structure or a stacked-layer structure.

< Structural example of display device 6>

For example, the protective layer 131 of the display device 1000 shown in fig. 36 may have a stacked structure of two or more layers instead of a single-layer structure. The protective layer 131 may have, for example, a three-layer stacked structure in which an insulator of an inorganic material is used as a first layer, an insulator of an organic material is used as a second layer, and an insulator of an inorganic material is used as a third layer. Fig. 45 shows a partial sectional view of the display device 1000E, in which the protective layer 131a is an insulator of an inorganic material, the protective layer 131b is an insulator of an organic material, and the protective layer 131c is an insulator of an inorganic material, that is, the protective layer 131 including the protective layer 131a, the protective layer 131b, and the protective layer 131c has a multilayer structure. In addition, as shown in fig. 45, by using an insulator of an organic material as the protective layer 131b, the protective layer 131b can be provided as a planarizing film.

< Structural example of display device 7>

For example, the display device 1000 of fig. 36 may include a coloring layer (color filter) or the like. The display device 1000F shown in fig. 46 has a structure including a coloring layer 166R, a coloring layer 166G, and a coloring layer 166B between the adhesive layer 107 and the substrate 110, for example. The colored layer 166R, the colored layer 166G, and the colored layer 166B may be formed over the substrate 110, for example. In addition, in the case where the light-emitting device 130R includes a light-emitting layer that emits red (R) light, the light-emitting device 130G includes a light-emitting layer that emits green (G) light, and the light-emitting device 130B includes a light-emitting layer that emits blue (B) light, the colored layer 166R is red, the colored layer 166G is green, and the colored layer 166B is blue.

< Structural example 8 of display device >

Further, for example, the display device 1000 of fig. 36 may also use a light emitting device including an LED (including a Micro LED) instead of using a light emitting device including an organic EL element. In the display device 1000G of fig. 47A, as an example, the connection layer 152a is provided on the conductor 126a, the LED chip 150a is provided on the connection layer 152a, and the common electrode 115 is provided on the LED chip 150 a. Similarly, the conductor 126b is provided with a connection layer 152b, the connection layer 152b is provided with an LED chip 150b, and the LED chip 150b is provided with the common electrode 115. Similarly, the conductor 126c is provided with a connection layer 152c, the connection layer 152c is provided with an LED chip 150c, and the LED chip 150c is provided with the common electrode 115.

In the display device 1000G of fig. 47A, an insulator 125 is formed on the side surfaces of the connection layer 152a and the LED chip 150a, as an example. At this time, by forming the insulator 125 by the ALD method, the insulator 125 can be formed between the LED chip 150a and the conductor 126a as well. Note that the insulator 125 between the LED chip 150b and the conductor 126b is also the same.

The LED chip is a light emitting diode in which an electrode serving as a cathode, an electrode serving as an anode, a p-type semiconductor, an n-type semiconductor, and a light emitting layer are provided over a substrate. Note that in this specification and the like, the description may be made with the "LED chip" replaced with the "light emitting diode" in some cases.

In particular, in the present specification, a light emitting diode having an area of an LED chip of 10000 μm ² or less may be referred to as a micro light emitting diode, a light emitting diode having an area of an LED chip of more than 10000 μm ² and 1mm ² or less may be referred to as a sub-millimeter light emitting diode, and a light emitting diode having an area of an LED chip of more than 1mm ² may be referred to as a macro light emitting diode. Note that the area of the LED chip here may be, for example, the area of the top surface or the bottom surface of the substrate 181 in fig. 49A, 49C, and 49D described later. Or the area of the LED chip may be, for example, the area of the top surface or the bottom surface of the electrode 183A in fig. 49B described later.

For example, a light emitting diode having an area of 100 μm ² or less of an LED chip can be said to be a Micro light emitting diode (Micro LED chip). Further, as a light emitting diode usable for an LED package having an area of 1mm ², for example, a Micro LED chip or a Mini LED chip may be used in some cases.

In the display device according to one embodiment of the present invention, the LED package may use a micro light emitting diode, a sub-millimeter light emitting diode, or a macro light emitting diode. In particular, the display device according to one embodiment of the present invention preferably includes a micro light emitting diode or a sub-millimeter light emitting diode, and more preferably includes a micro light emitting diode.

In particular, the area of the LED chip of the light emitting diode is preferably 1mm ² or less, more preferably 10000 μm ² or less, still more preferably 3000 μm ² or less, still more preferably 700 μm ² or less.

The area of the light emitting region of the light emitting diode is preferably 1mm ² or less, more preferably 10000 μm ² or less, further preferably 3000 μm ² or less, and further preferably 700 μm ² or less. Note that the area of the light emitting region of the light emitting diode here may be, for example, the area of the top surface or the bottom surface of the light emitting layer 184 in fig. 49A to 49D described later.

In this embodiment, a case where a micro light emitting diode is used as a light emitting diode will be described in particular. Note that in this embodiment mode, a micro light emitting diode having a double heterojunction is described. Note that the light emitting diode is not particularly limited, and for example, a micro light emitting diode having a quantum well junction, a light emitting diode using a nanopillar, or the like may also be used.

Fig. 47B shows a specific structural example of the LED chip 150 a. The LED chip 150a includes, for example, a substrate 153a on the connection layer 152a, a connection layer 154a on the substrate 153a, a conductor 155a on the connection layer 154a, a semiconductor layer 156a on the conductor 155a, a light emitting layer 157a on the semiconductor layer 156a, and a semiconductor layer 158a on the light emitting layer 157 a. The LED chip 150b and the LED chip 150c may have the same configuration as the LED chip 150 a. In addition, in the LED chips 150a to 150c, only the light-emitting layer (emission color) may be different and other components may be the same. In addition, the common electrode 115 is located on the semiconductor layer 158a. In fig. 47B, the conductor 126a, the connection layer 152a, the common electrode 115, and the protective layer 131 are shown in addition to the LED chip 150 a.

The connection layer 152a may use a conductive material. As the connection layer 152a, for example, metals such as gold, silver, and tin, alloys containing these metals, conductive films, or conductive pastes can be used. Gold may be suitably used for the connection layer 152a, for example. The connection layer 152a may be formed using a printing method, a transfer method, or a spraying method.

As the substrate 153a and the connection layer 154a, for example, a conductive silicon substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, a metal substrate, or an alloy substrate can be used. The metal substrate includes one or more substrates selected from tungsten, copper, gold, nickel, and titanium. As an example of the alloy substrate, a si—al alloy substrate can be given.

The conductor 155a is electrically connected to the substrate 153a through the connection layer 154 a. As the conductor 155a, for example, a conductive layer functioning as a reflective electrode can be used. That is, the conductors 155a may use materials usable for the conductors 112a to 112c and the conductors 126a to 126 c.

The substrate 153a is electrically connected to the conductor 126a through the connection layer 152 a. In the display device 1000G, the connection layer 152a, the substrate 153a, the connection layer 154a, and the conductor 155a are used together as a pixel electrode.

The light emitting layer 157a is sandwiched between the semiconductor layer 156a and the semiconductor layer 158 a. The light-emitting layer 157a has a function of emitting light by bonding of electrons and holes. One of the semiconductor layer 156a and the semiconductor layer 158a may use an n-type semiconductor layer, and the other may use a p-type semiconductor layer. The light emitting layer 157a may use an n-type, i-type, or p-type semiconductor layer. In other words, the semiconductor layer can be used for each of the semiconductor layer 156a, the light-emitting layer 157a, and the semiconductor layer 158 a. Note that the semiconductor layer 156a, the light-emitting layer 157a, and the semiconductor layer 158a are sometimes collectively referred to as an LED layer.

The LED layer is formed to emit light such as red light, yellow light, green light, blue light, or ultraviolet light. The structure of the LED layer is not particularly limited, and may be a homojunction structure having a pn junction or a pin junction, a heterojunction structure or a double heterojunction structure, or a MIS (Metal Insulator Semiconductor: metal-insulator-semiconductor) junction. The LED layers may also have a superlattice structure, a single quantum well structure, or a multiple quantum well (MQW: multi Quantum Well) structure. In addition, the LED layer may use a nano-pillar.

For example, a compound containing a group 13 element and a group 15 element can be used for the LED layer. Examples of the group 13 element include aluminum, gallium, and indium. Examples of the group 15 element include nitrogen, phosphorus, arsenic and antimony. The LED layer may use, for example, a gallium-phosphorus compound, a gallium-arsenic compound, a gallium-aluminum-arsenic compound, an aluminum-gallium-indium-phosphorus compound, gallium nitride (GaN), an indium-gallium nitride compound, or a selenium-zinc compound.

For example, gallium nitride may be used for the LED layer that emits light in the ultraviolet to blue wavelength region. An indium-gallium nitride compound may be used for the LED layer that emits light in the ultraviolet to green wavelength region. As the LED layer that emits light in the wavelength region of green to red, an aluminum-gallium-indium-phosphorus compound or a gallium-arsenic compound may be used. A gallium-arsenic compound may be used for the LED layer that emits light in the wavelength region of infrared.

The display device 1000G has a structure in which a plurality of LED chips are provided, but the entire display portion may be constituted by one LED chip.

The display device 1000G has a structure in which one LED chip emits light of one color, but may have a structure in which one LED chip emits light of two or more colors. That is, the LED chip included in the display device 1000G may have a stacked structure in which a semiconductor layer of one of n-type and p-type, a light-emitting layer, and a semiconductor layer of the other of n-type and p-type are provided for each color.

In addition, fig. 48 shows a structure of a display device including a light emitting device having an LED (including a Micro LED) unlike the display device 1000G. The display device 1000H shown in fig. 48 is different from the display device 1000G in that the display device is mounted with a packaged LED chip. Specifically, the display device 1000H has a structure in which the LED package 170R, LED package 170G and the LED package 170B are provided as light emitting devices in the pixel layer PXAL.

In the display device 1000H of fig. 48, as an example, the insulators 599 are provided with the conductors 111a to 111c and the conductors 112a to 112c. Further, protective layers 116 are provided on the conductors 111a to 111c, the conductors 112a to 112c, and the insulator 599. The protective layer 116 is formed so as to fill an opening portion of the insulator 599 with the conductor 596 as a bottom surface. In particular, the protective layer 116 is preferably provided so as to cover the respective end portions of the conductors 111a to 111c and the conductors 112a to 112c.

For example, a resin such as an acrylic resin, a polyimide resin, an epoxy resin, or a silicone resin is preferably used as the protective layer 116. By providing the protective layer 116, the conductors 117a and 117b, which will be described later, can be prevented from contacting each other and shorting. In addition, the protective layer 116 may not be provided on the insulator 599, the conductors 111a to 111c, and the conductors 112a to 112c, as the case may be.

An opening is provided in a region of the protective layer 116 overlapping a part of each of the conductors 111a to 111c and a region overlapping a part of each of the conductors 112a to 112 c. Further, the protective layer 116 is provided with a conductor 117a and a conductor 117b. In particular, the conductor 117a is provided so as to fill the opening provided in the region of the protective layer 116 overlapping the respective portions of the conductors 112a to 112c, and the conductor 117b is provided so as to fill the opening provided in the region of the protective layer 116 overlapping the respective portions of the conductors 111a to 111 c.

As the conductors 117a and 117b, for example, a conductive paste containing a material such as silver, carbon, or copper, or a bump containing a material such as gold or solder can be suitably used. Further, it is preferable to use a conductive material having a low contact resistance with the conductor 117a (the conductor 117 b) for each of the conductors 112a to 112c (the conductors 111a to 111 c) and the electrode 172 (the electrode 173) described later, which are electrically connected to the conductor 117a (the conductor 117 b). For example, when silver paste is used as the conductor 117a (the conductor 117 b), the contact resistance with the conductor 117a (the conductor 117 b) can be reduced by using aluminum, titanium, copper, or an alloy of silver, palladium, and copper (ag—pd—cu (APC)) as each conductive material for the conductors 112a to 112c (the conductors 111a to 111 c) and the electrode 172 (the electrode 173) described later.

The LED package 170R, LED, the LED package 170G, and the LED package 170B are mounted on the conductors 117a and 117B. Fig. 49A shows a specific structural example of the LED package 170R, LED package 170G and the LED package 170B included in the display device 1000H of fig. 48.

The LED package 170 of fig. 49A includes a substrate 171, an electrode 172, an electrode 173, a heat sink 174, an adhesive layer 175, a housing 176, leads 177, leads 179, a sealing layer 178, balls 189, and an LED chip 180.

The LED chip 180 includes a substrate 181, a semiconductor layer 182, an electrode 183, a light emitting layer 184, a semiconductor layer 185, an electrode 186, and an electrode 187.

The substrate 171 may be, for example, a glass epoxy substrate, a polyimide substrate, a ceramic substrate, an alumina substrate, or an aluminum nitride substrate.

The electrode 172 and the electrode 173 are formed on the top surface, the side surface, and the bottom surface of the substrate 171. In particular, the electrode 172 formed on the top surface, the side surface, and the bottom surface of the substrate 171 is used as one wiring, and similarly, the electrode 173 formed on the top surface, the side surface, and the bottom surface of the substrate 171 is used as the other wiring. Note that the electrode 172 and the electrode 173 are in a non-conductive state.

Further, the substrate 171 is provided with a heat sink 174. The heat sink 174 has a function of releasing heat generated in the LED chip 180, for example.

The same material may be used for the electrode 172, the electrode 173, and the heat sink 174. For example, one element selected from nickel, copper, silver, platinum, and gold, or an alloy material having a content of the element of 50% or more may be used for the electrode 172, the electrode 173, and the heat sink 174.

The electrode 172, the electrode 173, and the heat sink 174 may be formed by the same process.

The LED chip 180 is attached to the substrate 171 by an adhesive layer 175. Specifically, the substrate 181 of the LED chip 180 is provided so as to overlap with the heat sink 174 of the substrate 171 via the adhesive layer 175. The material of the adhesive layer 175 is not particularly limited. For example, by using an adhesive having conductivity as a material of the adhesive layer 175, heat dissipation of the LED chip 180 can be improved.

As the substrate 181, a single crystal substrate such as a sapphire substrate, a silicon carbide substrate, a silicon substrate, or a gallium nitride substrate can be used.

In the LED chip 180, a semiconductor layer 182 is formed on a substrate 181. In addition, an electrode 183 is formed over a portion of the semiconductor layer 182, and a light-emitting layer 184 is formed over another portion of the semiconductor layer 182. Further, a semiconductor layer 185 is formed over the light-emitting layer 184, an electrode 186 is formed over the semiconductor layer 185, and an electrode 187 is formed over a portion of the electrode 186.

In the LED chip 180, the light emitting layer 184 is sandwiched between the semiconductor layer 182 and the semiconductor layer 185. In the light emitting layer 184, electrons and holes are bonded to emit light. Further, one of the semiconductor layer 182 and the semiconductor layer 185 is an n-type semiconductor layer, and the other of the semiconductor layer 182 and the semiconductor layer 185 is a p-type semiconductor layer.

In addition, in the light emitting diode included in each of the LED chips of the LED package 170R, LED and the LED package 170B mounted in the display device 1000H of fig. 48, a stacked structure including a pair of semiconductor layers and a light emitting layer between the pair of semiconductor layers is formed so as to emit light of red, green, blue, or the like. Accordingly, the color of light emitted from the light emitting diode can be freely determined according to the respective LED chips of the LED packages 170R, LED, 170G and 170B, respectively. As the stacked structure, for example, a gallium-phosphorus compound, a gallium-arsenic compound, a gallium-aluminum-arsenic compound, an aluminum-gallium-indium-phosphorus compound, a gallium nitride, an indium-gallium nitride compound, or a selenium-zinc compound can be used.

In addition, the light emitting color of the light emitting diode included in the LED chip 180 of the LED package 170 may be cyan, magenta, yellow, or white in addition to red, green, and blue.

Electrode 183 is electrically connected to electrode 172 through lead 177. In other words, the electrode 183 is used as a pixel electrode of the light emitting diode. In addition, the electrode 187 is electrically connected to the electrode 173 through the lead 179. That is, the electrode 187 is used as a common electrode of the light emitting diode.

Examples of the bonding method of the electrode 183 and the wire 177, the bonding method of the electrode 172 and the wire 177, the bonding method of the electrode 187 and the wire 179, and the bonding method of the electrode 173 and the wire 179 include wire bonding. The type of the wire bonding method may be a thermocompression bonding method or an ultrasonic bonding method. In addition, in the bonding step of the lead 177 and the lead 179 by the wire bonding method, the ball 189 having the same material as the lead 179 is formed on the electrode 172, the electrode 173, the electrode 183, and the electrode 187.

For example, materials usable for the conductors 111a to 111c and the conductors 112a to 112c are preferably used for the electrodes 183, 186, and 187. In particular, since the light emitting layer 184 of the LED chip 180 emits light to the upper side of the LED package 170, the electrode 186 is preferably made of a conductive material having light transmittance among materials usable for the conductors 111a to 111c and the conductors 112a to 112 c. For the same reason, it is also preferable to use a conductive material having light transmittance among materials usable for the conductors 111a to 111c and the conductors 112a to 112c for the electrode 187.

As the lead 177 and the lead 179, for example, thin metal wires such as gold, an alloy containing gold, copper, or an alloy containing copper can be used.

As a material of the case 176, a resin may be used. The case 176 may cover the side surface of the sealing layer 178 or may not cover the top surface of the LED chip 180. That is, for example, the sealing layer 178 may be exposed on the top surface side of the LED chip 180. Further, a reflecting sheet made of ceramic or the like is preferably provided on the inner side surface of the case 176, specifically, around the LED chip 180 (around each of the substrate 181, the semiconductor layer 182, the electrode 183, the light-emitting layer 184, the semiconductor layer 185, the electrode 186, and the electrode 187). When a part of the light emitted from the light emitting layer 184 of the LED chip 180 is reflected by the reflective sheet, more light may be extracted from the LED package 170.

The interior of the housing 176 is filled with a sealing layer 178. For example, a resin having transparency to visible light is preferably used for the sealing layer 178. Specifically, for example, an ultraviolet curable resin or a visible light curable resin such as an epoxy resin or a silicone resin can be used as the sealing layer 178.

Further, for example, various optical members may be disposed on top surfaces of the resin layer 148, the LED package 170R, LED, the package 170G, and the LED package 170B of the display device 1000H. As the optical member, a polarizing plate, a retardation plate, a light diffusion layer (diffusion film or the like), an antireflection layer, a condensing film (condensing film) and the like can be used. Further, an antistatic film for suppressing adhesion of dust, a film having water repellency which is less likely to be stained, a hard coat film for suppressing damage in use, an impact absorbing layer, and other surface protective layers may be disposed on the top surfaces of the resin layer 148, the LED package 170R, LED package 170G, and the LED package 170B of the display device 1000H. For example, a glass layer or a silicon oxide layer (SiO _x layer) is provided as a surface protective layer, so that the surface can be prevented from being stained or damaged. Further, DLC (diamond-like carbon), alumina (AlO _x), a polyester material, a polycarbonate material, or the like may be used as the surface protective layer. In addition, a material having high transmittance to visible light is preferably used as the surface protective layer. In addition, a material having high hardness is preferably used for the surface protective layer.

Next, a structural example of an LED package 170 which is different from the LED package 170 of fig. 49A, which can be used for the LED package 170R, LED and the LED package 170B of the display device 1000H, will be described.

The LED package 170A1 shown in fig. 49B is different from the LED package 170 of fig. 49A in that: the substrate 171 is provided with an LED chip 180A. Note that the pixel electrode of the LED chip 180A is not bonded by the wiring 177 but by the adhesive layer 175.

The LED package 170A1 of fig. 49B includes a substrate 171, an electrode 172, an electrode 173, an adhesive layer 175, a housing 176, leads 179, a sealing layer 178, balls 189, and an LED chip 180A.

Further, in the LED package 170A1 of fig. 49B, the LED chip 180A includes an electrode 183A and a light emitting diode provided on the electrode 183A. The light emitting diode includes a semiconductor layer 182, a light emitting layer 184, a semiconductor layer 185, an electrode 186, and an electrode 187.

For example, a conductive substrate may be used for the electrode 183A. Examples of the type of the conductive substrate include a metal substrate.

Further, a semiconductor layer 182, a light-emitting layer 184, a semiconductor layer 185, an electrode 186, and an electrode 187 are sequentially formed over the electrode 183A.

Note that the semiconductor layer 182, the light emitting layer 184, the semiconductor layer 185, the electrode 186, and the electrode 187 are described with reference to the LED package 170 of fig. 49A.

In the LED package 170A1 of fig. 49B, the electrode 172 and the electrode 173 are formed on the top surface, the side surface, and the bottom surface of the substrate 171. In particular, the electrode 172 is also formed in a region of the substrate 171 where the LED chip 180A is disposed. The electrode 172 formed on the top surface, the side surface, and the bottom surface of the substrate 171 is used as one wiring, and similarly, the electrode 173 formed on the top surface, the side surface, and the bottom surface of the substrate 171 is used as the other wiring. Note that the electrode 172 and the electrode 173 are in a non-conductive state.

Further, the LED chip 180A is attached to the substrate 171 by the adhesive layer 175. Specifically, the electrode 183A of the LED chip 180A is provided so as to overlap with a region of a part of the electrode 172 of the substrate 171 through the adhesive layer 175. The adhesive layer 175 is an adhesive having conductivity.

As described above, in the case of using the LED chip 180A in which the light emitting diode is formed on the conductive substrate, the LED package 170A2 can be configured by bonding the pixel electrode of the LED chip 180A to the electrode 172 of the substrate 171 using the adhesive layer 175 without using the lead 177.

Next, a configuration example of an LED package which is different from the LED package 170 of fig. 49A and the LED package 170A1 of fig. 49B, which can be used for the LED package 170R, LED and the LED package 170B of the display device 1000H, will be described.

The LED package 170A2 shown in fig. 49C is different from the LED package of fig. 49A in that a color conversion layer 190 is provided on the inner side of the case 176.

Note that fig. 49C shows a structure in which the color conversion layer 190 is provided over the sealing layer 178, but the configuration of the color conversion layer 190 is not limited thereto. For example, the color conversion layer 190 may also be dispersed inside the sealing layer 178.

Phosphor and Quantum Dot (QD) are preferably used as the color conversion layer 190. In particular, since the peak width of the emission spectrum of the quantum dot is narrow, light emission with high color purity can be obtained. By using quantum dots for the color conversion layer 190, display quality of the display device 1000H can be improved.

The color conversion layer 190 has a function of converting light emitted from the light emitting layer 184 included in the LED chip 180 of the LED package 170A2 into light of other colors.

As the color conversion layer 190, for example, a color conversion layer that converts blue light into green light or a conversion layer that converts blue light into red light may be used. For example, when a blue light emitting diode is provided in the red subpixel, blue light emitted from the blue light emitting diode is converted into red light by the color conversion layer 190 and emitted to the upper side of the housing 176, that is, to the outside of the display device 1000H. In addition, for example, when a blue light emitting diode is provided in the green subpixel, blue light emitted from the blue light emitting diode is converted into green light by the color conversion layer 190 and emitted to the upper side of the housing 176, that is, to the outside of the display device 1000H.

The color conversion layer 190 may be formed using a droplet discharge method (e.g., an inkjet method), a coating method, an imprinting (imprinting) method, various printing methods (screen printing, offset printing), or the like. The color conversion layer 190 may be a color conversion film such as a quantum dot film.

As the phosphor, an organic resin layer on the surface of which the phosphor is printed or coated or an organic resin layer mixed with the phosphor can be used.

The material constituting the quantum dot is not particularly limited, and examples thereof include a group 14 element, a group 15 element, a group 16 element, a compound containing a plurality of group 14 elements, a group 4 to group 14 element and a group 16 element, a group 2 element and a group 16 element, a group 13 element and a group 15 element, a group 13 element and a group 17 element, a group 14 element and a group 15 element, a group 11 element and a group 17 element, iron oxides, titanium oxides, a chalcogenide spinel (spinel chalcogenide), a semiconductor cluster, and the like.

In particular, the method comprises the steps of, examples of the compound include cadmium selenide, cadmium sulfide, cadmium telluride, zinc selenide, zinc oxide, zinc sulfide, zinc telluride, mercury sulfide, mercury selenide, mercury telluride, indium arsenide, indium phosphide, gallium arsenide, gallium phosphide, indium nitride, gallium nitride, indium antimonide, gallium antimonide, aluminum phosphide, aluminum arsenide, aluminum antimonide, lead selenide, lead telluride, lead sulfide, indium selenide, indium telluride, indium sulfide, gallium selenide, arsenic sulfide, arsenic selenide, arsenic telluride, antimony sulfide, antimony selenide, antimony telluride, bismuth sulfide, bismuth selenide, bismuth telluride, silicon carbide, germanium, tin, selenium, tellurium, boron, carbon, phosphorus, boron nitride, boron phosphide, boron arsenide, aluminum nitride, aluminum sulfide, barium selenide, barium telluride, calcium sulfide, calcium selenide calcium telluride, beryllium sulfide, beryllium selenide, beryllium telluride, magnesium sulfide, magnesium selenide, germanium sulfide, germanium selenide, germanium telluride, tin sulfide, tin selenide, tin telluride, lead oxide, copper fluoride, copper chloride, copper bromide, copper iodide, copper oxide, copper selenide, nickel oxide, cobalt sulfide, iron oxide, iron sulfide, manganese oxide, molybdenum sulfide, vanadium oxide, tungsten oxide, tantalum oxide, titanium oxide, zirconium oxide, silicon nitride, germanium nitride, aluminum oxide, barium titanate, compounds of selenium zinc cadmium, compounds of indium arsenic phosphorus, compounds of cadmium selenium sulfur, compounds of cadmium selenium tellurium, compounds of indium gallium arsenic, compounds of indium gallium selenium, compounds of indium selenium sulfur, compounds of copper indium sulfur, combinations thereof, and the like. In addition, so-called alloy type quantum dots having a composition expressed in an arbitrary ratio may be used.

The quantum dot structure includes a Core type, a Core-Shell type, a Core-multishell type (Core-Multishell) type, and the like. In addition, in quantum dots, the proportion of surface atoms is high, so that the reactivity is high and aggregation is likely to occur. Therefore, the surface of the quantum dot is preferably attached with a protective agent or provided with a protective group. Thus, aggregation can be prevented and solubility to a solvent can be improved. In addition, electrical stability can be improved by reducing reactivity.

The smaller the size (diameter) of the quantum dot, the larger the band gap, and thus the size thereof is appropriately adjusted to obtain light of a desired wavelength. As the crystal size becomes smaller, the luminescence of the quantum dot shifts to the blue side (i.e., to the high energy side), and thus, by changing the size of the quantum dot, the luminescence wavelength thereof can be adjusted in a wavelength region of the spectrum covering the ultraviolet region, the visible region, and the infrared region. The size (diameter) of the quantum dot is, for example, 0.5nm or more and 20nm or less, preferably 1nm or more and 10nm or less. The smaller the size distribution of the quantum dot, the narrower the emission spectrum, and therefore, light emission with high color purity can be obtained. The shape of the quantum dot is not particularly limited, and may be spherical, rod-like, disk-like, or other shapes. Quantum rods, which are rod-shaped quantum dots, have a function of exhibiting directional light.

Or the LED package 170A2 may have a stacked structure of the color conversion layer 190 and the coloring layer inside or above it. Thus, when the light converted by the color conversion layer 190 passes through the coloring layer, the color purity of the light can be improved. In addition, a colored layer having the same color as the color of light emitted from the light-emitting layer 184 may be provided at a position overlapping with the LED chip 180 (the substrate 181, the semiconductor layer 182, the electrode 183, the light-emitting layer 184, the semiconductor layer 185, the electrode 186, and the electrode 187). By providing the coloring layers of the same color, the color purity of the light emitted from the light emitting layer 184 can be improved. In addition, when the LED package 170A2 is not provided with a coloring layer, the manufacturing process can be simplified.

The colored layer is a colored layer that transmits light in a specific wavelength region. For example, a color filter or the like that transmits light in a wavelength region of red, green, blue, or yellow may be used. Examples of the material that can be used for the coloring layer include a metal material, a resin material containing a pigment or a dye, and the like.

As described above, by providing the color conversion layer above the LED chip 180, light having good color purity can be emitted from the LED package 170 A2.

Next, a configuration example of an LED package which is different from the LED package 170 of fig. 49A, the LED package 170A1 of fig. 49B, and the LED package 170A2 of fig. 49C, which can be used for the LED package 170R, LED package 170G and the LED package 170B of the display device 1000H, will be described.

The LED package 170A3 shown in fig. 49D is different from the LED package 170 of fig. 49A in that: the substrate 181 of the LED chip 180 provided on the substrate 171 is located above, and the electrode 183 and the electrode 187 are located below.

When this structure is adopted, light from the layer 184 is emitted to the upper side of the LED package 170A3, and therefore the substrate 181 preferably has light transmittance.

In the LED package 170A3 of fig. 49D, the top surfaces of the electrodes 183 and 187 of the LED chip 180 face the substrate 171 side, and therefore, the bonding of the electrodes 183 and 172 and the bonding of the electrodes 187 and 173 are not performed by wires but by conductors serving as bumps. Specifically, electrode 183 is joined to electrode 172 by conductor 191, and electrode 187 is joined to electrode 173 by conductor 192.

As the conductor 191 and the conductor 192, materials usable for the conductor 117a and the conductor 117b can be used.

Next, the number of LED chips 180 that can be provided in the LED package 170 is described. Fig. 50A is an example of a top view of the LED package 170 of fig. 49A. Further, fig. 50A shows a substrate 181 of a constituent element of the LED chip 180. As shown in fig. 50A, the structure in which the LED package 170 includes one LED chip 180 on the substrate 171 is described as an example, but one embodiment of the present invention is not limited thereto. For example, the LED package 170 may have a structure in which the number of LED chips provided on the substrate 171 is plural instead of one.

As an example, fig. 50B shows a structure of an LED package 170S in which three of an LED chip 180R, LED chip 180G and an LED chip 180B are provided over a substrate 171. Note that fig. 50B shows a substrate 181R, LED of the components of the LED chip 180R, a substrate 181G of the components of the chip 180G, and a substrate 181B of the components of the LED chip 180B. The LED chips 180R, LED and 180G and 180B provided in the LED package 170S may include light emitting layers that emit light of different colors from each other. For example, by providing a light emitting diode that emits red light on the substrate 181R, providing a light emitting diode that emits green light on the substrate 181G, and providing a light emitting diode that emits blue light on the substrate 181B, the LED package 170S can emit light of three colors of red light, green light, and blue light.

In the above-described LED packages 170, 170A1, 170A2, 170A3, and 170S, the light emitting diodes (the LED chips 180R, LED, 180G, and 180B) may be driven by transistors having the same structure or transistors having different structures. For example, in the display device 1000H of fig. 48, one or more selected from the group consisting of a size of a transistor, a channel length, a channel width, and a structure, among a transistor driving the LED chip 180R in the LED package 170R, a transistor driving the LED chip 180G in the LED package 170G, and a transistor driving the LED chip 180B in the LED package 170B, may be different from each other. Specifically, one or both of the channel length and the channel width of the transistor may be changed according to the amount of current and the color to be used for light emission at a desired luminance.

In the display device 1000H of fig. 48, the top surface of the protective layer 116, the top surface and side surfaces of the conductive body 117a, the top surface and side surfaces of the conductive body 117B, and the side surfaces of the LED packages 170R, LED, 170G, 170B may be covered with the resin layer 148. When a black resin is used as the resin layer 148, display contrast of the display device 1000H can be improved. One or the other of the surface protection layer and the impact absorbing layer may be provided on one or more selected from the top surface of the resin layer 148, the top surface of each of the LED packages 170R, LED, 170G, and 170B. Since the LED packages 170R, LED and 170B each have a structure to emit light upward, the layers provided on the top surfaces of the LED packages 170R, LED and 170G and 170B preferably have visible light transmittance.

In the LED package 170R, LED package 170G and the LED package 170B, the conductors 112a to 112c, the conductor 117a, and the electrode 172 are sometimes referred to as pixel electrodes. Further, the conductors 112a to 112c, the conductor 117a, and a part of the electrode 172 are sometimes referred to as pixel electrodes.

Note that the display device according to one embodiment of the present invention is not limited to the structure of the display device 1000G shown in fig. 47 or the display device 1000H shown in fig. 48. The display device according to one embodiment of the present invention may have a structure in which the structure of the display device 1000G shown in fig. 47 or the structure of the display device 1000H shown in fig. 48 is appropriately changed.

For example, the display device according to one embodiment of the present invention may be configured such that a substrate formed with a plurality of light emitting diodes is bonded to the upper side of the substrate 310, instead of the structure in which a plurality of LED packages 170 are mounted to the upper side of the substrate 310.

As an example, fig. 51A shows a display device 1000I in which a substrate 410 formed with a plurality of light emitting diodes is attached to a structure (hereinafter, this structure is referred to as a laminate SST) of a protective layer 116 formed to a display device 1000H of fig. 48. In addition, fig. 51B shows a plurality of light emitting diodes and a substrate 410 formed with the plurality of light emitting diodes.

Note that in fig. 51A and 51B, the light emitting diodes 420R, 420G, and 420B are shown as a plurality of light emitting diodes. In addition, the light emitting diodes 420R, 420G, and 420B may be collectively referred to as light emitting diodes 420.

As an example, the light emitting diode 420R includes an electrode 183a, a semiconductor layer 182a, a light emitting layer 184a, a semiconductor layer 185a, and an electrode 186a. In addition, the light emitting diode 420G includes, as an example, an electrode 183b, a semiconductor layer 182b, a light emitting layer 184b, a semiconductor layer 185b, and an electrode 186b. In addition, the light emitting diode 420B includes an electrode 183c, a semiconductor layer 182c, a light emitting layer 184c, a semiconductor layer 185c, and an electrode 186c, as an example.

In the substrate 410 of fig. 51B, a semiconductor layer 185a to a semiconductor layer 185c are formed over the substrate 410. In addition, light-emitting layers 184a to 184c are formed in each partial region over the semiconductor layers 185a to 185c. Further, a semiconductor layer 182a is formed over the light-emitting layer 184a, a semiconductor layer 182b is formed over the light-emitting layer 184b, and a semiconductor layer 182c is formed over the light-emitting layer 184c. In addition, the protective layer 411 is formed so as to cover the top surface of the substrate 410, the top surfaces and the side surfaces of the semiconductor layers 185a to 185c, the side surfaces of the light-emitting layers 184a to 184c, and the top surfaces and the side surfaces of the semiconductor layers 182a to 182.

In addition, an opening is provided in a region of the protective layer 411 which overlaps with a part of the semiconductor layer 182a, and an electrode 183a is formed so as to cover a part of the protective layer 411 and the top surface of the semiconductor layer 182a which is a bottom surface of the opening. Similarly, an opening is provided in a region of the protective layer 411 which overlaps with a part of the semiconductor layer 182b, and an electrode 183b is formed so as to cover a part of the protective layer 411 and the top surface of the semiconductor layer 182b which is the bottom surface of the opening. Similarly, an opening is provided in a region of the protective layer 411 which overlaps with a part of the semiconductor layer 182c, and an electrode 183c is formed so as to cover a part of the protective layer 411 and the top surface of the semiconductor layer 182c which is the bottom surface of the opening.

In addition, an opening is provided in a region of the protective layer 411 which does not overlap with the semiconductor layer 182a and the light-emitting layer 184a and which overlaps with a part of the semiconductor layer 185a, and an electrode 186a is formed so as to cover a part of the protective layer 411 and the top surface of the semiconductor layer 185a which is a bottom surface of the opening. Similarly, an opening is provided in a region of the protective layer 411 which does not overlap with the semiconductor layer 182b and the light-emitting layer 184b and overlaps with a part of the semiconductor layer 185b, and an electrode 186b is formed so as to cover a part of the protective layer 411 and the top surface of the semiconductor layer 185b which is the bottom surface of the opening. Similarly, an opening is provided in a region of the protective layer 411 which does not overlap with the semiconductor layer 182c and the light-emitting layer 184c and overlaps with a part of the semiconductor layer 185c, and an electrode 186c is formed so as to cover a part of the protective layer 411 and the top surface of the semiconductor layer 185c which is the bottom surface of the opening.

The display device 1000I adopts a top emission type structure. Light emitted from the light emitting diodes 420R, 420G, and 420B is emitted to the substrate 410 side. Therefore, a material having high visible light transmittance is preferably used for the substrate 410. For example, as the substrate 410, a substrate having high visible light transmittance can be selected from substrates usable for the substrate BS.

As shown in fig. 51A and 51B, the light-emitting layer 184a is sandwiched between the semiconductor layer 182a and the semiconductor layer 185 a. In the light emitting layer 184a, electrons and holes are bonded to emit light. Further, one of the semiconductor layer 182a and the semiconductor layer 185a is an n-type semiconductor layer, and the other of the semiconductor layer 182a and the semiconductor layer 185a is a p-type semiconductor layer. Likewise, the light-emitting layer 184b is sandwiched between the semiconductor layer 182b and the semiconductor layer 185 b. In the light emitting layer 184b, electrons and holes are bonded to emit light. In addition, one of the semiconductor layer 182b and the semiconductor layer 185b is an n-type semiconductor layer, and the other of the semiconductor layer 182b and the semiconductor layer 185b is a p-type semiconductor layer. Likewise, the light-emitting layer 184c is sandwiched between the semiconductor layer 182c and the semiconductor layer 185 c. In the light emitting layer 184c, electrons and holes are bonded to emit light. In addition, one of the semiconductor layer 182c and the semiconductor layer 185c is an n-type semiconductor layer, and the other of the semiconductor layer 182c and the semiconductor layer 185c is a p-type semiconductor layer.

In addition, in each of the light emitting diode 420R, the light emitting diode 420G, and the light emitting diode 420B mounted in the display device 1000I of fig. 51A, a stacked structure including a pair of semiconductor layers and a light emitting layer between the pair of semiconductor layers is formed so as to exhibit light of red, green, blue, or the like. Therefore, the colors of the light emitted by the light emitting diodes 420R, 420G, and 420B can be freely determined. For example, the light emitting diodes 420R, 420G, and 420B may be a red light emitting diode, a green light emitting diode, and a blue light emitting diode, respectively. In addition, as the stacked structure, a stacked structure that can be used for a light emitting diode included in the LED package 170 of fig. 48 may be used.

In addition, the color of the light emitted by the light emitting diode 420 may be cyan, magenta, yellow or white in addition to red, green and blue.

The protective layer 411 may be, for example, an inorganic insulating film and an organic insulating film which can be used for the insulator 105. In addition, the protective layer 411 may use, for example, a material that can be used for the sealing layer 178 of the LED package 170 of fig. 49A.

The substrate 410 is bonded to the stacked body SST using conductors 193a to 193c and conductors 194a to 194c serving as bumps, respectively. Specifically, conductor 112a in laminate SST is bonded to electrode 183a of light emitting diode 420R via conductor 194a, conductor 111a in laminate SST is bonded to electrode 186a of light emitting diode 420R via conductor 193a, conductor 112B in laminate SST is bonded to electrode 183B of light emitting diode 420G via conductor 194B, conductor 111B in laminate SST is bonded to electrode 186B of light emitting diode 420G via conductor 193B, conductor 112c in laminate SST is bonded to electrode 183c of light emitting diode 420B via conductor 194c, and conductor 111c in laminate SST is bonded to electrode 186c of light emitting diode 420B via conductor 193 c.

In addition, materials usable for the conductors 117a or 117b can be used for the conductors 193a to 193c and the conductors 194a to 194 c.

In addition, the display device 1000I may use the color conversion layer 190 for the LED package 170A2 of fig. 49C. Specifically, by providing the color conversion layer 190 between one or more selected from the semiconductor layers 185a to 185c and the substrate 410 on the paths of light emitted from the light emitting diodes 420R, 420G, and 420B, the color of light emitted from the light emitting layer can be converted into other colors by the color conversion layer 190.

Further, the above-described structural examples of the plurality of display devices may be appropriately combined with each other.

< Structural example of light-emitting device >

Next, a structural example of a light emitting device which can be used for the above-described display device will be described.

As shown in fig. 52A, the light-emitting device includes an EL layer 763 between a pair of electrodes (a lower electrode 761 and an upper electrode 762). The EL layer 763 may be formed of a plurality of layers such as a layer 780, a light-emitting layer 771, and a layer 790.

The light-emitting layer 771 contains at least a light-emitting substance (also referred to as a light-emitting material).

When the lower electrode 761 and the upper electrode 762 are an anode and a cathode, respectively, the layer 780 includes one or more of a layer containing a substance having high hole injection property (a hole injection layer), a layer containing a substance having high hole transport property (a hole transport layer), and a layer containing a substance having high electron blocking property (an electron blocking layer). The layer 790 includes one or more of a layer containing a substance having high electron injection property (an electron injection layer), a layer containing a substance having high electron transport property (an electron transport layer), and a layer containing a substance having high hole blocking property (a hole blocking layer). In the case where the lower electrode 761 and the upper electrode 762 are a cathode and an anode, respectively, the structures of the layer 780 and the layer 790 are reversed as described above.

The structure including the layer 780, the light-emitting layer 771, and the layer 790 which are provided between a pair of electrodes can be used as a single light-emitting unit, and the structure of fig. 52A is referred to as a single structure in this specification.

Fig. 52B shows a modification example of the EL layer 763 included in the light-emitting device shown in fig. 52A. Specifically, the light-emitting device shown in fig. 52B includes a layer 781 over the lower electrode 761, a layer 782 over the layer 781, a light-emitting layer 771 over the layer 782, a layer 791 over the light-emitting layer 771, a layer 792 over the layer 791, and an upper electrode 762 over the layer 792.

In the case where the lower electrode 761 and the upper electrode 762 are an anode and a cathode, respectively, the layers 781, 782, 791, and 792 may be a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer, respectively, for example. In the case where the lower electrode 761 and the upper electrode 762 are a cathode and an anode, respectively, the layers 781, 782, 791, and 792 may be an electron injection layer, an electron transport layer, a hole transport layer, and a hole injection layer, respectively. By adopting the above layer structure, carriers can be efficiently injected into the light-emitting layer 771, and thus recombination efficiency of carriers in the light-emitting layer 771 can be improved.

As shown in fig. 52C and 52D, a structure in which a plurality of light-emitting layers (a light-emitting layer 771, a light-emitting layer 772, and a light-emitting layer 773) are provided between the layer 780 and the layer 790 is also a modification of the single structure. Note that although fig. 52C and 52D show examples including three light-emitting layers, the number of light-emitting layers in a light-emitting device having a single structure may be two or four or more. In addition, the light emitting device having a single structure may include a buffer layer between two light emitting layers.

As shown in fig. 52E and 52F, a structure in which a plurality of light emitting units (light emitting units 763a and 763 b) are connected in series with a charge generating layer 785 (also referred to as an intermediate layer) interposed therebetween is referred to as a series structure in this specification. In addition, the series structure may be referred to as a stacked structure. By adopting the series structure, a light-emitting device capable of emitting light with high luminance can be realized. In addition, the series structure can reduce the current for obtaining the same brightness as compared with the single structure, and thus can improve the reliability.

Fig. 52D and 52F illustrate examples in which the display device includes a layer 764 overlapping with the light-emitting device. Fig. 52D shows an example in which the layer 764 overlaps with the light-emitting device shown in fig. 52C, and fig. 52F shows an example in which the layer 764 overlaps with the light-emitting device shown in fig. 52E.

One or both of a color conversion layer and a color filter (coloring layer) can be used as the layer 764.

In fig. 52C and 52D, a light-emitting substance which emits light of the same color, or even the same light-emitting substance may be used for the light-emitting layer 771, the light-emitting layer 772, and the light-emitting layer 773. For example, a light-emitting substance which emits blue light may be used for the light-emitting layer 771, the light-emitting layer 772, and the light-emitting layer 773. Regarding the sub-pixel exhibiting blue light, blue light emitted from the light emitting device may be extracted. Further, with respect to the sub-pixel that exhibits red light and the sub-pixel that exhibits green light, by providing a color conversion layer as the layer 764 shown in fig. 52D, blue light emitted by the light-emitting device can be converted into light having a longer wavelength and extracted as red light or green light.

In addition, light-emitting substances which emit light of different colors may be used for the light-emitting layer 771, the light-emitting layer 772, and the light-emitting layer 773. It is preferable to use a structure that white light emission is obtained when light emitted from each of the light-emitting layer 771, the light-emitting layer 772, and the light-emitting layer 773 is mixed. For example, a light-emitting device having a single structure preferably includes a light-emitting layer containing a light-emitting substance that emits blue light and a light-emitting layer containing a light-emitting substance that emits visible light longer than the wavelength of blue light.

For example, in the case where a light-emitting device having a single structure includes three light-emitting layers, it is preferable to include a light-emitting layer containing a light-emitting substance that emits red (R) light, a light-emitting layer containing a light-emitting substance that emits green (G) light, and a light-emitting layer containing a light-emitting substance that emits blue (B) light. As the lamination order of the light emitting layers, for example, a red (R) light emitting layer, a green (G) light emitting layer, and a blue (B) light emitting layer may be laminated from the anode side, or a red (R) light emitting layer, a blue (B) light emitting layer, and a green (G) light emitting layer may be laminated from the anode side. In this case, a buffer layer may be provided between the red (R) light-emitting layer and the green (G) light-emitting layer or the blue (B) light-emitting layer.

In addition, for example, in the case where a light-emitting device having a single structure includes two light-emitting layers, a structure including a light-emitting layer containing a light-emitting substance that emits blue (B) light and a light-emitting layer containing a light-emitting substance that emits yellow (Y) light is preferably employed. This structure is sometimes referred to as a BY single structure.

As the layer 764 shown in fig. 52D, a color filter may be provided. The white light is transmitted through the color filter, whereby light of a desired color can be obtained.

The light-emitting device that emits white light preferably contains two or more kinds of light-emitting substances. To obtain white light emission, two kinds of light-emitting substances each having a complementary color relationship may be selected. For example, by placing the light-emitting color of the first light-emitting layer and the light-emitting color of the second light-emitting layer in a complementary relationship, a light-emitting device that emits light in white color as a whole can be obtained. In the case where white light emission is obtained by using three or more light-emitting layers as the light-emitting layers, the light-emitting colors of the three or more light-emitting layers may be combined to obtain a structure in which the light-emitting device emits white light as a whole.

In fig. 52E and 52F, light-emitting substances that emit light of the same color may be used for the light-emitting layer 771 and the light-emitting layer 772.

For example, in a light-emitting device included in a sub-pixel which emits light of each color, a light-emitting substance which emits blue light may be used for the light-emitting layer 771 and the light-emitting layer 772. Regarding the sub-pixel exhibiting blue light, blue light emitted from the light emitting device may be extracted. Further, with respect to the sub-pixel that exhibits red light and the sub-pixel that exhibits green light, by providing a color conversion layer as the layer 764 shown in fig. 52F, blue light emitted by the light-emitting device can be converted into light having a longer wavelength and extracted as red light or green light.

In addition, when the light-emitting device having the structure shown in fig. 52E or 52F is used for the sub-pixel which displays each color, a different light-emitting substance may be used depending on the sub-pixel. Specifically, in a light-emitting device included in a sub-pixel which emits red light, a light-emitting substance which emits red light may be used for the light-emitting layer 771 and the light-emitting layer 772. Similarly, in a light-emitting device included in a subpixel which emits green light, a light-emitting substance which emits green light may be used for the light-emitting layer 771 and the light-emitting layer 772. In a light-emitting device included in a subpixel which emits blue light, a light-emitting substance which emits blue light may be used for the light-emitting layer 771 and the light-emitting layer 772. It can be said that the display apparatus having such a structure uses the light emitting device having a series structure and has an SBS structure. This can provide advantages of both the tandem structure and the SBS structure. Thus, a display device with high reliability can be realized by emitting light with high luminance.

In fig. 52E and 52F, light-emitting substances that emit light of different colors may be used for the light-emitting layer 771 and the light-emitting layer 772. When the light emitted from the light-emitting layer 771 and the light emitted from the light-emitting layer 772 are in a complementary color relationship, white light emission can be obtained. As the layer 764 shown in fig. 52F, a color filter may be provided. The white light is transmitted through the color filter, whereby light of a desired color can be obtained.

Note that, although fig. 52E and 52F illustrate an example in which the light emitting unit 763a includes one light emitting layer 771 and the light emitting unit 763b includes one light emitting layer 772, it is not limited thereto. Each of the light emitting units 763a and 763b may include two or more light emitting layers.

Further, although fig. 52E and 52F illustrate a light emitting device including two light emitting units, it is not limited thereto. The light emitting device may also include three or more light emitting units.

Specifically, the structure of the light emitting device shown in fig. 53A and 53C can be given.

Fig. 53A shows a structure including three light emitting units. Note that a structure including two light emitting units and a structure including three light emitting units may also be referred to as a two-stage series structure and a three-stage series structure, respectively.

Further, as shown in fig. 53A, a plurality of light emitting units (light emitting unit 763A, light emitting unit 763b, and light emitting unit 763 c) are connected in series with each other via charge generating layers (charge generating layers 785a-b and charge generating layers 785 b-c). Specifically, in the light-emitting device shown in fig. 53A, a light-emitting unit 763A, charge generation layers 785a-b, a light-emitting unit 763b, charge generation layers 785b-c, and a light-emitting unit 763c are stacked in this order. In addition, the light-emitting unit 763a includes a layer 780a, a light-emitting layer 771, and a layer 790a, the light-emitting unit 763b includes a layer 780b, a light-emitting layer 772, and a layer 790b, and the light-emitting unit 763c includes a layer 780c, a light-emitting layer 773, and a layer 790c.

For the charge generation layers 785a-b and the charge generation layers 785b-c, reference is made to the description of the charge generation layer 785 described above.

In the structure shown in fig. 53A, the light-emitting layer 771, the light-emitting layer 772, and the light-emitting layer 773 preferably contain light-emitting substances that emit light of the same color as each other. Specifically, the following structure may be adopted: a light-emitting layer 771 the light-emitting layer 772 and the light-emitting layer 773 each include red (R) light emission Structure of the substance (so-called R\ R\R tertiary series structure); a light-emitting layer 771 the light-emitting layer 772 and the light-emitting layer 773 each include green (G) light emission Structure of the substance (so-called G\ G\G tertiary series structure); or a light-emitting layer 771 the light-emitting layer 772 and the light-emitting layer 773 each include blue (B) light emission Structure of the substance (so-called B\ b\b tertiary tandem structure). In the structure shown in fig. 53A, the light-emitting layer 771, the light-emitting layer 772, and the light-emitting layer 773 may contain light-emitting substances which emit different colors. The structure shown in fig. 53A may be a structure in which the colors of light emitted from the light-emitting layer 771, the light-emitting layer 772, and the light-emitting layer 773 are mixed to be white (W). In the structure shown in fig. 53A, the color filter layer 764 may be formed similarly to fig. 52D or 52F.

Note that the light-emitting substances each emitting the same color are not limited to the above-described structure. For example, as shown in fig. 53B, a tandem-type light-emitting device in which light-emitting units including a plurality of light-emitting substances are stacked may be used. Fig. 53B shows a structure in which a plurality of light emitting units (light emitting units 763a and 763B) are connected in series with each other through a charge generating layer 785. In addition, the light-emitting unit 763a includes a layer 780a, a light-emitting layer 771b, a light-emitting layer 771c, and a layer 790a, and the light-emitting unit 763b includes a layer 780b, a light-emitting layer 772a, a light-emitting layer 772b, a light-emitting layer 772c, and a layer 790b.

In the structure shown in fig. 53B, white light emission (W) can be realized when the light emitting colors of the light emitting layer 771a, the light emitting layer 771B, and the light emitting layer 771c are mixed. In addition, white light emission (W) can be realized when the light emitting colors of the light emitting layer 772a, the light emitting layer 772b, and the light emitting layer 772c are mixed. That is, the structure shown in fig. 53B is a W/W two-stage series structure. Note that the order of lamination of the light-emitting layer 771a, the light-emitting layer 771b, and the light-emitting layer 771c is not particularly limited. Likewise, the order of stacking the light-emitting layer 772a, the light-emitting layer 772b, and the light-emitting layer 772c is not particularly limited. The practitioner can appropriately select the most appropriate lamination sequence. Although not shown, the structure shown in fig. 53B may be a three-stage or four-or more-stage serial structure.

In addition, in the case of using a light emitting device having a series structure, there can be mentioned: a B/Y two-stage series structure including a light emitting unit emitting yellow (Y) light and a light emitting unit emitting blue (B) light; comprises RG/B two-stage series structure of a light-emitting unit for emitting red (R) light and green (G) light and a light-emitting unit for emitting blue (B) light; the light emitting device comprises a B\Y\B three-stage series structure sequentially comprising a light emitting unit for emitting blue (B) light, a light emitting unit for emitting yellow (Y) light and a light emitting unit for emitting blue (B) light; the light emitting device comprises a light emitting unit for emitting blue (B) light, a light emitting unit for emitting yellow-green (YG) light and a B\YG\B three-stage series structure of the light emitting unit for emitting blue (B) light in sequence; and a B\G\B three-stage series structure comprising in order a light emitting unit emitting blue (B) light, a light emitting unit emitting green (G) light, and a light emitting unit emitting blue (B) light, etc

Further, as shown in fig. 53C, a light-emitting unit including one light-emitting substance and a light-emitting unit including a plurality of light-emitting substances may be combined.

Specifically, in the structure shown in fig. 53C, a plurality of light emitting units (light emitting unit 763a, light emitting unit 763b, and light emitting unit 763C) are connected in series with each other via charge generating layers (charge generating layers 785a-b and charge generating layers 785 b-C). In addition, the light-emitting unit 763a includes a layer 780a, a light-emitting layer 771, and a layer 790a, the light-emitting unit 763b includes a layer 780b, a light-emitting layer 772a, a light-emitting layer 772b, a light-emitting layer 772c, and a layer 790b, and the light-emitting unit 763c includes a layer 780c, a light-emitting layer 773, and a layer 790c.

For example, in the structure shown in fig. 53C, a b\r·g·yg B three-stage series structure or the like may be employed, in which the light emitting unit 763a is a light emitting unit that emits blue (B) light, the light emitting unit 763B is a light emitting unit that emits red (R) light, green (G) light, and yellow-green (YG) light, and the light emitting unit 763C is a light emitting unit that emits blue (B) light.

For example, as the number of stacked layers and the color order of the light emitting units, there may be mentioned a two-stage structure in which B and Y are stacked from the anode side, a two-stage structure in which B and X are stacked, a three-stage structure in which B, Y and B are stacked, a three-stage structure in which B and X are stacked, a three-stage structure in which R and Y are stacked from the anode side, a two-stage structure in which R and G are stacked, a two-stage structure in which G and R are stacked, a three-stage structure in which G, R and G are stacked, a three-stage structure in which R, G and R are stacked, or the like may be adopted as the number of stacked layers and the color order of the light emitting layers in the light emitting unit X. In addition, another layer may be provided between the two light-emitting layers.

Note that in fig. 52C and 52D, as shown in fig. 53B, each of the layers 780 and 790 may have a stacked structure of two or more layers independently.

In fig. 52E and 52F, the light-emitting unit 763a includes a layer 780a, a light-emitting layer 771, and a layer 790a, and the light-emitting unit 763b includes a layer 780b, a light-emitting layer 772, and a layer 790b.

In the case where the lower electrode 761 and the upper electrode 762 are an anode and a cathode, respectively, the layers 780a and 780b each include one or more of a hole injection layer, a hole transport layer, and an electron blocking layer. In addition, each of the layers 790a and 790b includes one or more of an electron injection layer, an electron transport layer, and a hole blocking layer. In the case where the lower electrode 761 and the upper electrode 762 are a cathode and an anode, respectively, the structures of the layer 780a and the layer 790a are inverted from the above, and the structures of the layer 780b and the layer 790b are also inverted from the above.

In the case where the lower electrode 761 and the upper electrode 762 are an anode and a cathode, respectively, for example, the layer 780a includes a hole injection layer and a hole transport layer over the hole injection layer, and may further include an electron blocking layer over the hole transport layer. In addition, the layer 790a includes an electron transport layer, and may further include a hole blocking layer between the light emitting layer 771 and the electron transport layer. In addition, the layer 780b includes a hole transport layer, and may further include an electron blocking layer on the hole transport layer. In addition, the layer 790b includes an electron transport layer and an electron injection layer over the electron transport layer, and may further include a hole blocking layer between the light emitting layer 772 and the electron transport layer. In the case where the lower electrode 761 and the upper electrode 762 are a cathode and an anode, respectively, for example, the layer 780a includes an electron injection layer and an electron transport layer over the electron injection layer, and may further include a hole blocking layer over the electron transport layer. In addition, the layer 790a includes a hole transport layer, and may further include an electron blocking layer between the light emitting layer 771 and the hole transport layer. In addition, the layer 780b includes an electron transport layer, and may further include a hole blocking layer on the electron transport layer. In addition, the layer 790b includes a hole transport layer and a hole injection layer over the hole transport layer, and may further include an electron blocking layer between the light emitting layer 772 and the hole transport layer.

Further, when a light emitting device having a tandem structure is manufactured, two light emitting units are stacked with a charge generation layer 785 interposed therebetween. The charge generation layer 785 has at least a charge generation region. The charge generation layer 785 has a function of injecting electrons into one of the two light emitting cells and injecting holes into the other when a voltage is applied between the pair of electrodes.

Next, materials that can be used for the light emitting device are described.

As the electrode on the side from which light is extracted out of the lower electrode 761 and the upper electrode 762, a conductive film that transmits visible light is used. Further, as the electrode on the side from which light is not extracted, a conductive film that reflects visible light is preferably used. In the case where the display device includes a light-emitting device that emits infrared light, it is preferable to use a conductive film that transmits visible light and infrared light as an electrode on the side where light is extracted and use a conductive film that reflects visible light and infrared light as an electrode on the side where light is not extracted.

The electrode on the side not extracting light may be a conductive film transmitting visible light. In this case, the electrode is preferably arranged between the reflective layer and the EL layer 763. In other words, the light emitted from the EL layer 763 can be reflected by the reflective layer and extracted from the display device.

As a material for forming a pair of electrodes of the light-emitting device, a metal, an alloy, a conductive compound, a mixture thereof, or the like can be suitably used. Specific examples of the material include metals such as aluminum, titanium, chromium, manganese, iron, cobalt, nickel, copper, gallium, zinc, indium, tin, molybdenum, tantalum, tungsten, palladium, gold, platinum, silver, yttrium, and neodymium, and alloys thereof in suitable combination. Examples of the material include indium tin oxide (also referred to as in—sn oxide or ITO), in—si—sn oxide (also referred to as ITSO), indium zinc oxide (in—zn oxide), and in—w—zn oxide. Further, as the material, an alloy containing aluminum (aluminum alloy) is exemplified. Examples of the alloy containing aluminum include an alloy of aluminum (Al), nickel (Ni), and lanthanum (La) (al—ni—la). Further, as the material, an alloy of silver, palladium, and copper (ag—pd—cu, also referred to as APC) can be given. Examples of the material include rare earth metals such as lithium, cesium, calcium, and strontium, europium, ytterbium, and the like, and alloys and graphene thereof, which are not listed above and belong to group 1 or group 2 of the periodic table.

The light emitting device preferably employs an optical microcavity resonator (microcavity) structure. Therefore, one of the pair of electrodes included in the light-emitting device preferably includes an electrode having visible light transmittance and visible light reflectance (semi-transparent-semi-reflective electrode), and the other preferably includes an electrode having reflectivity to visible light (reflective electrode). When the light emitting device has a microcavity structure, light emission obtained from the light emitting layer can be made to resonate between the two electrodes, and light emitted from the light emitting device can be improved.

Note that, for example, a conductive body having transparency and reflectivity to visible light is preferably used as the semi-transmissive-semi-reflective electrode. Further, for example, the semi-transmissive-semi-reflective electrode may have a stacked-layer structure of a conductive layer which can function as a reflective electrode and a conductive layer which can function as an electrode having visible light transmittance (also referred to as a transparent electrode).

The transparent electrode has a light transmittance of 40% or more. For example, an electrode having a transmittance of 40% or more of visible light (light having a wavelength of 400nm or more and less than 750 nm) is preferably used as the transparent electrode of the light-emitting device. The reflectance of the semi-transmissive-semi-reflective electrode to visible light is 10% or more and 95% or less, preferably 30% or more and 80% or less. The reflectance of the reflective electrode to visible light is 40% or more and 100% or less, preferably 70% or more and 100% or less. The resistivity of these electrodes is preferably 1×10 ^-2 Ω cm or less.

The light emitting device includes at least a light emitting layer. The light-emitting device may further include, as a layer other than the light-emitting layer, a layer containing a substance having high hole injection property, a substance having high hole transport property, a hole blocking material, a substance having high electron transport property, an electron blocking material, a substance having high electron injection property, or a bipolar substance (a substance having high electron transport property and hole transport property). For example, the light emitting device may include one or more of a hole injection layer, a hole transport layer, a hole blocking layer, a charge generation layer, an electron blocking layer, an electron transport layer, and an electron injection layer in addition to the light emitting layer.

The light-emitting device may use a low-molecular compound or a high-molecular compound, and may further include an inorganic compound. The layer constituting the light-emitting device may be formed by a method such as a vapor deposition method (including a vacuum vapor deposition method), a transfer method, a printing method, an inkjet method, or a coating method.

The light-emitting layer comprises one or more light-emitting substances. As the light-emitting substance, for example, a substance exhibiting a light-emitting color such as blue, violet, bluish violet, green, yellowish green, yellow, orange, or red is suitably used. Further, as the light-emitting substance, a substance that emits near infrared light may be used.

Examples of the luminescent material include a fluorescent material, a phosphorescent material, a TADF material, and a quantum dot material.

Examples of the fluorescent material include pyrene derivatives, anthracene derivatives, triphenylene derivatives, fluorene derivatives, carbazole derivatives, dibenzothiophene derivatives, dibenzofuran derivatives, dibenzoquinoxaline derivatives, quinoxaline derivatives, pyridine derivatives, pyrimidine derivatives, phenanthrene derivatives, and naphthalene derivatives.

Examples of the phosphorescent material include an organometallic complex (particularly iridium complex) having a 4H-triazole skeleton, a 1H-triazole skeleton, an imidazole skeleton, a pyrimidine skeleton, a pyrazine skeleton or a pyridine skeleton, an organometallic complex (particularly iridium complex) having a phenylpyridine derivative having an electron-withdrawing group as a ligand, a platinum complex and a rare earth metal complex.

The light-emitting layer may contain one or more organic compounds (e.g., a host material and an auxiliary material) in addition to the light-emitting substance (guest material). As the one or more organic compounds, one or both of a substance having high hole-transporting property (hole-transporting material) and a substance having high electron-transporting property (electron-transporting material) can be used. As the hole transporting material, the following substances having high hole transporting properties which can be used for the hole transporting layer can be used. As the electron transporting material, the following materials having high electron transporting properties which can be used for the electron transporting layer can be used. Furthermore, as one or more organic compounds, bipolar materials or TADF materials may also be used.

For example, the light-emitting layer preferably contains a combination of a phosphorescent material, a hole-transporting material that easily forms an exciplex, and an electron-transporting material. By adopting such a structure, luminescence of ExTET (Exciplex-TRIPLET ENERGY TRANSFER: exciplex-triplet energy transfer) utilizing energy transfer from the exciplex to a light-emitting substance (phosphorescent material) can be obtained efficiently. Further, by selecting, as the exciplex, a combination that forms light having a wavelength overlapping with that of the absorption band on the lowest energy side of the light-emitting substance, energy transfer can be made smooth, and light emission can be obtained efficiently. By adopting the above structure, high efficiency, low voltage driving, and long life of the light emitting device can be simultaneously realized.

The hole injection layer is a layer containing a material having high hole injection property, which injects holes from the anode to the hole transport layer. Examples of the material having high hole injection property include an aromatic amine compound and a composite material containing a hole transporting material and an acceptor material (electron acceptor material).

As the hole transporting material, the following substances having high hole transporting properties which can be used for the hole transporting layer can be used.

As the acceptor material, for example, oxides of metals belonging to groups 4 to 8 of the periodic table can be used. Specifically, examples of the oxide of the metal include molybdenum oxide, vanadium oxide, niobium oxide, tantalum oxide, chromium oxide, tungsten oxide, manganese oxide, and rhenium oxide. Molybdenum oxide is particularly preferred because it is also stable in the atmosphere, has low hygroscopicity, and is easy to handle. In addition, an organic acceptor material containing fluorine may be used. In addition, organic acceptor materials such as quinone dimethane derivatives, tetrachloroquinone derivatives, and hexaazatriphenylene derivatives can also be used.

For example, a material containing a hole-transporting material and an oxide of a metal belonging to groups 4 to 8 of the periodic table (typically molybdenum oxide) can be used as the material having high hole-injecting property.

The hole transport layer is a layer that transports holes injected from the anode through the hole injection layer to the light emitting layer. The hole transport layer is a layer containing a hole transporting material. As the hole transporting material, a material having a hole mobility of 1X 10 ^-6cm²/Vs or more is preferably used. Note that as long as the hole transport property is higher than the electron transport property, substances other than the above may be used. As the hole transporting material, a material having high hole transporting property such as a pi-electron rich heteroaromatic compound (for example, carbazole derivative, thiophene derivative, and furan derivative), an aromatic amine (a compound having an aromatic amine skeleton), or the like is preferably used.

The electron blocking layer is disposed in contact with the light emitting layer. The electron blocking layer is a layer having hole transport property and containing a material capable of blocking electrons. The electron blocking material among the above hole transport materials may be used for the electron blocking layer.

The electron blocking layer has hole transport properties and therefore may also be referred to as a hole transport layer. In addition, a layer having electron blocking property among the hole transport layers may also be referred to as an electron blocking layer.

The electron transport layer is a layer that transports electrons injected from the cathode through the electron injection layer to the light emitting layer. The electron transport layer is a layer containing an electron transport material. As the electron-transporting material, a material having an electron mobility of 1X 10 ^-6cm²/Vs or more is preferably used. Note that as long as the electron transport property is higher than the hole transport property, substances other than the above may be used. Examples of the electron-transporting material include materials having high electron-transporting properties such as metal complexes having a quinoline skeleton, metal complexes having a benzoquinoline skeleton, metal complexes having an oxazole skeleton, metal complexes having a thiazole skeleton, oxadiazole derivatives, triazole derivatives, imidazole derivatives, oxazole derivatives, thiazole derivatives, phenanthroline derivatives, quinoline derivatives including quinoline ligands, benzoquinoline derivatives, quinoxaline derivatives, dibenzoquinoxaline derivatives, pyridine derivatives, bipyridine derivatives, pyrimidine derivatives, and nitrogen-containing heteroaromatic compounds.

The hole blocking layer is disposed in contact with the light emitting layer. The hole blocking layer is a layer having electron transport property and containing a material capable of blocking holes. The hole blocking material may be used for the hole blocking layer.

The hole blocking layer has electron transport properties and therefore may also be referred to as an electron transport layer. In addition, a layer having hole blocking property among the electron transport layers may also be referred to as a hole blocking layer.

The electron injection layer is a layer containing a material having high electron injection property, which injects electrons from the cathode to the electron transport layer. As the material having high electron injection properties, alkali metal, alkaline earth metal, or a compound thereof can be used. As the material having high electron injection properties, a composite material containing an electron-transporting material and a donor material (electron-donor material) may be used.

In addition, the difference between the lowest unoccupied molecular orbital (LUMO: lowest Unoccupied Molecular Orbital) level of a material having high electron injection and the work function value of the material used for the cathode is preferably small (specifically, 0.5eV or less).

Examples of the electron injection layer include alkali metals, alkaline earth metals, and their compounds such as lithium, cesium, ytterbium, lithium fluoride (LiF), cesium fluoride (CsF), calcium fluoride (CaF _x, x is an arbitrary number), lithium 8- (hydroxyquinoline) (abbreviated as Liq), lithium 2- (2-pyridyl) phenol (abbreviated as LiPP), lithium 2- (2-pyridyl) -3-hydroxypyridine (pyridinolato) (abbreviated as LiPPy), lithium 4-phenyl-2- (2-pyridyl) phenol (abbreviated as LiPPP), lithium oxide (LiO _x), and cesium carbonate. The electron injection layer may have a stacked structure of two or more layers. Examples of the stacked structure include a structure in which lithium fluoride is used as the first layer and ytterbium is provided as the second layer.

The electron injection layer may also comprise an electron transport material. For example, compounds having a non-common electron pair and having an electron-deficient heteroaromatic ring may be used for the electron-transporting material. Specifically, a compound having one or more selected from a pyridine ring, a diazine ring (for example, a pyrimidine ring, a pyrazine ring, and a pyridazine ring), and a triazine ring may be used.

The LUMO level of the organic compound having an unshared electron pair is preferably-3.6 eV or more and-2.3 eV or less. In general, the highest occupied molecular orbital (HOMO: highest Occupied Molecular Orbital) energy level and LUMO energy level of an organic compound can be estimated using CV (cyclic voltammetry), photoelectron spectroscopy, absorption spectroscopy, or reverse-light electron spectroscopy.

For example, 4, 7-diphenyl-1, 10-phenanthroline (abbreviated as BPhen), 2, 9-bis (naphthalen-2-yl) -4, 7-diphenyl-1, 10-phenanthroline (abbreviated as NBPhen), and a diquinoxalino [2,3-a:2',3' -c ] phenazine (abbreviated as HATNA), 2,4, 6-tris [3' - (pyridin-3-yl) biphenyl-3-yl ] -1,3, 5-triazine (abbreviated as TmPPPyTz) and the like are used for organic compounds having an unshared electron pair. In addition, NBPhen has a high glass transition temperature (Tg) as compared with BPhen, and thus has high heat resistance.

As described above, the charge generation layer has at least the charge generation region. The charge generation region preferably includes an acceptor material, and for example, preferably includes a hole transport material and an acceptor material which can be applied to the hole injection layer.

The charge generation layer preferably includes a layer containing a substance having high electron injection property. This layer may also be referred to as an electron injection buffer layer. The electron injection buffer layer is preferably disposed between the charge generation region and the electron transport layer. By providing the electron injection buffer layer, the injection barrier between the charge generation region and the electron transport layer can be relaxed, so electrons generated in the charge generation region are easily injected into the electron transport layer.

The electron injection buffer layer preferably contains an alkali metal or an alkaline earth metal, for example, a compound that may contain an alkali metal or a compound of an alkaline earth metal. Specifically, the electron injection buffer layer preferably contains an inorganic compound containing an alkali metal and oxygen or an inorganic compound containing an alkaline earth metal and oxygen, and more preferably contains an inorganic compound containing lithium and oxygen (for example, lithium oxide (Li ₂ O)). In addition, a material applicable to the above-described electron injection layer can be suitably used as the electron injection buffer layer.

The charge generation layer preferably includes a layer containing a material having high electron-transport property. This layer may also be referred to as an electronic relay layer. The electron relay layer is preferably disposed between the charge generation region and the electron injection buffer layer. When the charge generation layer does not include the electron injection buffer layer, the electron relay layer is preferably disposed between the charge generation region and the electron transport layer. The electron relay layer has a function of preventing interaction of the charge generation region and the electron injection buffer layer (or the electron transport layer) and smoothly transferring electrons.

As the electron mediator, a phthalocyanine material such as copper (II) phthalocyanine (abbreviated as CuPc) or a metal complex having a metal-oxygen bond and an aromatic ligand is preferably used.

Note that the above-described charge generation region, electron injection buffer layer, and electron relay layer may not be clearly distinguished depending on the cross-sectional shape, characteristics, and the like.

In addition, the charge generation layer may also include a donor material instead of an acceptor material. For example, the charge generation layer may include a layer containing an electron transport material and a donor material which can be applied to the electron injection layer.

When the light emitting units are stacked, the charge generation layer is provided between the two light emitting units, whereby the rise of the driving voltage can be suppressed.

< Structural example of Pixel Circuit >

Here, a structural example of a pixel circuit which can be included in the pixel layer PXAL is described.

Fig. 54A and 54B illustrate a structural example of a pixel circuit which can be included in the pixel layer PXAL and the light-emitting device 130 connected to the pixel circuit. In addition, fig. 54A is a diagram showing connection of each circuit element included in the pixel circuit 400 included in the pixel layer PXAL, and fig. 54B is a diagram schematically showing a relationship between the circuit layer SICL including the drive circuit 30, the layer OSL having a plurality of transistors included in the pixel circuit, and the layer EML including the light-emitting device 130. In addition, the pixel layer PXAL of the display device 1000 shown in fig. 54B includes, for example, a layer OSL and a layer EML. The transistors 500A, 500B, and 500C included in the layer OSL shown in fig. 54B correspond to, for example, the transistor 500 in fig. 36 and the transistor 200 in fig. 43. In addition, the light emitting device 130 included in the layer EML shown in fig. 54B corresponds to the light emitting device 130R, the light emitting device 130G, or the light emitting device 130B in fig. 36.

For example, the pixel circuit 400 shown in fig. 54A and 54B includes a transistor 500A, a transistor 500B, a transistor 500C, and a capacitor 600. The transistors 500A, 500B, and 500C may be, for example, transistors that can be used for the transistor 500 or the transistor 200. In other words, the transistors 500A, 500B, and 500C may be OS transistors. Alternatively, the transistors 500A, 500B, and 500C may be Si transistors. In particular, when the transistors 500A, 500B, and 500C are OS transistors, the transistors 500A, 500B, and 500C each preferably include a back gate, and in this case, the back gates and the gates may be supplied with the same signal or different signals. Note that fig. 54A and 54B show that the transistors 500A, 500B, and 500C include back gates, but the transistors 500A, 500B, and 500C may not include back gates.

The transistor 500B includes a gate electrode electrically connected to the transistor 500A, a first electrode electrically connected to the light emitting device 130, and a second electrode electrically connected to the wiring ANO. The wiring ANO is a wiring for supplying a potential of the current to the light emitting device 130.

The transistor 500A includes a first electrode electrically connected to the gate of the transistor 500B, a second electrode electrically connected to the wiring SL serving as a source line, and a gate having a function of controlling switching of an on state and an off state according to the potential of the wiring G1 serving as a gate line.

The transistor 500C includes a first electrode electrically connected to the wiring V0, a second electrode electrically connected to the light emitting device 130, and a gate electrode having a function of controlling switching of an on state and an off state according to a potential of the wiring G2 serving as a gate line. The wiring V0 is a wiring for supplying a reference potential and a wiring for outputting a current flowing through the pixel circuit 400 to the driving circuit 30.

The capacitor 600 includes a conductive film electrically connected to the gate electrode of the transistor 500B and a conductive film electrically connected to the second electrode of the transistor 500C.

The light emitting device 130 includes a first electrode electrically connected to the first electrode of the transistor 500B and a second electrode electrically connected to the wiring VCOM. The wiring VCOM is a wiring to which a potential for supplying a current to the light emitting device 130 is applied.

Thereby, the intensity of light emitted by the light emitting device 130 can be controlled according to an image signal supplied to the gate electrode of the transistor 500B. In addition, unevenness in voltage between the gate and the source of the transistor 500B can be suppressed by the reference potential of the wiring V0 applied through the transistor 500C.

In addition, a current value that can be used when setting a pixel parameter can be output from the wiring V0. More specifically, the wiring V0 may be used as a monitoring line that outputs a current flowing through the transistor 500B or a current flowing through the light emitting device 130 to the outside. The current output to the wiring V0 is converted into a voltage by a source follower circuit, for example, and is output to the outside. Further, for example, the AI accelerator included in the peripheral circuit PRPH described in the above embodiment is converted into a digital signal by an a/D converter or the like and output to the peripheral circuit.

In addition, in the configuration shown as an example in fig. 54B, wiring for electrically connecting the pixel circuit 400 and the driving circuit 30 can be shortened, so that wiring resistance of the wiring can be reduced. Therefore, data can be written at a high speed, and thus the display device 1000 can be driven at a high speed. Thus, even if the number of pixel circuits 400 included in the display device 1000 is large, a sufficient frame period can be ensured, and thus the pixel density of the display device 1000 can be increased. In addition, by increasing the pixel density of the display device 1000, the sharpness of an image displayed by the display device 1000 can be improved. For example, the pixel density of the display device 1000 may be 500ppi or more, preferably 1000ppi or more, more preferably 3000ppi or more, still more preferably 5000ppi or more, and still more preferably 6000ppi or more. Accordingly, the display device 1000 may be, for example, a display device for AR or VR, and may be suitably used for an electronic apparatus having a relatively short distance between a display unit such as a Head Mount Display (HMD) and a user.

< Layout of pixels >

Here, a pixel layout is described. The arrangement of the sub-pixels is not particularly limited, and various methods may be employed. Examples of the arrangement of the subpixels include a stripe arrangement, an S-stripe arrangement, a matrix arrangement, a Delta arrangement, a bayer arrangement (Bayer arrangement), and a Pentile arrangement.

Examples of the top surface shape of the sub-pixel include a polygonal shape such as a triangle, a quadrangle (including a rectangle and a square), a pentagon, and the like, and a shape in which corners of the polygonal shape are rounded, an ellipse, and a circle. Here, the top surface shape of the sub-pixel corresponds to the top surface shape of the light emitting region of the light emitting device.

The pixels 80 shown in fig. 55A are arranged in stripes. The pixel 80 shown in fig. 55A is composed of three sub-pixels of sub-pixel 80a, sub-pixel 80b, and sub-pixel 80 c. For example, as shown in fig. 56A, the sub-pixel 80a may be the red sub-pixel R, the sub-pixel 80B may be the green sub-pixel G, and the sub-pixel 80c may be the blue sub-pixel B.

The pixel 80 shown in fig. 55B adopts an S stripe arrangement. The pixel 80 shown in fig. 55B is composed of three sub-pixels of sub-pixel 80a, sub-pixel 80B, and sub-pixel 80 c. For example, as shown in fig. 56B, the sub-pixel 80a may be the blue sub-pixel B, the sub-pixel 80c may be the red sub-pixel R, and the sub-pixel 80B may be the green sub-pixel G.

Fig. 55C shows an example in which subpixels of respective colors are arranged in a zigzag shape. Specifically, the upper sides of the two sub-pixels (for example, sub-pixel 80a and sub-pixel 80b or sub-pixel 80b and sub-pixel 80 c) arranged in the column direction are shifted in position in a plan view. For example, as shown in fig. 56C, the sub-pixel 80a may be the red sub-pixel R, the sub-pixel 80B may be the green sub-pixel G, and the sub-pixel 80C may be the blue sub-pixel B.

The pixel 80 shown in fig. 55D includes a pixel 80a having a top surface shape of an approximately trapezoid with rounded corners, a sub-pixel 80b having a top surface shape of an approximately triangle with rounded corners, and a sub-pixel 80c having a top surface shape of an approximately quadrangle or an approximately hexagon with rounded corners. In addition, the light emitting area of the sub-pixel 80a is larger than that of the sub-pixel 80b. Thus, the shape and size of each sub-pixel can be independently determined. For example, the size of a sub-pixel including a light emitting device with high reliability may be smaller, for example. For example, as shown in fig. 56D, the sub-pixel 80a may be the green sub-pixel G, the sub-pixel 80B may be the red sub-pixel R, and the sub-pixel 80c may be the blue sub-pixel B.

The pixels 70A and 70B shown in fig. 55E are arranged in Pentile. Fig. 55E shows an example in which pixels 70A including a sub-pixel 80A and a sub-pixel 80B and pixels 70B including a sub-pixel 80B and a sub-pixel 80c are alternately arranged. For example, as shown in fig. 56E, the sub-pixel 80a may be the red sub-pixel R, the sub-pixel 80B may be the green sub-pixel G, and the sub-pixel 80c may be the blue sub-pixel B.

The pixels 70A and 70B shown in fig. 55F and 55G are arranged in Delta. The pixel 70A includes two sub-pixels (sub-pixel 80A and sub-pixel 80 b) in the upper row (first row) and one sub-pixel (sub-pixel 80 c) in the lower row (second row). The pixel 70B includes one subpixel (subpixel 80 c) in the upper row (first row) and two subpixels (subpixel 80a and subpixel 80B) in the lower row (second row). For example, as shown in fig. 56F, the sub-pixel 80a may be the red sub-pixel R, the sub-pixel 80B may be the green sub-pixel G, and the sub-pixel 80c may be the blue sub-pixel B.

Fig. 55F shows an example in which each sub-pixel has an approximately quadrangular top surface shape with rounded corners, and fig. 55G shows an example in which each sub-pixel has a rounded top surface shape.

In photolithography, the finer the processed pattern, the less the influence of diffraction of light can be ignored, so that fidelity is lowered when the pattern of the photomask is transferred by exposure, and it is difficult to process the resist mask into a desired shape. Therefore, even if the pattern of the photomask is rectangular, a pattern with rounded corners is formed in many cases. Thus, the top surface of the subpixel may have a polygonal corner with a circular shape, an elliptical shape, or a circular shape.

In the method for manufacturing a display device according to one embodiment of the present invention, the EL layer is processed into an island shape using a resist mask. The resist film formed on the EL layer needs to be hardened at a temperature lower than the heat-resistant temperature of the EL layer. Therefore, the curing of the resist film may be insufficient depending on the heat-resistant temperature of the material of the EL layer and the curing temperature of the resist material. The resist film which is insufficiently cured may have a shape different from a desired shape when processed. As a result, the corners of the EL layer whose top surface is polygonal may have a circular shape, an elliptical shape, or a circular shape. For example, when forming a resist mask having a square top surface shape, a resist mask having a circular top surface shape may be formed, and the top surface shape of the EL layer may be circular.

In order to form the top surface of the EL layer into a desired shape, a technique of correcting the mask pattern in advance (OPC (Optical Proximity Correction: optical proximity correction) technique) may be used so that the design pattern coincides with the transfer pattern. Specifically, in the OPC technique, a correction pattern is added to a pattern corner or the like on a mask pattern.

The pixels 80 shown in fig. 57A to 57C adopt a stripe arrangement.

Fig. 57A shows an example in which each sub-pixel has a rectangular top surface shape, fig. 57B shows an example in which each sub-pixel has a top surface shape connecting two semicircles and a rectangular shape, and fig. 57C shows an example in which each sub-pixel has an elliptical top surface shape.

The pixels 80 shown in fig. 57D to 57F are arranged in a matrix.

Fig. 57D shows an example in which each sub-pixel has a square top surface shape, fig. 57E shows an example in which each sub-pixel has an approximately square top surface shape with rounded corners, and fig. 57F shows an example in which each sub-pixel has a rounded top surface shape.

The pixel 80 shown in fig. 57A to 57F is constituted by four sub-pixels of a sub-pixel 80a, a sub-pixel 80b, a sub-pixel 80c, and a sub-pixel 80 d. The sub-pixels 80a, 80b, 80c, and 80d emit light of different colors, respectively. For example, the sub-pixels 80a, 80b, 80c, and 80d may be red, green, blue, and white sub-pixels, respectively. For example, as shown in fig. 58A and 58B, the sub-pixels 80a, 80B, 80c, and 80d may be red, green, blue, and white sub-pixels, respectively. Alternatively, the sub-pixels 80a, 80b, 80c, and 80d may be red, green, blue, and infrared light emitting sub-pixels, respectively.

The sub-pixel 80d includes a light emitting device. The light emitting device includes, for example, a pixel electrode, an EL layer, and a common electrode. The pixel electrodes may be made of the same material as the conductors 112a to 112c or the conductors 126a to 126 c. The EL layer may be formed using the same material as the first layer 113a, the second layer 113b, or the third layer 113 c.

Fig. 57G shows an example in which one pixel 80 is configured in two rows and three columns. The upper row (first row) of pixels 80 includes three sub-pixels (sub-pixel 80a, sub-pixel 80b, and sub-pixel 80 c) and the lower row (second row) includes three sub-pixels 80d. In other words, the pixel 80 includes the sub-pixel 80a and the sub-pixel 80d in the left column (first column), the sub-pixel 80b and the sub-pixel 80d in the center column (second column), and the sub-pixel 80c and the sub-pixel 80d in the right column (third column). As shown in fig. 57G, by matching the arrangement of the sub-pixels in the upper row and the lower row, dust and the like generated in the manufacturing process can be efficiently removed. Thus, a display device with high display quality can be provided.

Fig. 57H shows an example in which one pixel 80 is configured in two rows and three columns. The pixel 80 includes three sub-pixels (sub-pixel 80a, sub-pixel 80b, and sub-pixel 80 c) in the upper row (first row) and one sub-pixel (sub-pixel 80 d) in the lower row (second row). In other words, the pixel 80 includes the sub-pixel 80a in the left column (first column), the sub-pixel 80b in the center column (second column), and the sub-pixel 80c in the right column (third column), and the pixel 80d is included across the above three columns.

As shown in fig. 58C and 58D, for example, in the pixel 80 shown in fig. 57G and 57H, the sub-pixel 80a may be the red sub-pixel R, the sub-pixel 80B may be the green sub-pixel G, the sub-pixel 80C may be the blue sub-pixel B, and the sub-pixel 80D may be the white sub-pixel W.

Next, an example of a pixel layout which can be used for the display device 1000H in fig. 48 and the display device 1000G in fig. 47 is described. That is, the pixel layouts of the display devices 1000H and 1000G may be regarded as the LED chips 150a to 150c of the display device 1000G of fig. 47 or the LED chips 180R, LED and 180B of the display device 1000H of fig. 48 in a plan view.

The pixel 80 shown in fig. 59A is an example in which each sub-pixel has a rectangular top surface shape, and each sub-pixel is arranged with its long sides adjacent. The sub-pixels may be arranged in contact with each other or may be arranged in non-contact with each other.

The pixel 80 shown in fig. 59A is composed of three sub-pixels, that is, a sub-pixel 80a, a sub-pixel 80b, and a sub-pixel 80 c. As one example, the sub-pixels 80a, 80b, and 80c emit light of different colors from each other. For example, the different colors here may be red (R), green (G), and blue (B). Accordingly, as shown in fig. 59B, the sub-pixels 80a, 80B, and 80c may be red (R), green (G), and blue (B) sub-pixels, respectively.

In fig. 59B, the colors of light emitted by each of the sub-pixels 80a, 80B, and 80C may be cyan (C), magenta (M), yellow (Y), and white (W) in addition to red (R), green (G), and blue (B).

The number of sub-pixels of the pixel 80 shown in fig. 59A is three, but the number of sub-pixels of the pixel 80 shown in fig. 59A may be one, two, or four or more. For example, as shown in fig. 59C, the pixel 80 is composed of four sub-pixels of sub-pixel 80a, sub-pixel 80b, sub-pixel 80C, and sub-pixel 80 d. As with the pixel 80 of fig. 59A, the pixel 80 of fig. 59C may have a structure in which the sub-pixel 80a, the sub-pixel 80b, the sub-pixel 80C, and the sub-pixel 80d emit light of different colors, respectively. For example, the different colors here may be red (R), green (G), blue (B), and white (W). Accordingly, as shown in fig. 59D, the sub-pixels 80a, 80B, 80c, and 80D may be red (R), green (G), blue (B), and white (W) sub-pixels, respectively.

In fig. 59D, the colors of light emitted by each of the sub-pixels 80a, 80B, 80C, and 80D may be cyan (C), magenta (M), and yellow (Y) in addition to red (R), green (G), blue (B), and white (W).

Note that although the pixel 80 in fig. 59A and 59C is shown as an example in which the long sides of the sub-pixels are adjacent to each other, the pixel 80 may be arranged in which the short sides of the sub-pixels are adjacent to each other.

Fig. 59E shows an example in which each sub-pixel has a square top surface shape and an electrode is formed.

The pixel 80 shown in fig. 59E is composed of three sub-pixels, that is, a sub-pixel 80a, a sub-pixel 80b, and a sub-pixel 80c, and a conductor 81 serving as an electrode.

As one example, the sub-pixels 80a, 80b, and 80c emit light of different colors from each other. For example, the different colors here may be red (R), green (G), and blue (B). Accordingly, as shown in fig. 59F, the sub-pixels 80a, 80B, and 80c may be red (R), green (G), and blue (B) sub-pixels, respectively.

In fig. 59F, the colors of light emitted by each of the sub-pixels 80a, 80B, and 80C may be cyan (C), magenta (M), yellow (Y), and white (W) in addition to red (R), green (G), and blue (B).

The conductor 81 is used as a common electrode of the light emitting diode included in the sub-pixel 80a, the sub-pixel 80b, and the sub-pixel 80c, for example. In particular, the common electrode is preferably used as a cathode electrode of the light emitting diode included in each of the sub-pixel 80a, the sub-pixel 80b, and the sub-pixel 80 c.

The conductor 81 corresponds to, for example, the electrode 172 or the electrode 173 in the LED package 170 of fig. 49A. Accordingly, as a material usable for the electric conductor 81, for example, a material usable for the electrode 172 or the electrode 173 can be used.

As shown in fig. 59G, the conductor 81 may be provided so that the sub-pixel 80a, the sub-pixel 80b, and the sub-pixel 80c are all located above the conductor 81. That is, the sub-pixel 80a, the sub-pixel 80b, and the sub-pixel 80c are provided on the conductor 81. The conductor 81 of the pixel 80 of fig. 59G corresponds to the electrode 172 in the LED package 170A1 of fig. 49B.

Although the pixel 80 in fig. 59G does not show the conductor corresponding to the electrode 173 in the LED package 170A1 in fig. 49B, the pixel 80 in fig. 59G may include the conductor corresponding to the electrode 173.

Although the number of electrodes of the pixel 80 shown in fig. 59E is one, the number of electrodes of the pixel 80 shown in fig. 59E may be two or more. For example, the number of electrodes in the pixel 80 may be determined based on the number of sub-pixels. As an example, in the pixel 80 of fig. 59E, in the case where an anode and a cathode are provided in each of three sub-pixels, the number of electrodes provided in the pixel 80 may be six. Further, as an example, when an anode electrode and a common electrode serving as a cathode electrode are provided in each of three sub-pixels in the pixel 80 of fig. 59E, the number of electrodes provided in the pixel 80 may be four.

In the pixel 80 of fig. 59E, the conductor 81 has a square top surface shape, but the top surface shape of the conductor 81 may have various shapes such as an approximate trapezoid shape with rounded corners, an approximate square shape with rounded corners, an approximate hexagon shape with rounded corners, a shape connecting a semicircle and a rectangle, a circle or an ellipse.

In addition, one of the plurality of sub-pixels included in the pixel 80 shown in each of fig. 55A to 55G, 57A to 57H, 59A and 59C may be replaced with the conductor 81.

Note that the insulator, the conductor, and the semiconductor disclosed in this specification or the like can be formed by a PVD (Physical Vapor Deposition; physical vapor deposition) method or a CVD method. Examples of the PVD method include sputtering, resistance heating vapor deposition, electron beam vapor deposition, MBE (Molecular Beam Epitaxy: molecular beam epitaxy) and PLD. Further, the CVD method includes a plasma CVD method and a thermal CVD method. In particular, examples of the thermal CVD method include a metal organic chemical vapor deposition (MOCVD: metal Organic Chemical Vapor Deposition) method and an ALD method.

Since the thermal CVD method is a deposition method using no plasma, there is an advantage in that defects caused by plasma damage are not generated.

Deposition by the thermal CVD method may be performed as follows: the source gas and the oxidizing agent are supplied simultaneously into the processing chamber, and the pressure in the processing chamber is set to atmospheric pressure or reduced pressure, so that the source gas and the oxidizing agent react near or on the substrate to deposit on the substrate.

In addition, deposition by the ALD method may be performed as follows: the pressure in the process chamber is set to atmospheric pressure or reduced pressure, the source gases for reaction are sequentially introduced into the process chamber, and the gases are repeatedly introduced in this order. For example, two or more source gases are sequentially supplied into the process chamber by switching respective on/off valves (also referred to as high-speed valves) so as not to allow a plurality of source gas mixing modes to introduce an inert gas (e.g., argon or nitrogen) or the like at the same time as or after the first source gas is introduced, and then a second source gas is introduced. Note that when the inert gas is introduced simultaneously, the inert gas is used as a carrier gas, and furthermore, the inert gas may be introduced simultaneously with the introduction of the second source gas. Alternatively, the first source gas may be evacuated by vacuum pumping without introducing the inert gas, and then the second source gas may be introduced. A first source gas is adsorbed onto the substrate surface to deposit a first thinner layer, and then a second source gas is introduced to react with the first thinner layer, whereby the second thinner layer is laminated on the first thinner layer to form a thin film. By repeatedly introducing the gas in this order a plurality of times until a desired thickness is obtained, a thin film having good step coverage can be formed. Since the thickness of the thin film can be adjusted according to the number of times of repeatedly introducing the gases in sequence, the ALD method can accurately adjust the thickness to be suitable for the case of manufacturing the micro FET.

Various films such as the metal film, the semiconductor film, and the inorganic insulating film disclosed In the above-described embodiments can be formed by a thermal CVD method such as an MOCVD method or an ALD method, and for example, when depositing an in—ga—zn—o film, trimethylindium (In (CH ₃)₃), trimethylgallium (Ga (CH ₃)₃), and dimethylzinc (Zn (CH ₃)₂)) may be used, and triethylgallium (Ga (C ₂H₅)₃) may be used instead of trimethylgallium, and diethylzinc (Zn (C ₂H₅)₂)) may be used instead of dimethylzinc.

For example, in forming a hafnium oxide film using a deposition apparatus using an ALD method, the following two gases are used: a source gas obtained by vaporizing a liquid containing a solvent and a hafnium precursor compound (for example, hafnium alkoxide, hafnium tetramethyl amide (hafnium amide such as TDMAH, hf [ N (CH ₃)₂]₄)), and ozone (O ₃) used as an oxidizing agent), and further, as another material, there may be mentioned hafnium tetra (ethylmethylamide).

For example, in forming an aluminum oxide film using a deposition apparatus using an ALD method, the following two gases are used: a source gas obtained by vaporizing a liquid containing a solvent and an aluminum precursor compound (for example, trimethylaluminum (TMA, al (CH ₃)₃), etc.), and H ₂ o used as an oxidizing agent, tris (dimethylamide) aluminum, triisobutylaluminum, and aluminum tris (2, 6-tetramethyl-3, 5-heptanedionate) are also examples of other materials.

For example, in the case of forming a silicon oxide film using a deposition apparatus using an ALD method, hexachlorodisilane is adsorbed on a surface to be deposited, and radicals of an oxidizing gas (e.g., O ₂ or nitrous oxide) are supplied to react with the adsorbate.

For example, when a tungsten film is deposited using a deposition apparatus using an ALD method, an initial tungsten film is formed by sequentially and repeatedly introducing WF ₆ gas and B ₂H₆ gas, and then a tungsten film is formed by sequentially and repeatedly introducing WF ₆ gas and H ₂ gas. Note that SiH ₄ gas may be used instead of B ₂H₆ gas.

For example, when an In-Ga-Zn-O film is deposited as an oxide semiconductor film using a deposition apparatus using an ALD method, a precursor (generally, for example, sometimes referred to as a precursor or a metal precursor) and an oxidizing agent (generally, for example, sometimes referred to as a reactant, or a non-metal precursor) are sequentially and repeatedly introduced to form the film. Specifically, for example, in (CH ₃)₃ gas and O ₃ gas as an oxidizing agent) as a precursor is introduced to form an in—o layer, then Ga (CH ₃)₃ gas and O ₃ gas as an oxidizing agent) as a precursor is introduced to form a GaO layer, and then Zn (CH ₃)₂ gas and O ₃ gas as an oxidizing agent) as a precursor is introduced to form a ZnO layer. Note that the order of these layers is not limited to the above example. In addition, these gases may also be used to form mixed oxide layers such as In-Ga-O layers, in-Zn-O layers, ga-Zn-O layers, and the like. Note that, although H ₂ O gas obtained by bubbling with an inert gas (e.g., ar) may be used instead of O ₃ gas, O ₃ gas containing no H is preferably used. In (C ₂H₅)₃ gas) may be used instead of In (CH ₃)₃ gas, and Ga (C ₂H₅)₃ gas) may be used instead of Ga (CH ₃)₃ gas). In addition, zn (C ₂H₅)₂ gas) may be used instead of Zn (CH ₃)₂ gas).

In addition, the screen ratio (aspect ratio) of the display portion included in the electronic device according to one embodiment of the present invention is not particularly limited. For example, the display portion may correspond to 1:1 (square), 4: 3. 16: 9. 16: 10. 21:9 or 32:9, etc.

The shape of the display portion included in the electronic device according to one embodiment of the present invention is not particularly limited. For example, the display portion may correspond to various shapes such as a rectangular shape, a polygonal shape (e.g., an octagonal shape), a circular shape, or an elliptical shape.

Embodiment 5

In this embodiment mode, a transistor which can be used for a semiconductor device according to one embodiment mode of the present invention will be described, and specifically, the transistor 500 described in embodiment mode 4 will be described.

< Structural example of transistor >

Fig. 60A, 60B, and 60C are top and cross-sectional views of a transistor 500 that can be used in a semiconductor device according to one embodiment of the invention. The transistor 500 can be used for a semiconductor device according to one embodiment of the present invention.

Fig. 60A is a top view of transistor 500. Fig. 60B and 60C are cross-sectional views of the transistor 500. Here, fig. 60B is a sectional view of a portion along the chain line A1-A2 in fig. 60A, which corresponds to a sectional view in the channel length direction of the transistor 500. Fig. 60C is a sectional view of a portion along the dash-dot line A3-A4 in fig. 60A, which corresponds to a sectional view in the channel width direction of the transistor 500. Note that, in the plan view of fig. 60A, some constituent elements are omitted for clarity.

As shown in fig. 60A to 60C, the transistor 500 includes a metal oxide 531a, a metal oxide 531b, a conductor 542a, a conductor 542b, an insulator 580, a conductor 560, and an insulator 550.

The metal oxide 531a is disposed on a substrate (not shown), for example. The metal oxide 531b is disposed on the metal oxide 531 a. The conductors 542a and 542b are disposed on the metal oxide 531b so as to be separated from each other. Further, an insulator 580 is disposed on the conductor 542a and the conductor 542 b. In particular, the insulator 580 is formed with an opening in a region between the conductor 542a and the conductor 542 b. Further, the conductor 560 is disposed in the opening. The insulator 550 is disposed between the metal oxide 531b, the conductor 542a, the conductor 542b, and the insulator 580 and the conductor 560. Here, as shown in fig. 60B and 60C, the top surface of the conductor 560 is preferably substantially aligned with the top surfaces of the insulators 550 and 580. Hereinafter, the metal oxide 531a and the metal oxide 531b may be collectively referred to as the metal oxide 531. The conductors 542a and 542b may be collectively referred to as conductors 542.

In the transistor 500 illustrated in fig. 60A to 60C, the side surfaces of the conductors 542a and 542b on the side of the conductor 560 have a substantially vertical shape. The transistor 500 shown in fig. 60A to 60C is not limited to this, and the angle formed by the side surfaces and the bottom surface of the conductor 542a and the conductor 542b may be 10 ° or more and 80 ° or less, and preferably 30 ° or more and 60 ° or less. The opposite side surfaces of the conductor 542a and the conductor 542b may have a plurality of surfaces.

Note that in the transistor 500, two layers of the metal oxide 531a and the metal oxide 531b are stacked in a region where a channel is formed (hereinafter also referred to as a channel formation region) and in the vicinity thereof, but the present invention is not limited thereto. For example, the metal oxide 531b may have a single-layer structure or a stacked structure of three or more layers. The metal oxide 531a and the metal oxide 531b may each have a stacked structure of two or more layers.

Here, the conductor 560 is used as a gate electrode of the transistor, and the conductors 542a and 542b are used as source electrodes or drain electrodes. As described above, the conductor 560 is embedded in the opening of the insulator 580 and is sandwiched in the region between the conductor 542a and the conductor 542 b. Here, the arrangement of the conductors 560, 542a, and 542b is selected to be self-aligned with respect to the opening of the insulator 580. In other words, in the transistor 500, a gate electrode can be arranged in a self-aligned manner between a source electrode and a drain electrode. Thus, since the conductor 560 can be formed without providing a margin for alignment, the occupied area of the transistor 500 can be reduced. Thus, the display device can be made high definition. In addition, a display device with a narrow frame can be realized.

As shown in fig. 60B, the conductor 560 preferably includes a conductor 560a provided inside the insulator 550 and a conductor 560B embedded in the inside of the conductor 560 a. Note that in fig. 60B and 60C, the conductor 560 has a two-layered structure, but the present invention is not limited thereto. For example, the conductor 560 may have a single-layer structure or a stacked structure of three or more layers.

Transistor 500 preferably includes insulator 514 disposed on a substrate (not shown), insulator 516 disposed on insulator 514, conductor 505 disposed so as to be embedded in insulator 516, insulator 522 disposed on insulator 516 and conductor 505, and insulator 524 disposed on insulator 522. The metal oxide 531a is preferably disposed on the insulator 524.

As shown in fig. 60B and 60C, it is preferable that an insulator 554 is disposed between the insulator 522, the insulator 524, the metal oxide 531a, the metal oxide 531B, the conductor 542a, the conductor 542B, and the insulator 550 and the insulator 580. Here, as shown in fig. 60B and 60C, the insulator 554 preferably contacts the side surface of the insulator 550, the top surface and side surface of the conductor 542a, the top surface and side surface of the conductor 542B, the metal oxide 531a, the metal oxide 531B, the side surface of the insulator 524, and the top surface of the insulator 522.

An insulator 574 and an insulator 581 serving as interlayer films are preferably provided over the transistor 500. Here, insulator 574 is preferably in contact with the top surfaces of conductor 560, insulator 550, and insulator 580.

Insulator 522, insulator 554, and insulator 574 preferably have a function of suppressing diffusion of hydrogen (for example, one or both of a hydrogen atom and a hydrogen molecule). For example, insulator 522, insulator 554, and insulator 574 preferably have lower hydrogen permeability than insulator 524, insulator 550, and insulator 580. Further, the insulator 522 and the insulator 554 preferably have a function of suppressing diffusion of oxygen (for example, one or both of an oxygen atom and an oxygen molecule). For example, insulator 522 and insulator 554 preferably have lower oxygen permeability than insulator 524, insulator 550 and insulator 580.

Further, it is preferable to provide conductors 540 (conductors 540a and 540 b) which are electrically connected to the transistor 500 and function as plugs. Further, insulators 541 (an insulator 541a and an insulator 541 b) are provided so as to be in contact with side surfaces of the conductors 540 serving as plugs. That is, the insulator 541 is provided so as to be in contact with the inner walls of the openings of the insulators 554, 580, 574, and 581. Further, a first conductor of the conductor 540 may be provided so as to contact the side surface of the insulator 541, and a second conductor may be provided inside the first conductor. Here, the height of the top surface of the conductor 540 may be substantially the same as the height of the top surface of the insulator 581. In the transistor 500, the first conductor of the conductor 540 and the second conductor of the conductor 540 are stacked, but the present invention is not limited thereto. For example, the conductor 540 may have a single-layer structure or a stacked structure of three or more layers. When the structure has a laminated structure, ordinals may be given in the order of formation to distinguish them.

A metal oxide used as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor) is preferably used for the metal oxide 531 (the metal oxide 531a and the metal oxide 531 b) including a channel formation region in the transistor 500. For example, as the metal oxide to be the channel formation region of the metal oxide 531, a metal oxide having a band gap of 2eV or more, preferably 2.5eV or more is preferably used.

The metal oxide preferably contains at least indium (In) or zinc (Zn). In particular, indium (In) and zinc (Zn) are preferably contained. In addition, the element M is preferably contained. The element M may be one or more selected from aluminum (Al), gallium (Ga), yttrium (Y), tin (Sn), boron (B), titanium (Ti), iron (Fe), nickel (Ni), germanium (Ge), zirconium (Zr), molybdenum (Mo), lanthanum (La), cerium (Ce), neodymium (Nd), hafnium (Hf), tantalum (Ta), tungsten (W), magnesium (Mg), and cobalt (Co). In particular, the element M is preferably one or more of aluminum (Al), gallium (Ga), yttrium (Y), and tin (Sn). Further, the element M more preferably contains one or both of Ga and Sn.

In addition, the thickness of the region of the metal oxide 531b that does not overlap the conductor 542 may be smaller than the thickness of the region that overlaps the conductor 542. This occurs because a portion of the top surface of the metal oxide 531b is removed when the conductors 542a and 542b are formed. When a conductive film to be the conductor 542 is deposited on the top surface of the metal oxide 531b, a low resistance region is sometimes formed near the interface with the conductive film. In this manner, by removing a low-resistance region between the conductor 542a and the conductor 542b on the top surface of the metal oxide 531b, channel formation can be suppressed in this region.

In one embodiment of the present invention, a display device including a transistor having a small size and having high definition can be provided. Further, by including a transistor with a large on-state current, a display device with high luminance can be provided. Further, by including a transistor which operates at a high speed, a display device which operates at a high speed can be provided. Further, by including a transistor whose electric characteristics are stable, a display device with high reliability can be provided. Further, by including a transistor with a small off-state current, a display device with low power consumption can be provided.

A detailed structure of the transistor 500 which can be used for the display device according to one embodiment of the present invention will be described.

The conductor 505 is arranged to include a region overlapping with the metal oxide 531 and the conductor 560. Further, the electric conductor 505 is preferably provided in such a manner as to be embedded in the insulator 516.

The conductor 505 includes a conductor 505a and a conductor 505b. The conductor 505a is provided so as to contact the bottom surface and the side wall of the opening provided in the insulator 516. The conductor 505b is provided so as to be fitted in a recess formed in the conductor 505 a. Here, the height of the top surface of the conductor 505b is substantially equal to the height of the top surface of the conductor 505a and the height of the top surface of the insulator 516.

As the conductor 505a, a conductive material having a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (for example, N ₂ O, NO and NO ₂), and copper atoms is preferably used. In addition, a conductive material having a function of suppressing diffusion of oxygen (for example, one or both of an oxygen atom and an oxygen molecule) is preferably used.

By using a conductive material having a function of suppressing diffusion of hydrogen as the conductor 505a, diffusion of impurities such as hydrogen contained in the conductor 505b to the metal oxide 531 through the insulator 524 can be suppressed. Further, by using a conductive material having a function of suppressing diffusion of oxygen as the conductive body 505a, the conductive body 505b can be suppressed from being oxidized and the conductivity from being lowered. Examples of the conductive material having a function of suppressing oxygen diffusion include titanium, titanium nitride, tantalum nitride, ruthenium, and ruthenium oxide. Thus, the conductor 505a may be a single layer or a stacked layer of the above-described conductive material. For example, titanium nitride may be used as the conductor 505 a.

As the conductor 505b, a conductive material containing tungsten, copper, or aluminum as a main component is preferably used. For example, tungsten may be used for the conductor 505 b.

Here, the conductor 560 is sometimes used as a first gate (sometimes referred to as a top gate) electrode. The electrical conductor 505 is sometimes used as a second gate (sometimes referred to as a bottom gate) electrode. In this case, V _th of the transistor 500 can be controlled by changing the potential applied to the conductor 505 independently of the potential applied to the conductor 560. In particular, by applying a negative potential to the conductor 505, V _th of the transistor 500 can be further increased and the off-state current can be reduced. Therefore, in the case where a negative potential is applied to the conductor 505, the drain current when the potential applied to the conductor 560 is 0V can be reduced compared to the case where a negative potential is not applied to the conductor 505.

The conductor 505 is preferably larger than the channel formation region in the metal oxide 531. In particular, as shown in fig. 60C, the conductor 505 preferably extends to a region outside of an end portion intersecting with the metal oxide 531 in the channel width direction. That is, it is preferable that the conductor 505 and the conductor 560 overlap each other with an insulator therebetween on the outer side of the side surface of the metal oxide 531 in the channel width direction.

By having the above-described structure, the channel formation region of the metal oxide 531 can be electrically surrounded by the electric field of the conductor 560 serving as the first gate electrode and the electric field of the conductor 505 serving as the second gate electrode.

As shown in fig. 60C, the conductor 505 is extended to serve as a wiring. However, the present invention is not limited to this, and a conductor serving as a wiring may be provided under the conductor 505.

Insulator 514 is preferably used as a barrier insulating film for preventing impurities such as water and hydrogen from being mixed into transistor 500 from the substrate side. Accordingly, it is preferable to use an insulating material having a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (for example, N ₂ O, NO and NO ₂), copper atoms, and the like (not easily allowing the impurities to permeate therethrough) as the insulator 514. Or an insulating material having a function of suppressing diffusion of oxygen (for example, one or both of an oxygen atom and an oxygen molecule) (not easily allowing the oxygen to permeate therethrough) is preferably used.

For example, aluminum oxide or silicon nitride is preferably used as the insulator 514. This can suppress diffusion of impurities such as water and hydrogen from the substrate side to the transistor 500 side with respect to the insulator 514. Or, for example, oxygen contained in the insulator 524 or the like can be suppressed from diffusing to the substrate side more than the insulator 514.

The dielectric constants of the insulator 516, the insulator 580, and the insulator 581 serving as interlayer films are preferably lower than those of the insulator 514. By using a material having a low dielectric constant for the interlayer film, parasitic capacitance generated between wirings can be reduced. For example, silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon nitride may be used for the insulator 516, the insulator 580, and the insulator 581. As the insulator 516, the insulator 580, and the insulator 581, for example, silicon oxide to which fluorine is added, silicon oxide to which carbon and nitrogen are added, or silicon oxide having voids can be used. The materials used for the insulator 516, the insulator 580, and the insulator 581 may be appropriately combined.

Insulator 522 and insulator 524 are used as gate insulators.

Here, in the insulator 524 in contact with the metal oxide 531, oxygen is preferably desorbed by heating. In this specification and the like, oxygen desorbed by heating is sometimes referred to as excess oxygen. For example, silicon oxide or silicon oxynitride may be used as the insulator 524 as appropriate. By providing an insulator containing oxygen in contact with the metal oxide 531, oxygen vacancies in the metal oxide 531 can be reduced, and thus the reliability of the transistor 500 can be improved.

Specifically, as the insulator 524, an oxide material that releases a part of oxygen by heating is preferably used. The oxide that releases oxygen by heating is an oxide film in which the release amount of oxygen converted to oxygen atoms in TDS analysis is 1.0×10 ¹⁸atoms/cm³ or more, preferably 1.0×10 ¹⁹atoms/cm³ or more, more preferably 2.0×10 ¹⁹atoms/cm³ or more, or 3.0×10 ²⁰atoms/cm³ or more. The surface temperature of the film in the TDS analysis is preferably in the range of 100 ℃ to 700 ℃, or 100 ℃ to 400 ℃.

Like the insulator 514, the insulator 522 is preferably used as a barrier insulating film for preventing impurities such as water and hydrogen from being mixed into the transistor 500 from the substrate side. For example, insulator 522 preferably has a lower hydrogen permeability than insulator 524. By surrounding the insulator 524, the metal oxide 531, and the insulator 550 with the insulator 522, the insulator 554, and the insulator 574, entry of impurities such as water and hydrogen into the transistor 500 from the outside can be suppressed.

The insulator 522 preferably has a function of suppressing diffusion of oxygen (for example, one or both of an oxygen atom and an oxygen molecule) (the oxygen is not easily transmitted). For example, insulator 522 preferably has a lower oxygen permeability than insulator 524. The insulator 522 is preferably provided with a function of suppressing diffusion of impurities such as oxygen, water, and hydrogen, because diffusion of oxygen contained in the metal oxide 531 to the substrate side can be reduced. In addition, the reaction of the conductor 505 with oxygen contained in the insulator 524 and the metal oxide 531 can be suppressed.

As the insulator 522, an insulator containing an oxide of one or both of aluminum and hafnium is preferably used. Examples of the insulator containing an oxide of one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, and an oxide containing aluminum and hafnium (hafnium aluminate). When the insulator 522 is formed using such a material, the insulator 522 is used as a layer which suppresses release of oxygen from the metal oxide 531 and entry of impurities such as hydrogen into the metal oxide 531 from the peripheral portion of the transistor 500.

Alternatively, for example, alumina, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the insulator. Further, the insulator may be subjected to nitriding treatment. Further, silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the insulator.

As the insulator 522, for example, an insulator containing a so-called high-k material such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO ₃), or (Ba, sr) TiO ₃ (BST) may be used in a single layer or a stacked layer. As miniaturization and high integration of transistors progress, problems such as leakage current may occur due to thinning of the gate insulating film. By using a high-k material as an insulator for the gate insulator, the gate potential of the transistor when operating can be reduced while maintaining physical thickness.

The insulator 522 and the insulator 524 may have a stacked structure of two or more layers. In this case, the stacked structure is not limited to the stacked structure using the same material, and may be a stacked structure using a different material. For example, an insulator similar to insulator 524 may be provided under insulator 522.

The metal oxide 531 includes a metal oxide 531a and a metal oxide 531b on the metal oxide 531 a. When the metal oxide 531a is provided below the metal oxide 531b, diffusion of impurities from a structure formed below the metal oxide 531a to the metal oxide 531b can be suppressed.

The metal oxide 531 preferably has a stacked structure of oxide layers in which the atomic ratios of the metal atoms are different from each other. For example, in the case where the metal oxide 531 contains at least indium (In) and the element M, the atomic ratio of the element M among all the constituent elements of the metal oxide 531a is preferably larger than the atomic ratio of the element M among all the constituent elements of the metal oxide 531 b. Further, the atomic ratio of the element M to In the metal oxide 531a is preferably larger than the atomic ratio of the element M to In the metal oxide 531 b.

Preferably, the energy of the conduction band bottom of the metal oxide 531a is made higher than the energy of the conduction band bottom of the metal oxide 531 b. In other words, the electron affinity of the metal oxide 531a is preferably smaller than that of the metal oxide 531 b.

Here, in the junction of the metal oxide 531a and the metal oxide 531b, the energy level of the conduction band bottom changes gently. In other words, the above-described case may be expressed as that the energy level of the conduction band bottom of the junction of the metal oxide 531a and the metal oxide 531b is continuously changed or continuously joined. For this reason, it is preferable to reduce the defect state density of the mixed layer formed at the interface of the metal oxide 531a and the metal oxide 531 b.

Specifically, by including a common element (main component) in addition to oxygen in the metal oxide 531a and the metal oxide 531b, a mixed layer having a low defect state density can be formed. For example, in the case where the metal oxide 531b is an in—ga—zn oxide, a ga—zn oxide, gallium oxide, or the like can be used as the metal oxide 531 a.

Specifically, as the metal oxide 531a, in: ga: zn=1: 3:4[ atomic number ratio ] or 1:1:0.5[ atomic number ratio ]. In addition, as the metal oxide 531b, in: ga: zn=1: 1:1[ atomic number ratio ], 4:2:3[ atomic number ratio ] or 3:1:2[ atomic number ratio ].

At this time, the main path of the carriers is the metal oxide 531b. By providing the metal oxide 531a with the above structure, the defect state density of the interface between the metal oxide 531a and the metal oxide 531b can be reduced. Therefore, the influence of interface scattering on carrier conduction is reduced, and thus the transistor 500 can obtain a large on-state current and high frequency characteristics.

The metal oxide 531b is provided with a conductor 542 (a conductor 542a and a conductor 542 b) serving as a source electrode and a drain electrode. As the conductor 542, for example, a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, an alloy containing two or more kinds of the metal elements as components, or an alloy combining two or more kinds of the metal elements is preferably used. As the conductor 542, for example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, and an oxide containing lanthanum and nickel are preferably used. Further, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel are conductive materials which are not easily oxidized or materials which absorb oxygen and maintain conductivity are preferable.

By forming the above-described conductor 542 in contact with the metal oxide 531, the oxygen concentration in the vicinity of the conductor 542 in the metal oxide 531 may be reduced. In addition, a metal compound layer containing a metal included in the conductor 542 and a component of the metal oxide 531 may be formed in the vicinity of the conductor 542 in the metal oxide 531. In this case, the carrier concentration increases in a region near the conductor 542 of the metal oxide 531, which becomes a low-resistance region.

Here, a region between the conductor 542a and the conductor 542b is formed so as to overlap with the opening of the insulator 580. Accordingly, the conductor 560 can be arranged in self-alignment between the conductor 542a and the conductor 542 b.

Insulator 550 is used as a gate insulator. The insulator 550 is preferably disposed in contact with the top surface of the metal oxide 531 b. As the insulator 550, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon and nitrogen, or silicon oxide having voids can be used. In particular, silicon oxide and silicon oxynitride are preferable because they have thermal stability.

Like insulator 524, the concentration of impurities such as water and hydrogen in insulator 550 is preferably reduced. The thickness of the insulator 550 is preferably 1nm or more and 20nm or less.

Further, an insulator may be provided between the insulator 580, the insulator 554, the conductor 542, the metal oxide 531b, and the insulator 550. For example, aluminum oxide or hafnium oxide is preferably used as the insulator. By providing this insulator, one or more of detachment of oxygen from the metal oxide 531b, excessive supply of oxygen to the metal oxide 531b, and oxidation of the conductor 542 can be suppressed.

A metal oxide may also be provided between the insulator 550 and the conductor 560. The metal oxide preferably inhibits oxygen diffusion from insulator 550 to conductor 560. This can suppress oxidation of the conductor 560 due to oxygen in the insulator 550.

The metal oxide is sometimes used as part of the gate insulator. Therefore, in the case where silicon oxide or silicon oxynitride is used for the insulator 550, a metal oxide which is a high-k material having a high relative dielectric constant is preferably used as the metal oxide. By providing the gate insulator with a stacked structure of the insulator 550 and the metal oxide, a stacked structure having high thermal stability and a high relative dielectric constant can be formed. Accordingly, the gate potential applied when the transistor operates can be reduced while maintaining the physical thickness of the gate insulator. In addition, the Equivalent Oxide Thickness (EOT) of the insulator used as the gate insulator can be reduced.

Specifically, as the metal oxide, for example, a metal oxide containing one or two or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, and magnesium can be used. In particular, as the metal oxide, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) is preferably used as an insulator containing an oxide of one or both of aluminum and hafnium.

Although the conductor 560 has a two-layer structure in fig. 60B and 60C, it may have a single-layer structure or a stacked-layer structure of three or more layers.

The conductor 560a preferably has a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (for example, N ₂O、NO、NO₂) and copper atoms. Or a conductive material having a function of suppressing diffusion of oxygen (for example, one or both of an oxygen atom and an oxygen molecule) is preferably used.

By providing the conductor 560a with a function of suppressing diffusion of oxygen, the oxidation of the conductor 560b due to oxygen contained in the insulator 550 can be suppressed, and the decrease in conductivity can be suppressed. Examples of the conductive material having a function of suppressing diffusion of oxygen include tantalum, tantalum nitride, ruthenium, and ruthenium oxide.

As the conductor 560b, a conductive material containing tungsten, copper, or aluminum as a main component is preferably used. Further, since the conductor 560 is also used as a wiring, a conductor having high conductivity is preferably used. For example, a conductive material containing tungsten, copper, or aluminum as a main component may be used. The conductor 560b may have a stacked structure, and for example, a stacked structure of titanium or titanium nitride and the above-described conductive material may be used.

As shown in fig. 60A and 60C, in a region of the metal oxide 531b which does not overlap with the conductor 542, that is, in a channel formation region of the metal oxide 531, a side surface of the metal oxide 531 is covered with the conductor 560. Thereby, the electric field of the conductor 560 serving as the first gate electrode can be easily influenced to the side surface of the metal oxide 531. This can improve the on-state current and frequency characteristics of the transistor 500.

As with insulator 514, insulator 554 is preferably used as a barrier insulating film for inhibiting impurities such as water and hydrogen from entering transistor 500 from the side of insulator 580. For example, insulator 554 preferably has a lower hydrogen permeability than insulator 524. Further, as shown in fig. 60B and 60C, the insulator 554 preferably contacts the side surface of the insulator 550, the top and side surfaces of the conductor 542a, the top and side surfaces of the conductor 542B, the metal oxide 531a, the metal oxide 531B, and the side surface of the insulator 524. By adopting such a structure, hydrogen contained in the insulator 580 can be suppressed from entering the metal oxide 531 from the top surface or the side surface of the conductor 542a, the conductor 542b, the metal oxide 531a, the metal oxide 531b, and the insulator 524.

The insulator 554 preferably has a function of suppressing diffusion of oxygen (for example, one or both of an oxygen atom and an oxygen molecule) (not easily allowing the oxygen to permeate). For example, insulator 554 preferably has a lower oxygen permeability than insulator 580 or insulator 524.

Insulator 554 is preferably deposited by sputtering. Oxygen may be added near the region of insulator 524 in contact with insulator 554 by depositing insulator 554 using a sputtering method under an atmosphere containing oxygen. Thereby, oxygen can be supplied from this region into the metal oxide 531 through the insulator 524. Here, by providing the insulator 554 with a function of suppressing diffusion of oxygen to the upper side, diffusion of oxygen from the metal oxide 531 to the insulator 580 can be prevented. Further, by making the insulator 522 have a function of suppressing diffusion of oxygen to the lower side, diffusion of oxygen from the metal oxide 531 to the substrate side can be prevented. Thus, oxygen is supplied to the channel formation region in the metal oxide 531. This reduces oxygen vacancies in the metal oxide 531 and suppresses normally-on of the transistor.

As the insulator 554, for example, an insulator containing an oxide of one or both of aluminum and hafnium is preferably deposited. Note that as an insulator containing an oxide of one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, and an oxide containing aluminum and hafnium (hafnium aluminate) are preferably used.

Insulator 580 is preferably disposed on insulator 524, metal oxide 531 and conductor 542 through insulator 554. For example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon oxide added with fluorine, silicon oxide added with carbon and nitrogen, or silicon oxide having voids is preferably used for the insulator 580. In particular, silicon oxide and silicon oxynitride are preferable because they have thermal stability. In particular, a material such as silicon oxide, silicon oxynitride, or silicon oxide having voids is preferable because a region containing oxygen which is desorbed by heating is easily formed.

The concentration of impurities such as water and hydrogen in insulator 580 is preferably reduced. In addition, the top surface of insulator 580 may also be planarized.

Insulator 574 is preferably used as a barrier insulating film for preventing impurities such as water and hydrogen from being mixed into insulator 580 from above, similarly to insulator 514. As the insulator 574, for example, an insulator usable for the insulator 514 or the insulator 554 may be used.

An insulator 581 serving as an interlayer film is preferably provided over the insulator 574. Like insulator 524, the concentration of impurities such as water and hydrogen in insulator 581 is preferably reduced.

The conductors 540a and 540b are disposed in openings formed in the insulator 581, the insulator 574, the insulator 580, and the insulator 554. The conductors 540a and 540b are disposed so as to face each other with the conductor 560 interposed therebetween. In addition, the top surfaces of the conductors 540a and 540b may be level with the top surface of the insulator 581.

Further, an insulator 541a is provided so as to contact the inner walls of the openings of the insulator 581, the insulator 574, the insulator 580, and the insulator 554, and a first conductor of the conductor 540a is formed so as to contact the side surfaces thereof. The conductor 542a is located at least in a portion of the bottom of the opening, and the conductor 540a is in contact with the conductor 542 a. Similarly, insulator 541b is provided so as to contact the inner walls of the openings of insulator 581, insulator 574, insulator 580, and insulator 554, and a first conductor of conductor 540b is formed so as to contact the side surfaces thereof. The conductor 542b is located at least in a portion of the bottom of the opening, and the conductor 540b is in contact with the conductor 542 b.

The conductors 540a and 540b are preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductors 540a and 540b may have a stacked structure.

When a stacked structure is used for the conductor 540, the conductor having the function of suppressing diffusion of impurities such as water and hydrogen is preferably used as a conductor in contact with the conductor 542, the insulator 554, the insulator 580, the insulator 574, and the insulator 581. For example, tantalum nitride, titanium nitride, ruthenium, or ruthenium oxide is preferably used as the conductor. In addition, a conductive material having a function of suppressing diffusion of impurities such as water and hydrogen may be used in a single layer or a stacked layer. By using this conductive material, oxygen added to the insulator 580 can be prevented from being absorbed by the conductors 540a and 540 b. Further, impurities such as water and hydrogen can be prevented from entering the metal oxide 531 from the layer above the insulator 581 through the conductors 540a and 540 b.

As the insulator 541a and the insulator 541b, for example, an insulator usable for the insulator 554 may be used. Since the insulator 541a and the insulator 541b are provided in contact with the insulator 554, impurities such as water and hydrogen can be prevented from being mixed into the metal oxide 531 from the insulator 580 through the conductors 540a and 540 b. In addition, oxygen in the insulator 580 can be suppressed from being absorbed by the conductors 540a and 540 b.

Although not shown, conductors serving as wirings may be arranged so as to be in contact with the top surface of the conductor 540a and the top surface of the conductor 540 b. As the conductor used for the wiring, a conductive material containing tungsten, copper, or aluminum as a main component is preferably used. The conductor may have a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above-mentioned conductive material. The electrical conductor may also be formed so as to be embedded in an opening in the insulator.

< Materials constituting transistors >

The following describes constituent materials that can be used for the transistor.

[ Substrate ]

As a substrate for forming the transistor 500, an insulator substrate, a semiconductor substrate, or a conductor substrate can be used, for example. Examples of the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (yttria stabilized zirconia substrate, etc.), and a resin substrate. The semiconductor substrate includes, for example, a semiconductor substrate including silicon or germanium. Or, as the semiconductor substrate, for example, a compound semiconductor substrate containing silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide can be given. The semiconductor substrate may be a semiconductor substrate having an insulator region in the semiconductor substrate, for example, an SOI substrate. Examples of the conductor substrate include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate. Examples of the conductive substrate include a substrate containing a metal nitride and a substrate containing a metal oxide. Examples of the conductor substrate include an insulator substrate provided with a conductor or a semiconductor, a semiconductor substrate provided with a conductor or an insulator, and a conductor substrate provided with one of a semiconductor and an insulator. Alternatively, a substrate having elements provided over these substrates may be used. Examples of the element provided over the substrate include a capacitor element, a resistor, a switching element, a light-emitting element, and a memory element.

[ Insulator ]

Examples of the insulator include insulating oxides, nitrides, oxynitrides, metal oxides, metal oxynitrides, and metal oxynitrides.

For example, when miniaturization or high integration of a transistor is performed, a problem of leakage current may occur due to thinning of a gate insulator. By using a high-k material as an insulator for the gate insulator, the voltage can be reduced when the transistor is operated while maintaining the physical thickness. On the other hand, by using a material having a low relative dielectric constant for an insulator serving as an interlayer film, parasitic capacitance generated between wirings can be reduced. Therefore, the material is preferably selected according to the function of the insulator.

Examples of the insulator having a relatively high dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, aluminum and hafnium-containing oxides, aluminum and hafnium-containing oxynitrides, silicon and hafnium-containing oxides, silicon and hafnium-containing oxynitrides, and silicon and hafnium-containing nitrides.

Examples of the insulator having a low relative dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon and nitrogen, silicon oxide having voids, and resin.

The transistor using an oxide semiconductor is surrounded by insulators (an insulator 514, an insulator 522, an insulator 554, and an insulator 574) having a function of suppressing permeation of impurities such as water and hydrogen, and oxygen, whereby the electric characteristics of the transistor can be stabilized. As the insulator having a function of suppressing permeation of impurities such as water and hydrogen and oxygen, for example, a single layer or a stacked layer including one or more insulators selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum can be used. Specifically, examples of the insulator having a function of suppressing permeation of impurities such as water and hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. Examples of the insulator having a function of suppressing permeation of impurities such as water and hydrogen and oxygen include metal nitrides such as aluminum nitride, aluminum titanium nitride, silicon oxynitride and silicon nitride.

The insulator used as the gate insulator is preferably an insulator having a region containing oxygen which is desorbed by heating. For example, by adopting a structure in which silicon oxide or silicon oxynitride having a region containing oxygen which is desorbed by heating is in contact with the metal oxide 531, oxygen vacancies contained in the metal oxide 531 can be filled.

[ Electric conductor ]

As the conductor, for example, a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, an alloy containing two or more kinds of the metal elements as components, or an alloy combining two or more kinds of the metal elements is preferably used. As the conductor, for example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, or the like is preferably used. Further, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel are conductive materials which are not easily oxidized or materials which absorb oxygen and maintain conductivity are preferable. Further, as the conductor, for example, a semiconductor having high conductivity typified by polycrystalline silicon containing an impurity element (for example, phosphorus) or a silicide (for example, nickel silicide) may be used.

In addition, a plurality of conductors made of the above materials may be stacked. For example, a stacked-layer structure of a material containing the above metal element and a conductive material containing oxygen may be used. In addition, a stacked structure of a material containing the above metal element and a conductive material containing nitrogen may be used. In addition, a stacked-layer structure in which a material containing the above metal element, a conductive material containing oxygen, and a conductive material containing nitrogen are combined may also be employed.

In addition, in the case where a metal oxide is used for a channel formation region of a transistor, a stacked-layer structure in which a material containing the above-described metal element and a conductive material containing oxygen are combined is preferably used as a conductive body serving as a gate electrode. In this case, it is preferable to provide a conductive material containing oxygen on the channel formation region side. By disposing the conductive material containing oxygen on the channel formation region side, oxygen detached from the conductive material is easily supplied to the channel formation region.

In particular, as the conductor used as the gate electrode, a conductive material containing a metal element and oxygen contained in a metal oxide forming a channel is preferably used. For example, a conductive material containing the above metal element and nitrogen may be used as the conductive material. For example, a conductive material containing nitrogen such as titanium nitride or tantalum nitride may be used as the conductive material. For example, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide to which silicon is added may be used as the conductor. In addition, indium gallium zinc oxide containing nitrogen may also be used. By using the above material, hydrogen contained in the metal oxide forming the channel may be trapped in some cases. Or hydrogen entering from an insulator or the like outside may sometimes be trapped.

At least a part of this embodiment can be implemented in combination with other embodiments described in this specification as appropriate.

Embodiment 6

In this embodiment mode, a metal oxide (hereinafter also referred to as an oxide semiconductor) that can be used for the OS transistor described in the above embodiment mode is described.

The metal oxide for the OS transistor preferably contains at least indium or zinc, more preferably contains indium and zinc. For example, the metal oxide preferably contains indium, M (M is one or more selected from gallium, aluminum, yttrium, tin, silicon, boron, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt), and zinc. In particular, M is preferably one or more selected from gallium, aluminum, yttrium, and tin, more preferably gallium.

The metal oxide can be formed by a CVD method such as a sputtering method or an MOCVD method, an ALD method, or the like.

Hereinafter, an oxide containing indium (In), gallium (Ga), and zinc (Zn) is described as an example of a metal oxide. Note that oxides containing indium (In), gallium (Ga), and zinc (Zn) are sometimes referred to as In-Ga-Zn oxides.

< Classification of Crystal Structure >

Examples of the crystalline structure of the oxide semiconductor include amorphous (including completely amorphous)、CAAC(c-axis-aligned crystalline)、nc(nanocrystalline)、CAC(cloud-aligned composite)、 single crystal (SINGLE CRYSTAL) and polycrystalline (poly crystal).

In addition, the crystalline structure of the film or substrate can be evaluated using X-Ray Diffraction (XRD) spectroscopy. For example, the XRD spectrum measured by GIXD (Grazing-INCIDENCE XRD) measurement can be used for evaluation. In addition, GIXD method is also called thin film method or Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained by GIXD measurement may be simply referred to as XRD spectrum.

For example, the peak shape of the XRD spectrum of the quartz glass substrate is substantially bilaterally symmetrical. On the other hand, the peak shape of the XRD spectrum of the In-Ga-Zn oxide film having a crystal structure is not bilaterally symmetrical. The peak shape of the XRD spectrum is not bilateral symmetry to indicate the presence of crystals in the film or in the substrate. In other words, unless the peak shape of the XRD spectrum is bilaterally symmetrical, it cannot be said that the film or substrate is in an amorphous state.

In addition, the crystalline structure of the film or substrate can be evaluated using a diffraction pattern (also referred to as a nanobeam electron diffraction pattern) observed by a nanobeam electron diffraction method (NBED: nano Beam Electron Diffraction). For example, a halo is observed in a diffraction pattern of a quartz glass substrate, and it can be confirmed that the quartz glass is in an amorphous state. In addition, a spot-like pattern was observed In the diffraction pattern of the In-Ga-Zn oxide film deposited at room temperature without the halo being observed. It is therefore speculated that an In-Ga-Zn oxide deposited at room temperature is In an intermediate state that is neither monocrystalline or polycrystalline nor amorphous, and it cannot be concluded that the In-Ga-Zn oxide is amorphous.

Structure of oxide semiconductor

In addition, in the case of focusing attention on the structure of an oxide semiconductor, the classification of the oxide semiconductor may be different from the above classification. For example, oxide semiconductors can be classified into single crystal oxide semiconductors and non-single crystal oxide semiconductors other than the single crystal oxide semiconductors. Examples of the non-single crystal oxide semiconductor include the CAAC-OS and nc-OS described above. Further, a polycrystalline oxide semiconductor, an a-like OS (amorphorus-like oxide semiconductor), and an amorphous oxide semiconductor are included in the non-single crystal oxide semiconductor.

Details of the CAAC-OS, nc-OS, and a-like OS will be described herein.

[CAAC-OS]

The CAAC-OS is an oxide semiconductor including a plurality of crystal regions, the c-axis of which is oriented in a specific direction. The specific direction refers to the thickness direction of the CAAC-OS film, the normal direction of the surface on which the CAAC-OS film is formed, or the normal direction of the surface of the CAAC-OS film. The crystallization region is a region having periodicity of atomic arrangement. Note that the crystal region is also a region in which lattice arrangements are uniform when the atomic arrangements are regarded as lattice arrangements. The CAAC-OS may have a region where a plurality of crystal regions are connected in the a-b plane direction, and the region may have distortion. In addition, distortion refers to a portion in which the direction of lattice arrangement changes between a region in which lattice arrangements are uniform and other regions in which lattice arrangements are uniform among regions in which a plurality of crystal regions are connected. In other words, CAAC-OS refers to an oxide semiconductor that is c-axis oriented and has no significant orientation in the a-b plane direction.

Each of the plurality of crystal regions is composed of one or more fine crystals (crystals having a maximum diameter of less than 10 nm). In the case where the crystal region is composed of one minute crystal, the maximum diameter of the crystal region is less than 10nm. In the case where the crystal region is composed of a plurality of fine crystals, the maximum diameter of the crystal region may be about several tens of nm.

In addition, the CAAC-OS has a layered crystal structure (also referred to as a layered structure) In which a layer containing indium (In) and oxygen (hereinafter, in layer), and a layer containing gallium (Ga), zinc (Zn), and oxygen (hereinafter, (Ga, zn) layer) are stacked In the In-Ga-Zn oxide. In addition, indium and gallium may be substituted for each other. Therefore, the (Ga, zn) layer sometimes contains indium. In addition, sometimes the In layer contains gallium. Note that sometimes the In layer contains zinc. The layered structure is observed as a lattice image, for example in a high resolution TEM (Transmission Electron Microscope) image.

For example, when structural analysis is performed on a CAAC-OS film using an XRD device, a peak representing c-axis orientation is detected at or near 2θ=31° in Out-of-plane XRD measurement using θ/2θ scanning. Note that the position (2θ value) of the peak indicating the c-axis orientation may vary depending on the kind and composition of the metal element constituting the CAAC-OS.

Further, for example, a plurality of bright spots (spots) are observed in the electron diffraction pattern of the CAAC-OS film. In addition, when a spot of an incident electron beam (also referred to as a direct spot) passing through a sample is taken as a symmetry center, a certain spot and other spots are observed at a point-symmetrical position.

When the crystal region is observed from the above specific direction, the lattice arrangement in the crystal region is basically a hexagonal lattice, but the unit cell is not limited to a regular hexagon, and may be a non-regular hexagon. In addition, the distortion may have a lattice arrangement such as pentagonal or heptagonal. In addition, no clear grain boundary (grain boundary) was observed near the distortion of CAAC-OS. That is, distortion of the lattice arrangement suppresses the formation of grain boundaries. This is probably because CAAC-OS can accommodate distortion due to low density of arrangement of oxygen atoms in the a-b face direction or change in bonding distance between atoms due to substitution of metal atoms, or the like.

In addition, the crystal structure in which a clear grain boundary is confirmed is called "polycrystal". Since the grain boundary serves as a recombination center and carriers are trapped, there is a possibility that one or both of the decrease in on-state current and the decrease in field-effect mobility of the transistor may be caused. Therefore, CAAC-OS, in which no definite grain boundary is confirmed, is one of crystalline oxides that provide a semiconductor layer of a transistor with an excellent crystalline structure. Note that, in order to constitute the CAAC-OS, a structure containing Zn is preferable. For example, in—zn oxide and in—ga—zn oxide are preferable because occurrence of grain boundaries can be further suppressed as compared with In oxide.

CAAC-OS is an oxide semiconductor with high crystallinity and no clear grain boundary is confirmed. Therefore, it can be said that in the CAAC-OS, a decrease in electron mobility due to grain boundaries does not easily occur. Further, since crystallinity of an oxide semiconductor is sometimes reduced by one or both of contamination of impurities and generation of defects, CAAC-OS is said to be an oxide semiconductor having few impurities and defects (e.g., oxygen vacancies). Therefore, the physical properties of the oxide semiconductor including CAAC-OS are stable. Therefore, an oxide semiconductor including CAAC-OS has high heat resistance and high reliability. In addition, CAAC-OS is also stable to high temperatures (so-called thermal budget) in the manufacturing process. Thus, by using the CAAC-OS for the OS transistor, the degree of freedom in the manufacturing process can be increased.

[nc-OS]

In nc-OS, atomic arrangements in minute regions (for example, regions of 1nm to 10nm, particularly, regions of 1nm to 3 nm) have periodicity. In other words, nc-OS has a minute crystal. For example, the size of the fine crystals is 1nm to 10nm, particularly 1nm to 3nm, and the fine crystals are called nanocrystals. Furthermore, the nc-OS did not observe regularity of crystal orientation between different nanocrystals. Therefore, the orientation was not observed in the whole film. Therefore, nc-OS is sometimes not different from a-like OS and amorphous oxide semiconductor in some analysis methods. For example, when a structural analysis is performed on an nc-OS film using an XRD device, a peak indicating crystallinity is not detected in an Out-of-plane XRD measurement using a θ/2θ scan. In addition, when an electron diffraction (also referred to as selective electron diffraction) using an electron beam having a beam diameter larger than that of nanocrystals (for example, 50nm or more) is performed on the nc-OS film, a diffraction pattern resembling a halo pattern is observed. On the other hand, when an electron diffraction (also referred to as a "nanobeam electron diffraction") using an electron beam having a beam diameter equal to or smaller than the size of a nanocrystal (for example, 1nm or more and 30nm or less) is performed on an nc-OS film, an electron diffraction pattern in which a plurality of spots are observed in an annular region centered on a direct spot may be obtained.

[a-like OS]

The a-like OS is an oxide semiconductor having a structure between nc-OS and an amorphous oxide semiconductor. The a-like OS contains holes or low density regions. That is, the crystallinity of the a-like OS is lower than that of nc-OS and CAAC-OS. The concentration of hydrogen in the film of a-like OS is higher than that in the films of nc-OS and CAAC-OS.

[ Formation of oxide semiconductor ]

Next, the details of the CAC-OS will be described. In addition, CAC-OS is related to material composition.

[CAC-OS]

The CAC-OS refers to, for example, a constitution in which elements contained in a metal oxide are unevenly distributed, wherein the size of a material containing unevenly distributed elements is 0.5nm or more and 10nm or less, preferably 1nm or more and 3nm or less or an approximate size. Note that a state in which one or more metal elements are unevenly distributed in a metal oxide and a region including the metal elements is mixed is also referred to as a mosaic shape or a patch shape hereinafter, and the size of the region is 0.5nm or more and 10nm or less, preferably 1nm or more and 3nm or less or an approximate size.

The CAC-OS is a structure in which a material is divided into a first region and a second region, and the first region is mosaic-shaped and distributed in a film (hereinafter also referred to as cloud-shaped). That is, CAC-OS refers to a composite metal oxide having a structure in which the first region and the second region are mixed.

Here, the atomic number ratios of In, ga and Zn with respect to the metal elements constituting the CAC-OS of the In-Ga-Zn oxide are each represented by [ In ], [ Ga ] and [ Zn ]. For example, in CAC-OS of In-Ga-Zn oxide, the first region is a region whose [ In ] is larger than that In the composition of the CAC-OS film. Further, the second region is a region whose [ Ga ] is larger than [ Ga ] in the composition of the CAC-OS film. Further, for example, the first region is a region whose [ In ] is larger than that In the second region and whose [ Ga ] is smaller than that In the second region. Further, the second region is a region whose [ Ga ] is larger than that In the first region and whose [ In ] is smaller than that In the first region.

Specifically, the first region is a region mainly composed of indium oxide or indium zinc oxide. The second region is a region mainly composed of gallium oxide or gallium zinc oxide. In other words, the first region may be referred to as a region mainly composed of In. The second region may be referred to as a region containing Ga as a main component.

Note that a clear boundary between the first region and the second region may not be observed.

The CAC-OS In the In-Ga-Zn oxide is constituted as follows: in the material composition containing In, ga, zn, and O, a region having a part of the main component Ga and a region having a part of the main component In are irregularly present In a mosaic shape. Therefore, it is presumed that the CAC-OS has a structure in which metal elements are unevenly distributed.

The CAC-OS can be formed by, for example, sputtering without heating the substrate. In the case of forming CAC-OS by the sputtering method, as the deposition gas, any one or more selected from inert gas (for example, typically, argon), oxygen gas, and nitrogen gas may be used. In addition, the lower the flow rate ratio of the oxygen gas in the total flow rate of the deposition gas at the time of deposition, the better. For example, the flow rate ratio of the oxygen gas in the total flow rate of the deposition gas at the time of deposition is set to 0% or more and less than 30%, preferably 0% or more and 10% or less.

For example, in the CAC-OS of the In-Ga-Zn oxide, it was confirmed that the structure In which the region mainly composed of In (first region) and the region mainly composed of Ga (second region) were unevenly distributed and mixed was obtained from an EDX-plane analysis (mapping) image obtained by an energy dispersive X-ray analysis method (EDX: ENERGY DISPERSIVE X-ray spectroscopy).

Here, the first region is a region having higher conductivity than the second region. That is, when carriers flow through the first region, conductivity as a metal oxide is exhibited. Thus, when the first region is distributed in a cloud in the metal oxide, high field effect mobility (μ) can be achieved.

On the other hand, the second region is a region having higher insulation than the first region. That is, when the second region is distributed in the metal oxide, leakage current can be suppressed.

Therefore, in the case of using the CAC-OS for the transistor, the CAC-OS can be provided with a switching function (function of controlling on/off) by a complementary effect of the conductivity due to the first region and the insulation due to the second region. In other words, the CAC-OS material has a conductive function in one part and an insulating function in the other part, and has a semiconductor function in the whole material. By separating the conductive function from the insulating function, each function can be improved to the maximum extent. Thus, by using CAC-OS for the transistor, high on-state current (I _on), high field-effect mobility (μ), and good switching operation can be achieved.

Further, a transistor using CAC-OS has high reliability. Therefore, CAC-OS is most suitable for various semiconductor devices such as display devices.

Oxide semiconductors have various structures and various characteristics. The oxide semiconductor according to one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, a-likeOS, CAC-OS, nc-OS, and CAAC-OS.

< Transistor with oxide semiconductor >

Here, a case where the above oxide semiconductor is used for a transistor will be described.

By using the oxide semiconductor described above for a transistor, a transistor with high field effect mobility can be realized. Further, a transistor with high reliability can be realized.

In particular, as the semiconductor layer forming the channel, an oxide containing indium (In), gallium (Ga), and zinc (Zn) (also referred to as IGZO) is preferably used. Alternatively, an oxide containing indium (In), aluminum (Al), and zinc (Zn) (also referred to as IAZO) may be used as the semiconductor layer. Alternatively, an oxide containing indium (In), aluminum (Al), gallium (Ga), and zinc (Zn) (also referred to as IAGZO) may be used as the semiconductor layer.

An oxide semiconductor having a low carrier concentration is preferably used for the transistor. For example, the carrier concentration in the oxide semiconductor is 1×10 ¹⁷cm^-3 or less, preferably 1×10 ¹⁵cm^-3 or less, more preferably 1×10 ¹³cm^-3 or less, further preferably 1×10 ¹¹cm^-3 or less, still more preferably less than 1×10 ¹⁰cm^-3, and 1×10 ^-9cm^-3 or more. In the case of reducing the carrier concentration in the oxide semiconductor film, the impurity concentration in the oxide semiconductor film can be reduced to reduce the defect state density. In this specification and the like, a state in which the impurity concentration is low and the defect state density is low is referred to as a high-purity intrinsic or substantially high-purity intrinsic. Further, an oxide semiconductor having a low carrier concentration is sometimes referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.

Since the high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film has a low defect state density, it is possible to have a low trap state density.

The charge trapped in the trap state of the oxide semiconductor may take a long time to disappear, and may act like a fixed charge. Therefore, the transistor in which the channel formation region is formed in the oxide semiconductor having a high trap state density may have unstable electrical characteristics.

Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in a nearby film. Examples of the impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon. Note that impurities in an oxide semiconductor refer to elements other than the main component constituting the oxide semiconductor, for example. For example, an element having a concentration of less than 0.1 atomic% can be said to be an impurity.

< Impurity >

Here, the influence of each impurity in the oxide semiconductor will be described.

When the oxide semiconductor contains silicon or carbon which is one of group 14 elements, a defect state is formed in the oxide semiconductor. Therefore, the concentration of silicon or carbon in the oxide semiconductor (concentration measured by secondary ion mass spectrometry (SIMS: secondary Ion Mass Spectrometry)) is set to 2X 10 ¹⁸atoms/cm³ or less, preferably 2X 10 ¹⁷atoms/cm³ or less.

When the oxide semiconductor contains an alkali metal or an alkaline earth metal, a defect state is sometimes formed to form a carrier. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal easily has normally-on characteristics. Therefore, the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor measured by SIMS is 1×10 ¹⁸atoms/cm³ or less, preferably 2×10 ¹⁶atoms/cm³ or less.

When the oxide semiconductor contains nitrogen, electrons are easily generated as carriers, and the carrier concentration is increased, so that the oxide semiconductor is n-type. As a result, a transistor using an oxide semiconductor containing nitrogen for a semiconductor tends to have normally-on characteristics. Or when the oxide semiconductor contains nitrogen, a trap state is sometimes formed. As a result, the electrical characteristics of the transistor may be unstable. Therefore, the nitrogen concentration in the oxide semiconductor measured by SIMS is set to be less than 5×10 ¹⁹atoms/cm³, preferably 5×10 ¹⁸atoms/cm³ or less, more preferably 1×10 ¹⁸atoms/cm³ or less, and still more preferably 5×10 ¹⁷atoms/cm³ or less.

Hydrogen contained in the oxide semiconductor reacts with oxygen bonded to a metal atom to generate water, and thus oxygen vacancies are sometimes formed. When hydrogen enters the oxygen vacancy, electrons are sometimes generated as carriers. In addition, some of the hydrogen may be bonded to oxygen bonded to a metal atom, thereby generating electrons as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen easily has normally-on characteristics. Thus, it is preferable to reduce hydrogen in the oxide semiconductor as much as possible. Specifically, the hydrogen concentration in the oxide semiconductor measured by SIMS is set to be less than 1×10 ²⁰atoms/cm³, preferably less than 1×10 ¹⁹atoms/cm³, more preferably less than 5×10 ¹⁸atoms/cm³, and still more preferably less than 1×10 ¹⁸atoms/cm³.

By using an oxide semiconductor whose impurity is sufficiently reduced for a channel formation region of a transistor, the transistor can have stable electrical characteristics.

The structure shown in this embodiment mode can be used in combination with the structure shown in other embodiment modes as appropriate.

Embodiment 7

In this embodiment, a display module applicable to an electronic device according to one embodiment of the present invention will be described.

< Structural example of display Module >

First, a display module including a display device applicable to an electronic apparatus according to one embodiment of the present invention will be described.

Fig. 61A is a perspective view of the display module 1280. The display module 1280 includes a display device 1000 and an FPC1290.

Display module 1280 includes a substrate 1291 and a substrate 1292. The display module 1280 includes a display 1281. The display unit 1281 is an image display area in the display module 1280, and can see light from each pixel provided in a pixel unit 1284 described below.

Fig. 61B is a schematic perspective view of a structure on the substrate 1291 side. The circuit portion 1282, a pixel circuit portion 1283 on the circuit portion 1282, and a pixel portion 1284 on the pixel circuit portion 1283 are stacked over the substrate 1291. Further, a terminal portion 1285 for connection to the FPC1290 is provided at a portion of the substrate 1291 which does not overlap with the pixel portion 1284. The terminal portion 1285 and the circuit portion 1282 are electrically connected by a wiring portion 1286 configured by a plurality of wirings.

The pixel portion 1284 and the pixel circuit portion 1283 correspond to, for example, the pixel layer PXAL. The circuit portion 1282 corresponds to the circuit layer SICL, for example.

The pixel portion 1284 includes a plurality of pixels 1284a that are periodically arranged. An enlarged view of one pixel 1284a is shown on the right side of fig. 61B. The pixel 1284a includes a light emitting device 1430a, a light emitting device 1430b, and a light emitting device 1430c that emit light of different colors from each other. The light emitting devices 1430a, 1430B, and 1430c correspond to the light emitting devices 130R, 130G, and 130B described above, for example. The plurality of light emitting devices may be arranged in a stripe arrangement as shown in fig. 61B. In addition, various arrangement methods such as Delta arrangement and Pentile arrangement may be employed.

The pixel circuit portion 1283 includes a plurality of pixel circuits 1283a that are periodically arranged.

One pixel circuit 1283a controls light emission of three light emitting devices included in one pixel 1284 a. One pixel circuit 1283a may be configured of three circuits that control light emission of one light emitting device. For example, the pixel circuit 1283a may have a structure including at least one selection transistor, one transistor for current control (a driving transistor), and a capacitor for one light-emitting device. At this time, a gate signal is input to the gate of the selection transistor, and a source signal is input to one of the source and the drain. Thus, an active matrix display device is realized.

The circuit portion 1282 includes a circuit that drives each pixel circuit 1283a of the pixel circuit portion 1283. For example, one or both of the gate line driver circuit and the source line driver circuit are preferably included. Further, the memory device may have one or more circuits selected from an arithmetic circuit, a memory circuit, and a power supply circuit.

The FPC1290 serves as a wiring for supplying a video signal or a power supply potential from the outside to the circuit portion 1282. Further, an IC may be mounted on the FPC 1290.

The display module 1280 can have a structure in which one or both of the pixel circuit portion 1283 and the circuit portion 1282 are stacked under the pixel portion 1284, and thus the display portion 1281 can have a very high aperture ratio (effective display area ratio). For example, the aperture ratio of the display portion 1281 may be 40% or more and less than 100%, preferably 50% or more and 95% or less, and more preferably 60% or more and 95% or less. In addition, the pixels 1284a can be arranged at an extremely high density, and thus the display portion 1281 can have extremely high definition. For example, the display unit 1281 is preferably provided with pixels 1284a having a resolution of 20000ppi or less, 30000ppi or less and 2000ppi or more, more preferably 3000ppi or more, still more preferably 5000ppi or more, and still more preferably 6000ppi or more.

Such a display module 1280 is very clear, and is therefore suitable for VR devices such as head-mounted displays and glasses-type AR devices. For example, since the display module 1280 has a display portion 1281 with extremely high definition, in a structure in which the display portion of the display module 1280 is viewed through a lens, a user cannot see pixels even if the display portion is enlarged using the lens, whereby display with high immersion can be achieved. In addition, the display module 1280 may also be applied to an electronic device having a relatively small display portion. For example, the display unit is suitable for a wearable electronic device such as a wristwatch type device.

Embodiment 8

In this embodiment mode, an example of an electronic device using a display device is described as an example of an electronic device according to an embodiment of the present invention.

Fig. 62A and 62B illustrate the external appearance of the electronic device 8300 of the head mounted display.

The electronic device 8300 includes a housing 8301, a display portion 8302, an operation button 8303, and a band-shaped fixing tool 8304.

The operation button 8303 has a function of a power button or the like. In addition, the electronic device 8300 may include buttons in addition to the operation buttons 8303.

In addition, as shown in fig. 62C, a lens 8305 may be provided between the display portion 8302 and the eyes of the user. The user can see the enlarged image on the display portion 8302 with the lens 8305, and thus the sense of realism is improved. At this time, as shown in fig. 62C, a dial 8306 for changing the position of the lens for eyepiece focusing may be provided.

For example, a display device with extremely high definition is preferably used for the display portion 8302. By using a display device with high definition as the display portion 8302, even if the lens 8305 is used for enlargement as shown in fig. 62C, an image with high sense of realism can be displayed without the pixels being seen by the user.

Fig. 62A to 62C show examples when one display portion 8302 is included. By adopting the above structure, the number of components can be reduced.

The display unit 8302 displays two images, that is, a right-eye image and a left-eye image, in parallel in the left and right areas, respectively. Thereby, a stereoscopic image using binocular parallax can be displayed.

Further, one image viewable by both eyes may be displayed on the entire area of the display unit 8302. Thus, panoramic images across both ends of the field of view can be displayed, and thus the sense of realism is improved.

Here, the electronic device 8300 preferably has a mechanism for changing the curvature of the display portion 8302 to an appropriate value according to one or more selected from the size of the head and the position of the eyes of the user, for example. For example, the user may adjust the curvature of the display portion 8302 by operating the dial 8307 for adjusting the curvature of the display portion 8302. Further, a sensor (for example, a camera, a touch sensor, and a noncontact sensor) that detects the size of the head or the position of the eyes of the user may be provided in the housing 8301, and a mechanism that adjusts the curvature of the display portion 8302 based on the detection data of the sensor may be provided.

When the lens 8305 is used, it is preferable to have a structure that synchronizes the curvature of the display portion 8302 and adjusts the position and angle of the lens 8305. The dial 8306 may have a function of adjusting the angle of the lens.

Fig. 62E and 62F show a structure of a driving portion 8308 having a curvature for controlling the display portion 8302. The driving portion 8308 is fixed to a part of the display portion 8302. The driving portion 8308 has a function of deforming the display portion 8302 by changing or moving a portion fixed to the display portion 8302.

Fig. 62E shows a schematic view of a user 8310 with a larger head wearing the frame 8301. At this time, the driving portion 8308 adjusts the shape of the display portion 8302 so that the curvature becomes smaller (the radius of curvature becomes larger).

On the other hand, fig. 62F shows a case where the user 8311 having a smaller head than the user 8310 wears the housing 8301. In addition, the user 8311 has a narrower separation between eyes than the user 8310. At this time, the driving unit 8308 adjusts the shape of the display unit 8302 so that the curvature of the display unit 8302 becomes larger (the radius of curvature becomes smaller). In fig. 62F, the position and shape of the display portion 8302 in fig. 62E are shown by broken lines.

In this way, the electronic device 8300 can provide the optimal display to the various users of the young, the old, and the man by adopting the configuration of adjusting the curvature of the display portion 8302.

Further, by changing the curvature of the display portion 8302 in accordance with the content displayed on the display portion 8302, a high sense of realism can be provided to the user. For example, the curvature of the display portion 8302 may be vibrated to express the shake. In this way, various shows can be made according to the scenes in the content, providing a new experience for the user. In this case, by interlocking with the vibration module provided in the housing 8301, a display with a higher sense of reality can be realized.

As shown in fig. 62D, the electronic device 8300 may include two display portions 8302.

Since two display portions 8302 are included, the user can see one display portion with one eye and the other display portion with the other eye. Thus, even when 3D display or the like is performed using parallax, a high-resolution video can be displayed. The display portion 8302 is curved in an arc shape about the eyes of the user. Thus, the distance from the eyes of the user to the display surface of the display unit is equal, and the user can see a more natural image. Since the eyes of the user are positioned in the normal direction of the display surface of the display unit, the influence of the brightness and chromaticity of the light from the display unit can be substantially ignored even when the brightness and chromaticity of the light change according to the angle at which the display unit is viewed, and therefore, a more realistic image can be displayed.

Fig. 63A to 63C are diagrams showing the appearance of an electronic device 8300 different from the electronic device 8300 shown in each of fig. 62A to 62D. Specifically, for example, fig. 63A to 63C differ from fig. 62A to 62D in that: comprising a fixed tool 8304a worn on the head; including a pair of lenses 8305.

The user can see the display on the display portion 8302 through the lens 8305. Preferably, the display portion 8302 is curved. Because the user can feel a high sense of realism. Further, different images displayed on different areas of the display section 8302 are seen through the lenses 8305, respectively, and three-dimensional display or the like using parallax can be performed. Further, one embodiment of the present invention is not limited to the configuration in which one display portion 8302 is provided, and two display portions 8302 may be provided so that one display portion is arranged for one eye of a user.

The display portion 8302 is preferably a display device with extremely high definition, for example. By using a display device with high definition as the display portion 8302, even if the lens 8305 is used for enlargement as shown in fig. 63C, an image with high sense of realism can be displayed without the pixels being seen by the user.

The head mount display of the electronic device according to one embodiment of the present invention may be configured as an electronic device 8200 of an eyeglass type head mount display shown in fig. 63D.

The electronic device 8200 includes a mounting portion 8201, a lens 8202, a main body 8203, a display portion 8204, and a cable 8205. Further, a battery 8206 is incorporated in the mounting portion 8201.

Power is supplied from the battery 8206 to the main body 8203 via the cable 8205. The main body 8203 has a wireless receiver, and can display received image information and the like on the display unit 8204. Further, the main body 8203 has a camera, whereby information of the eyeball or eyelid movement of the user can be utilized as an input method.

In addition, a plurality of electrodes may be provided to the mounting portion 8201 at positions contacted by the user to detect a current flowing through the electrodes according to the eye movement of the user, thereby realizing a function of recognizing the line of sight of the user. Further, the electrode may have a function of monitoring the pulse of the user based on the current flowing through the electrode. The mounting unit 8201 may have various sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor, or may have a function of displaying biological information of the user on the display unit 8204 or a function of changing an image displayed on the display unit 8204 in synchronization with the operation of the head of the user.

Fig. 64A to 64C are diagrams showing the appearance of an electronic device 8750 different from the electronic device 8300 shown in each of fig. 62A to 62D and fig. 63A to 63C and the electronic device 8200 shown in fig. 63D.

Fig. 64A is a perspective view showing the front, top, and left sides of the electronic device 8750, and fig. 64B and 64C are perspective views showing the back, bottom, and right sides of the electronic device 8750.

The electronic device 8750 includes a pair of display devices 8751, a housing 8752, a pair of mounting portions 8754, a buffer member 8755, a pair of lenses 8756, and the like. The pair of display devices 8751 are provided at positions where the inside of the housing 8752 can be seen through the lens 8756.

Here, one of the pair of display devices 8751 corresponds to, for example, the display device DSP0 shown in fig. 1. Although not shown, the electronic device 8750 shown in fig. 64A to 64C includes an electronic component (for example, the peripheral circuit PRPH described in embodiment 3) having the processing unit described in the above embodiment. Further, although not illustrated, the electronic device 8750 illustrated in fig. 64A to 64C includes a camera. The camera can capture the eyes of the user and the vicinity thereof. Although not shown, the electronic device 8750 shown in fig. 64A to 64C includes a motion detection unit, an audio device, a control unit, a communication unit, and a battery in the housing 8752.

The electronic device 8750 is an electronic device for VR. A user wearing the electronic device 8750 can see an image displayed on the display device 8751 through the lens 8756. Further, by causing the pair of display devices 8751 to display different images, three-dimensional display using parallax can be performed.

The back surface side of the housing 8752 is provided with an input terminal 8757 and an output terminal 8758. A cable that supplies an image signal from an image output apparatus or the like or power for charging a battery provided in the housing 8752 may be connected to the input terminal 8757. The output terminal 8758 is used as a sound output terminal, for example, and can be connected to headphones or earphones.

The housing 8752 preferably has a mechanism in which the left and right positions of the lens 8756 and the display device 8751 can be adjusted so that the lens 8756 and the display device 8751 are positioned at the most appropriate positions according to the position of the eyes of the user. In addition, it is also preferable to have a mechanism in which the focus is adjusted by changing the distance between the lens 8756 and the display device 8751.

By using the camera, the display device 8751, and the electronic component, the electronic device 8750 can estimate the state of the user of the electronic device 8750 and display information on the estimated state of the user on the display device 8751. Or information about the state of a user of an electronic device connected to the electronic device 8750 through a network may be displayed on the display device 8751.

Cushioning member 8755 is the portion that contacts the user's face (e.g., forehead and cheek). By the buffer member 8755 being closely adhered to the face of the user, light leakage can be prevented and the immersion can be further improved. The cushioning member 8755 preferably uses a soft material to seal against the face of the user when the electronic device 8750 is mounted on the user. For example, rubber, silicone rubber, polyurethane, sponge, or the like can be used. In addition, when a cloth, leather (for example, natural leather or synthetic leather) or the like is used as the cushioning member 8755 to cover the surface of the sponge, a gap is not easily generated between the face of the user and the cushioning member 8755, and light leakage can be appropriately prevented. In addition, when such a material is used, it is preferable not only to make the user feel skin friendly, but also to prevent the user from feeling cold when it is put on in a colder season or the like. When the buffer member 8755, the mounting portion 8754, or other members that contact the skin of the user are detachably structured, cleaning and exchange are easy, which is preferable.

The electronic device of the present embodiment may further include an earphone 8754a. The earphone 8754a includes a communication unit (not shown) and has a function of performing wireless communication. The earphone 8754a may output sound data by using a wireless communication function. In addition, the headphones 8754a may also have a vibration mechanism that is used as a bone conduction headphone.

In addition, as in the earphone 8754B shown in fig. 64C, the earphone 8754A may be directly connected to the mount 8754 or connected by a wire. The earphone 8754B and the mount 8754 may include a magnet. Accordingly, the earphone 8754B can be fixed to the mounting portion 8754 by magnetic force and can be easily accommodated, which is preferable.

The headphones 8754a can also include a sensor portion. The sensor unit can be used to estimate the state of the user of the electronic device.

The electronic device according to one embodiment of the present invention may further include one or more selected from the group consisting of an antenna, a battery, a camera, a speaker, a microphone, a touch sensor, and an operation button, in addition to any one of the above configuration examples.

The electronic device according to one embodiment of the present invention may include a secondary battery, and the secondary battery may be preferably charged by noncontact power transmission.

Examples of the secondary battery include lithium ion secondary batteries (for example, lithium polymer batteries (lithium ion polymer batteries) using gel-like electrolytes), nickel hydrogen batteries, nickel cadmium batteries, organic radical batteries, lead storage batteries, air secondary batteries, nickel zinc batteries, and silver zinc batteries.

The electronic device according to an embodiment of the present invention may include an antenna. By receiving the signal from the antenna, an image, information, and the like can be displayed on the display unit. Further, when the electronic device includes an antenna and a secondary battery, the antenna may be used for noncontact power transmission.

An image having a resolution of, for example, 4K2K, 8K4K, 16K8K or higher can be displayed on the display portion of the electronic device according to one embodiment of the present invention.

Embodiment 9

In this embodiment mode, an electronic device including a display device manufactured by one embodiment mode of the present invention will be described.

The electronic device illustrated below includes a display device according to one embodiment of the present invention in a display portion. Therefore, the electronic device shown below is an electronic device that can realize high definition.

One embodiment of the present invention includes a display device and one or more selected from an antenna, a battery, a housing, a camera, a speaker, a microphone, a touch sensor, and an operation button.

As the secondary battery, for example, the description of the secondary battery described in embodiment 8 can be referred to.

The electronic device according to an embodiment of the present invention may include an antenna. For example, the description of the antenna described in embodiment 8 can be referred to as an antenna.

Examples of the electronic device include electronic devices having a relatively large screen, such as a television set, a notebook personal computer, a display device, a digital signage, a pachinko machine, and a game machine. Examples of the electronic device include a digital camera, a digital video camera, a digital photo frame, a mobile phone, a portable game machine, a portable information terminal, and a sound reproducing device.

The electronic device according to one embodiment of the present invention can be assembled along a plane or a curved surface of an inner wall or an outer wall of a building such as a house or a high building. The electronic device may be assembled along a plane or a curved surface of an interior or exterior of an automobile or the like.

Mobile telephone set

The information terminal 5500 shown in fig. 65A is a mobile phone (smart phone) which is one of information terminals. The information terminal 5500 includes a housing 5510 and a display portion 5511, and the display portion 5511 includes a touch panel as an input interface and buttons are provided on the housing 5510.

Wearable terminal

Fig. 65B is an external view of an information terminal 5900 showing an example of a wearable terminal. The information terminal 5900 includes a housing 5901, a display portion 5902, an operation button 5903, a crown 5904, and a band 5905.

[ Information terminal ]

Fig. 65C shows a notebook information terminal 5300. As an example, in the notebook information terminal 5300 shown in fig. 65C, the housing 5330a has a display portion 5331, and the housing 5330b has a keyboard portion 5350.

Note that, in the above examples, fig. 65A to 65C show a smart phone, a wearable terminal, and a notebook information terminal as examples of electronic devices, but may be applied to information terminals other than a smart phone, a wearable terminal, and a notebook information terminal. Examples of information terminals other than smart phones, wearable terminals, and notebook-type information terminals include PDAs (Personal DIGITAL ASSISTANT) and desktop information terminals and workstations.

[ Camera ]

Fig. 65D is an external view of a camera 8000 mounted with a viewfinder 8100.

The camera 8000 includes a housing 8001, a display portion 8002, operation buttons 8003, and shutter buttons 8004. Further, a detachable lens 8006 is attached to the camera 8000.

In the camera 8000, the lens 8006 and the frame body may also be formed as one body.

The camera 8000 can perform shooting by pressing the shutter button 8004 or touching the display portion 8002 serving as a touch panel.

The housing 8001 includes an interposer having electrodes, and may be connected to, for example, a flash device in addition to the viewfinder 8100.

The viewfinder 8100 includes a housing 8101, a display portion 8102, and buttons 8103.

The housing 8101 is attached to the camera 8000 by an embedder using the embedder to be embedded in the camera 8000. The viewfinder 8100 may display an image or the like received from the camera 8000 on the display portion 8102.

The button 8103 is used as a power button.

The display device according to one embodiment of the present invention can be used for the display portion 8002 of the camera 8000 and the display portion 8102 of the viewfinder 8100. A viewfinder may be incorporated in the camera 8000.

[ Game machine ]

Fig. 65E is an external view of the portable game machine 5200 showing an example of the game machine. The portable game machine 5200 includes a housing 5201, a display portion 5202, and a button 5203.

The video of the portable game machine 5200 can be output from a display device such as a television device, a personal computer display, a game display, or a head mount display.

By using the display device described in the above embodiment for the portable game machine 5200, the portable game machine 5200 with low power consumption can be realized. Further, by virtue of low power consumption, heat generation from the circuit can be reduced, whereby influence on the circuit itself, peripheral circuits, and modules due to heat generation can be reduced.

In fig. 65E, a portable game machine is shown as an example of a game machine, but the electronic apparatus according to one embodiment of the present invention is not limited to this. Examples of the electronic device according to one embodiment of the present invention include a stationary game machine, a arcade game machine installed in an amusement facility (for example, a game center, an amusement park, etc.), and a ball pitching machine for ball striking practice installed in a sports facility.

Television apparatus

Fig. 65F is a perspective view showing a television apparatus. The television device 9000 includes a housing 9002, a display portion 9001, a speaker 9003, an operation key 9005 (including a power switch or an operation switch, for example), a connection terminal 9006, and a sensor 9007 (the sensor has a function of measuring force, displacement, position, speed, acceleration, angular velocity, rotation number, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, an electric field, current, voltage, electric power, radiation, flow, humidity, inclination, vibration, smell, or infrared ray, or a function of detecting or sensing smell or light (including visible light or invisible light (for example, infrared ray or ultraviolet ray, for example)). The storage device according to one embodiment of the present invention can be incorporated in a television device. The display portion 9001, which is 50 inches or more or 100 inches or more, for example, can be incorporated into a television set.

By using the display device described in the above embodiment modes for the television device 9000, the television device 9000 with low power consumption can be realized. Further, by virtue of low power consumption, heat generation from the circuit can be reduced, whereby influence on the circuit itself, peripheral circuits, and modules due to heat generation can be reduced.

[ Moving object ]

The display device according to one embodiment of the present invention is applicable to the vicinity of a driver's seat of an automobile as a moving body.

Fig. 65G is a view showing the vicinity of the front windshield in the automobile room. Fig. 65G shows a display panel 5701 mounted on a dashboard, a display panel 5702, a display panel 5703, and a display panel 5704 mounted on a pillar.

The display panels 5701 to 5703 may display one or more of navigation information, a speedometer, a tachometer, a travel distance, an amount of fuel to be added, a gear state, and a setting of an air conditioner. In addition, the user can appropriately change the display content and layout displayed on the display panel according to the preference, and the designability can be improved. The display panels 5701 to 5703 can also be used as illumination devices.

By displaying an image captured by an imaging unit provided in the vehicle body on the display panel 5704, a view (dead angle) blocked by the pillar can be supplemented. That is, by displaying an image captured by an imaging unit provided outside the automobile, a dead angle can be supplemented, and safety can be improved. In addition, by displaying the image of the part which is not seen in the supplementary view, the safety can be confirmed more naturally and more comfortably. The display panel 5704 may be used as an illumination device.

The display device according to one embodiment of the present invention can be applied to, for example, display panels 5701 to 5704.

Although an automobile is described as an example of the moving body in the above example, the moving body is not limited to an automobile. For example, as a moving body, an electric car, a monorail, a ship, a flying object (for example, a helicopter, an unmanned plane (unmanned plane), an airplane, a rocket), or the like can be given, and the display body device according to one embodiment of the present invention can be applied to these moving bodies.

Digital signage

Fig. 65H shows an example of a digital signage that can be wall-hung. Fig. 65H shows an example of a digital signage 6200 hanging a wall 6201. The display device according to one embodiment of the present invention can be applied to, for example, a display portion of a digital signage 6200. In addition, the digital signage 6200 may be provided with an interface or the like of a touch panel or the like.

Note that, the electronic devices that can be hung on a wall are shown above as one example of the digital signage, but the kind of the digital signage is not limited thereto. For example, as the digital signage, there may be mentioned: a digital signage mounted to the post; a digital signage placed on the floor; or a digital signage disposed on a roof or side wall of a building.

[ Description of the symbols ]

DSP: display device, DSP0: display device, DSP1A: display device, DSP1B: display device, DSP1C: display device, DSP1D: display device, DSP1DA: display device, DSP1DB: display device, DSP1E: display device, DSP1F: display device, DSP2A: display device, DSP2AA: display device, DSP2B: display device, DSP2C: display device, DSP2D: display device, DSP2DA: display device, DSP2E: display device, DSP2F: display device, DSP2G: a display device, DSP2H: display device PXAL: pixel layer, EML: layer, OSL: layer LINL: wiring layer SICL: circuit layer, LIA: region, BS: substrate, DIS: display unit, DRV: drive circuit area, ARA [1,1]: region, ARA [1,2]: region, ARA [1, q-1]: region, ARA [1, q ]: region, ARA [2,1]: region, ARA [2,2]: region, ARA [2, q-1]: region, ARA [2, q ]: region, ARA [ p-1,1]: the region, ARA [ p-1 ], 2]: region, ARA [ p-1, q-1]: region, ARA [ p-1, q ]: region, ARA [ p,1]: region, ARA [ p,2]: region, ARA [ p, q-1]: region, ARA [ p, q ]: region, ARD [1,1]: circuit area, ARD [1,2]: circuit area, ARD [1, q-1]: circuit area, ARD [1, q ]: circuit area, ARD [2,1]: circuit area, ARD [2,2]: circuit area, ARD [2, q-1]: circuit area, ARD [2, q ]: a circuit region, ARD [ p-1,1]: circuit area, ARD [ p-1,2]: circuit area, ARD [ p-1, q-1]: circuit area, ARD [ p-1, q ]: circuit area, ARD [ p,1]: circuit area, ARD [ p,2]: circuit area, ARD [ p, q-1]: circuit area, ARD [ p, q ]: circuit area, PRPH: peripheral circuit, SD: drive circuit, SDS: circuit, DMS: distribution circuit, GD: drive circuit, GDS: circuit, DMG: distribution circuit, CTR: control part, MD: storage device, PG: a voltage generating circuit, GPS: image processing unit, CKS: clock signal generation circuit, TMC: timing controller, BW: bus, CLM: column driving circuit, RWD: row driving circuit, CD: circuit, CD [1]: circuit, CD [ j ]: circuit, CD [ n ]: circuit, ALP: pixel array, PX: pixels, PX [1,1]: pixels, PX [ m,1]: pixels, PX [1, n ]: pixels, PX [ m, n ]: pixels, PX [ i, j ]: pixel, M1: transistor, M2: transistor, M3: transistor, M5: transistor, M6: transistor, M11: a transistor(s), M12: transistor, SW1: switch, SW3: switch, SW4: switch, SW5: switch, SW6: switch, SW7: switch, SW8: switch, SW11: switch, SW11I: switch, SW12: switch, SW12I: switch, SW13: switch, SW13I: switch, C1: capacitor, C2: capacitor, C3: capacitor, C4: capacitor, LD: light emitting device, INV: inverter circuit, N1: node, N2: node, N3: node, NB: node, SL: wiring, SL [1]: wiring, SL [ j ]: wiring line, SL [ n ]: wiring, GL: wiring, GL [1]: wiring, GL [ i ]: wiring, GL [ m ]: wiring, GL1: wiring, GL3: wiring, GL4: wiring, GL5: wiring, GL6: wiring, GL7: wiring, GL11: wiring, GL12: wiring, GL13: wiring, SWL11: wiring, SWL12: wiring, SWL13: wiring, VE0: wiring, VE1: wiring, VE2: wiring, VE3: wiring, VE4: wiring, VE5: wiring, VE6: wiring, G1: wiring, G2: wiring, ANO: wiring line, VCOM: wiring, V0: wiring, GEM: conductor, SDMB: electrical conductor, SDMT: conductor, PLG: conductor, EC: conductor, BGM: conductor, T11: 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insulator, 580: insulator, 581: insulator, 592: an insulator (insulator), 594: insulator, 596: conductor, 598: insulator, 599: insulator, 600: capacitor, 761: a lower electrode 762: upper electrode, 763: EL layer, 764: layer, 771: light emitting layer, 771a: light emitting layer, 771b: light emitting layer, 771c: a light emitting layer, 772: a light emitting layer 772a: light emitting layer 772b: light emitting layer 772c: light emitting layer, 773: luminescent layer, 780: layer, 780a: layer, 780b: layer, 780c: layer, 781: layer, 782: layer, 785: charge generation layer, 785a-b: a charge generation layer, 785b-c: charge generation layer 790: layer 790a: layer 790b: layer 790c: layer, 791: layer, 792: layer, 1000: display device, 1000A: display device, 1000B1: display device, 1000B2: display device, 1000B3: display device, 1000B4: display device, 1000C: display device, 1000D: display device, 1000E: display device, 1000F: display device, 1000G: display device, 1000H: display device, 1000I: display device 1280: a display module, 1281: display unit 1290: FPC, 1282: circuit part, 1283: pixel circuit unit, 1283a: pixel circuit, 1284: pixel portion 1284a: pixel, 1285: terminal portion 1286: wiring portion 1291: substrate, 1292: substrate, 1430a: light emitting device, 1430b: light emitting device, 1430c: light emitting device, 5200: portable game machine, 5201: frame body, 5202: display unit, 5203: button, 5300: notebook information terminal, 5330a: frame 5330b: a frame body, 5331: display portion, 5350: keyboard portion, 5500: information terminal, 5510: frame body, 5511: display part, 5701: display panel, 5702: display panel, 5703: display panel, 5704: display panel, 5900: information terminal, 5901: frame body, 5902: display unit, 5903: operation button, 5904: crown, 5905: watchband, 6200: digital signage, 6201: wall, 8000: camera, 8001: frame body, 8002: display unit, 8003: operation button, 8004: shutter button, 8006: lens, 8100: viewfinder, 8101: frame body, 8102: display unit, 8103: button, 8200: electronic device, 8201: wearing part, 8202: lens, 8203: main body, 8204: display unit, 8205: cable, 8206: battery, 8300: electronic device, 8301: frame body, 8302: display unit, 8303: operation button, 8304: fixing tool, 8304a: fixing tool, 8305: lens, 8310: user, 8311: user, 8750: electronic device, 8751: a display device, 8752: frame body 8754: wearing part 8754a: earphone, 8754B: earphone, 8755: cushioning member, 8756: lens, 8757: input terminal, 8758: output terminal, 9000: television apparatus 9001: display unit, 9002: frame body, 9003: speaker, 9005: operation key, 9006: connection terminal, 9007: sensor for detecting a position of a body

Claims

1. A display device, comprising:

A pixel; and

The electrical circuitry is configured to provide a voltage across the circuit,

Wherein the pixel comprises a light emitting device, a driving transistor, a first switch, a second switch, a third switch, a fourth switch and a first capacitor,

The circuit includes a fifth switch, a sixth switch and a second capacitor,

The gate of the driving transistor is electrically connected to the first terminal of the first switch, the first terminal of the second switch and the first terminal of the first capacitor,

One of a source and a drain of the driving transistor is electrically connected to the second terminal of the first capacitor, the first terminal of the fourth switch and the anode of the light emitting device,

The other of the source and the drain of the drive transistor is electrically connected to the second terminal of the second switch and the first terminal of the third switch,

A second terminal of the first switch is electrically connected to a first terminal of the second capacitor,

And a first terminal of the fifth switch is electrically connected to a first terminal of the sixth switch and a second terminal of the second capacitor.

2. The display device according to claim 1,

Wherein the first switch comprises an n-channel first transistor,

The second switch comprises an n-channel second transistor,

The third switch includes an n-channel third transistor,

The fourth switch includes an n-channel fourth transistor,

One of a source and a drain of the first transistor is electrically connected to a first terminal of the first switch,

The other of the source and the drain of the first transistor is electrically connected to the second terminal of the first switch,

One of the source and the drain of the second transistor is electrically connected to the first terminal of the second switch,

The other of the source and the drain of the second transistor is electrically connected to the second terminal of the second switch,

One of a source and a drain of the third transistor is electrically connected to a first terminal of the third switch,

The other of the source and the drain of the third transistor is electrically connected to the second terminal of the third switch,

One of a source and a drain of the fourth transistor is electrically connected to a first terminal of the fourth switch,

And the other of the source and the drain of the fourth transistor is electrically connected to the second terminal of the fourth switch.

3. A display device, comprising:

A pixel; and

The electrical circuitry is configured to provide a voltage across the circuit,

Wherein the pixel comprises a light emitting device, a driving transistor, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a first capacitor and a third capacitor,

The circuit includes a sixth switch, a seventh switch, an eighth switch, and a second capacitor,

The drive transistor includes a first gate and a second gate,

The first gate of the driving transistor is electrically connected to the first terminal of the first switch, the first terminal of the second switch, and the first terminal of the first capacitor,

One of a source and a drain of the driving transistor is electrically connected to the second terminal of the first capacitor, the first terminal of the third capacitor, the second terminal of the second switch, the first terminal of the third switch, and the first terminal of the fourth switch,

A second gate of the driving transistor is electrically connected to a second terminal of the third capacitor and a first terminal of the fifth switch,

A second terminal of the third switch is electrically connected to an anode of the light emitting device,

A second terminal of the first switch is electrically connected to a first terminal of the second capacitor and a first terminal of the eighth switch,

And a first terminal of the sixth switch is electrically connected to a first terminal of the seventh switch and a second terminal of the second capacitor.

4. A display device according to claim 3,

Wherein the first switch comprises an n-channel first transistor,

The second switch comprises an n-channel second transistor,

The third switch includes an n-channel third transistor,

The fourth switch includes an n-channel fourth transistor,

The fifth switch comprises an n-channel fifth transistor,

The other of the source and the drain of the fourth transistor is electrically connected to the second terminal of the fourth switch,

One of a source and a drain of the fifth transistor is electrically connected to a first terminal of the fifth switch,

And the other of the source and the drain of the fifth transistor is electrically connected to the second terminal of the fifth switch.

5. A display device, comprising:

A pixel; and

The electrical circuitry is configured to provide a voltage across the circuit,

Wherein the pixel comprises a light emitting device, a driving transistor, a first switch, a third switch, a fourth switch, a fifth switch, a first capacitor and a third capacitor,

The drive transistor includes a first gate and a second gate,

A first gate of the drive transistor is electrically connected to a first terminal of the first switch and a first terminal of the first capacitor,

One of a source and a drain of the driving transistor is electrically connected to the second terminal of the first capacitor, the first terminal of the third switch, and the first terminal of the fourth switch,

6. The display device according to claim 5,

Wherein the first switch comprises an n-channel first transistor,

The third switch includes an n-channel third transistor,

The fourth switch includes an n-channel fourth transistor,

The fifth switch comprises an n-channel fifth transistor,

7. A display device, comprising:

A pixel; and

The electrical circuitry is configured to provide a voltage across the circuit,

Wherein the pixel comprises a light emitting device, a driving transistor, a first switch, a second switch, a third switch, a fourth switch, a first capacitor and a second capacitor,

The circuit includes a fifth switch and a sixth switch,

8. The display device according to claim 7,

Wherein the first switch comprises an n-channel first transistor,

The second switch comprises an n-channel second transistor,

The third switch includes an n-channel third transistor,

The fourth switch includes an n-channel fourth transistor,

9. A display device, comprising:

A pixel; and

The electrical circuitry is configured to provide a voltage across the circuit,

The circuit includes a fifth switch and a sixth switch,

The gate of the drive transistor is electrically connected to the first terminal of the second switch, the first terminal of the first capacitor and the first terminal of the second capacitor,

A second terminal of the second capacitor is electrically connected to a first terminal of the first switch,

And a first terminal of the fifth switch is electrically connected to the first terminal of the sixth switch and the second terminal of the first switch.

10. The display device according to claim 9,

Wherein the first switch comprises an n-channel first transistor,

The second switch comprises an n-channel second transistor,

The third switch includes an n-channel third transistor,

The fourth switch includes an n-channel fourth transistor,

11. A display device, comprising:

A pixel; and

The electrical circuitry is configured to provide a voltage across the circuit,

Wherein the pixel comprises a light emitting device, a driving transistor, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, an eighth switch, a first capacitor, a second capacitor and a third capacitor,

The circuit includes a sixth switch and a seventh switch,

The drive transistor includes a first gate and a second gate,

The first gate of the driving transistor is electrically connected to the first terminal of the first switch, the first terminal of the second switch, the first terminal of the eighth switch, and the first terminal of the first capacitor,

And a second terminal of the second capacitor is electrically connected to the first terminal of the sixth switch and the first terminal of the seventh switch.

12. The display device according to claim 11,

Wherein the first switch comprises an n-channel first transistor,

The second switch comprises an n-channel second transistor,

The third switch includes an n-channel third transistor,

The fourth switch includes an n-channel fourth transistor,

The fifth switch comprises an n-channel fifth transistor,

13. A display device, comprising:

A pixel; and

The electrical circuitry is configured to provide a voltage across the circuit,

The circuit includes a sixth switch and a seventh switch,

The drive transistor includes a first gate and a second gate,

The first gate of the driving transistor is electrically connected to the first terminal of the second switch, the first terminal of the eighth switch, the first terminal of the first capacitor and the first terminal of the second capacitor,

And the second terminal of the first switch is electrically connected with the first terminal of the sixth switch and the first terminal of the seventh switch.

14. The display device according to claim 13,

Wherein the first switch comprises an n-channel first transistor,

The second switch comprises an n-channel second transistor,

The third switch includes an n-channel third transistor,

The fourth switch includes an n-channel fourth transistor,

The fifth switch comprises an n-channel fifth transistor,

15. The display device according to any one of claims 1 to 14,

Wherein the light emitting device comprises an organic EL device.

16. An electronic device, comprising:

the display device of claim 15; and

A frame body.