CN118158023A - Bus module signal acquisition control method, device, equipment and storage medium - Google Patents
Bus module signal acquisition control method, device, equipment and storage medium Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
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- H04L12/40013—Details regarding a bus controller
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- H—ELECTRICITY
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Abstract
The invention discloses a bus module signal acquisition control method, a device, equipment and a storage medium. The invention generates a reference trigger signal through a control bus module; generating trigger signals for controlling the operation of the corresponding sensors according to the reference trigger signals and the operating frequencies of the sensors; triggering a plurality of corresponding sensors to work according to the trigger signals, and acquiring time stamps of the corresponding trigger moments of the plurality of sensors; determining trigger delay time of a plurality of sensors according to the time stamps; respectively carrying out delay compensation on a plurality of sensors according to the trigger delay time; respectively marking the time stamps corresponding to the plurality of sensors; and correspondingly splicing the acquired data of the plurality of sensors according to the timestamp marking result, and transmitting the acquired data to a host control system. The invention can realize the consistency of signal triggering in the data acquisition function of the bus module, and can perform centralized processing on the acquired data of a plurality of sensor devices, thereby ensuring the reliable control of output load.
Description
Technical Field
The present invention relates to the field of bus module control technologies, and in particular, to a method, an apparatus, a device, and a storage medium for controlling signal acquisition of a bus module.
Background
Bus modules are widely used in industrial automation systems. The bus module is provided with at least one communication network port, and the communication network port is connected to the host control system for data transmission. And the bus module is also provided with an IO wiring terminal group, and the IO wiring terminal group is connected to industrial equipment such as a reed relay, a temperature sensor, a flow sensor, a pressure sensor, a liquid level transmitter and the like through a connecting cable so as to perform data acquisition on the industrial equipment or a remote control function on the industrial equipment.
In some special application scenarios, multi-view measurement needs to be performed on the measured object, at this time, the IO terminal group of the bus module is connected with a plurality of sensor devices, such as laser sensors, and the bus module transmits data collected by the plurality of sensors to the host control system for centralized processing. To avoid the lack of clock delay or accuracy of each sensor and the adverse effects of information interaction, it is often necessary to ensure signal triggering synchronicity between the sensor devices. In addition, in order to realize accurate control of the output load, collected data of a plurality of sensor devices need to be processed in a centralized manner and then uploaded to a host control system. Therefore, the invention provides a reliable bus module signal acquisition control method, which is a problem to be solved by those skilled in the art.
Disclosure of Invention
The embodiment of the invention provides a bus module signal acquisition control method, device, equipment and storage medium aiming at the defects, which are used for solving the problems existing in the prior art.
In order to solve the above technical problems, an embodiment of the present invention provides a bus module signal acquisition control method, including:
Taking a system clock in the bus module as a reference clock, and controlling a second pulse calibration module in the bus module to generate a reference trigger signal;
generating trigger signals for controlling the operation of a plurality of sensors according to the reference trigger signals and the operating frequencies of the sensors;
Triggering a plurality of corresponding sensors to work according to the triggering signals, and acquiring time stamps of the corresponding triggering moments of the plurality of sensors;
determining trigger delay time of a plurality of sensors according to the time stamps;
Respectively carrying out delay compensation on a plurality of sensors according to the trigger delay time;
marking the time stamps corresponding to the plurality of sensors respectively;
Correspondingly splicing the acquired data of the plurality of sensors according to the timestamp marking result;
transmitting the acquired data of the plurality of sensors after the splicing processing to a host control system;
The step of controlling the second pulse calibration module in the bus module to generate a reference trigger signal by taking the system clock in the bus module as a reference clock comprises the following steps:
setting a standard trigger frequency and a standard counter in the bus module;
controlling the frequency of outputting the reference trigger signal through the standard trigger frequency;
And taking a second pulse clock as a reference, and performing half-period delay control on the output of the reference trigger signal through the standard counter.
Preferably, before the transmitting the collected data of the plurality of sensors after the splicing processing to the host control system, the method includes:
transmitting the acquired data of the plurality of sensors after the splicing processing to first-in first-out data buffers corresponding to the sensors;
converting the parallel acquired data into serial acquired data;
And sequentially uploading the serial acquired data in each first-in first-out data buffer to the host control system according to a preset priority order.
Preferably, the performing the stitching processing on the collected data of the plurality of sensors according to the timestamp marking result includes:
taking a coordinate system in which the first sensor is positioned as a reference coordinate system;
Obtaining a first conversion relation from the reference coordinate system to a preset reference coordinate system through calibration;
obtaining a second conversion relation from a coordinate system where a second sensor is located to the preset reference coordinate system through calibration;
According to the second conversion relation, correspondingly converting the data on the coordinate system where the second sensor is located to the preset reference coordinate system to obtain first intermediate coordinate system data;
And correspondingly transforming the first intermediate coordinate system data to the reference coordinate system according to the first transformation relation so as to realize data splicing.
Preferably, the performing the stitching processing on the collected data of the plurality of sensors according to the timestamp marking result includes:
Obtaining a space coordinate transformation relation through pairwise calibration;
carrying out space transformation on data under the own coordinate system of each sensor;
and converting the data of each sensor in the own coordinate system into the same coordinate system so as to realize the splicing of the data of multiple sensors.
Preferably, before the triggering of the corresponding plurality of sensors according to the trigger signal to obtain the time stamps of the corresponding triggering moments of the plurality of sensors, the method further includes:
and filtering the pulse waveform of the trigger signal.
Preferably, signal parameters of pulse waveforms of the trigger signals are monitored in real time; wherein the signal parameters include level, frequency, phase, bandwidth and signal strength information;
According to the signal parameters, identifying noise interference of pulse waveforms of the trigger signals;
And filtering the pulse waveforms of the trigger signals according to the noise interference.
Preferably, the filtering the pulse waveform of the trigger signal further includes:
Monitoring the change of the communication environment in real time;
And adjusting filtering parameters in real time according to the change of the communication environment.
In order to solve the above technical problems, an embodiment of the present invention provides an automatic splicing control device for a spliced screen, where the device includes:
The reference trigger module is used for controlling the second pulse calibration module in the bus module to generate a reference trigger signal by taking the system clock in the bus module as a reference clock;
The trigger signal generation module is used for generating trigger signals for controlling the operation of the corresponding sensors according to the reference trigger signals and the operating frequencies of the sensors;
The time stamp determining module is used for triggering a plurality of corresponding sensors to work according to the trigger signals and obtaining time stamps of the plurality of corresponding trigger moments of the sensors;
The delay calculation module is used for determining trigger delay time of the plurality of sensors according to the time stamps;
the delay compensation module is used for respectively carrying out delay compensation on the plurality of sensors according to the trigger delay time;
The marking module is used for marking the time stamps corresponding to the plurality of sensors respectively;
the data splicing module is used for correspondingly splicing the acquired data of the plurality of sensors according to the timestamp marking result;
the transmission module is used for transmitting the acquired data of the plurality of sensors after the splicing processing to the host control system;
Wherein, the benchmark trigger module includes:
The setting unit is used for setting standard trigger frequency and standard counter in the bus module;
the control unit is used for controlling and outputting the frequency of the reference trigger signal through the standard trigger frequency;
and the delay control unit is used for carrying out half-period delay control on the output of the reference trigger signal by taking the second pulse clock as a reference through the standard counter.
In order to solve the above technical problems, an embodiment of the present invention provides an automatic splicing control device for a spliced screen, including: at least one processor, at least one memory and computer program instructions stored in the memory, which when executed by the processor, implement the method as in the first aspect of the embodiments described above.
To solve the above technical problem, an embodiment of the present invention provides a storage medium having stored thereon computer program instructions which, when executed by a processor, implement a method as in the first aspect of the above embodiments.
In summary, the embodiment of the invention provides a method, a device, equipment and a storage medium for controlling signal acquisition of a bus module. The invention takes the system clock in the bus module as the reference clock to control the bus module to generate the reference trigger signal; generating trigger signals for controlling the operation of a plurality of sensors according to the reference trigger signals and the operating frequencies of the sensors; triggering a plurality of corresponding sensors to work according to the triggering signals, and acquiring time stamps of the corresponding triggering moments of the plurality of sensors; determining trigger delay time of a plurality of sensors according to the time stamps; respectively carrying out delay compensation on a plurality of sensors according to the trigger delay time; marking the time stamps corresponding to the plurality of sensors respectively; and correspondingly splicing the acquired data of the plurality of sensors according to the timestamp marking result, and transmitting the acquired data to a host control system. Therefore, the invention can realize the consistency of signal triggering in the data acquisition function of the bus module, and can perform centralized processing on the acquired data of a plurality of sensor devices, thereby ensuring the reliable control of the output load.
Drawings
In order to more clearly illustrate the technical solution of the embodiments of the present invention, the drawings that are needed to be used in the embodiments of the present invention will be briefly described, and other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a flow chart of a bus module signal acquisition control method according to an embodiment of the invention.
Fig. 2 is a timing diagram of a reference trigger signal and a first sensor trigger signal according to an embodiment of the present invention.
Fig. 3 is a timing diagram of a reference trigger signal and a second sensor trigger signal according to an embodiment of the present invention.
Fig. 4 is a flow chart of controlling the bus module to generate the reference trigger signal by using the system clock inside the bus module as the reference clock according to an embodiment of the present invention.
Fig. 5 is a timing diagram of delay control of a reference trigger signal according to an embodiment of the present invention.
Fig. 6 is a schematic flow chart before transmitting collected data of a plurality of sensors after the splicing process to a host control system according to an embodiment of the present invention.
Fig. 7 is a flow chart of a splicing process for corresponding collected data of a plurality of sensors according to a time stamp marking result in an embodiment of the present invention.
Fig. 8 is a flow chart of another embodiment of the invention for performing a splicing process on the collected data of a plurality of sensors according to the timestamp marking result.
Fig. 9 is a schematic structural diagram of an automatic splicing control device for a spliced screen according to an embodiment of the present invention.
Fig. 10 is a schematic structural diagram of an automatic splicing control device for a spliced screen according to an embodiment of the present invention.
Detailed Description
Features and exemplary embodiments of various aspects of the present invention will be described in detail below, and in order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely configured to illustrate the invention and are not configured to limit the invention. It will be apparent to one skilled in the art that the present invention may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the invention by showing examples of the invention.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises an element.
Referring to fig. 1, fig. 1 is a schematic flow chart of a bus module signal acquisition control method provided by the application, the method includes the following steps:
s1, taking a system clock in the bus module as a reference clock, and controlling a second pulse calibration module in the bus module to generate a reference trigger signal.
Specifically, the bus module of the present application uses FPGA (Field-Programmable GATE ARRAY, i.e., field-Programmable gate array, which is a product of further development based on PAL, GAL, CPLD, etc.) as a core for system control. In this embodiment, the reference trigger signal is generated with the system clock of the FPGA as the reference clock.
S2, generating trigger signals for controlling the corresponding sensors to work according to the reference trigger signals and the working frequencies of the sensors.
Specifically, in the present embodiment, the first trigger signal for controlling the operation of the first sensor is generated according to the reference trigger signal and the operating frequency of the first sensor.
Specifically, in the present embodiment, the second trigger signal for controlling the operation of the second sensor is generated according to the reference trigger signal and the operating frequency of the second sensor. It is understood that one sensor needs to be controlled corresponding to one trigger signal, and the number of the sensors is set according to the needs of the user, which is not particularly limited herein.
Specifically, the operating frequency of each sensor is different, and thus the frequency of the trigger signal controlling the operation of each sensor is also different. In this embodiment, after the initial trigger signal of the corresponding sensor is generated by the reference trigger signal, pulse stretching processing is further required to be performed on the trigger signal, so as to obtain the corresponding sensor trigger signal. It is understood that the rising edges of the pulses of the sensor trigger signal after the pulse stretching process and the sensor trigger signal before the pulse stretching process are in an aligned state, and the falling edges of the pulses of the trigger signals for the operation of the plurality of sensors may be set according to the operation characteristics of the sensors, which is not particularly limited herein.
And S3, triggering a plurality of corresponding sensors to work according to the trigger signals, and acquiring time stamps of the corresponding trigger moments of the plurality of sensors.
Referring to fig. 2, fig. 2 is a timing chart of a reference trigger signal and a first sensor trigger signal according to the present application.
Specifically, the bus module generates a reference trigger signal of 5HZ with reference to the system clock. In combination with the working frequency of the first sensor, the system generates a first trigger signal of 5HZ, wherein the first trigger signal is a single-period high-level signal, and the signal period is 200ms. Since the signal triggering the first sensor to operate has a pulse width limitation, the pulse width is determined by the characteristics of the first sensor, so that the pulse stretching needs to be performed on the first trigger signal with a single period. It can be understood that the rising edges of the first trigger signal and the first sensor trigger signal are in an aligned state, so that the nanosecond time stamp of the first sensor trigger moment can be accurately obtained, and when the rising edge of the first sensor trigger signal is generated, the count value of the system counter is the nanosecond time stamp of the first sensor trigger moment.
Referring to fig. 3, fig. 3 is a timing chart of a reference trigger signal and a second sensor trigger signal provided by the present application.
Specifically, the bus module generates a reference trigger signal of 200HZ with reference to the system clock. In combination with the working frequency of the first sensor, the system generates a second trigger signal of 100HZ, wherein the second trigger signal is a single-period high-level signal, and the signal period is 10ms. Since the signal triggering the second sensor to operate has a pulse width limitation, the pulse width is determined by the characteristics of the second sensor, so that the second trigger signal with a single period needs to be subjected to pulse stretching. It can be understood that the rising edges of the second trigger signal and the second sensor trigger signal must be in an aligned state, so as to accurately obtain the nanosecond timestamp of the second sensor trigger moment, and when the rising edge of the second sensor trigger signal is generated, the count value of the system counter is the nanosecond timestamp of the second sensor trigger moment.
S4, determining trigger delay time of the plurality of sensors according to the time stamps.
S4, determining trigger delay time of the plurality of sensors according to the time stamps.
Specifically, referring to fig. 3, when the rising edge of the second trigger signal is generated, the count value of the system counter is a nanosecond timestamp of the trigger time of the second sensor. The system compares the nanosecond time stamp with a preset trigger time stamp to determine the trigger delay time T of the second sensor. After determining the trigger delay time T of the second sensor, the system performs delay compensation. It can be appreciated that after the delay compensation of the trigger time of the second sensor, the rising edge of the compensated second trigger signal is advanced by a time T compared to before.
Specifically, in this embodiment, the system performs pulse stretching processing on the second trigger signal after delay compensation, so as to obtain the trigger signal timing sequence of the second sensor.
S6, marking the time stamps corresponding to the plurality of sensors respectively.
And S7, correspondingly splicing the acquired data of the plurality of sensors according to the timestamp marking result.
Specifically, in this embodiment, since the trigger signal or the trigger instruction of each sensor is based on the reference trigger signal generated by the bus module, and the nanosecond time stamp when the sensor triggers corresponds to the count value of the counter in the bus module system, the data information of each sensor is in the same time coordinate system, so that the consistency of signal triggering in the data acquisition function of the bus module can be ensured.
Specifically, as the sensors are distributed in multiple views for detecting and obtaining complete acquired data of the detected object. Therefore, on the basis that the sensors are in the same time coordinate system, the data of the multiple sensors are unified to the same data coordinate system, and the complete acquired data are obtained through splicing.
S8, transmitting the acquired data of the plurality of sensors after the splicing processing to a host control system.
Referring to fig. 4, fig. 4 is a flow chart of controlling the bus module to generate a reference trigger signal by using a system clock inside the bus module as a reference clock according to the present application.
The method for controlling the second pulse calibration module in the bus module to generate a reference trigger signal by taking the system clock in the bus module as a reference clock comprises the following steps:
s11, setting a standard trigger frequency and a standard counter in a bus module;
s12, controlling the frequency of the output reference trigger signal through the standard trigger frequency;
and S13, taking the second pulse clock as a reference, and performing half-period delay control on the output of the reference trigger signal through a standard counter.
Referring to fig. 5, fig. 5 is a timing chart of delay control of a reference trigger signal according to the present application.
Specifically, in the present embodiment, when the standard counter counts to 1 and the count flag signal is 1, the reference trigger signal is generated.
Specifically, in this embodiment, the second pulse calibration module in the bus module calibrates the second pulse signal with respect to the system clock of the bus module, and outputs a reference trigger signal.
Specifically, the GNSS timing module generates 1 second pulse signal every 1S, and the FPGA in the bus module receives and analyzes the data message of the second pulse signal to obtain the coordinated universal time at the current moment. The reference trigger signal output by the bus module delays the pulse signal by half period, the corresponding time of the half period is longer than the corresponding half period value of the pulse signal fluctuation period, and thus the output reference trigger signal avoids the influence of the pulse signal fluctuation period and can accurately and stably output the signal.
In summary, the application provides a bus module signal acquisition control method, in the scheme, a reference trigger signal is generated by controlling a bus module; generating trigger signals for controlling the operation of the corresponding sensors according to the reference trigger signals and the operating frequencies of the sensors; triggering a plurality of corresponding sensors to work according to the trigger signals, and acquiring time stamps of the corresponding trigger moments of the plurality of sensors; determining trigger delay time of a plurality of sensors according to the time stamps; respectively carrying out delay compensation on a plurality of sensors according to the trigger delay time; respectively marking the time stamps corresponding to the plurality of sensors; and correspondingly splicing the acquired data of the plurality of sensors according to the timestamp marking result, and transmitting the acquired data to a host control system. The application can realize the consistency of signal triggering in the data acquisition function of the bus module, and can perform centralized processing on the acquired data of a plurality of sensor devices, thereby ensuring the reliable control of output load. Therefore, the application can realize the consistency of signal triggering in the data acquisition function of the bus module, and can perform centralized processing on the acquired data of a plurality of sensor devices, thereby ensuring the reliable control of the output load.
Based on the above embodiments:
referring to fig. 6, fig. 6 is a schematic flow chart before transmitting the collected data of the plurality of sensors after the splicing process to the host control system.
As a preferred embodiment, before transmitting the collected data of the plurality of sensors after the splicing process to the host control system, it includes:
s711, transmitting acquired data of the plurality of sensors after the splicing processing to first-in first-out data buffers corresponding to the sensors;
S721, converting parallel acquired data into serial acquired data;
S731, sequentially uploading the serial collected data in each first-in first-out data buffer to the host control system according to a preset priority order.
Specifically, in this embodiment, the priority management unit in the bus module converts parallel data into serial data, and sequentially uploads the sensor data in each buffer area to the host control system according to a preset priority order, so that the problem of mutual preemption of parallel-to-serial conversion occurring when each sensor data is uploaded to the host control system is avoided.
Specifically, the priority order of uploading the sensor data in the present application can be adjusted by user definition according to the requirements of different functions of the system, which is not limited herein.
Referring to fig. 7, fig. 7 is a flow chart of a splicing process for corresponding collected data of a plurality of sensors according to a time stamp marking result provided by the present application.
As a preferred embodiment, the splicing processing of the acquired data of the plurality of sensors according to the timestamp marking result includes:
S71, taking a coordinate system where the first sensor is located as a reference coordinate system;
S72, obtaining a first conversion relation from a reference coordinate system to a preset reference coordinate system through calibration;
S73, obtaining a second conversion relation from a coordinate system where the second sensor is located to a preset reference coordinate system through calibration;
S74, correspondingly transforming the data on the coordinate system where the second sensor is located to a preset reference coordinate system according to the second conversion relation to obtain first intermediate coordinate system data;
And S75, correspondingly transforming the data of the first intermediate coordinate system to the reference coordinate system according to the first transformation relation so as to realize data splicing.
Specifically, in this embodiment, since the collected data point sets are located in two different sensor coordinate systems, in order to ensure the integrity of the data, the collected data of different sensors needs to be spliced.
Specifically, in this embodiment, the coordinate system O1 where the first sensor is located is first used as a reference coordinate system, the coordinate system O1 where the first sensor is located and the coordinate system O2 where the second sensor is located are obtained through calibration and are converted into a conversion relation of a preset reference coordinate system O, then the coordinate system O2 where the second sensor is located is correspondingly converted into the preset reference coordinate system O, after the first intermediate coordinate system data is obtained, the first intermediate coordinate system data is converted into the coordinate system O1 where the first sensor is located, and all acquired data can be converted into the coordinate system O1 where the first sensor is located, thereby implementing the acquisition data stitching.
Referring to fig. 8, fig. 8 is a flow chart of another splicing process for the collected data of multiple sensors according to the timestamp marking result provided by the present application.
As a preferred embodiment, the splicing processing of the acquired data of the plurality of sensors according to the timestamp marking result includes:
S741, obtaining a space coordinate transformation relation through pairwise calibration;
s751, carrying out space transformation on data under the own coordinate system of each sensor;
s761, converting the data of each sensor in the own coordinate system into the same coordinate system so as to realize the splicing of the data of multiple sensors.
Specifically, for a multi-sensor system, the spatial coordinate transformation relation is required to be acquired by performing pairwise calibration, and then the data under the coordinate system of each sensor is subjected to spatial transformation and converted into the same coordinate system, so that the multi-sensor data can be spliced. It will be appreciated that the selection and conversion manner of the actual reference coordinate system may be set according to different schemes, and is not specifically limited herein.
Specifically, a three sensor stitching system is taken as an example. The coordinate system where the first sensor is located is a coordinate system O, the coordinate system O is taken as a reference coordinate system, the coordinate system of the second sensor is O1, and the coordinate system of the second sensor is O2. Taking the second sensor as an example, the conversion relation between the coordinate system O1 of the second sensor and the coordinate system O of the first sensor relative to the reference coordinate system O1O is obtained through calibration, and the coordinate system O1 of the second sensor is converted into the reference coordinate system O1O and then into the coordinate system O of the first sensor. As above, the coordinate system O2 of the second sensor is converted into the coordinate system O of the first sensor, thereby realizing data stitching of 3 sensors.
As a preferred embodiment, before triggering the corresponding plurality of sensors to operate according to the trigger signal and acquiring the time stamps of the corresponding trigger moments of the plurality of sensors, the method further includes:
And filtering the pulse waveform of the trigger signal.
Specifically, in this embodiment, the bus module generates a trigger signal that controls the operation of the corresponding plurality of sensors, and the trigger signal is susceptible to electromagnetic interference and high-frequency noise during transmission to the corresponding sensors. Therefore, in order to improve the reliability of the application for triggering the operation of a plurality of sensors, the pulse waveform of the triggering signal is subjected to filtering processing.
As a preferred embodiment, filtering the pulse waveform of the trigger signal includes:
Monitoring signal parameters of pulse waveforms of trigger signals in real time; wherein the signal parameters include level, frequency, phase, bandwidth and signal strength information;
According to the signal parameters, identifying noise interference of pulse waveforms of the trigger signals;
And filtering the pulse waveforms of the trigger signals according to noise interference.
As a preferred embodiment, filtering the pulse waveform of the trigger signal further includes:
Monitoring the change of the communication environment in real time;
the filtering parameters are adjusted in real time according to the change of the communication environment.
Specifically, in the present embodiment, parameters of the filter, including cut-off frequency, passband width, gain, attenuation, and the like, are dynamically adjusted according to the communication environment and the monitoring result to ensure a reliable filtering effect.
Referring to fig. 9, an embodiment of the present invention provides a bus module signal acquisition control device, including:
the reference trigger module 1 is used for controlling a second pulse calibration module in the bus module to generate a reference trigger signal by taking a system clock in the bus module as a reference clock;
The trigger signal generation module 2 is used for generating trigger signals for controlling the corresponding sensors to work according to the reference trigger signals and the working frequencies of the sensors;
The time stamp determining module 3 is used for triggering a plurality of corresponding sensors to work according to the trigger signals and obtaining time stamps of the plurality of sensors at corresponding trigger moments;
the delay calculation module 4 is used for determining trigger delay time of the plurality of sensors according to the time stamps;
the delay compensation module 5 is used for respectively carrying out delay compensation on the plurality of sensors according to the trigger delay time;
a marking module 6, configured to mark time stamps corresponding to the plurality of sensors respectively;
the data splicing module 7 is used for correspondingly splicing the acquired data of the plurality of sensors according to the timestamp marking result;
The transmission module 8 is used for transmitting the acquired data of the plurality of sensors after the splicing processing to the host control system;
Wherein, reference trigger module 1 includes:
a setting unit 11 for setting a standard trigger frequency and a standard counter inside the bus module;
A control unit 12 for controlling the frequency of the output reference trigger signal by the standard trigger frequency;
and the delay control unit 13 is used for performing half-period delay control on the output of the reference trigger signal by using the second pulse clock as a reference through the standard counter.
In addition, a bus module signal acquisition control method according to the embodiment of the present invention described in connection with fig. 1 may be implemented by a bus module signal acquisition control device. Fig. 10 shows a schematic hardware structure of a bus module signal acquisition control device according to an embodiment of the present invention.
The bus module signal acquisition control device may include a processor 401 and a memory 402 in which computer program instructions are stored.
In particular, the processor 401 may include a Central Processing Unit (CPU), or an Application SPECIFIC INTEGRATED Circuit (ASIC), or may be configured as one or more integrated circuits that implement embodiments of the present invention.
Memory 402 may include mass storage for data or instructions. By way of example, and not limitation, memory 402 may comprise a hard disk drive (HARD DISK DRIVE, HDD), a floppy disk drive, flash memory, optical disk, magneto-optical disk, magnetic tape, or a universal serial bus (Universal Serial Bus, USB) drive, or a combination of two or more of the foregoing. Memory 402 may include removable or non-removable (or fixed) media, where appropriate. Memory 402 may be internal or external to the data processing apparatus, where appropriate. In a particular embodiment, the memory 402 is a non-volatile solid state memory. In a particular embodiment, the memory 402 includes Read Only Memory (ROM). The ROM may be mask programmed ROM, programmable ROM (PROM), erasable PROM (EPROM), electrically Erasable PROM (EEPROM), electrically rewritable ROM (EAROM), or flash memory, or a combination of two or more of these, where appropriate.
The processor 401 reads and executes the computer program instructions stored in the memory 402 to implement any of the bus module signal acquisition control methods in the above embodiments.
In one example, the bus module signal acquisition control device may also include a communication interface 403 and a bus 410. As shown in fig. 10, the processor 401, the memory 402, and the communication interface 403 are connected to each other by a bus 410 and perform communication with each other.
The communication interface 403 is mainly used to implement communication between each module, device, unit and/or apparatus in the embodiment of the present invention.
Bus 410 includes hardware, software, or both, that couple the components of the bus module signal acquisition control device to one another. By way of example, and not limitation, the buses may include an Accelerated Graphics Port (AGP) or other graphics bus, an Enhanced Industry Standard Architecture (EISA) bus, a Front Side Bus (FSB), a HyperTransport (HT) interconnect, an Industry Standard Architecture (ISA) bus, an infiniband interconnect, a Low Pin Count (LPC) bus, a memory bus, a micro channel architecture (MCa) bus, a Peripheral Component Interconnect (PCI) bus, a PCI-Express (PCI-X) bus, a Serial Advanced Technology Attachment (SATA) bus, a video electronics standards association local (VLB) bus, or other suitable bus, or a combination of two or more of the above. Bus 410 may include one or more buses, where appropriate. Although embodiments of the invention have been described and illustrated with respect to a particular bus, the invention contemplates any suitable bus or interconnect.
In addition, in combination with the method for controlling signal acquisition of the bus module in the above embodiment, the embodiment of the invention may be implemented by providing a computer readable storage medium. The computer readable storage medium has stored thereon computer program instructions; the computer program instructions, when executed by a processor, implement any of the bus module signal acquisition control methods of the above embodiments.
It should also be noted that the exemplary embodiments mentioned in this disclosure describe some methods or systems based on a series of steps or devices. The present invention is not limited to the order of the above-described steps, that is, the steps may be performed in the order mentioned in the embodiments, or may be performed in a different order from the order in the embodiments, or several steps may be performed simultaneously.
In the foregoing, only the specific embodiments of the present invention are described, and it will be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working processes of the systems, modules and units described above may refer to the corresponding processes in the foregoing method embodiments, which are not repeated herein. It should be understood that the scope of the present invention is not limited thereto, and any equivalent modifications or substitutions can be easily made by those skilled in the art within the technical scope of the present invention, and they should be included in the scope of the present invention.
Claims (10)
1. The bus module signal acquisition control method is characterized by comprising the following steps of:
Taking a system clock in the bus module as a reference clock, and controlling a second pulse calibration module in the bus module to generate a reference trigger signal;
generating trigger signals for controlling the operation of a plurality of sensors according to the reference trigger signals and the operating frequencies of the sensors;
Triggering a plurality of corresponding sensors to work according to the triggering signals, and acquiring time stamps of the corresponding triggering moments of the plurality of sensors;
determining trigger delay time of a plurality of sensors according to the time stamps;
Respectively carrying out delay compensation on a plurality of sensors according to the trigger delay time;
marking the time stamps corresponding to the plurality of sensors respectively;
Correspondingly splicing the acquired data of the plurality of sensors according to the timestamp marking result;
transmitting the acquired data of the plurality of sensors after the splicing processing to a host control system;
The step of controlling the second pulse calibration module in the bus module to generate a reference trigger signal by taking the system clock in the bus module as a reference clock comprises the following steps:
setting a standard trigger frequency and a standard counter in the bus module;
controlling the frequency of outputting the reference trigger signal through the standard trigger frequency;
And taking a second pulse clock as a reference, and performing half-period delay control on the output of the reference trigger signal through the standard counter.
2. The bus module signal acquisition control method according to claim 1, characterized by comprising, before the transmitting the acquired data of the plurality of sensors after the splicing process to the host control system:
transmitting the acquired data of the plurality of sensors after the splicing processing to first-in first-out data buffers corresponding to the sensors;
converting the parallel acquired data into serial acquired data;
And sequentially uploading the serial acquired data in each first-in first-out data buffer to the host control system according to a preset priority order.
3. The method for controlling signal acquisition of a bus module according to claim 1, wherein the performing a splicing process on the acquired data of the plurality of sensors according to the timestamp marking result comprises:
taking a coordinate system in which the first sensor is positioned as a reference coordinate system;
Obtaining a first conversion relation from the reference coordinate system to a preset reference coordinate system through calibration;
obtaining a second conversion relation from a coordinate system where a second sensor is located to the preset reference coordinate system through calibration;
According to the second conversion relation, correspondingly converting the data on the coordinate system where the second sensor is located to the preset reference coordinate system to obtain first intermediate coordinate system data;
And correspondingly transforming the first intermediate coordinate system data to the reference coordinate system according to the first transformation relation so as to realize data splicing.
4. The method for controlling signal acquisition of a bus module according to claim 1, wherein the performing a splicing process on the acquired data of the plurality of sensors according to the timestamp marking result comprises:
Obtaining a space coordinate transformation relation through pairwise calibration;
carrying out space transformation on data under the own coordinate system of each sensor;
and converting the data of each sensor in the own coordinate system into the same coordinate system so as to realize the splicing of the data of multiple sensors.
5. The method for controlling signal acquisition of a bus module according to claim 1, further comprising, before the triggering of the corresponding plurality of sensors according to the trigger signal to operate and the obtaining of the time stamps of the corresponding triggering moments of the plurality of sensors:
and filtering the pulse waveform of the trigger signal.
6. The method for controlling signal acquisition of a bus module according to claim 5, wherein filtering the pulse waveform of the trigger signal comprises:
monitoring signal parameters of pulse waveforms of the trigger signals in real time; wherein the signal parameters include level, frequency, phase, bandwidth and signal strength information;
According to the signal parameters, identifying noise interference of pulse waveforms of the trigger signals;
And filtering the pulse waveforms of the trigger signals according to the noise interference.
7. The method for controlling signal acquisition of a bus module according to claim 6, wherein filtering the pulse waveform of the trigger signal further comprises:
Monitoring the change of the communication environment in real time;
And adjusting filtering parameters in real time according to the change of the communication environment.
8. A bus module signal acquisition control device, the device comprising:
The reference trigger module is used for controlling the second pulse calibration module in the bus module to generate a reference trigger signal by taking the system clock in the bus module as a reference clock;
The trigger signal generation module is used for generating trigger signals for controlling the operation of the corresponding sensors according to the reference trigger signals and the operating frequencies of the sensors;
The time stamp determining module is used for triggering a plurality of corresponding sensors to work according to the trigger signals and obtaining time stamps of the plurality of corresponding trigger moments of the sensors;
The delay calculation module is used for determining trigger delay time of the plurality of sensors according to the time stamps;
the delay compensation module is used for respectively carrying out delay compensation on the plurality of sensors according to the trigger delay time;
The marking module is used for marking the time stamps corresponding to the plurality of sensors respectively;
the data splicing module is used for correspondingly splicing the acquired data of the plurality of sensors according to the timestamp marking result;
the transmission module is used for transmitting the acquired data of the plurality of sensors after the splicing processing to the host control system;
Wherein, the benchmark trigger module includes:
The setting unit is used for setting standard trigger frequency and standard counter in the bus module;
the control unit is used for controlling and outputting the frequency of the reference trigger signal through the standard trigger frequency;
and the delay control unit is used for carrying out half-period delay control on the output of the reference trigger signal by taking the second pulse clock as a reference through the standard counter.
9. A bus module signal acquisition control device, comprising: at least one processor, at least one memory, and computer program instructions stored in the memory, which when executed by the processor, implement the method of any one of claims 1-7.
10. A storage medium having stored thereon computer program instructions, which when executed by a processor, implement the method of any of claims 1-7.
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