CN118157801A

CN118157801A - Media communication system and media communication device and method with signal synchronization mechanism

Info

Publication number: CN118157801A
Application number: CN202211555474.3A
Authority: CN
Inventors: 杜明哲; 蔡旻轩; 叶俊邑; 颜宇聪
Original assignee: Realtek Semiconductor Corp
Current assignee: Realtek Semiconductor Corp
Priority date: 2022-12-06
Filing date: 2022-12-06
Publication date: 2024-06-07

Abstract

The invention relates to a media communication system, a media communication device with a signal synchronization mechanism and a method thereof. A media communication device with a signal synchronization mechanism. The local clock generation circuit generates a reference clock signal and a media clock signal. The time correction circuit performs a time correction procedure with an external device and generates time correction information, and further corrects the reference clock signal and the media clock signal according to the time correction information to generate a corrected reference clock signal and a corrected media clock signal on a standard time domain respectively. The media frequency processing circuit generates a sampling signal according to the corrected media clock signal. The signal processing circuit generates time-related information according to the timing of the correction reference clock signal, and further processes the input media signal according to the time-related information and the sampling signal to generate an output media signal.

Description

Media communication system and media communication device and method with signal synchronization mechanism

Technical Field

The present invention relates to media communication technology, and more particularly, to a media communication system and a media communication apparatus and method with a signal synchronization mechanism.

Background

In a system for playing media, a media provider needs to communicate with a media receiver to transmit a media signal from the media provider to the media receiver for playing. For example, a CD player as a media provider may transmit audio to a multi-channel speaker as a media receiver, where sound is played. However, an accurate signal synchronization mechanism is required between the speakers of different channels for synchronized playback. In order to achieve accurate signal synchronization, the media supply and the media receiving end often need additional circuits to provide accurate frequency correction, resulting in increased circuit cost.

Disclosure of Invention

In view of the foregoing, it is an objective of the present invention to provide a media communication system and a media communication apparatus and method with a signal synchronization mechanism, so as to improve the prior art.

The present invention includes a media communication device with a signal synchronization mechanism, comprising: a local clock generating circuit, a time correction circuit, a media frequency processing circuit and a signal processing circuit. The local clock generation circuit is configured to generate a reference clock signal and a media clock signal. The time correction circuit is configured to perform a time correction procedure with an external device and generate time correction information, and further corrects the reference clock signal and the media clock signal according to the time correction information, so as to generate a corrected reference clock signal and a corrected media clock signal on a standard time domain respectively. The media frequency processing circuit is configured to generate a sampling signal according to the corrected media clock signal. The signal processing circuit is configured to generate time-related information according to the correction reference clock signal, and further process the input media signal according to the time-related information and the sampling signal and generate an output media signal.

The invention also comprises a media communication method with a signal synchronization mechanism, which is applied to a media communication device and comprises the following steps: causing the local clock generation circuit to generate a reference clock signal and a media clock signal; the time correction circuit and the external device are made to perform a time correction program and generate time correction information, and the reference clock signal and the media clock signal are further corrected according to the time correction information, so that a corrected reference clock signal and a corrected media clock signal which are positioned on a standard time domain are respectively generated; the media frequency processing circuit generates a sampling signal according to the corrected media clock signal; and enabling the signal processing circuit to generate time related information according to the timing of the correction reference clock signal, and further processing the input media signal according to the time related information and the sampling signal to generate an output media signal.

The features, implementation and functions of the present invention are described in detail below with reference to the preferred embodiments shown in the drawings.

Drawings

FIG. 1 is a block diagram of a media communication system according to one embodiment of the invention;

FIGS. 2A and 2B are block diagrams of a media communication device with a signal synchronization mechanism according to an embodiment of the invention;

FIG. 3 is a block diagram of a signal processing circuit according to an embodiment of the invention;

FIG. 4 is a block diagram of a signal processing circuit according to another embodiment of the present invention; and

FIG. 5 is a flow chart of a method of media communication according to an embodiment of the invention.

Detailed Description

One of the objectives of the present invention is to provide a media communication system and a media communication device and method with signal synchronization mechanism, wherein the setting of a time correction circuit directly corrects the homologous reference frequency and sampling frequency to a standard time domain, so that the generated time-related information corresponds to the standard time domain, and the input media signal can be processed without setting an additional time domain conversion circuit, thereby greatly reducing the circuit setting cost.

Please refer to fig. 1. Fig. 1 shows a block diagram of a media communication system 100 in accordance with an embodiment of the present invention. The media communication system 100 includes a plurality of media communication devices 110 having a signal synchronization mechanism. In one embodiment, the media communication device 110 includes a media supply (talker) TL and six media sinks (listener) LS 1-LS 6.

In one application scenario, the media provider TL may be a music player or a computer. The media receiving ends LS1 to LS6 may be, for example, but not limited to, speakers corresponding to one channel respectively, so that the media receiving ends LS1 to LS6 form a multi-channel audio playing device. In fig. 1, media receiving ends LS1 to LS6 are shown by taking 5.1 channels as an example. However, in other embodiments, the media communication system 100 may also be configured with a different number of media sinks corresponding to other numbers of channels.

Thus, the media supply TL is configured to process the input media signal MIT and to generate the output media signal MOT. The media receiving ends LS 1-LS 6 are configured to receive the input media signal MIL for processing to generate an output media signal MOL for playing, wherein the output media signal MOT generated by the media supply end TL is the input media signal MIL received by the media receiving ends LS 1-LS 6.

Please refer to fig. 2A and fig. 2B. Fig. 2A and fig. 2B are block diagrams of a media communication device 110 with a signal synchronization mechanism according to an embodiment of the invention. The media communication device 110 includes: a local clock generation circuit 200, a time correction circuit 210, a media frequency processing circuit 220, and a signal processing circuit 230.

The local clock generation circuit 200 is configured to generate a reference clock signal RCK and a media clock signal MCK. In one embodiment, the local clock generation circuit 200 is implemented with an oscillator having a precision higher than a predetermined range, such as, but not limited to, a quartz oscillator.

The time correction circuit 210 is configured to perform a time correction process with an external device (not shown) and generate time correction information TC, and further corrects the reference clock signal RCK and the media clock signal MCK according to the time correction information TC, so as to generate a corrected reference clock signal RCKC and a corrected media clock signal MCKC respectively in a standard time domain.

In one embodiment, the time correction circuit 210 performs a time correction procedure with an external device according to the universal precision time protocol (generalized time precision protocol).

In more detail, the external device may be a master frequency device (grandmaster) set based on a universal precision time protocol. The time correction circuit 210 may be used as a slave device (slave) to calculate the average path delay time with the neighboring external device by exchanging messages with the master frequency device for the path delay (PATH DELAY) request and the path delay response. The time correction circuit 210 may also calculate a ratio (rate) with respect to the master frequency device by performing synchronization (sync) and follow-up (follow-up) message exchange with the master frequency device.

By the above procedure, the time correction information TC generated by the time correction circuit 210 may include the frequency of the master frequency device and the time offset between the slave device (the time correction circuit 210) and the master frequency device. After the correction of the time correction information TC, the reference clock signal RCK and the media clock signal MCK become the corrected reference clock signal RCKC and the corrected media clock signal MCKC synchronized with the standard time domain of the main frequency device.

The media frequency processing circuit 220 is configured to generate the sampling signal SS according to the corrected media clock signal MCKC. In one embodiment, the media frequency processing circuit 220 may be further configured to generate, for example and without limitation, a Master Clock (MCLK) and a Bit Clock (BCLK) for use by other desired circuits. The invention is not limited thereto.

The signal processing circuit 230 is configured to generate time-related information TRI according to the timing of the corrected reference clock signal RCKC, and further process the input media signal according to the time-related information TRI and the sampling signal SS and generate an output media signal.

In one embodiment, when the media communication device 110 is configured as the media supply TL, the media generation circuit 240 configured to generate the input media signal MIT is further included as shown in fig. 2A, so that the signal processing circuit 230 processes the input media signal MIT and generates the output media signal MOT.

When the media communication device 110 is configured as the media receiving ends LS1 to LS6, as shown in fig. 2B (representatively shown as the media receiving end LS 1), the media communication device further includes a media playing circuit 250, so that the signal processing circuit 230 processes the input media signal MILs to generate an output media signal MOL, and the media playing circuit 250 plays the output media signal MOL.

The following further describes the more detailed structure and operation of the signal processing circuit 230 when the media communication device 110 is configured as the media supply terminal TL and the media receiving terminals LS1 to LS6, respectively.

Please refer to fig. 3 at the same time. Fig. 3 shows a block diagram of the signal processing circuit 230 according to an embodiment of the invention. In the present embodiment, the media communication device 110 is configured as a media provider TL. In the media supply TL, the signal processing circuit 230 includes a timing circuit 300, a time stamp fifo 310, an analog-to-digital conversion circuit 320, a data fifo 330, a packet processing circuit 340, and a transmission circuit 350.

The timing circuit 300 is configured to clock the sampling signal SS according to the corrected reference clock signal RCKC to generate the time stamp information TS corresponding to the standard time domain as the time related information TRI.

The time stamp FIFO 310 is configured to temporarily store time stamp information TS.

The analog-to-digital conversion circuit 320 is configured to perform analog-to-digital conversion on the input media signal MIT in analog form generated by the media generation circuit 240 according to the sampling signal SS to generate digital data DD.

The data FIFO circuit 330 is configured to temporarily store the digital data DD.

There may be a slight difference in timing due to the difference in the paths generated by the time stamp information TS and the digital data DD. Therefore, the time stamp information TS and the digital data DD are temporarily stored by the time stamp fifo 310 and the data fifo 330, respectively, and then are accessed by the packet processing circuit 340, wherein the time stamp information TS represents a time point when the corresponding digital data DD is sampled.

The packet processing circuit 340 further generates a plurality of packets according to the corresponding digital data DD and the timestamp information TS, and outputs the plurality of packets as the output media signal MOT. In one embodiment, the packet processing circuit 340 generates packets based on, for example, but not limited to, the IEEE 1722 protocol. However, the present invention is not limited thereto.

In one embodiment, the packet processing circuit 340 is configured to add an offset OFF to the time stamp information TS to generate a packet in combination with the digital data DD. In one embodiment, the offset OFF is the maximum delay time in all paths corresponding to the objects to be transmitted (e.g., the media receiving ends LS1 to LS6 shown in fig. 1) of the digital data DD, and a small buffer time is added to take into account the path delays of the different transmitted objects, so that the predicted playing time is equal to the time stamp information TS plus the offset OFF, and the playing time of the digital data DD by the media receiving ends LS1 to LS6 is ensured to be consistent.

The transmitting circuit 350 is configured to transmit the output media signal MOT to the media receiving ends LS1 to LS6.

Please refer to fig. 4 at the same time. Fig. 4 shows a block diagram of a signal processing circuit 230 according to another embodiment of the invention. In the present embodiment, the media communication device 110 is configured as one of the media receiving ends LS 1-LS 6. The media sink LS1 will be described as an example. In the media sink LS1, the signal processing circuit 230 includes a receiving circuit 400, a packet processing circuit 410, a data FIFO circuit 420, a timing circuit 430 and a digital-to-analog conversion circuit 440.

The receiving circuit 400 is configured to receive an input media signal MILs from the media supply TL. In more detail, the input media signal MILs received by the media receiving terminal LS1 is actually the output media signal MOT transmitted by the media supplying terminal TL.

The packet processing circuit 410 is configured to process each of a plurality of packets included in the input media signal MILs to read the time stamp information TS and the digital data DD.

The data FIFO circuit 420 is configured to temporarily store the digital data DD.

The timing circuit 430 is configured to clock according to the corrected reference clock signal RCKC, and further generate presentation time (presentation time) information PT corresponding to the standard time domain as time-related information TRI corresponding to the time stamp information TS. Since the time stamp information TS is already located in the standard time domain, the timing circuit 430 can process the time stamp information TS in real time, and only the first time stamp information TS needs to be processed, so that the first-in first-out circuit is not required to be additionally provided to store the time stamp information TS.

In one embodiment, the presentation time information PT is actually generated according to the time stamp information TS and the offset OFF of each packet, so that the different media receiving ends LS1 to LS6 can play the digital data DD at the correct timing sequence according to the uniform predicted playing time.

The digital-to-analog conversion circuit 440 is configured to receive the sampling signal SS according to the presentation time information PT, and further perform digital-to-analog conversion on the digital data DD according to the sampling signal SS, so as to generate an analog signal and output the analog signal as the output media signal MOL, so that the media playing circuit 250 plays the output media signal MOL. In one embodiment, the presentation time information PT may have a function as enabled, so that the digital-to-analog conversion circuit 440 receives the sampling signal SS at a time point corresponding to the presentation time information PT and performs digital-to-analog conversion on the digital data DD accordingly.

In some technologies, the media supply end generates time stamp information and digital data respectively by using reference frequencies and sampling frequencies of different sources, and additionally converts the time stamp information into a standard time domain when performing packet processing, and generates packets according to the time stamp information and the digital data in the standard time domain. The media receiving end also has the same frequency configuration mode, besides the first-in first-out circuit for storing the time stamp information, the frequency recovery circuit is required to be arranged to convert the time stamp information from the standard time domain to the internal time domain and to adjust the internal frequency according to the standard time domain so as to process the digital data. The cost of the circuit is greatly increased.

The media communication device directly corrects the homologous reference frequency and the sampling frequency to the standard time domain by the setting of the time correction circuit, so that the generated time-related information corresponds to the standard time domain, and the input media signal can be processed without the setting of an additional time domain conversion circuit, thereby greatly reducing the circuit setting cost.

It should be noted that in the circuits of fig. 2A, 2B, 3 and 4, part of the circuits may be implemented entirely in hardware circuits and may be integrated in one circuit. Some of the circuitry may be implemented by running software on circuitry configured as a processing unit.

For example, in the medium supply TL, the local clock generation circuit 200, the medium frequency processing circuit 220, the timing circuit 300, and the transmission circuit 350 can be implemented by hardware circuits and integrated into a physical layer circuit (PHY). The time correction circuit 210, the time stamp FIFO 310, and the packet processing circuit 340 may be implemented by a processing circuit operating software or firmware. The analog-to-digital conversion circuit 320 and the data FIFO 330 may be implemented by hardware circuits and integrated into a single signal processing circuit.

In the media receiving ends LS1 to LS6, the local clock generating circuit 200, the media frequency processing circuit 220, the receiving circuit 400 and the timing circuit 430 can be all implemented by hardware circuits and integrated into a physical layer circuit. The time correction circuit 210 and the packet processing circuit 410 may be implemented by a processing circuit operating software or firmware. The data FIFO 420 and the DAC 440 may be implemented by hardware circuits and integrated into a single signal processing circuit.

It should be noted that the above circuit configuration is only an example. In other embodiments, other hardware and software configurations and integration may be implemented. The invention is not limited thereto.

Please refer to fig. 5. Fig. 5 shows a flow chart of a method 500 for media communication in accordance with an embodiment of the invention.

In addition to the foregoing devices, the present invention further discloses a media communication method 500 applied to, for example, but not limited to, the media communication device 110 of fig. 2A or 2B. One embodiment of a media communication method 500 is shown in fig. 5 and includes the following steps.

In step S510, the local clock generating circuit 200 generates the reference clock signal RCK and the media clock signal MCK.

In step S520, the time correction circuit 210 and the external device perform a time correction process and generate time correction information TC, and further correct the reference clock signal RCK and the media clock signal MCK according to the time correction information TC to generate a corrected reference clock signal RCKC and a corrected media clock signal MCKC respectively.

In step S530, the medium frequency processing circuit 220 generates a sampling signal SS according to the corrected medium clock signal MCKC.

In step S540, the signal processing circuit 230 is enabled to generate the time-related information TRI according to the calibration reference clock signal RCKC, and further process the input media signal (e.g. the input media signal MIT of the media supply terminal TL or the input media signals MILs of the media receiving terminals LS1 to LS 6) and generate the output media signal (e.g. the output media signal MOT of the media supply terminal TL or the input media signal MOL of the media receiving terminals LS1 to LS 6) according to the time-related information TRI and the sampling signal SS.

It should be noted that the above embodiment is only an example. In other embodiments, those skilled in the art will appreciate that modifications may be made without departing from the spirit of the invention.

In summary, the media communication system and the media communication device and method with signal synchronization mechanism of the present invention directly correct the homologous reference frequency and sampling frequency to the standard time domain by setting the time correction circuit, so that the generated time-related information corresponds to the standard time domain, and the input media signal can be processed without setting an additional time domain conversion circuit, thereby greatly reducing the circuit setting cost.

Although the embodiments of the present disclosure have been described above, these embodiments are not limited thereto, and those skilled in the art can make various changes to the technical features of the present disclosure according to the explicit or implicit disclosure of the present disclosure, where the various changes may be within the scope of protection sought herein, in other words, the scope of protection of the present disclosure shall be defined by the claims of the present disclosure.

[ Symbolic description ]

100 Media communication system

110 Media communication device

200 Local clock generating circuit

210 Time correction circuit

220 Media frequency processing circuit

230 Signal processing circuit

240 Media generation circuit

250 Media playing circuit

300 Timing circuit

310 Time stamp FIFO circuit

320 Analog-to-digital conversion circuit

330 Data FIFO circuit

340 Packet processing circuit

350 Transfer circuit

400 Receiving circuit

Packet processing circuit 410

420 Data FIFO circuit

430 Timing circuit

440 Digital-to-analog conversion circuit

500 Media communication method

S510-S540 steps

DD digital data

LS 1-LS 6 media receiving end

MCK media clock signal

MCKC correction of media clock signal

MIL, MIT, input media signal

MOL, MOT, output media signal

PT presentation time information

RCK reference clock signal

RCKC correction of reference clock signals

SS sampling signal

TL media supply end

TRI time related information

TS, timestamp information.

Claims

1. A media communication device with a signal synchronization mechanism, comprising:

A local clock generating circuit configured to generate a reference clock signal and a media clock signal;

The time correction circuit is configured to perform a time correction procedure with an external device and generate time correction information, and further corrects the reference clock signal and the media clock signal according to the time correction information to generate a corrected reference clock signal and a corrected media clock signal on a standard time domain respectively;

a media frequency processing circuit configured to generate a sampling signal according to the corrected media clock signal; and

The signal processing circuit is configured to generate time related information according to the timing of the correction reference clock signal, and further process an input media signal according to the time related information and the sampling signal and generate an output media signal.

2. The media communication device of claim 1, wherein the media communication device is a media supply and further comprising a media generation circuit configured to generate the input media signal, the signal processing circuit comprising:

A timing circuit configured to clock the sampling signal according to the corrected reference clock signal to generate a time stamp information corresponding to the standard time domain as the time-related information;

an analog-to-digital conversion circuit configured to perform analog-to-digital conversion on the input media signal according to the sampling signal to generate digital data;

a packet processing circuit configured to generate a plurality of packets according to the corresponding digital data and the time stamp information, so as to output as the output media signal; and

A transmitting circuit configured to transmit the output media signal to a media receiving end.

3. The media communication device of claim 2, wherein the signal processing circuit further comprises:

A time stamp first-in first-out circuit configured to temporarily store the time stamp information; and

A data FIFO circuit configured to temporarily store the digital data;

the packet processing circuit is configured to access the time stamp information and the digital data from the time stamp FIFO circuit and the data FIFO circuit, respectively, to generate the plurality of packets.

4. A media communications device as in claim 3, wherein the packet processing circuit is configured to add an offset to the time stamp information to generate the plurality of packets with the digital data.

5. The media communication device of claim 1, wherein the media communication device is a media sink and further comprising a media playing circuit configured to play the output media signal, the signal processing circuit comprising:

A receiving circuit configured to receive the input media signal from a media supply;

A packet processing circuit configured to process each of a plurality of packets included in the input media signal to read a time stamp information and a digital data;

The timing circuit is configured to time according to the correction reference clock signal, and further generates presentation time information corresponding to the standard time domain according to the time stamp information as the time related information; and

And a digital-to-analog conversion circuit configured to receive the sampling signal according to the presentation time information, and further perform digital-to-analog conversion on the digital data according to the sampling signal, so as to generate an analog signal and output the analog signal as the output media signal.

6. The media communication device of claim 5, wherein the signal processing circuit further comprises a data FIFO circuit configured to temporarily store the digital data;

the digital-to-analog conversion circuit is configured to access the digital data from the data FIFO circuit for digital-to-analog conversion.

7. The media communication device of claim 6, wherein the presentation time information is substantially generated from the time stamp information and an offset for each of the packets.

8. The media communication device of claim 1, wherein the time correction circuit performs the time correction procedure with the external device according to a universal precision time protocol.

9. A media communication method with signal synchronization mechanism is applied in a media communication device, comprising:

a local clock generating circuit is made to generate a reference clock signal and a media clock signal;

enabling a time correction circuit and an external device to perform a time correction program and generate time correction information, and further correcting the reference clock signal and the media clock signal according to the time correction information to respectively generate a corrected reference clock signal and a corrected media clock signal on a standard time domain;

A media frequency processing circuit generates a sampling signal according to the corrected media clock signal; and

A signal processing circuit is enabled to generate time related information according to the timing of the correction reference clock signal, and further processes an input media signal according to the time related information and the sampling signal to generate an output media signal.

10. A media communication system, comprising:

a media supply terminal and a plurality of media receiving terminals, respectively comprising:

A signal processing circuit configured to generate time-related information according to the timing of the corrected reference clock signal, and further to process an input media signal according to the time-related information and the sampling signal and generate an output media signal;

Wherein the output media signal generated by the media supply terminal is used as the input media signal of the plurality of media receiving terminals.