CN118157683A - Self-zooming ADC - Google Patents

Abstract

The invention discloses a self-zooming ADC (analog-to-digital converter), which comprises two DACs, a low-pass digital filter LPF (LPF), a transfer function, a quantizer and three adders, wherein an input V _IN enters a first adder and a second adder, then enters a loop filter and then enters the quantizer to obtain low-order number output, two paths of the output are respectively sent into the first DAC, then enter the second adder to perform successive approximation, the other path of the output is simultaneously sent into the low-pass digital filter LPF and a third adder, the low-pass digital filter LPF obtains high-order number output, the output of the low-pass digital filter LPF enters the second DAC in two paths to perform successive approximation, and the other path of the output enters the third adder to be combined to output Y _OUT. The invention has the advantages of ensuring high input swing and relatively low power consumption while ensuring the requirement of high precision.

Description

Self-zooming ADC

Technical Field

The invention relates to the technical field of semiconductor integrated circuits, in particular to a self-zooming ADC.

Background

In the ADC of the conventional boom structure, an additional coarse quantization ADC is required to perform coarse quantization on the input signal, so as to reduce quantization error of the sigma-delta ADC (sigma-delta ADC), but the additional coarse quantization ADC increases power consumption and area of the system.

In the past designs, generally, an ADC for converting an audio signal employed a SAR ADC having an accuracy of 13 bits or more. Although the successive approximation analog-to-digital converter (SAR ADC) can easily meet the requirements of the ADC on the bandwidth and the signal amplitude of an input signal, the SAR ADC is usually only 12 bits due to the limitation of matching precision of resistance and capacitance in the DAC. Additional matching correction techniques are required to achieve SAR ADCs above 12 bits. Correction techniques not only increase area, but also increase the complexity of the circuit design. Because of the large resistance and capacitance of the DAC of the SAR ADC, a signal driving circuit needs to be added in front of the SAR ADC, and the circuit increases large power consumption.

The need for precision can be addressed when processing signals using conventional multi-order sigma-delta ADCs, but this is energy inefficient.

Therefore, the boom architecture has emerged that uses one coarse quantization ADC (generally, SAR ADC) to perform coarse quantization on an input signal, and sets a reference voltage of the ΔΣ ADC according to the coarse quantization, thereby reducing quantization error of the ΔΣ ADC quantizer, and combining high precision of the ΔΣ ADC and high energy efficiency of the SAR ADC.

As shown in fig. 1, one path of input Vin passes through a SAR ADC to obtain an output result K, the other path of input Vin enters a first adder, the output result K enters a DAC and then enters the first adder, the result after the difference is made, the result after the difference is sent to a second adder, the output of the second adder enters a loop filter with a transfer function of H (Z) and then enters a quantizer to obtain an output yΔΣm, and at this time, the output yΔΣm is sent to the second adder again to make the difference.

The boom technique is to coarsely quantize the input signal and then apply the difference to SIGMA DELTA ADC. Since the signal after the difference is smaller than 1 LSB of the coarsely quantized ADC, the amplitude of the quantizer feedback DAC can also be set small.

SIGMA DELTA ADC of the boom architecture can be understood as having a SAR ADC at the front of SIGMA DELTA for coarse quantization and then giving the margin to SIGMA DELTA for processing. The SIGMA DELTA ADC of the boom architecture can achieve nearly the same full swing input amplitude as the SAR ADC.

But the boom extra coarse quantization ADC increases the power consumption and area of the system and this function, self-boom, can be achieved using a digital filter instead of a SAR ADC.

As shown in fig. 2, the quantizer output of SIGMA DELTA ADC is digitally filtered to obtain a digital output corresponding to the amplitude of the input signal.

Although we can reduce the requirements of analog circuit accuracy and device matching degree by sampling technique and noise shaping technique, the continuous exponential increase of the oversampling rate to obtain a linearly improved effective bit number is unacceptable when the accuracy requirement is too high, for example, the oversampling cycle number is required to reach 2++16=65536 only with the resolution of 16 bits of first-order delta sigma-delta, which is not practical.

Disclosure of Invention

In order to solve the above technical problems, the present invention provides a self-zooming ADC, which uses a sigma-delta ADC to reduce the requirement for the oversampling rate, and the problem that the input swing is limited by the increase of the order is not occurred due to the use of a boom architecture.

The technical scheme adopted is as follows:

The utility model provides a self-zooming ADC, including two DACs, low pass digital filter LPF, transfer function, quantizer and three adder, input V _IN gets into the low-order number output that the loop filter got after getting into the quantizer after getting into first adder and second adder, two way again get into the second adder after sending into first DAC one way and carry out successive approximation, the other way is sent into low pass digital filter LPF and third adder simultaneously, low pass digital filter LPF obtains the output of high-order number, low pass digital filter LPF's output divides two way to get into after getting into the second DAC one way first adder and carries out successive approximation, the other way gets into the third adder after merging output Y _OUT.

Further preferred embodiments of the present invention provide that the loop filter with transfer function H (Z) comprises a two-stage analog integrator.

The invention also provides a self-zooming ADC, which comprises a DAC, a low-pass digital filter LPF, a transfer function, a quantizer and two adders, wherein the input V _IN enters the first adder and then enters the transfer function and then enters the quantizer to obtain low-bit output, two paths of low-bit output are respectively sent to the second adder, the other path of low-bit output is sent to the low-pass digital filter LPF, the low-pass digital filter LPF obtains high-bit output, the output of the low-pass digital filter LPF is also sent to the second adder, the output of the second adder is divided into two paths, one path of output Y _OUT is output, and the other path of output enters the first adder to perform successive approximation after entering the DAC.

Further preferably, the transfer function H (Z) comprises a two-stage loop filter.

The working flow of the self-zooming ADC can be expressed as that the output of a quantizer of a sigma-delta ADC is subjected to a digital filter to obtain a coarse quantization result, the input is subjected to a difference between the coarse quantization result and the result, and then the coarse quantization result is submitted to a second-order sigma-delta ADC for quantization. The ADC guarantees high-precision requirements, high input swing and relatively low power consumption.

Further preferably, the transfer function H (Z) comprises a two-stage loop filter.

Compared with the prior art, the invention has the beneficial effects that:

The ADC of the invention ensures high input swing while ensuring the requirement of high precision, and has relatively low power consumption.

The ADC of the invention uses relatively less hardware consumption and power consumption, has low requirements on matching and precision of devices, but can obtain higher ADC conversion precision and signal bandwidth and excellent input swing, which cannot be done by other types of ADCs. The ADC of the type is applied to an active noise reduction system, and has the characteristics of low power consumption, small area and high precision, so that the product has strong competitiveness.

Drawings

FIG. 1 is a schematic diagram of a prior art ADC;

FIG. 2 is a schematic diagram of SIGMA DELTA ADC in the prior art;

FIG. 3 is a schematic diagram of a self-zooming ADC of embodiment 1 of the present invention;

FIG. 4 is a schematic diagram of a self-zooming ADC of embodiment 2 of the present invention;

FIG. 5 is a schematic diagram of a transfer function H (Z) in an embodiment of the invention;

fig. 6 is a circuit diagram of an analog portion of a self-zooming ADC in an embodiment of the invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be further described in detail with reference to the accompanying drawings, fig. 1 to 6 and examples. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention. In addition, the technical features of the embodiments of the present invention described below may be combined with each other as long as they do not collide with each other.

Example 1

As shown in fig. 3, this embodiment is a self-zooming ADC, which includes two DACs, a low-pass digital filter LPF, a loop filter with transfer function H (Z), a quantizer and three adders, wherein an input V _IN enters the first adder and the second adder, then enters the low-bit output obtained by the quantizer after entering the transfer function, one path is divided into two paths, and enters the second adder to perform successive approximation, the other path is simultaneously sent into the low-pass digital filter LPF and the third adder, the low-pass digital filter LPF obtains high-bit output, the output of the low-pass digital filter LPF enters the first adder to perform successive approximation after entering the second DAC in two paths, and the other path enters the third adder to combine and output Y _OUT.

In this embodiment, the loop filter with transfer function H (Z) includes a two-stage analog integrator. As shown in figure 5 of the drawings,

In this embodiment, the quantizer Q is 2.25 bits, and 5 bits after passing through the low pass digital filter LPF, and the high order feedback is realized by the low order quantizer.

Example 2

As shown in fig. 4, the present embodiment is a self-zooming ADC, which includes a DAC, a low-pass digital filter LPF, a transfer function H (Z), a quantizer Q and two adders, wherein an input V _IN enters the first adder, enters the transfer function H (Z), then enters the quantizer Q to obtain a low-order output, and is sent to the second adder in one way, and sent to the low-pass digital filter LPF in the other way, and the low-pass digital filter LPF to obtain a high-order output, and the output of the low-pass digital filter LPF is also sent to the second adder, and the output of the second adder is sent to the first adder in two ways, and one way is sent to Y _OUT, and the other way is sent to the DAC and then sent to the first adder for successive approximation.

As shown in fig. 5, in the present embodiment, the loop filter with the transfer function H (Z) includes a two-stage analog integrator.

Further, as shown in fig. 6, in the self-zooming ADC, the analog part has two integrators and a 2.25bit quantizer, and the digital part has a digital filter. The DAC capacitor array is 5 bits, and the total capacitance value is 9pF.

According to the embodiment of the invention, through self-boom technology, the ADC provided by the invention uses relatively less hardware consumption and power consumption, has low requirements on matching and precision of devices, but can obtain higher ADC conversion precision and signal bandwidth and excellent input swing, which cannot be achieved by other types of ADCs. The ADC of the type is applied to an active noise reduction system, and has the characteristics of low power consumption, small area and high precision, so that the product has strong competitiveness.

The self-zooming ADC of the embodiment of the invention can be applied to various analog-to-digital signal conversion places by the self-zooming structure SIGMA DELTA ADC, and has strong competitiveness.

Examples:

slowly varying signals with bandwidths below 1-2 kHz are often encountered in a variety of applications such as sensor interfaces, biomedical signal processing, and industrial instrumentation. The amplitude of such signals can vary widely, from a few microvolts to a few volts, so ADCs for such applications require DR values above 110 dB and high linearity. Since many such applications involve battery powered systems, such as wearable medical devices and portable instruments, this class of ADC must also be very energy efficient, requiring less than milliwatts of power consumption. The linearity requirements for such applications must also control INL to within parts-per-million (ppm), i.e., SNDR is close to DR.

When the self-zooming ADC of the embodiment is used in the application field, the total power consumption of the self-zooming ADC under a 1.8V power supply is 385 mu W when the sampling rate is 4MHz, the dynamic range is up to 114.5dB, and the peak signal-to-noise ratio is up to 110.1dB, so that the self-zooming ADC can be used in the application field.

It will be readily appreciated by those skilled in the art that the foregoing description is merely a preferred embodiment of the invention and is not intended to limit the invention, but any modifications, equivalents, improvements or alternatives falling within the spirit and principles of the invention are intended to be included within the scope of the invention.

Claims (4)

1. The self-zooming ADC is characterized by comprising two DACs, a low-pass digital filter LPF, a transfer function, a quantizer and three adders, wherein an input V _IN enters a first adder and a second adder, then enters a loop filter and then enters the quantizer to obtain low-order number output, two paths of the output are fed into the second adder to perform successive approximation after one path of the output is fed into the first DAC, the other path of the output is simultaneously fed into the low-pass digital filter LPF and a third adder, the low-pass digital filter LPF obtains high-order number output, the output of the low-pass digital filter LPF enters the first adder to perform successive approximation after the output of the low-pass digital filter LPF enters the second DAC after the two paths of the output enter the third adder, and the output Y _OUT is combined after the other path of the output.

2. A self-zooming ADC as recited in claim 1, wherein the loop filter having a transfer function of H (Z) comprises a two-stage analog integrator.

3. The self-zooming ADC is characterized by comprising a DAC, a low-pass digital filter LPF, a transfer function, a quantizer and two adders, wherein an input V _IN enters the first adder and then enters the transfer function and then enters the quantizer to obtain low-bit output, two paths of low-bit output are respectively sent to the second adder, the other path of low-bit output is sent to the low-pass digital filter LPF, the low-pass digital filter LPF obtains high-bit output, the output of the low-pass digital filter LPF is also sent to the second adder, the output of the second adder is divided into two paths, one path of output Y _OUT is sent to the first adder, and the other path of output enters the DAC and then enters the first adder to perform successive approximation.

4. A self-zooming ADC according to claim 3 wherein the loop filter of transfer function H (Z) comprises a two stage analog integrator.