CN118153496A - A FPGA Architecture Visualization Method - Google Patents

Abstract

The present invention provides an FPGA architecture visualization method, which relates to the field of FPGA design. The method comprises: obtaining a first loading instruction, loading a target architecture file for describing the FPGA architecture and a resource mapping file for mapping hardware resources, constructing a first two-dimensional array based on the target architecture file and the resource mapping file, instantiating each basic construction unit based on the first two-dimensional array, releasing resources of the first two-dimensional array after generating a first matrix, constructing a first key-value mapping dictionary based on the first matrix, releasing resources of the first matrix after generating the first key-value mapping dictionary, and generating a visualization file according to information in the first key-value mapping dictionary, so as to help users improve work efficiency.

Description

A FPGA Architecture Visualization Method

Technical Field

The present invention relates to the field of FPGA design, and in particular to a FPGA architecture visualization method.

Background technique

With the rapid development of technology, the scale and complexity of chip design are growing exponentially. Traditional visualization tools are difficult to meet the needs of modern chip design in terms of performance and efficiency. Especially when dealing with ultra-large-scale FPGA designs, designers and engineers face problems such as insufficient memory management, poor interactive experience, and slow data processing, which greatly limits the efficiency of chip design. In view of the lack of efficient visualization tools for large-scale chips, a solution that can handle the growing scale of chip design is urgently needed.

Summary of the invention

In view of the above technical problems, the technical solution adopted by the present invention is:

A method for visualizing an FPGA architecture, the method comprising the following steps:

S1: Obtain a first loading instruction to load a target architecture file for describing an FPGA architecture and a resource mapping file for mapping hardware resources.

S2: Based on the target architecture file and the resource mapping file, construct a first two-dimensional array, wherein the first two-dimensional array is used to record the location information and type information of each basic construction unit in sequence.

S3: Based on the position information and type information of each basic construction unit recorded in the first two-dimensional array, each basic construction unit is instantiated, an instance corresponding to each basic construction unit is generated, and a first matrix is generated, wherein the first matrix includes the position information, color information, site information and clock information of each basic construction unit.

S4: Release the resources of the first two-dimensional array.

S5: constructing a first key-value mapping dictionary based on the first matrix; wherein the key of the first key-value mapping dictionary is the location information of each basic construction unit, and the value of the first key-value mapping dictionary is the instance corresponding to each basic construction unit.

S6: Release the resources of the first matrix.

S7: Generate a visualization file according to the information in the first key-value mapping dictionary.

The present invention has at least the following beneficial effects:

When visualizing the target architecture file, first obtain the first loading instruction, load the target architecture file and the resource mapping file for mapping hardware resources according to the first loading instruction, and construct the first two-dimensional array according to the target architecture file and the resource mapping file, then generate the first matrix according to the first two-dimensional array, and release the resources of the first two-dimensional array to reduce the pressure of memory resources. Then generate the first key-value mapping dictionary according to the first matrix, and release the memory resources of the first matrix to reduce the pressure of memory resources, and finally construct the visualization file according to the information in the first key-value mapping dictionary, which reduces the waste of memory resources, and the visualization method is more convenient and improves work efficiency.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

FIG1 is a flow chart of a method for visualizing an FPGA architecture according to an embodiment of the present invention.

Detailed ways

The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

1 , an embodiment of the present invention provides a method for visualizing an FPGA architecture, comprising the following steps:

S1: Obtain a first loading instruction to load a target architecture file for describing an FPGA architecture and a resource mapping file for mapping hardware resources.

Specifically, the first loading instruction is an instruction to select the "load architecture information" button in the software. After the selection, the technicians in this field determine the target architecture file according to actual needs. The first loading instruction can be input through a human-computer interaction device such as a mouse, keyboard, touch screen, etc., which will not be repeated here.

Specifically, the resource mapping file is used to describe the color, size and other information of each subsequent module.

S1 includes the following steps:

S11: After acquiring the first loading instruction, locate to a first preset folder, wherein the first preset folder contains the architecture file to be loaded.

Specifically, the first preset folder is a folder set by technical personnel in the field for storing architecture files. Technical personnel in the field can change the path of the first preset folder according to their own needs. In this embodiment, the default path of the first preset folder is the resource folder under the root directory of the software. Technical personnel in the field can also choose other folders.

S12: Obtain a first selection instruction input by the user, and use the architecture file selected by the first selection instruction as the target architecture file.

S12 includes the following steps:

S121: Triggering a file selection dialog box.

S122: Filter out files in the first preset folder that are in a format different from that of the architecture file to be loaded through a filter, so that the file selection dialog box only displays files in the same format as that of the architecture file to be loaded.

S123: Obtain the architecture file selected by the user.

S124: Determine whether the architecture file selected by the user is a correct architecture file. If so, use the architecture file selected by the user as the target architecture file.

S125: When it is determined that the architecture file selected by the user is an incorrect architecture file, an error prompt message is generated and S123 is re-executed.

Specifically, the function of filtering files having a format different from that of the architecture file to be loaded is implemented through Qt's file dialogue component QFileDialog and a filter.

As described above, only preset fixed-type files are displayed, which reduces the probability of users selecting the wrong file type and improves robustness.

Specifically, in this embodiment, the architecture file format is in json format.

As mentioned above, the json format is clear and easy to read. It can be opened and viewed or edited directly in the code editor, which is convenient for developers and users to view and understand the data content. Almost all programming languages provide json parsing libraries, which means that no matter which language other users are good at, they can easily read and process json data. And json has a fast parsing speed and can load and process data efficiently. Data in json format is easy to modify and expand, and new attributes can be added without changing the existing data structure. To support new chips or new resource types, just add or update the relevant entries in the json file. json is one of the standard formats for front-end and back-end communication. Even if the service needs to be deployed in the cloud, the server and client can easily exchange data through json, which facilitates data synchronization between the server and the client. json files are text files, which makes them very convenient to port between different systems and networks, share data between different software and tools, and promote the interoperability and portability of the tool chain. The data structure and attributes of the architecture resources are standardized, and other developers can focus on other key functions of the software instead of dealing with compatibility issues of data formats. In multi-person collaborative projects, standardized data structures help reduce communication costs and improve development efficiency. JSON files are easy to incorporate into version control systems, such as Git, to facilitate tracking of historical changes and collaborative work. Modifications to files can be clearly displayed through differences, which facilitates code review and change management. JSON objects are usually self-describing, containing key-value pairs, where the key describes the purpose of the value, which makes the purpose and usage of the data structure more obvious. Without the need for additional metadata or schema definition, developers can understand the structure and intent of the data directly from the JSON data.

Specifically, the first selection instruction may be inputted by a mouse, a touch screen or other devices capable of performing information interaction with a computer, which will not be described in detail herein.

As described above, when a technician in this field selects an architecture file that is not in json format, an error prompt message is generated to remind the technician in this field, thereby reducing the probability of loading an erroneous architecture file and improving work efficiency.

S2: Based on the target architecture file and the resource mapping file, a first two-dimensional array is constructed, where the first two-dimensional array is used to sequentially record the location information and type information of each basic construction unit.

S3: Based on the position information and type information of each basic construction unit recorded in the first two-dimensional array, each basic construction unit is instantiated, an instance corresponding to each basic construction unit is generated, and a first matrix is generated, wherein the first matrix includes the position information, color information, site information and clock information of each basic construction unit.

S4: Release the resources of the first two-dimensional array.

As described above, after the first matrix is constructed, the memory resources occupied by the first two-dimensional array are released, thereby reducing the occupation of memory resources and optimizing the memory usage efficiency.

S5: Based on the first matrix, construct a first key-value mapping dictionary, where the key of the first key-value mapping dictionary is the location information of each basic construction unit, and the value of the first key-value mapping dictionary is the instance corresponding to each basic construction unit.

As described above, constructing the first key-value mapping dictionary according to the first matrix can optimize the access speed and facilitate subsequent rapid retrieval and updating of the status of the basic construction unit.

S6: Release the resources of the first matrix.

In the above, after the first key-value mapping dictionary is constructed, the memory resources occupied by the first matrix are released, which further reduces the occupation of memory resources and optimizes the usage efficiency.

S7: Generate a visualization file according to the information in the first key-value mapping dictionary.

Specifically, this embodiment uses the Qt5 graphical interface for visualization. The Qt5 graphical interface will draw the physical layout of the FPGA based on the basic construction units and corresponding instances stored in the first key-value mapping dictionary, and generate visual features such as size and color of the target architecture file in combination with the resource mapping file, so that the graphical interface is more intuitive, which is convenient for technical personnel in this field to efficiently process complex FPGA structures and improve work efficiency.

S8: Visually displaying the chip architecture according to the visualization file, including:

The visualization file is analyzed to obtain architecture information of the chip, wherein the architecture information includes dimension and size data of the chip.

According to the architecture information of the chip, the view layout on the display interface is automatically adjusted so that the entire chip architecture is properly displayed on the display interface.

As described above, the view layout on the display interface is appropriately displayed according to the architecture information of the chip, which is helpful for the user to control the architecture of the chip during the design process.

S9: Manually adjust the view of the chip architecture on the display interface according to the adjustment instruction.

S9 includes the following steps:

S91: Acquire adjustment instructions, which include interactive zoom instructions, view rotation instructions, module highlighting and information prompting instructions, and dynamic rendering instructions.

S92: When the adjustment instruction is an interactive zoom instruction, switching the macro overview and micro details on the display interface according to the interactive zoom instruction, wherein the interactive zoom instruction includes the user sliding a mouse wheel to zoom in or out the view.

S93: When the adjustment instruction is a view rotation instruction, the chip view on the display interface is rotated according to the view rotation instruction to display the architecture layout from different angles.

S94: When the adjustment instruction is a module highlighting and information prompting instruction, a specific module and the name of the specific module are highlighted on the display interface according to the module highlighting and information prompting instruction, wherein the module highlighting and information prompting instruction includes the user hovering the mouse over the specific module.

S95: When the adjustment instruction is a dynamic rendering instruction, dynamically render the chip view on the display interface.

As mentioned above, when rendering is performed in a dynamic rendering manner, the view on the display area will be dynamically rendered as the user operates. This means that every action of the user - whether it is zooming, rotating or module querying - will be reflected instantly on the interface, without waiting for a long time to load, further improving work efficiency.

Specifically, it also includes:

When it is detected that the user focuses on a certain position of the chip with the mouse, the user zoom level is dynamically calculated:

When zoomed in to a first preset multiple, the module names within the current display interface are displayed.

Specifically, the steps of displaying the module names within the current display interface include:

When the module name hiding instruction is obtained, the module name in the display area is hidden.

When the module name display instruction is obtained, the module name hidden in the display area is displayed.

As described above, the module names in the display area are displayed or hidden according to actual needs, which is convenient for designers to design chip layout.

Additionally, the following steps are included:

When the internal module display instruction is obtained and the image is enlarged to a second preset multiple, the internal site information of the logical resource is displayed, wherein the site information is pre-defined in the architecture file and the resource mapping file.

When the internal module hiding instruction is obtained, the site information of the internal module displayed in the display area is hidden.

Among them, the first preset multiple and the second preset multiple are set by technicians in this field according to actual needs, and will not be repeated here.

The present embodiment provides a method for visualizing an FPGA architecture. When visualizing a target architecture file, first obtain a first loading instruction, load the target architecture file and a resource mapping file for mapping hardware resources according to the first loading instruction, and construct a first two-dimensional array according to the target architecture file and the resource mapping file. Then, generate a first matrix according to the first two-dimensional array, and release the resources of the first two-dimensional array to reduce the pressure of memory resources. Then, generate a first key-value mapping dictionary according to the first matrix, and release the memory resources of the first matrix to reduce the pressure of memory resources. Finally, construct a visualization file according to the information in the first key-value mapping dictionary, thereby reducing the waste of memory resources, and the visualization method is more convenient and improves work efficiency.

Although some specific embodiments of the present invention have been described in detail by way of example, it will be appreciated by those skilled in the art that the above examples are provided for illustration only and are not intended to limit the scope of the present invention. It will also be appreciated by those skilled in the art that various modifications may be made to the embodiments without departing from the scope and spirit of the present invention. The scope of the present invention is defined by the appended claims.

Claims (10)

1. An FPGA architecture visualization method, the method comprising the steps of:

S1: acquiring a first loading instruction, and loading a target architecture file for describing an FPGA architecture and a resource mapping file for mapping hardware resources;

s2: constructing a first two-dimensional array based on the target architecture file and the resource mapping file, wherein the first two-dimensional array is used for sequentially recording the position information and the type information of each basic construction unit;

S3: instantiating each basic construction unit based on the position information and the type information of each basic construction unit recorded in the first two-dimensional array, generating an instance corresponding to each basic construction unit, and generating a first matrix, wherein the first matrix comprises the position information, the color information, the site information and the clock information of each basic construction unit;

S4: releasing the resources of the first two-dimensional array;

S5: constructing a first key value mapping dictionary based on the first matrix; wherein the keys of the first key value mapping dictionary are position information of each basic construction unit, and the values of the first key value mapping dictionary are examples corresponding to each basic construction unit;

s6: releasing the resources of the first matrix;

s7: and generating a visual file according to the information in the first key value mapping dictionary.

2. The method according to claim 1, wherein S1 comprises the steps of:

S11: after the first loading instruction is acquired, positioning to a first preset folder, wherein the first preset folder comprises a framework file to be loaded;

S12: and acquiring a first selection instruction input by a user, and taking the architecture file selected by the first selection instruction as a target architecture file.

3. The method according to claim 2, wherein said step S12 comprises:

s121: triggering a file selection dialog;

S122: filtering out files with different file formats from the architecture file formats to be loaded in the first preset folder through a filter, so that the file selection dialog box only displays files with the same file formats as the architecture file formats to be loaded;

S123: acquiring a framework file selected by a user;

s124: judging whether the architecture file selected by the user is a correct architecture file, if so, taking the architecture file selected by the user as a target architecture file.

4. A method according to claim 3, characterized in that the method further comprises:

s125: when it is determined that the architecture file selected by the user is an erroneous architecture file, an error hint is generated and S123 is re-executed.

5. The method according to claim 1, wherein the method further comprises:

s8: and visually displaying the chip architecture according to the visual file, wherein the visual file comprises the following steps:

Analyzing the visual file to obtain the architecture information of the chip, wherein the architecture information comprises the dimension and the size data of the chip;

and according to the architecture information of the chip, automatically adjusting the view layout on the display interface, so that the whole chip architecture is properly displayed on the display interface.

6. The method of claim 5, wherein the method further comprises:

s9: and manually adjusting the view of the chip architecture on the display interface according to the adjustment instruction.

7. The method according to claim 6, wherein the step S9 includes:

Acquiring an adjustment instruction, wherein the adjustment instruction comprises an interactive zoom instruction, a view rotation instruction, a module highlighting and information prompting instruction and a dynamic rendering instruction;

When the adjustment instruction is an interactive zoom instruction, switching a macroscopic overview and microscopic details on a display interface according to the interactive zoom instruction, wherein the interactive zoom instruction comprises a user sliding a mouse wheel to zoom in or out the view;

when the adjustment instruction is a view rotation instruction, rotating a chip view on a display interface according to the view rotation instruction, and displaying architecture layout from different angles;

When the adjustment instruction is a module highlighting and information prompting instruction, highlighting a specific module and the name of the specific module on a display interface according to the module highlighting and information prompting instruction, wherein the module highlighting and information prompting instruction comprises a user hovering a mouse on the specific module;

and when the adjustment instruction is a dynamic rendering instruction, dynamically rendering the chip view on the display interface.

8. The method of claim 7, wherein the method further comprises:

when the user is monitored to focus on a position of the chip through the mouse, dynamically calculating the zoom level of the user:

And when the first preset multiple is enlarged, displaying the module name in the current display interface range.

9. The method according to claim 7 or 8, characterized in that the method further comprises:

when a module name hiding instruction is acquired, hiding the module name in the display area;

When a module name display instruction is acquired, the module name hidden in the display area is displayed.

10. The method of claim 5, wherein the method further comprises:

The adjustment instructions further include an internal module site information display instruction and an internal module site information hiding instruction,

When an internal module display instruction is acquired and amplified to a second preset multiple, internal site information of the logic resource is displayed, wherein the site information is predefined in a framework file and a resource mapping file;

when the internal module hiding instruction is acquired, the site information of the internal module displayed in the display area is hidden.