CN1181527C - Non-contact, non-invasive method of sorting CMOS chips - Google Patents
Non-contact, non-invasive method of sorting CMOS chips Download PDFInfo
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- CN1181527C CN1181527C CNB991020812A CN99102081A CN1181527C CN 1181527 C CN1181527 C CN 1181527C CN B991020812 A CNB991020812 A CN B991020812A CN 99102081 A CN99102081 A CN 99102081A CN 1181527 C CN1181527 C CN 1181527C
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Abstract
A method for testing an integrate circuit by utilizing, such as, a on-chip testing circuit of an induction coil having non-contact emitting element can magnetically induct output of the testing circuit by utilizing a non-contact, non-invasive method. A non-contact power coupling element having a on-chip induction coil can be used to activate an active circuit element to generate a voltage over the power coupling element. Power and magnetic detection provided by using induction enable the velocity of on-chip clock exceed 10 MHz. Said method overcomes limit caused by size of scribing groove and can be applied for a multi-chip wafer in a wafer manufacturing process, meaning that the method can be applied in an intermediate step, especially in an early step.
Description
Technical field
The present invention relates in general to the design and the manufacturing of semiconductor and IC, relates in particular to by using noncontact, non-intruding magnetic induction check to have improving one's methods such as the disk of the micro semiconductor element of complementary metal-oxide-semiconductor (CMOS) device.
Background technology
Modern electronic equipment uses various integrated circuits to carry out various logic functions, comprises for example simple designs of wrist-watch, and comprises for example more complicated design of data handling system.Integrated circuit (IC) is basically by for example gate, amplifier, and many interconnected circuit elements such as inverter are formed, and these interconnected circuit elements are by for example transistor, and diode, electronic components such as resistance constitute.These elements all are microminiaturized, are produced on the common substrate.
The substrate of integrated circuit is made of the semi-conducting material such as silicon or germanium, with certain distribution to these materials mix (mixing) with specific impurity produce solid-state components, for example complementary metal-oxide-semiconductor (CMOS) device.IC can be an individual layer, forms interconnecting lead between the circuit element on the substrate; Also can be multilayer, form interconnection vias at adjacent layer and non-adjacent interlayer.
The IC chip is generally made by the disk processing technology.According to this method, bigger semiconductor wafer at first is processed to thin type plain film (disk), and is usually rounded.Mixed or etching in the surface of disk then, may form multilayer, to form many chips on single disk, promptly each chip can separate from disk separately, to use as individual devices.Chip on the given disk can be identical, the chip of the difference in functionality type that also can distribute on single disk.Disk physics is cut into small pieces so that chip (IC) is separated.Connect upper conductor (interconnecting with other electronics or power circuit after being used for) for then each IC, and be encapsulated in the protecting sheathing.Can produce many chips by a disk.
ICs is especially as a large amount of computer components, microprocessor for example, application-specific integrated circuit (ASIC) (ASICs), ancillary equipment, controller, random access memory etc.Along with the appearance of high-speed computer, higher for the job requirement of this ICs, for example require it to be operated in 100MHz or higher.Owing to have only chip operation under extra high speed, some defective just may be found, and some defective that therefore is used for the IC of supercomputing often is difficult to be detected in manufacture process.Thereby be necessary to be provided for technology near test I Cs under the condition of work.
Invented the method that is used to test the CMOS chip that is connected to suitable testing equipment by the IC lead-in wire.This testing equipment detects (scanning) various logic signal, and provides power to the various test circuits on the chip.Yet the IC that is used to test lead-in wire requires chip to small part packed (if not exclusively encapsulation).Hope can be determined chip failing before encapsulation, therefore needn't carry out the encapsulation step of back to test result for the chip that lost efficacy.
In manufacture process, especially wish to determine as early as possible chip failing.The typical CMOS chip processes of making comprises about 120 steps, and wherein only about half of step is used to form actual circuit element, and only about half of step is used to form the interconnection of element.If along with the carrying out of manufacture process, can then needn't carry out (costliness) manufacturing step of back again at each step test chip.
Prior art also comprises the method that the lead-in wire that allows self-testing unit or probe and circuit element on the chip directly contact, and does not require that outside lead is connected to IC earlier.Yet contact owing to will carry out actual physical with the element on chip or the chip, therefore this method may be brought the problem of damage chip.Other intrusion measuring technology can reduce the rate of finished products of disk, only forms damage sometimes after test, therefore, may show working properlyly at the test period chip, but becomes inefficacy thereafter.By on disk, provide scribe line (kerf) structure to make damage reduce to minimum in abutting connection with the chip place, the test circuit in this structure is used for determining whether this chip is qualified.Yet use the scribe line to be difficult to the bigger chip of test, promptly this scribe line of measuring distance has circuit (the being positioned at chip edge) part of suitable distance.
Summary of the invention
According to the above, be desirable to provide and detect improving one's methods of integrated circuit defect, make and can in chip manufacturing proces, carry out in one or more intermediate steps, and avoid damaging chip.If this method can more early be applied to any part or any element of circuit, no matter and the Edge Distance distance of they and chip, then this method is more superior.
An object of the present invention is to provide the method for distinguishing the inefficacy integrated circuit.
Another object of the present invention provides the method that can realize in the one or more intermediate steps of disk manufacturing.
Another purpose of the present invention provides noncontact and non-invasive method, to avoid test chip is caused damage.
A kind of method of testing integrated circuits can achieve the above object, it generally includes following steps: make a plurality of circuit elements on the substrate of integrated circuit, be at least a circuit element and form the test circuit that comprises the noncontact radiated element, and excitation has this circuit element of this test circuit, thereby can survey the output of this test circuit with noncontact, non-invasive method by this radiated element.This method can promptly be applied to the intermediate steps of manufacture process in The field during the disk processing on the disk of multicore sheet, is particularly useful in the early stage step, and for example behind the deposit polysilicon layer, but before one or more layers metal of deposit on the polysilicon layer.
Can utilize on the same substrate of integrated circuit to form noncontact power coupling element and come, thereby make this power coupling element generation voltage by the magnetic field of applying variation for this induction coil to tested circuit element power supply (excitation is provided) with induction coil on the sheet.This noncontact radiated element equally also comprises inductance coil, can monitor the output of this test circuit like this by the magnetic induction technology.Use inductive power supply and magnetic induction to allow to surpass the clock test of 10 megahertzes with speed on the sheet.Use the noncontact tie point also to overcome a difficult problem relevant with the scribe line size.
Description of drawings
In the detailed text description below, above-mentioned and other purpose of the present invention, characteristics and advantage will more manifest.
The detailed description of following illustrated execution mode can be understood the present invention itself, best occupation mode, further purpose and advantage thereof better below reading in conjunction with the drawings, wherein:
Fig. 1 is the plane graph of an execution mode of the multi-chip semiconductor disk that constitutes according to the present invention, can be at the various circuit elements of the early stage test chip (integrated circuit) of disk manufacture process;
Fig. 2 is that the details of Fig. 1 is described, and expresses a chip, relevant scribing sheet groove structures, and the several noncontacts that are used for observation circuit, non-intruding tie point;
Fig. 3 is the schematic diagram that is used to illustrate the power coupling element of the active circuit on the chip that is used for encouraging Fig. 2;
Several figure of Fig. 4 represent level relevant with the power coupling element of Fig. 3 and the foreign current that is used to encourage this power coupling element, and the output voltage of the oscillator of Fig. 5; And
Fig. 5 is the schematic diagram of ring oscillator of the voltage tester of the power coupling element that can utilize Fig. 3 that forms in the chip of Fig. 2, and it provides the radiated element of the output that is connected to this oscillator.
Embodiment
With reference now to accompanying drawing,, Fig. 1 particularly, it has represented an execution mode of the semiconductor wafer 10 that constitutes according to the present invention.Disk 10 provides a common substrate for a plurality of independently integrated circuits (or chip 12), and Fig. 2 has expressed in a plurality of integrated circuits (or chip).The method that the purpose of this invention is to provide in ic manufacturing process early stage testing integrated circuits is especially when they still are present on the public disk 10 with the form of chip 12.Therefore, though the state of disk 10 as shown in the figure may comprise last state (wherein all chips 12 have substantially all been finished manufacturing), the present invention also is used for the one or more intermediate steps test chips 12 made in the manufacture process of disk.
In the illustrated embodiment, each chip 12 substantially all is identical, promptly carry out same production stage simultaneously and form these chips, by being used on disk 10, producing the figure that the mother matrix (reticle) (lithography tool) that repeats graphics chip forms each chip.Also can make disk 10 with other semi-conducting material, for example silicon or germanium carry out suitable doping as requested and produce circuit element and interconnection.Can utilize conventional method (deposit, etching etc.) to form element and interconnection.Chip 12 can also be a single or multiple lift.
With reference to figure 2, can be virtually any size and shape according to the given chip 12 of concrete application; Preferably adopt rectangle, can make surperficial utilance the best of disk 10 like this.Edge at chip 12 forms scribing sheet groove structures 14, and it may comprise the conventionally test circuit that is used to measure this chip.Scribe line 14 has several pads (not showing), is used for producing physics with external testing lead-in wire and probe and contacts.In addition, provide a plurality of noncontacts, non-intruding tie point, with the circuit element in each intermediate steps test chip 12 of making at disk 10.These tie points comprise a plurality of power coupling elements 16, and a plurality of radiated element 18 (size of illustrated scribe line 14 and tie point 16 and 18 is also disproportionate with respect to the overall size of chip 12).
In Fig. 3, further express the power coupling element 16 that the circuit that is used in the test chip 12 produces power.In the present embodiment, power coupling element 16 comprises sheet interior loop 20, and it is connected to diode bridge 22, and its output is in parallel with electric capacity 24 and resistance 26, produces the output voltage V dd that is used for on-chip test circuit.Coil 20 utilizes external coil 28 induced powers that have alternating current Iext to flow through.Fig. 4 has illustrated Iext, the relation between Vdd and the Vrect (the absolute output of diode bridge).
Voltage from power coupling element 16 can provide power for the various circuit in the chip 12, ring oscillator 30 for example shown in Figure 5.Ring oscillator 30 comprises a plurality of inverters 32, and their output couples together, and the signal Vosc that can be used as clock (oscillator) is provided for other circuit element on the chip 12.The output of ring oscillator 30 can be delivered to radiated element 18, and radiated element 18 comprises a divider 34, and its output is connected to coil 36 on another sheet.Utilize a magnetic induction signal that 38 read coil 36 produce to check the accuracy of ring oscillator 30.Inductive head 38 can adopt the induction coil of another kind of form, and magnetic resistance (MR) detector is better as is known in the industry perhaps to adopt example, the magnetoresistive element that it uses resistance to change with the magnetic field that changes.
Those skilled in the art will appreciate that, except ring oscillator, also can monitor many other active circuits.Also can utilize the MR head directly to respond to the data of surveying from chip in addition exports.Can make use modulation and load-modulate technology.The field modulation is modulated (AM) or frequency modulation(FM) (FM) electric current to rf amplitude and is added on the coil 20.This AM or FM signal have comprised the information that chip is transmitted to external test arrangements.Same induction coil (28 and 20) system also is used to accept to send to from testing apparatus the low frequency power signal of chip, and the data transmission of chip is returned testing apparatus.Except being connected in parallel the other variableimpedance with coil 20, load-modulate is similar with a modulation technique.This variableimpedance is transmitted to the data-modulated of external test arrangements from chip at high band.Consequently the impedance in the high band inductive coupler coils changes, and therefore is detected in testing apparatus.These two kinds of methods all require to start the stand-by period (startup latencies), have therefore limited the Validity Test flow.It is preferred forms that MR surveys.
The complexity of test circuit is as requested arranged the tie point 16 and 18 on the chip 12.Can finish test with the single power head (coil 28) and the single detecting head (MR detecting head 38) that move in proper order near each tie point, or the use power head of working simultaneously and certain combination (for example encouraging many ring oscillators with two power head) of detecting head.Scribe line 14 also can have the noncontact tie point, and these tie points can be used for the non-intruding test of the intermediate steps that disk makes like this, and the physics contact pad in the scribe line 14 can be used for after disk machines.Final step before any damage that produces in the chip scribe line when testing in this way all only is created in packaging and testing.After this test can utilize the outside lead that is connected to this IC to finish after encapsulation.Also can provide power to circuit, monitor this circuit with a noncontact launch point by the physics contact pad of scribe line.
Though present embodiment has illustrated the disk manufacturing process of having made many chips on the disk, yet the present invention can certainly be applied to have only on each disk the chip manufacturing process of a chip.
Major advantage of the present invention is field monitoring IC in the disk manufacture process, and can therefore can early not determine the ICs that lost efficacy in the course of processing owing to producing damage with direct contact of test lead or probe.For example can be after making the polysilicon layer of disk 10, begin test before which floor metal of deposit thereon.In addition, utilize prior art, use the induced power coupling test is tested with the speed up to 10-100MHz, therefore make the present invention can be applied to the element of high speed processing system with the magnetic resistance detector.The present invention has also overcome the restriction of scribe line physical dimension, no matter how far circuit can be tested apart from the edge of chip.
Though the present invention describes in conjunction with concrete execution mode, this description does not have limiting meaning.For those those skilled in the art that describe with reference to the present invention, the various modifications of disclosed execution mode and other execution mode of the present invention all are conspicuous.Therefore can give these modifications of phase and not break away from the defined the spirit and scope of the present invention of additional claims.
Claims (20)
1. the method for a testing integrated circuits comprises the following steps:
On the substrate of integrated circuit, make a plurality of circuit elements;
Be at least a circuit element and form test circuit, this test circuit comprises the noncontact radiated element;
Excitation has this circuit element of this test circuit; And
On this radiated element, survey the output of this testing element.
2. the process of claim 1 wherein:
This integrated circuit is first integrated circuit;
These a plurality of circuit elements are first circuit element groups;
This test circuit is first test circuit;
This noncontact radiated element is the first noncontact radiated element; And
The substrate of this integrated circuit is the disk of carrying second integrated circuit, and wherein this method is further comprising the steps of:
On the substrate of second integrated circuit, make second circuit element group,
A second circuit element that is at least in the second circuit element group forms second test circuit, and this second test circuit comprises the second noncontact radiated element,
Excitation has this circuit element of second test circuit,
On second radiated element, survey the output of second test circuit.
3. the process of claim 1 wherein that described manufacturing step comprises the making polysilicon layer, also be included in one or more layers metal of deposit on this polysilicon layer, wherein said depositing step carries out after described excitation and detection steps.
4. the process of claim 1 wherein:
Described manufacturing step comprises makes the oscillator that frequency is at least 10MHz; And
Described detection steps comprises the output frequency that detects radiated element.
5. the process of claim 1 wherein to have scribing sheet groove structures, and described formation step is produced on radiated element within the edge at described integrated circuit edge.
6. the method for claim 1 also is included in the step of making noncontact power coupling element on this integrated circuit, and wherein said incentive step is included in the step that produces voltage on this power coupling element.
7. the method for claim 6, wherein
This power coupling element comprises the induction coil that is produced on this substrate; And
Described generation step comprises the step that described induction coil is applied the magnetic field of variation.
8. the process of claim 1 wherein:
This noncontact radiated element comprises the induction coil that is produced on this substrate; And
Described sensing step comprises the magnetic induction head is placed near the induction coil of noncontact radiated element.
9. the method for claim 8 also is included in the step of making noncontact power coupling element on this integrated circuit, and wherein said incentive step is included in the step that produces voltage on this power coupling element.
10. the method for claim 9, wherein:
Described manufacturing step comprises makes the step that frequency is at least the oscillator of 10MHz; And
Described detection steps comprises the step of the output frequency that detects radiated element.
11. an integrated circuit comprises:
Substrate;
Be produced on a plurality of circuit elements on the described substrate; And
Be produced on the described substrate, be used to test the device of at least one described circuit element, described testing apparatus comprises the noncontact radiated element.
12. a semiconductor wafer has a plurality of integrated circuits, described integrated circuit comprises: substrate; Be produced on a plurality of circuit elements on the described substrate; And be produced on the described substrate, be used to test the device of at least one described circuit element, described testing apparatus comprises the noncontact radiated element.
13. the integrated circuit of claim 11, wherein:
Described circuit element comprises polysilicon layer and one or more layers metal; And
Described testing apparatus allows described at least one described circuit element of one or more layers metal Pretesting of deposit on described polysilicon layer.
14. the integrated circuit of claim 11, wherein:
Described at least one circuit element comprises that also frequency is at least the oscillator of 10MHz; And
Described test circuit produces periodically output signal on described radiated element.
15. the integrated circuit of claim 11 also comprises the scribing sheet groove structures that is positioned at this circuit element edge, described noncontact radiated element is positioned within the described edge.
16. the integrated circuit of claim 11, wherein said testing apparatus comprise the noncontact power coupling element of the device with excitation described at least one circuit element of work on described substrate.
17. the integrated circuit of claim 16, wherein:
Described exciting bank comprises the induction coil of work on described substrate.
18. the integrated circuit of claim 11, wherein:
Described noncontact radiated element comprises the induction coil of work on described substrate.
19. the integrated circuit of claim 18, wherein said testing apparatus comprise the noncontact power coupling element of the device with excitation described at least one circuit element of work on described substrate.
20. the integrated circuit of claim 19, wherein:
Described at least one circuit element comprises that also frequency is at least the oscillator of 10MHz; And
Described testing apparatus produces periodically output signal on described radiated element.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US3908098A | 1998-03-10 | 1998-03-10 | |
| US039080 | 1998-03-10 | ||
| US039,080 | 1998-03-10 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1242599A CN1242599A (en) | 2000-01-26 |
| CN1181527C true CN1181527C (en) | 2004-12-22 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB991020812A Expired - Fee Related CN1181527C (en) | 1998-03-10 | 1999-03-05 | Non-contact, non-invasive method of sorting CMOS chips |
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| Country | Link |
|---|---|
| CN (1) | CN1181527C (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108519550B (en) * | 2018-03-28 | 2020-06-23 | 上海华岭集成电路技术股份有限公司 | Integrated circuit wafer test optimization method |
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- 1999-03-05 CN CNB991020812A patent/CN1181527C/en not_active Expired - Fee Related
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| Publication number | Publication date |
|---|---|
| CN1242599A (en) | 2000-01-26 |
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