CN118151446A - Display panel - Google Patents

Abstract

The present invention provides a display panel including a first substrate, a plurality of scan lines, a plurality of data lines, a plurality of pixel structures, a common electrode layer, a peripheral wiring and a first shielding electrode. The first substrate has a display area and a peripheral area outside the display area. A plurality of scan lines and a plurality of data lines are arranged on the first substrate. These scan lines intersect with these data lines and define a plurality of pixel areas. A plurality of pixel structures are respectively arranged in these pixel areas, and each has an active element and a pixel electrode electrically connected to each other. The common electrode layer is arranged in the display area. The common electrode layer includes a plurality of common electrodes, and the plurality of common electrodes overlap the plurality of pixel electrodes of these pixel structures, and each common electrode is located between the first substrate and the corresponding pixel electrode. The peripheral wiring is arranged in the peripheral area. The first shielding electrode is arranged in the peripheral area and is located between the peripheral wiring and the pixel electrode. The first shielding electrode and the common electrode layer are formed on the first transparent conductive layer.

Description

Display Panel

Technical Field

The present invention relates to a display technology, and in particular to a display panel.

Background technique

With various display applications, display panels have long been prevalent in people's daily lives. In current display panels, the display of images is achieved by multiple pixel structures arranged in the display area. In order to transmit the control signal of the driver chip to these pixel structures, peripheral wiring is required in the peripheral area outside the display area. In recent years, in pursuit of higher visual experience and the appearance quality of the display, the visibility of displays with high screen-to-body ratio (such as borderless displays or ultra-narrow border displays) has gradually opened up in the market. However, while the display panel pursues a narrow border design, the circuit layout space in its peripheral area will be significantly reduced. Therefore, the peripheral wiring must often be arranged close to the edge of the display area, so that when the display panel is operated for a long time, the edge pixels in the display area are prone to accumulate charge and cause light leakage at the display edge due to the bias influence of the peripheral wiring.

Summary of the invention

The present invention is directed to a display panel with better display quality.

According to an embodiment of the present invention, a display panel includes a first substrate, a plurality of scan lines, a plurality of data lines, a plurality of pixel structures, a common electrode layer, a peripheral wiring and a first shielding electrode. The first substrate has a display area and a peripheral area outside the display area. A plurality of scan lines and a plurality of data lines are arranged on the first substrate. These scan lines intersect with these data lines and define a plurality of pixel areas. A plurality of pixel structures are respectively arranged in these pixel areas, and each has an active element and a pixel electrode electrically connected to each other. A common electrode layer is arranged in the display area. The common electrode layer includes a plurality of common electrodes. A plurality of common electrodes overlap a plurality of pixel electrodes of these pixel structures. Each common electrode is located between the first substrate and the corresponding pixel electrode. The peripheral wiring is arranged in the peripheral area. The first shielding electrode is arranged in the peripheral area and is located between the peripheral wiring and the pixel electrode. The first shielding electrode and the common electrode layer are formed on the first transparent conductive layer.

In the display panel according to the embodiment of the present invention, the peripheral wiring is formed on a metal layer located between the first substrate and the first transparent conductive layer.

In the display panel according to the embodiment of the present invention, a plurality of data lines or a plurality of scan lines are formed in the metal layer.

In the display panel according to the embodiment of the present invention, the peripheral wiring is a common electrode line or a wiring of a gate driving circuit.

In the display panel according to the embodiment of the present invention, the first shielding electrode extends from the common electrode layer, and the first shielding electrode and the common electrode layer are electrically connected to each other.

In the display panel according to the embodiment of the present invention, the first shielding electrode is electrically independent from the common electrode layer.

In the display panel according to the embodiment of the present invention, the first shielding electrode overlaps the peripheral wiring.

In the display panel according to the embodiment of the present invention, the display panel further comprises a second shielding electrode, which is arranged in the peripheral area and overlaps the peripheral wiring. The second shielding electrode is located between the peripheral wiring and the first shielding electrode.

In the display panel according to an embodiment of the present invention, the peripheral routing is formed on the first metal layer, the second shielding electrode is formed on the second metal layer, the first metal layer is located between the first substrate and the second metal layer, and the second metal layer is located between the first metal layer and the first transparent conductive layer.

In the display panel according to the embodiment of the present invention, the potential of the first shielding electrode is the same as the potential of the second shielding electrode.

In the display panel according to the embodiment of the present invention, the potential of the first shielding electrode is a common potential or a ground potential.

In the display panel according to the embodiment of the present invention, the display panel is an in-cell touch display panel.

Based on the above, in a display panel of an embodiment of the present invention, a plurality of pixel structures are provided in the display area, and a peripheral wiring is provided in the peripheral area outside the display area. The peripheral wiring is arranged adjacent to the display area. By arranging a shielding electrode between the peripheral wiring and the display area, it is possible to effectively prevent charges from accumulating on the pixel electrodes of the pixel structures adjacent to the peripheral area due to the bias of the peripheral wiring, thereby solving the light leakage phenomenon at the edge of the display area of the display panel after the reliability test.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic top view of a display panel according to a first embodiment of the present invention;

FIG2 is an enlarged schematic diagram of a local area of the display panel of FIG1 ;

FIG3 is a schematic cross-sectional view of the display panel of FIG2 ;

4 is a schematic top view of a display panel according to a second embodiment of the present invention;

FIG5 is an enlarged schematic diagram of a local area of the display panel of FIG4 ;

FIG6 is a schematic cross-sectional view of the display panel of FIG5 ;

7 is a schematic top view of a display panel according to a third embodiment of the present invention;

FIG8 is an enlarged schematic diagram of a local area of the display panel of FIG7 ;

FIG9 is a schematic cross-sectional view of the display panel of FIG8 ;

10 is a schematic top view of a display panel according to a variation of the third embodiment of the present invention;

FIG11 is a schematic top view of a display panel according to a fourth embodiment of the present invention;

FIG12 is an enlarged schematic diagram of a local area of the display panel of FIG11;

FIG. 13 is a schematic cross-sectional view of the display panel of FIG. 12 .

Description of Reference Numerals

10, 10A, 20, 30: display panel;

101: a first substrate;

101S: Surface;

102: a second substrate;

110: gate insulating layer;

120: first passivation layer;

130: second passivation layer;

150: liquid crystal layer;

170: light-shielding pattern layer;

170OP, OP: opening;

200: circuit block;

CE: common electrode;

CEL: common electrode layer;

CEP: common electrode pattern;

DA: display area;

DE: drain;

DL: data line;

GDC: gate drive circuit;

GE: gate;

GL: scan line;

GLW: gate signal line;

ML1, ML1-A: first metal layer;

ML2, ML2-A, ML2-B: second metal layer;

PA: peripheral area;

PE: pixel electrode;

PW, PW-A, PW-B: peripheral routing;

PX: pixel structure;

PXA: pixel area;

PXe: edge pixel structure;

PXR(1)~PXR(M): pixel structure row;

PXC(1)~PXC(N): pixel structure column;

SC: semiconductor pattern;

SE: source;

SHE1, SHE1-A, SHE1-B, SHE1-B’: first shielding electrodes;

SHE2, SHE2': second shielding electrodes;

STE: strip electrode;

T: active element;

TCL1, TCL1-A, TCL1-B: first transparent conductive layer;

TCL2: second transparent conductive layer;

VIA: contact hole;

W1, W2: width;

WA: wiring area;

X, Y, Z: direction;

Z1, Z2, Z3, Z3’, Z4: area;

A-A’, B-B’, C-C’, D-D’: section lines.

Detailed ways

Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

FIG. 1 is a schematic top view of a display panel according to a first embodiment of the present invention. FIG. 2 is an enlarged schematic view of a local area Z1 of the display panel of FIG. 1 . FIG. 3 is a schematic cross-sectional view of the display panel of FIG. 2 along the section line A-A'. For the sake of clarity, FIG. 1 omits the illustration of the scan line GL and the data line DL in FIG. 2 , and FIG. 2 omits the illustration of the second substrate 102, the gate insulating layer 110, the light shielding pattern layer 170 and the liquid crystal layer 150 in FIG. 3 .

1 to 3, the display panel 10 includes a first substrate 101, a second substrate 102 and a liquid crystal layer 150. The liquid crystal layer 150 is disposed between the first substrate 101 and the second substrate 102. That is, the display panel 10 of this embodiment is a liquid crystal display panel, but is not limited thereto.

The first substrate 101 is provided with a display area DA and a peripheral area PA outside the display area DA. The display panel 10 is provided with a plurality of scan lines GL, a plurality of data lines DL and a plurality of pixel structures PX in the display area DA, and is disposed on the surface 101S of the first substrate 101. The plurality of scan lines GL intersect with the plurality of data lines DL and define a plurality of pixel areas PXA. The plurality of pixel structures PX are respectively disposed in these pixel areas PXA. For example, in the present embodiment, the plurality of scan lines GL are arranged on the first substrate 101 along a direction Y (i.e., a first direction) at intervals, and the plurality of data lines DL are arranged on the first substrate 101 along a direction X (i.e., a second direction) at intervals, wherein the direction X is optionally perpendicular to the direction Y. Each scan line GL extends along the direction X, and each data line DL extends substantially along the direction Y. For example, the extension direction of each data line DL may be the direction Y, or the extension direction of each data line DL may have an angle with the direction Y (for example, but not limited to, an angle less than or equal to 15 degrees). Each pixel structure PX can be electrically connected to a scan line GL and a data line DL. More specifically, the pixel structures PX can be arranged into a plurality of pixel structure rows and a plurality of pixel structure columns along the direction X and the direction Y, respectively. For example, in the present embodiment, the plurality of pixel structures PX can be arranged into M pixel structure rows PXR(1) to PXR(M) and N pixel structure columns PXC(1) to PXC(N), where M and N are positive integers greater than 1.

The pixel structure PX in each pixel area PXA has an active element T, a common electrode CE and a pixel electrode PE, and the active element T and the pixel electrode PE are electrically connected to each other. For example, the active element T includes a gate GE, a source SE, a drain DE and a semiconductor pattern SC. Among them, the gate GE can be formed by a portion extending from the scan line GL. The semiconductor pattern SC is arranged to overlap the gate GE. It should be noted that the overlapping relationship here, for example, refers to the overlap of the semiconductor pattern SC and the gate GE along the direction Z. In the present embodiment, the direction Z may be a direction perpendicular to the surface 101S of the first substrate 101. If not specifically mentioned below, the overlapping relationship between the two components is defined in the same way, and the overlapping direction will not be repeated.

The semiconductor pattern SC can be used as a channel layer of the active device T, and the source electrode SE and the drain electrode DE are electrically connected to two different regions of the semiconductor pattern SC respectively. The material of the semiconductor pattern SC may include an amorphous silicon semiconductor, a single crystal silicon semiconductor, a polycrystalline silicon semiconductor, or a metal oxide semiconductor. In the present embodiment, the active device T is, for example, an amorphous silicon thin film transistor (a-Si TFT), but is not limited thereto. In other embodiments, the active device T may also be a polycrystalline silicon thin film transistor (polycrystalline silicon TFT, poly-Si TFT) or a metal oxide semiconductor thin film transistor (metal oxide semiconductor TFT). In some embodiments, an ohmic contact layer may be provided between the source electrode SE and the semiconductor pattern SC and between the drain electrode DE and the semiconductor pattern SC, and the material of the ohmic contact layer may be, for example, a doped amorphous silicon layer, but is not limited thereto.

In this embodiment, the gate GE is optionally disposed between the semiconductor pattern SC and the first substrate 101 to form a bottom-gate thin-film-transistor, but the present invention is not limited thereto. In other embodiments, the gate GE may also be disposed on a side of the semiconductor pattern SC away from the first substrate 101 to form a top-gate thin-film-transistor.

The step of forming the active device T may include: forming a gate GE, a gate insulating layer 110, a semiconductor pattern SC, a source electrode SE and a drain electrode DE in sequence on a first substrate 101, wherein the gate GE and the scan line GL may be formed on a first metal layer ML1, and the source electrode SE, the drain DE and the data line DL may be formed on a second metal layer ML2, but not limited thereto. The materials of the first metal layer ML1 and the second metal layer ML2 may include metal (e.g., molybdenum, aluminum, copper, nickel, chromium), alloys, nitrides of metal materials, oxides of metal materials, oxynitrides of metal materials, or other suitable materials, or stacked layers of metal materials and other conductive materials.

In the present embodiment, a first passivation layer 120 and a second passivation layer 130 are further provided between the pixel electrode PE and the active element T. The first passivation layer 120 is provided between the second passivation layer 130 and the active element T. The materials of the first passivation layer 120 and the second passivation layer 130 may include, for example, an inorganic insulating material, an organic insulating material, or a combination thereof, but are not limited thereto. In addition, the first passivation layer 120 and the second passivation layer 130 may each include a single-layer structure or a multi-layer stacked structure. In the present embodiment, the first passivation layer 120 and the second passivation layer 130 may have a contact hole VIA provided overlapping the drain DE of the active element T, and the pixel electrode PE is electrically connected to the drain DE of the active element T via the contact hole VIA, but are not limited thereto.

Furthermore, the display panel 10 is further provided with a common electrode layer CEL between the active element T and the pixel electrode PE, the common electrode layer CEL is arranged in the display area DA, and the common electrode layer CEL includes a plurality of common electrodes CE. The plurality of common electrodes CE of the common electrode layer CEL overlap the plurality of pixel electrodes PE of the plurality of pixel structures PX, and are arranged between the first passivation layer 120 and the second passivation layer 130. That is, the common electrode layer CEL is located between the first substrate 101 and the pixel electrode PE, but is not limited thereto. In the present embodiment, the common electrode CE of each pixel structure PX is located between the first substrate 101 and the corresponding pixel electrode PE, that is, the pixel structure PX of the present embodiment is a pixel structure with an upper pixel electrode and a lower common electrode.

In this embodiment, the common electrode layer CEL can be divided into a plurality of common electrode patterns CEP, each common electrode pattern CEP overlaps with a plurality of pixel areas PXA, and each common electrode pattern CEP includes a plurality of common electrodes CE electrically connected to each other, but the present invention is not limited thereto.

For example, the pixel electrode PE may include a plurality of strip electrodes STE and a plurality of openings OP. These strip electrodes STE and these openings OP may be arranged alternately along direction X, but are not limited thereto. In other embodiments, the plurality of strip electrodes STE and the plurality of openings OP may be arranged alternately along a direction different from direction X (e.g., direction Y). Each opening OP is located between two adjacent strip electrodes STE (as shown in FIG. 2 ). The electric field formed between the pixel electrode PE and the common electrode CE may control the direction of the liquid crystal molecules in the liquid crystal layer 150 through these openings OP to display the corresponding picture. In this embodiment, each common electrode CE may receive a common potential (Common Voltage), but is not limited thereto.

In the present embodiment, the pixel electrode PE and the common electrode layer CEL are each light-transmissive, and the manufacturing material thereof may be a transparent conductive material. For example, the transparent conductive material may include a metal oxide (e.g., indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, or other suitable oxides, or a stacked layer of at least two of the above), but is not limited thereto. In the present embodiment, the common electrode layer CEL may be formed on the first transparent conductive layer TCL1, and the pixel electrode PE may be formed on the second transparent conductive layer TCL2, and the first transparent conductive layer TCL1 is located between the first substrate 101 and the second transparent conductive layer TCL2.

It is particularly noted that in this embodiment, the display panel 10 may be a display panel with a touch function, such as an in-cell touch display panel. In addition to receiving a common potential during the display period of the display panel 10 to form an electric field with the pixel electrode PE to drive the liquid crystal molecules in the liquid crystal layer 150, the plurality of common electrode patterns CEP of the common electrode layer CEL may also serve as touch sensing electrodes during the touch period of the display panel 10, but the present invention is not limited thereto.

In the present embodiment, the display panel 10 is further provided with a circuit block 200 for driving a plurality of pixel structures PX in the peripheral area PA of the first substrate 101. For example, the circuit block 200 may include a gate driving circuit, a source driving circuit, a touch sensing circuit, or a combination thereof, but is not limited thereto. In other embodiments, the circuit block 200 may be disposed on a flexible printed circuit board, and the flexible printed circuit board is coupled to the pads located in the peripheral area PA of the first substrate 101; or the circuit block 200 may be disposed on a system printed circuit board, and the system printed circuit board is electrically connected to the pads located in the peripheral area PA of the first substrate 101 via the flexible printed circuit board.

The control signal of the circuit block 200 can be transmitted to the pixel structure PX in the display area DA, or the sensing signal in the display area DA can be transmitted to the circuit block 200. In addition, the display panel 10 also includes a peripheral routing line PW arranged in the peripheral area PA and extending on at least one side of the display area DA. It should be noted that, for the sake of clarity, only one peripheral routing line PW adjacent to the display area DA is shown in the peripheral area PA of Figure 1, which does not mean that the present invention is limited to the contents of the accompanying drawings. In other embodiments, the number, shape, position and type of the peripheral routing lines PW can be adjusted according to different application requirements. In this embodiment, the peripheral routing lines PW of Figures 1 to 3 are also formed in the second metal layer ML2 as are the source SE, drain DE and data line DL.

It is particularly noted that a peripheral line PW shown in Figures 1 and 2 is arranged close to the edge of the display area DA. This arrangement can minimize the layout space of the peripheral line PW in the peripheral area PA, thereby achieving a narrow frame design of the display panel 10.

In the present embodiment, the peripheral wiring PW of Figures 1 to 3 may be a common electrode line, and the common electrode line may receive a common potential, but is not limited to this. In the present embodiment, the peripheral wiring PW is arranged around the display area DA. However, the present invention is not limited to this. In other embodiments not shown, the peripheral wiring PW may also extend only within the peripheral area PA outside the left and right sides of the display area DA of Figure 1, or the peripheral wiring PW may also extend only within the peripheral area PA outside the left side of the display area DA of Figure 1 or within the peripheral area PA outside the right side. In the present embodiment, the extension direction of the peripheral wiring PW extending on the left and right sides of the display area DA may be roughly parallel to the direction Y, but is not limited to this.

In the present embodiment, a plurality of pixel structures PX may be arranged into M pixel structure rows PXR(1) to PXR(M) and N pixel structure columns PXC(1) to PXC(N), and the pixel structures PX located at opposite ends of each pixel structure row or the pixel structures PX located at opposite ends of each pixel structure column may be referred to as edge pixel structures PXe. In order to simplify the drawings, FIG. 1 only indicates a pixel structure PX located at one end of a pixel structure row as an edge pixel structure PXe for illustration. The edge pixel structure PXe is the pixel structure PX that is closest to the peripheral routing PW in each pixel structure row or each pixel structure column of the display panel 10. Therefore, in order to effectively avoid the coupling effect between the peripheral routing PW and the pixel electrode PE of the edge pixel structure PXe, which causes the charge to accumulate on the pixel electrode PE of the edge pixel structure PXe due to the bias voltage or DC signal of the peripheral routing PW, the display panel 10 is provided with a first shielding electrode SHE1 between the peripheral routing PW and the pixel electrode PE of the edge pixel structure PXe to shield the coupling effect of the peripheral routing PW on the pixel electrode PE of the edge pixel structure PXe.

In this embodiment, the first shielding electrode SHE1 may extend from the common electrode layer CEL. That is, the first shielding electrode SHE1 and the common electrode layer CEL may be formed on the same conductive film layer, that is, the first shielding electrode SHE1 and the common electrode layer CEL may be formed on the first transparent conductive layer TCL1 and connected to each other, so the first shielding electrode SHE1 and the common electrode layer CEL have the same potential. For example, the edge pixel structure PXe may be a pixel structure PX located at opposite ends of each pixel structure row of the pixel structure rows PXR(1) to PXR(M) (for example, a pixel structure PX located at the leftmost end and a pixel structure PX located at the rightmost end of each pixel structure row), and the first shielding electrode SHE1 may extend from the common electrode CE of the edge pixel structure PXe (for example, extending to the left from the common electrode CE of the pixel structure PX located at the leftmost end of each pixel structure row and extending to the right from the common electrode CE of the pixel structure PX located at the rightmost end of each pixel structure row to form the first shielding electrode SHE1), and the first shielding electrode SHE1 is located between the peripheral routing PW and the pixel electrode PE of the edge pixel structure PXe, but is not limited to this.

In order to effectively shield the electric field of the peripheral routing wire PW to avoid the pixel electrode PE of the edge pixel structure PXe from being affected, in the present embodiment, the first shielding electrode SHE1 may overlap at least a portion of the peripheral routing wire PW, but the present invention is not limited thereto. FIG. 3 shows that the first shielding electrode SHE1 overlaps a portion of the peripheral routing wire PW, that is, a portion of the orthographic projection of the peripheral routing wire PW on the first substrate 101 overlaps the orthographic projection of the first shielding electrode SHE1 on the first substrate 101, but the present invention is not limited thereto. In other embodiments, the first shielding electrode SHE1 may overlap the entire peripheral routing wire PW, that is, the entire area of the orthographic projection of the peripheral routing wire PW on the first substrate 101 overlaps the orthographic projection of the first shielding electrode SHE1 on the first substrate 101, but the present invention is not limited thereto.

In addition, because the first shielding electrode SHE1 extends from the common electrode layer CEL and is electrically connected to each other, and the common electrode pattern CEP of the common electrode layer CEL also serves as a touch sensing electrode during the touch control of the display panel 10, the width W1 of the first shielding electrode SHE1 is preferably not too large so as not to affect the touch accuracy of the display panel 10, but the present invention is not limited thereto. In the present embodiment, the first shielding electrode SHE1 is formed by extending from the common electrode layer CEL along a direction, and the first shielding electrode SHE1 has a width W1 in the extending direction, and the plurality of strip electrodes STE and the plurality of openings OP of the pixel electrode PE are alternately arranged along a direction, and the strip electrodes STE have a width W2 (or can be referred to as the short side width W2 of the strip electrodes STE) in the alternating arrangement direction, and the ratio of the width W1 of the first shielding electrode SHE1 to the width W2 of the strip electrodes STE can be, for example, less than or equal to 2, so as not to affect the touch accuracy of the display panel 10, but the ratio of the width W1 of the first shielding electrode SHE1 to the width W2 of the strip electrodes STE is not limited thereto. For example, in FIG. 3 , the first shielding electrode SHE1 is formed by extending from the common electrode layer CEL along a direction parallel to the direction X, the plurality of strip electrodes STE and the plurality of openings OP of the pixel electrode PE are alternately arranged along the direction X, and the ratio of the width W1 of the first shielding electrode SHE1 in the direction X to the width W2 of the strip electrode STE in the direction X may be less than or equal to 2, but is not limited thereto.

By setting the first shielding electrode SHE1, it is possible to effectively prevent charges from accumulating on the pixel electrode PE of the pixel structure PX adjacent to the peripheral area PA due to the bias influence of the peripheral wiring PW, thereby solving the light leakage phenomenon at the edge of the display area DA of the display panel 10 after a reliability test (e.g., long-term operation) and improving the display quality of the display panel 10.

On the other hand, the display panel 10 may further include a light shielding pattern layer 170 disposed on the second substrate 102. The light shielding pattern layer 170 has a plurality of openings 170OP, and these openings 170OP overlap with a plurality of pixel electrodes PE and a plurality of common electrodes CE of a plurality of pixel structures PX, respectively. From another point of view, the light shielding pattern layer 170 may overlap with the peripheral area PA, a plurality of scan lines GL, a plurality of data lines DL, and a plurality of active elements T, and its plurality of openings 170OP may overlap with the pixel electrode PE and a portion of the common electrode layer CEL, respectively.

Other embodiments will be listed below to explain the present disclosure in detail, wherein the same components will be marked with the same symbols, and the description of the same technical content will be omitted. For the omitted parts, please refer to the aforementioned embodiments and will not be repeated below.

FIG4 is a schematic top view of a display panel according to a second embodiment of the present invention. FIG5 is an enlarged schematic view of a local area Z2 of the display panel of FIG4. FIG6 is a schematic cross-sectional view of the display panel of FIG5 along the section line B-B'. For a clear presentation, FIG4 omits the illustration of the scan line GL and the data line DL in FIG5, and FIG5 omits the illustration of the second substrate 102, the gate insulating layer 110, the light shielding pattern layer 170 and the liquid crystal layer 150 in FIG6.

Referring to FIGS. 4 to 6 , the difference between the display panel 10A of the present embodiment and the display panel 10 of FIGS. 1 to 3 is that the first shielding electrode SHE1-A of the display panel 10A of the present embodiment does not overlap the peripheral wiring PW-A, wherein the peripheral wiring PW-A is adjacent to the display area DA. For example, the distance between the peripheral wiring PW-A of the present embodiment and the display area DA may be greater than the distance between the peripheral wiring PW of FIGS. 1 to 3 and the display area DA. Therefore, in order to effectively shield the electric field of the peripheral wiring PW-A, the width W1 of the first shielding electrode SHE1-A may be greater than or equal to the width W2 of the strip electrode STE of the pixel electrode PE (i.e., the ratio of the width W1 of the first shielding electrode SHE1-A to the width W2 of the strip electrode STE may be greater than or equal to 1), and it does not need to extend to the area overlapping the peripheral wiring PW-A to achieve an effective electric field shielding effect. In addition, because the first shielding electrode SHE1-A extends from the common electrode layer CEL and is electrically connected to each other, and the common electrode pattern CEP of the common electrode layer CEL also serves as a touch sensing electrode during the touch control of the display panel 10A, the width W1 of the first shielding electrode SHE1-A cannot be too large to avoid affecting the touch control accuracy of the display panel 10A. For example, the ratio of the width W1 of the first shielding electrode SHE1-A to the width W2 of the strip electrode STE may be less than or equal to 2.

In this embodiment, the peripheral wiring PW-A of Figures 4 to 6 and the source SE, drain DE and data line DL are also formed on the second metal layer ML2-A, and the first shielding electrode SHE1-A and the common electrode layer CEL are also formed on the first transparent conductive layer TCL1-A.

In the embodiments of Figures 1 to 6 above, the common electrode of each pixel structure is located between the first substrate and the pixel electrode, the peripheral wiring is formed on the second metal layer, the common electrode and the first shielding electrode are formed on the first transparent conductive layer, the pixel electrode is formed on the second transparent conductive layer, and the first shielding electrode is located between the peripheral wiring and the pixel electrode of the edge pixel structure, so the first shielding electrode of the first transparent conductive layer located between the second metal layer and the second transparent conductive layer can shield the electric field of the peripheral wiring.

Next, the embodiment of FIG. 7 to FIG. 13 will be used to illustrate the method of shielding the electric field of the peripheral wiring in the embodiment where the peripheral wiring is formed in the first metal layer.

FIG7 is a schematic top view of a display panel according to a third embodiment of the present invention. FIG8 is an enlarged schematic view of a local area Z3 of the display panel of FIG7. FIG9 is a schematic cross-sectional view of the display panel of FIG8 along the section line C-C'. For a clear presentation, FIG7 omits the illustration of the scan line GL, the data line DL and the second shielding electrode SHE2 in FIG8, and FIG8 omits the illustration of the second substrate 102, the gate insulating layer 110, the light shielding pattern layer 170 and the liquid crystal layer 150 in FIG9.

Please refer to FIGS. 7 to 9 . The difference between the display panel 20 of the present embodiment and the display panel 10 of FIGS. 1 to 3 is that the types of peripheral wiring and the setting method of the shielding electrode are different. For example, in the present embodiment, the peripheral wiring PW-B is adjacent to the display area DA, and the peripheral wiring PW-B can be formed in the first metal layer ML1-A like the gate GE and the scan line GL, and the number of the peripheral wiring PW-B can be one or more, but not limited thereto. In the present embodiment, FIG. 8 is an example in which the extension direction of the peripheral wiring PW-B is the same as the extension direction of the data line DL, but the extension direction of the peripheral wiring PW-B is not limited thereto.

It is particularly noted that, although the first shielding electrode SHE1-B and the common electrode layer CEL of the present embodiment are the same film layer (such as the first transparent conductive layer TCL1-B), unlike the first shielding electrode SHE1 of FIG. 3 , the first shielding electrode SHE1-B and the common electrode layer CEL of the present embodiment are structurally separated from each other (i.e., the first shielding electrode SHE1-B and the common electrode layer CEL are not connected to each other). In other words, the first shielding electrode SHE1-B of the present embodiment does not extend from the common electrode layer CEL. In addition, the first shielding electrode SHE1-B of the present embodiment may be electrically independent from the common electrode layer CEL, but is not limited thereto. For example, unlike the common electrode layer CEL having a common potential, the first shielding electrode SHE1-B may have a ground potential, but is not limited thereto.

On the other hand, the first shielding electrode SHE1-B is located between the peripheral routing wire PW-B and the pixel electrode PE of the edge pixel structure, and at least a portion of the peripheral routing wire PW-B overlaps with the first shielding electrode SHE1-B, that is, at least a portion of the orthographic projection of the peripheral routing wire PW-B on the first substrate 101 overlaps with the orthographic projection of the first shielding electrode SHE1-B on the first substrate 101. In the present embodiment, the orthographic projection of the peripheral routing wire PW-B on the first substrate 101 is located within the orthographic projection of the first shielding electrode SHE1-B on the first substrate 101. That is, the entire peripheral routing wire PW-B closest to the display area DA overlaps with the first shielding electrode SHE1-B, but is not limited thereto. In other embodiments, a portion of the peripheral routing wire PW-B may overlap with the first shielding electrode SHE1-B, that is, a portion of the orthographic projection of the peripheral routing wire PW-B on the first substrate 101 overlaps with the orthographic projection of the first shielding electrode SHE1-B on the first substrate 101.

In the present embodiment, the display panel 20 may further optionally include a second shielding electrode SHE2, which is disposed in the peripheral area PA. The second shielding electrode SHE2 is located between the peripheral wiring PW-B and the first shielding electrode SHE1-B, and the second shielding electrode SHE2 overlaps the peripheral wiring PW-B and the first shielding electrode SHE1-B to strengthen the electric field shielding of the peripheral wiring PW-B. For example, the second shielding electrode SHE2 may be formed on the second metal layer ML2-B in the same manner as the source SE, the drain DE and the data line DL. The second shielding electrode SHE2 may have the same potential as the first shielding electrode SHE1-B, but is not limited thereto. For example, the second shielding electrode SHE2 may have a ground potential as the first shielding electrode SHE1-B, but is not limited thereto.

In the present embodiment, at least a portion of the peripheral wiring PW-B overlaps with the second shielding electrode SHE2, that is, at least a portion of the orthographic projection of the peripheral wiring PW-B on the first substrate 101 overlaps with the orthographic projection of the second shielding electrode SHE2 on the first substrate 101. In FIG. 7, PW-B/SHE2 is used to represent the overlapping peripheral wiring PW-B and the second shielding electrode SHE2. In addition, at least a portion of the second shielding electrode SHE2 overlaps with the first shielding electrode SHE1-B, that is, at least a portion of the orthographic projection of the second shielding electrode SHE2 on the first substrate 101 overlaps with the orthographic projection of the first shielding electrode SHE1-B on the first substrate 101. In the present embodiment, the orthographic projection of the second shielding electrode SHE2 on the first substrate 101 is located within the orthographic projection of the first shielding electrode SHE1-B on the first substrate 101, but is not limited thereto. In other embodiments, a portion of the orthographic projection of the second shielding electrode SHE2 on the first substrate 101 is located within the orthographic projection of the first shielding electrode SHE1-B on the first substrate 101.

In summary, the peripheral trace PW-B overlaps the first shielding electrode SHE1-B and the second shielding electrode SHE2, that is, the orthographic projection of the peripheral trace PW-B on the first substrate 101 overlaps the orthographic projection of the first shielding electrode SHE1-B on the first substrate 101 and the orthographic projection of the second shielding electrode SHE2 on the first substrate 101. In addition, since the first shielding electrode SHE1-B and the second shielding electrode SHE2 disposed overlapping the peripheral trace PW-B have the same potential (e.g., ground potential), the electric field of the peripheral trace PW-B can be effectively shielded to prevent charges from accumulating on the pixel electrode PE of the edge pixel structure due to the bias of the peripheral trace PW-B, thereby solving the light leakage phenomenon at the edge of the display area DA of the display panel 20 after a reliability test (e.g., under long-term operation) and improving the display quality of the display panel 20.

7 shows that the peripheral traces PW-B of the first metal layer ML1-A are disposed around the display area DA, but the present invention is not limited thereto. In other embodiments, the peripheral traces of the first metal layer may be located only in the peripheral areas PA on opposite sides of the display area DA.

FIG. 10 is a schematic top view of a display panel according to a variant embodiment of the third embodiment of the present invention. Referring to FIG. 10 , the difference between the display panel 20A of the present embodiment and the display panel 20 of FIG. 7 to FIG. 9 is that the peripheral routing, the first shielding electrode and the second shielding electrode are arranged differently. Specifically, in the present embodiment, the gate driving circuit GDC of the display panel 20A is arranged in the peripheral area PA on the left and right sides of the display area DA, and the peripheral routing (not shown) located in the routing area WA of the gate driving circuit GDC overlaps the first shielding electrode SHE1-B' and the second shielding electrode SHE2'. In FIG. 10 , WA (GDC)/SHE2' is used to represent the second shielding electrode SHE2' and the peripheral routing located in the routing area WA of the gate driving circuit GDC that overlap each other. For example, the peripheral routing located in the routing area WA of the gate driving circuit GDC may be a gate signal line, which is electrically connected to the scan line (not shown) located in the display area DA, and transmits the gate driving signal generated by the gate driving circuit GDC to the corresponding scan line, but is not limited thereto. In this embodiment, the peripheral wirings located in the wiring area WA of the gate driving circuit GDC are also formed in the first metal layer as are the scanning lines.

In the present embodiment, the first shielding electrode SHE1-B' is disposed in the peripheral area PA located on the left and right sides of the display area DA, the second shielding electrode SHE2' is disposed in the peripheral area PA located on the left and right sides of the display area DA, and the first shielding electrode SHE1-B' and the second shielding electrode SHE2' overlap a portion of the gate driving circuit GDC. Specifically, the first shielding electrode SHE1-B' and the second shielding electrode SHE2' overlap the peripheral wiring located in the wiring area WA of the gate driving circuit GDC to shield the electric field of the peripheral wiring located in the wiring area WA of the gate driving circuit GDC, thereby avoiding the accumulation of charges on the pixel electrode PE of the edge pixel structure, thereby solving the light leakage phenomenon of the display panel 20A at the edge of the display area DA after the reliability test (for example, under long-term operation) and improving the display quality of the display panel 20A. The cross-sectional schematic diagram of the local area Z3' of the display panel 20A of the present variant embodiment can be referred to Figure 9, and the remaining identical parts will not be repeated.

FIG. 11 is a schematic top view of a display panel according to a fourth embodiment of the present invention. FIG. 12 is an enlarged schematic view of a local area Z4 of the display panel of FIG. 10. FIG. 13 is a schematic cross-sectional view of the display panel of FIG. 12 along the section line D-D'. For a clear presentation, FIG. 11 omits the illustration of the scan line GL and the data line DL in FIG. 12, and FIG. 12 omits the illustration of the second substrate 102, the gate insulating layer 110, the light shielding pattern layer 170, and the liquid crystal layer 150 in FIG. 13.

Referring to FIGS. 11 to 13 , the difference between the display panel 30 of the present embodiment and the display panel 20 of FIGS. 7 to 9 is that the first shielding electrode is arranged differently. Specifically, in the present embodiment, the first shielding electrode SHE1 of the display panel 30 is arranged similarly to the first shielding electrode SHE1 of FIGS. 1 to 3 . That is, the first shielding electrode SHE1 of the display panel 30 extends from the common electrode layer CEL at one side of the edge of the display area DA and overlaps the peripheral trace PW-B. In addition, the first shielding electrode SHE1 also overlaps the second shielding electrode SHE2.

The first shielding electrode SHE1 and the second shielding electrode SHE2 of this embodiment may have the same potential, but are not limited thereto. It is particularly noted that, unlike the first shielding electrode SHE1-B and the second shielding electrode SHE2 of FIGS. 7 to 9 having a ground potential, the first shielding electrode SHE1 and the second shielding electrode SHE2 of this embodiment may have the same common potential as the common electrode layer CEL.

From another point of view, compared with the display panel 10 of Figures 1 to 3, since a second shielding electrode SHE2 is further provided between the first shielding electrode SHE1 and the peripheral wiring PW-B of the present embodiment, the shielding effect of the electric field of the peripheral wiring PW-B closest to the display area DA can be further enhanced to prevent charges from accumulating on the pixel electrode PE of the edge pixel structure due to the bias influence of the peripheral wiring PW-B, thereby solving the light leakage phenomenon at the edge of the display area DA of the display panel 30 after a reliability test (for example, under long-term operation) and improving the display quality of the display panel 30.

In the present embodiment, the first shielding electrode SHE1 overlaps at least a portion of the peripheral trace PW-B, that is, the orthographic projection of the first shielding electrode SHE1 on the first substrate 101 overlaps at least a portion of the orthographic projection of the peripheral trace PW-B on the first substrate 101, but the present invention is not limited thereto. In a variant embodiment of the present embodiment, the first shielding electrode may not overlap the peripheral trace PW-B, and the ratio of the width of the first shielding electrode to the width of the strip electrode STE may be greater than or equal to 1 and less than or equal to 2. That is, the first shielding electrode SHE1 in FIG. 13 may be replaced with the first shielding electrode SHE1-A of the second embodiment.

In addition, the shielding method of the first shielding electrode SHE1 and the second shielding electrode SHE2 for the peripheral trace PW-B in this embodiment (eg, FIG. 13 ) can also be applied to the modified embodiment of FIG. 10 , and the same parts will not be described again.

In the above-mentioned embodiments of FIG. 7 to FIG. 13, the common electrode of each pixel structure is located between the first substrate and the pixel electrode, the peripheral wiring is formed on the first metal layer, the second shielding electrode is formed on the second metal layer, the common electrode and the first shielding electrode are formed on the first transparent conductive layer, the pixel electrode is formed on the second transparent conductive layer, the first shielding electrode is located between the peripheral wiring and the pixel electrode of the edge pixel structure, and the second shielding electrode is located between the peripheral wiring and the first shielding electrode, so the first shielding electrode of the first transparent conductive layer and the second shielding electrode of the second metal layer located between the first metal layer and the second transparent conductive layer can shield the electric field of the peripheral wiring. In addition, the first shielding electrode and the second shielding electrode can have the same potential (for example, both have a ground potential or both have a common potential) to further enhance the shielding effect on the peripheral wiring.

In summary, in a display panel of an embodiment of the present invention, a plurality of pixel structures are provided in the display area, and a peripheral wiring is provided in the peripheral area outside the display area. The peripheral wiring is provided adjacent to the display area. By providing a shielding electrode between the peripheral wiring and the display area, it is possible to effectively prevent charges from accumulating on the pixel electrodes of the pixel structures adjacent to the peripheral area due to the bias of the peripheral wiring, thereby solving the light leakage phenomenon at the edge of the display area of the display panel after the reliability test.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims (12)

1. A display panel, comprising: A first substrate having a display area and a peripheral area outside the display area; A plurality of scanning lines are arranged on the first substrate; A plurality of data lines are disposed on the first substrate, and the plurality of scan lines intersect with the plurality of data lines and define a plurality of pixel areas; A plurality of pixel structures are respectively disposed in the plurality of pixel regions, and each of the plurality of pixel structures comprises an active element and a pixel electrode electrically connected to each other; A common electrode layer is arranged in the display area, the common electrode layer includes a plurality of common electrodes, the plurality of common electrodes overlap the plurality of pixel electrodes of the plurality of pixel structures, and each common electrode is located between the first substrate and the corresponding pixel electrode; A peripheral routing line is arranged in the peripheral area; and A first shielding electrode is disposed in the peripheral area, the first shielding electrode is located between the peripheral wiring and the pixel electrode, and the first shielding electrode and the common electrode layer are formed in a first transparent conductive layer. 2 . The display panel according to claim 1 , wherein the peripheral wiring is formed on a metal layer, and the metal layer is located between the first substrate and the first transparent conductive layer. 3 . The display panel according to claim 2 , wherein the plurality of data lines or the plurality of scan lines are formed on the metal layer. 4 . The display panel according to claim 1 , wherein the peripheral wiring is a common electrode line or a wiring of a gate driving circuit. 5 . The display panel according to claim 1 , wherein the first shielding electrode extends from the common electrode layer, and the first shielding electrode and the common electrode layer are electrically connected to each other. 6 . The display panel according to claim 1 , wherein the first shielding electrode is electrically independent from the common electrode layer. 7 . The display panel according to claim 5 , wherein the first shielding electrode overlaps the peripheral wiring. 8. The display panel according to claim 5 or 6, further comprising: The second shielding electrode is disposed in the peripheral area and overlaps the peripheral routing line. The second shielding electrode is located between the peripheral routing line and the first shielding electrode. 9. The display panel according to claim 8, characterized in that the peripheral routing is formed on a first metal layer, the second shielding electrode is formed on a second metal layer, the first metal layer is located between the first substrate and the second metal layer, and the second metal layer is located between the first metal layer and the first transparent conductive layer. 10 . The display panel according to claim 8 , wherein a potential of the first shielding electrode is the same as a potential of the second shielding electrode. 11 . The display panel according to claim 10 , wherein a potential of the first shielding electrode is a common potential or a ground potential. 12 . The display panel according to claim 1 , wherein the display panel is an embedded touch display panel.