CN118151446A

CN118151446A - Display panel

Info

Publication number: CN118151446A
Application number: CN202211565116.0A
Authority: CN
Inventors: 林志宾; 许祐端
Original assignee: Hannstar Display Corp
Current assignee: Hannstar Display Corp
Priority date: 2022-12-07
Filing date: 2022-12-07
Publication date: 2024-06-07

Abstract

The invention provides a display panel which comprises a first substrate, a plurality of scanning lines, a plurality of data lines, a plurality of pixel structures, a common electrode layer, peripheral wiring and a first shielding electrode. The first substrate has a display area and a peripheral area outside the display area. The plurality of scanning lines and the plurality of data lines are arranged on the first substrate. The scanning lines intersect the data lines and define a plurality of pixel areas. The pixel structures are respectively arranged in the pixel areas and are respectively provided with an active element and a pixel electrode which are electrically connected with each other. The common electrode layer is disposed in the display region. The common electrode layer comprises a plurality of common electrodes, the plurality of common electrodes are arranged to overlap the plurality of pixel electrodes of the pixel structures, and each common electrode is positioned between the first substrate and the corresponding pixel electrode. The peripheral trace is disposed in the peripheral region. The first shielding electrode is arranged in the peripheral area and is positioned between the peripheral wiring and the pixel electrode. The first shielding electrode and the common electrode layer are formed on the first transparent conductive layer.

Description

Display panel

Technical Field

The present disclosure relates to display technology, and more particularly, to a display panel.

Background

With various display applications, display panels have been used in daily life. In current display panels, the display of an image is achieved by a plurality of pixel structures disposed within a display area. In order to transmit the control signals of the driving chip to the pixel structures, peripheral traces are required to be disposed in the peripheral area outside the display area. In recent years, in order to pursue higher visual experience and appearance quality of displays, visibility of high-screen-ratio displays (e.g., borderless displays or ultra-narrow-frame displays) is gradually opened in the market. However, the layout space of the peripheral area of the display panel is significantly reduced while the display panel is pursued of a narrow bezel design. Therefore, the peripheral trace must be disposed close to the edge of the display area, so that the edge pixels in the display area are easy to accumulate charges and generate display edge light leakage due to the bias effect of the peripheral trace.

Disclosure of Invention

The invention is directed to a display panel with better display quality.

According to an embodiment of the invention, a display panel includes a first substrate, a plurality of scan lines, a plurality of data lines, a plurality of pixel structures, a common electrode layer, a peripheral wiring, and a first shielding electrode. The first substrate has a display area and a peripheral area outside the display area. The plurality of scanning lines and the plurality of data lines are arranged on the first substrate. The scanning lines intersect the data lines and define a plurality of pixel areas. The pixel structures are respectively arranged in the pixel areas and are respectively provided with an active element and a pixel electrode which are electrically connected with each other. The common electrode layer is disposed within the display region. The common electrode layer includes a plurality of common electrodes. The plurality of common electrodes overlap the plurality of pixel electrode arrangements of the pixel structures. Each common electrode is positioned between the first substrate and the corresponding pixel electrode. The peripheral trace is disposed in the peripheral region. The first shielding electrode is arranged in the peripheral area and is positioned between the peripheral wiring and the pixel electrode. The first shielding electrode and the common electrode layer are formed on the first transparent conductive layer.

In the display panel according to the embodiment of the invention, the peripheral trace is formed on the metal layer. The metal layer is located between the first substrate and the first transparent conductive layer.

In the display panel according to the embodiment of the invention, a plurality of data lines or a plurality of scan lines are formed on the metal layer.

In the display panel according to the embodiment of the invention, the peripheral wiring is a wiring of a common electrode line or a gate driving circuit.

In the display panel according to the embodiment of the invention, the first shielding electrode extends from the common electrode layer, and the first shielding electrode and the common electrode layer are electrically connected with each other.

In the display panel according to the embodiment of the invention, the first shielding electrode is electrically independent from the common electrode layer.

In the display panel according to the embodiment of the invention, the first shielding electrode is overlapped with the peripheral wiring.

In the display panel according to the embodiment of the invention, the display panel further includes a second shielding electrode disposed in the peripheral region and overlapping the peripheral trace. The second shielding electrode is positioned between the peripheral wiring and the first shielding electrode.

In the display panel according to the embodiment of the invention, the peripheral trace is formed on the first metal layer, the second shielding electrode is formed on the second metal layer, the first metal layer is located between the first substrate and the second metal layer, and the second metal layer is located between the first metal layer and the first transparent conductive layer.

In the display panel according to the embodiment of the invention, the potential of the first shielding electrode is the same as the potential of the second shielding electrode.

In the display panel according to the embodiment of the invention, the potential of the first shielding electrode is the common potential or the ground potential.

In the display panel according to the embodiment of the invention, the display panel is an in-cell touch display panel.

Based on the above, in the display panel according to an embodiment of the invention, a plurality of pixel structures are disposed in the display area, and a peripheral trace is disposed in a peripheral area outside the display area. The peripheral trace is disposed adjacent to the display area. By arranging the shielding electrode between the peripheral wiring and the display area, charges can be effectively prevented from accumulating on the pixel electrode of the pixel structure adjacent to the peripheral area due to the influence of the bias voltage of the peripheral wiring, so that the light leakage phenomenon of the display panel at the edge of the display area after the reliability test is solved.

Drawings

Fig. 1 is a schematic top view of a display panel according to a first embodiment of the present invention;

FIG. 2 is an enlarged schematic view of a partial area of the display panel of FIG. 1;

FIG. 3 is a schematic cross-sectional view of the display panel of FIG. 2;

Fig. 4 is a schematic top view of a display panel according to a second embodiment of the present invention;

FIG. 5 is an enlarged schematic view of a partial area of the display panel of FIG. 4;

FIG. 6 is a schematic cross-sectional view of the display panel of FIG. 5;

fig. 7 is a schematic top view of a display panel according to a third embodiment of the present invention;

FIG. 8 is an enlarged schematic view of a partial area of the display panel of FIG. 7;

FIG. 9 is a schematic cross-sectional view of the display panel of FIG. 8;

fig. 10 is a schematic top view of a display panel according to a modified embodiment of the third embodiment of the present invention;

fig. 11 is a schematic top view of a display panel according to a fourth embodiment of the present invention;

FIG. 12 is an enlarged schematic view of a partial area of the display panel of FIG. 11;

Fig. 13 is a schematic cross-sectional view of the display panel of fig. 12.

Description of the reference numerals

10. 10A, 20, 30: a display panel;

101: a first substrate;

101S: a surface;

102: a second substrate;

110: a gate insulating layer;

120: a first passivation layer;

130: a second passivation layer;

150: a liquid crystal layer;

170: a light shielding pattern layer;

170OP, OP: an opening;

200: a circuit block;

CE: a common electrode;

CELs: a common electrode layer;

CEP: a common electrode pattern;

DA: a display area;

DE: a drain electrode;

DL: a data line;

GDC: a gate driving circuit;

GE: a gate;

GL: a scanning line;

GLW: a gate signal line;

ML1, ML1-A: a first metal layer;

ML2, ML2-A, ML2-B: a second metal layer;

PA: a peripheral region;

PE: a pixel electrode;

PW, PW-A, PW-B: peripheral wiring;

PX: a pixel structure;

PXA: a pixel region;

PXe: an edge pixel structure;

PXR (1) to PXR (M): a row of pixel structures;

PXC (1) to PXC (N): a pixel structure column;

SC: a semiconductor pattern;

SE: a source electrode;

SHE1, SHE1-A, SHE1-B, SHE1-B': a first shielding electrode;

SHE2, SHE2': a second shielding electrode;

STE: a strip electrode;

T: an active device;

TCL1, TCL1-A, TCL1-B: a first transparent conductive layer;

TCL2: a second transparent conductive layer;

VIA: a contact hole;

w1, W2: a width;

WA: a wiring area;

x, Y, Z: a direction;

z1, Z2, Z3', Z4: a region;

A-A ', B-B', C-C ', D-D': and (5) cutting.

Detailed Description

Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.

Fig. 1 is a schematic top view of a display panel according to a first embodiment of the present invention. Fig. 2 is an enlarged schematic view of a partial region Z1 of the display panel of fig. 1. Fig. 3 is a schematic cross-sectional view of the display panel of fig. 2 along section line A-A'. For clarity of presentation, fig. 1 omits the illustration of the scan lines GL and the data lines DL in fig. 2, and fig. 2 omits the illustration of the second substrate 102, the gate insulating layer 110, the light shielding pattern layer 170, and the liquid crystal layer 150 in fig. 3.

Referring to fig. 1 to 3, the display panel 10 includes a first substrate 101, a second substrate 102 and a liquid crystal layer 150. The liquid crystal layer 150 is disposed between the first substrate 101 and the second substrate 102. That is, the display panel 10 of the present embodiment is a liquid crystal display panel, but not limited thereto.

The first substrate 101 is provided with a display area DA and a peripheral area PA other than the display area DA. The display panel 10 is provided with a plurality of scanning lines GL, a plurality of data lines DL, and a plurality of pixel structures PX in the display area DA, and is disposed on the surface 101S of the first substrate 101. The plurality of scanning lines GL intersect the plurality of data lines DL and define a plurality of pixel areas PXA. A plurality of pixel structures PX are disposed in the pixel regions PXA, respectively. For example, in the present embodiment, the plurality of scanning lines GL are arranged on the first substrate 101 at intervals along the direction Y (i.e. the first direction), and the plurality of data lines DL are arranged on the first substrate 101 at intervals along the direction X (i.e. the second direction), wherein the direction X is optionally perpendicular to the direction Y. Each scanning line GL extends along a direction X, and each data line DL extends along a direction Y. For example, the extending direction of each data line DL may be the direction Y, or the extending direction of each data line DL may have an included angle (for example, but not limited to an included angle less than or equal to 15 degrees) with the direction Y. Each pixel structure PX can be electrically connected to one scan line GL and one data line DL. More specifically, the pixel structures PX may be arranged in a plurality of pixel structure columns and a plurality of pixel structure rows along the direction X and the direction Y, respectively. For example, in the present embodiment, the plurality of pixel structures PX may be arranged into M pixel structure rows PXR (1) to PXR (M) and N pixel structure columns PXC (1) to PXC (N), wherein M and N are positive integers greater than 1.

The pixel structure PX in each pixel region PXA has an active element T, a common electrode CE and a pixel electrode PE, and the active element T and the pixel electrode PE are electrically connected to each other. For example, the active device T includes a gate electrode GE, a source electrode SE, a drain electrode DE, and a semiconductor pattern SC. The gate electrode GE may be formed as a part extending from the scanning line GL. The semiconductor pattern SC is disposed overlapping the gate electrode GE. Here, the overlapping relationship refers to, for example, that the semiconductor pattern SC and the gate electrode GE overlap each other along the direction Z. In the present embodiment, the direction Z may be a direction perpendicular to the surface 101S of the first substrate 101. In the following, unless otherwise mentioned, the overlapping relationship between two members is defined in the same manner, and the overlapping direction will not be described again.

The semiconductor pattern SC may serve as a channel layer of the active device T, and the source electrode SE and the drain electrode DE are electrically connected to different regions of the semiconductor pattern SC. The material of the semiconductor pattern SC may include an amorphous silicon semiconductor, a single crystal silicon semiconductor, a polycrystalline silicon semiconductor, or a metal oxide semiconductor. In the present embodiment, the active device T is, for example, an amorphous silicon thin film transistor (amorphous silicon thin film transistor, a-Si TFT), but not limited thereto. In other embodiments, the active element T may also be a polysilicon thin film transistor (polycrystalline silicon TFT, poly-Si TFT) or a metal oxide semiconductor thin film transistor (metal oxide semiconductor TFT). In some embodiments, an ohmic contact layer may be further disposed between the source electrode SE and the semiconductor pattern SC and between the drain electrode DE and the semiconductor pattern SC, and the material of the ohmic contact layer may be, for example, a doped amorphous silicon layer, but not limited thereto.

In the present embodiment, the gate electrode GE is optionally disposed between the semiconductor pattern SC and the first substrate 101 to form a bottom-gate thin-film-transistor (bottom-gate-thin-transistor), but not limited thereto. In other embodiments, the gate electrode GE may also be disposed on a side of the semiconductor pattern SC facing away from the first substrate 101 to form a top-gate thin-film-transistor (top-gate thin-film).

The step of forming the active device T may include: the gate electrode GE, the gate insulating layer 110, the semiconductor pattern SC, and the source electrode SE and the drain electrode DE are sequentially formed on the first substrate 101, wherein the gate electrode GE and the scan line GL can be formed on the first metal layer ML1, and the source electrode SE, the drain electrode DE, and the data line DL can be formed on the second metal layer ML2, but not limited thereto. The materials of the first metal layer ML1 and the second metal layer ML2 may include metals (e.g., molybdenum, aluminum, copper, nickel, chromium), alloys, nitrides of metal materials, oxides of metal materials, oxynitrides of metal materials, or other suitable materials, or stacked layers of metal materials and other conductive materials.

In this embodiment, a first passivation layer 120 and a second passivation layer 130 are further disposed between the pixel electrode PE and the active device T. The first passivation layer 120 is disposed between the second passivation layer 130 and the active device T. The materials of the first passivation layer 120 and the second passivation layer 130 may include, for example, an inorganic insulating material, an organic insulating material, or a combination thereof, but are not limited thereto. In addition, each of the first passivation layer 120 and the second passivation layer 130 may include a single layer structure or a multi-layer stack structure. In the present embodiment, the first passivation layer 120 and the second passivation layer 130 may have a contact hole VIA overlapping the drain electrode DE of the active device T, and the pixel electrode PE is electrically connected to the drain electrode DE of the active device T through the contact hole VIA, but is not limited thereto.

Further, the display panel 10 further includes a common electrode layer CEL disposed between the active device T and the pixel electrode PE, the common electrode layer CEL is disposed in the display area DA, and the common electrode layer CEL includes a plurality of common electrodes CE. The plurality of common electrodes CE of the common electrode layer CEL are disposed overlapping the plurality of pixel electrodes PE of the plurality of pixel structures PX and are located between the first passivation layer 120 and the second passivation layer 130. That is, the common electrode layer CEL is located between the first substrate 101 and the pixel electrode PE, but is not limited thereto. In this embodiment, the common electrode CE of each pixel structure PX is located between the first substrate 101 and the corresponding pixel electrode PE, that is, the pixel structure PX of this embodiment is a pixel structure of the upper pixel electrode and the lower common electrode.

In the present embodiment, the common electrode layer CEL may be divided into a plurality of common electrode patterns CEP, each of which overlaps with the plurality of pixel regions PXA, and each of which includes a plurality of common electrodes CE electrically connected to each other, but not limited thereto.

For example, the pixel electrode PE may include a plurality of stripe electrodes STE and a plurality of openings OP. The strip electrodes STE and the openings OP may be alternately arranged along the direction X, but not limited thereto. In other embodiments, the plurality of stripe-shaped electrodes STE and the plurality of openings OP may be alternately arranged along a direction (e.g., direction Y) different from the direction X. Each opening OP is located between two adjacent strip electrodes STE (as shown in fig. 2). The electric field formed between the pixel electrode PE and the common electrode CE can control the direction of the liquid crystal molecules in the liquid crystal layer 150 through the openings OP to display a corresponding picture. In the present embodiment, each Common electrode CE can receive a Common Voltage (Common Voltage), but not limited thereto.

In this embodiment, the pixel electrode PE and the common electrode layer CEL each have light transmittance, and the material used for manufacturing the pixel electrode PE and the common electrode layer CEL may be transparent conductive material. For example, the transparent conductive material may include a metal oxide (e.g., indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, or other suitable oxide, or a stacked layer of at least two thereof), but is not limited thereto. In the present embodiment, the common electrode layer CEL may be formed on the first transparent conductive layer TCL1, the pixel electrode PE may be formed on the second transparent conductive layer TCL2, and the first transparent conductive layer TCL1 is located between the first substrate 101 and the second transparent conductive layer TCL 2.

Specifically, in the present embodiment, the display panel 10 may be a display panel with a touch function, such as an in-cell touch (in-cell touch) display panel. The common electrode patterns CEP of the common electrode layer CEL can be used as touch sensing electrodes during the touch of the display panel 10, but not limited to, in addition to receiving a common potential during the display of the display panel 10 to form an electric field with the pixel electrode PE to drive the liquid crystal molecules in the liquid crystal layer 150.

In the present embodiment, the display panel 10 further includes a circuit block 200 for driving the plurality of pixel structures PX in the peripheral area PA of the first substrate 101. For example, the circuit block 200 may include a gate driving circuit, a source driving circuit, a touch sensing circuit, or a combination thereof, but is not limited thereto. In other embodiments, the circuit block 200 may be disposed on a flexible circuit board, and the flexible circuit board is coupled to the pads in the peripheral area PA of the first substrate 101; or the circuit block 200 may be disposed on a system circuit board, and the system circuit board is electrically connected to the pads located in the peripheral area PA of the first substrate 101 through the flexible circuit board.

The control signal of the circuit block 200 can be transmitted to the pixel structure PX in the display area DA, or the sensing signal in the display area DA can be transmitted to the circuit block 200, and the display panel 10 further includes a peripheral trace PW disposed in the peripheral area PA and extending at least on one side of the display area DA. It should be noted that, for clarity of presentation, only one peripheral trace PW adjacent to the display area DA is shown in the peripheral area PA of fig. 1, and the disclosure is not limited thereto. In other embodiments, the number, shape, location and type of the peripheral traces PW can be adjusted according to different application requirements. In the present embodiment, the peripheral wiring PW of fig. 1 to 3 is formed on the second metal layer ML2 as well as the source electrode SE, the drain electrode DE and the data line DL.

It is particularly noted that one of the peripheral traces PW shown in fig. 1 and 2 is disposed immediately adjacent to the edge of the display area DA. By such an arrangement, the layout space of the peripheral wiring PW in the peripheral area PA can be reduced as much as possible, thereby realizing a narrow bezel design of the display panel 10.

In the present embodiment, the peripheral wires PW of fig. 1 to 3 may be common electrode wires, and the common electrode wires may receive a common potential, but is not limited thereto. In the present embodiment, the peripheral trace PW is disposed around the display area DA. However, the present invention is not limited thereto. In other embodiments, not shown, the peripheral trace PW may extend only in the peripheral area PA outside the left and right sides of the display area DA in fig. 1, or the peripheral trace PW may extend only in the peripheral area PA outside the left side or the peripheral area PA outside the right side of the display area DA in fig. 1. In the present embodiment, the extending direction of the peripheral wires PW extending on the left and right sides of the display area DA may be substantially parallel to the direction Y, but is not limited thereto.

In the present embodiment, the plurality of pixel structures PX may be arranged into M pixel structure rows PXR (1) to PXR (M) and N pixel structure columns PXC (1) to PXC (N), and the pixel structures PX located at opposite ends of each pixel structure row or the pixel structures PX located at opposite ends of each pixel structure column may be referred to as edge pixel structures PXe. For simplicity of the drawing, only one pixel structure PX located at one end of one pixel structure row is denoted as an edge pixel structure PXe in fig. 1 for illustration. The edge pixel structure PXe is a pixel structure PX closest to the peripheral routing PW in each pixel structure row or each pixel structure column of the display panel 10, so in order to effectively avoid charge accumulated on the pixel electrode PE of the edge pixel structure PXe due to the bias voltage or the direct current signal influence of the peripheral routing PW caused by the coupling effect between the peripheral routing PW and the pixel electrode PE of the edge pixel structure PXe, the display panel 10 is provided with a first shielding electrode SHE1 between the peripheral routing PW and the pixel electrode PE of the edge pixel structure PXe to shield the coupling effect of the peripheral routing PW on the pixel electrode PE of the edge pixel structure PXe.

In this embodiment, the first shielding electrode SHE1 may extend from the common electrode layer CEL. That is, the first shielding electrode SHE1 and the common electrode layer CEL may be formed on the same conductive film layer, i.e., the first shielding electrode SHE1 and the common electrode layer CEL may be formed on the first transparent conductive layer TCL1 and connected to each other, so that the potentials of the first shielding electrode SHE1 and the common electrode layer CEL are the same as each other. For example, the edge pixel structures PXe may be pixel structures PX located at opposite ends of each of the pixel structure rows PXR (1) to PXR (M) (e.g., leftmost pixel structure PX and rightmost pixel structure PX located in each of the pixel structure rows), the first shielding electrode SHE1 may extend from the common electrode CE of the edge pixel structure PXe (e.g., extend leftwards from the common electrode CE of the leftmost pixel structure PX located in each of the pixel structure rows and rightwards from the common electrode CE of the rightmost pixel structure PX located in each of the pixel structure rows) to form the first shielding electrode SHE1, and the first shielding electrode SHE1 is located between the peripheral trace PW and the pixel electrode PE of the edge pixel structure PXe, but is not limited thereto.

In order to effectively shield the electric field of the peripheral trace PW to avoid the influence of the pixel electrode PE of the edge pixel structure PXe, in the present embodiment, the first shielding electrode SHE1 may overlap at least a portion of the peripheral trace PW, but is not limited thereto. Fig. 3 illustrates that the first shielding electrode SHE1 overlaps a portion of the peripheral trace PW, i.e., a portion of the front projection of the peripheral trace PW on the first substrate 101 overlaps the front projection of the first shielding electrode SHE1 on the first substrate 101, but is not limited thereto. In other embodiments, the first shielding electrode SHE1 may overlap all of the peripheral traces PW, i.e. all of the areas of the front projection of the peripheral traces PW on the first substrate 101 overlap the front projection of the first shielding electrode SHE1 on the first substrate 101, but is not limited thereto.

In addition, since the first shielding electrode SHE1 extends from the common electrode layer CEL and is electrically connected to each other, and the common electrode pattern CEP of the common electrode layer CEL also serves as a touch sensing electrode during the touch of the display panel 10, the width W1 of the first shielding electrode SHE1 is preferably not excessively large so as not to affect the touch accuracy of the display panel 10, but is not limited thereto. In the present embodiment, the first shielding electrode SHE1 is formed by extending from the common electrode layer CEL along a direction, and the first shielding electrode SHE1 has a width W1 along the extending direction, the plurality of stripe electrodes STE and the plurality of openings OP of the pixel electrode PE are alternately arranged along the direction, and the stripe electrodes STE have a width W2 (or a width W2 of a short side of the stripe electrodes STE) along the direction alternately arranged, and a ratio of the width W1 of the first shielding electrode SHE1 to the width W2 of the stripe electrodes STE may be, for example, less than or equal to 2 so as not to affect the touch accuracy of the display panel 10, but the ratio of the width W1 of the first shielding electrode SHE1 to the width W2 of the stripe electrodes STE is not limited thereto. For example, in fig. 3, the first shielding electrode SHE1 is formed by extending the common electrode layer CEL along a direction parallel to the direction X, the plurality of stripe electrodes STE and the plurality of openings OP of the pixel electrode PE are alternately arranged along the direction X, and a ratio of a width W1 of the first shielding electrode SHE1 in the direction X to a width W2 of the stripe electrodes STE in the direction X may be less than or equal to 2, but is not limited thereto.

By arranging the first shielding electrode SHE1, charges accumulated on the pixel electrode PE of the pixel structure PX adjacent to the peripheral area PA due to the bias influence of the peripheral wiring PW can be effectively avoided, so as to solve the problem of light leakage at the edge of the display area DA after the reliability test (e.g. under long-time operation) of the display panel 10 and improve the display quality of the display panel 10.

On the other hand, the display panel 10 may further include a light shielding pattern layer 170 disposed on the second substrate 102. The light shielding pattern layer 170 has a plurality of openings 170OP, and the openings 170OP are respectively overlapped with a plurality of pixel electrodes PE and a plurality of common electrodes CE of a plurality of pixel structures PX. From another point of view, the light shielding pattern layer 170 may overlap the peripheral area PA, the plurality of scanning lines GL, the plurality of data lines DL, and the plurality of active devices T, and the plurality of openings 170OP may overlap the pixel electrode PE and a portion of the common electrode layer CEL, respectively.

Other embodiments will be listed below to describe the present disclosure in detail, wherein like components will be denoted by like reference numerals, and descriptions of the same technical content will be omitted, and reference is made to the foregoing embodiments for parts, which will not be repeated below.

Fig. 4 is a schematic top view of a display panel according to a second embodiment of the present invention. Fig. 5 is an enlarged schematic view of a partial region Z2 of the display panel of fig. 4. Fig. 6 is a schematic cross-sectional view of the display panel of fig. 5 along section line B-B'. For clarity of presentation, fig. 4 omits the illustration of the scan lines GL and the data lines DL in fig. 5, and fig. 5 omits the illustration of the second substrate 102, the gate insulating layer 110, the light shielding pattern layer 170, and the liquid crystal layer 150 in fig. 6.

Referring to fig. 4 to 6, the display panel 10A of the present embodiment is different from the display panel 10 of fig. 1 to 3 only in that: the first shielding electrode SHE 1-up>A of the display panel 10A of the present embodiment does not overlap the peripheral trace PW-up>A, wherein the peripheral trace PW-up>A is adjacent to the display areup>A dup>A. For example, the distance between the peripheral trace PW-up>A and the display areup>A dup>A of the present embodiment may be larger than the distance between the peripheral trace PW and the display areup>A dup>A of fig. 1-3. Therefore, in order to effectively shield the electric field of the peripheral trace PW-up>A, the width W1 of the first shielding electrode SHE 1-up>A may be greater than or equal to the width W2 of the stripe electrode STE of the pixel electrode PE (i.e., the ratio of the width W1 of the first shielding electrode SHE 1-up>A to the width W2 of the stripe electrode STE may be greater than or equal to 1), and the effective electric field shielding effect may be achieved without extending to the areup>A overlapping the peripheral trace PW-up>A. In addition, since the first shielding electrode SHE1-a extends from the common electrode layer CEL and is electrically connected to each other, and the common electrode pattern CEP of the common electrode layer CEL also serves as a touch sensing electrode during the touch of the display panel 10A, the width W1 of the first shielding electrode SHE1-a may not be too large so as not to affect the touch accuracy of the display panel 10A. For example, the ratio of the width W1 of the first shielding electrode SHE1-A to the width W2 of the strip electrode STE may be, for example, less than or equal to 2.

In the present embodiment, the peripheral wiring PW-up>A of fig. 4 to 6 is formed on the second metal layer ML 2-up>A as well as the source electrode SE, the drain electrode DE and the datup>A line DL, and the first shielding electrode SHE 1-up>A and the common electrode layer CEL are formed on the first transparent conductive layer TCL 1-up>A as well.

In the embodiments of fig. 1 to 6, the common electrode of each pixel structure is located between the first substrate and the pixel electrode, the peripheral trace is formed on the second metal layer, the common electrode and the first shielding electrode are formed on the first transparent conductive layer, the pixel electrode is formed on the second transparent conductive layer, and the first shielding electrode is located between the peripheral trace and the pixel electrode of the edge pixel structure, so that the first shielding electrode of the first transparent conductive layer located between the second metal layer and the second transparent conductive layer can shield the electric field of the peripheral trace.

Next, a manner of shielding the peripheral wiring from an electric field in the embodiment in which the peripheral wiring is formed in the first metal layer will be described in the embodiments of fig. 7 to 13.

Fig. 7 is a schematic top view of a display panel according to a third embodiment of the present invention. Fig. 8 is an enlarged schematic view of a partial region Z3 of the display panel of fig. 7. Fig. 9 is a schematic cross-sectional view of the display panel of fig. 8 along section line C-C'. For clarity of presentation, fig. 7 omits the illustration of the scan lines GL, the data lines DL, and the second shielding electrode SHE2 in fig. 8, and fig. 8 omits the illustration of the second substrate 102, the gate insulating layer 110, the light shielding pattern layer 170, and the liquid crystal layer 150 in fig. 9.

Referring to fig. 7 to 9, the display panel 20 of the present embodiment is different from the display panel 10 of fig. 1 to 3 in that: the types of peripheral traces and the arrangement modes of the shielding electrodes are different. For example, in the present embodiment, the peripheral wires PW-B are adjacent to the display area DA, and the peripheral wires PW-B may be formed on the first metal layer ML1-a like the gate electrode GE and the scanning line GL, and the number thereof may be one or more, but is not limited thereto. In the present embodiment, fig. 8 illustrates that the extending direction of the peripheral trace PW-B is the same as the extending direction of the data line DL, but the extending direction of the peripheral trace PW-B is not limited thereto.

It is particularly noted that, although the first shielding electrode SHE1-B and the common electrode layer CEL of the present embodiment are the same film layer (e.g., the first transparent conductive layer TCL 1-B), unlike the first shielding electrode SHE1 of fig. 3, the first shielding electrode SHE1-B and the common electrode layer CEL of the present embodiment are structurally separated from each other (i.e., the first shielding electrode SHE1-B and the common electrode layer CEL are not connected to each other). That is, the first shielding electrode SHE1-B of the present embodiment does not extend from the common electrode layer CEL. In addition, the first shielding electrode SHE1-B of the present embodiment can be electrically independent from the common electrode layer CEL, but is not limited thereto. For example, the first shielding electrode SHE1-B may have a ground potential, but is not limited thereto, unlike the common electrode CEL having a common potential.

On the other hand, the first shielding electrode SHE1-B is located between the peripheral trace PW-B and the pixel electrode PE of the edge pixel structure, and at least a portion of the peripheral trace PW-B overlaps the first shielding electrode SHE1-B, i.e. at least a portion of the front projection of the peripheral trace PW-B on the first substrate 101 overlaps the front projection of the first shielding electrode SHE1-B on the first substrate 101. In the present embodiment, the front projection of the peripheral trace PW-B on the first substrate 101 is located within the front projection of the first shielding electrode SHE1-B on the first substrate 101. That is, all of the peripheral traces PW-B closest to the display area DA are overlapped with the first shielding electrode SHE1-B, but not limited thereto. In other embodiments, a portion of the peripheral trace PW-B may overlap the first shielding electrode SHE1-B, i.e., a portion of the orthographic projection of the peripheral trace PW-B on the first substrate 101 overlaps the orthographic projection of the first shielding electrode SHE1-B on the first substrate 101.

In the present embodiment, the display panel 20 further optionally includes a second shielding electrode SHE2 disposed in the peripheral area PA. The second shielding electrode SHE2 is located between the peripheral trace PW-B and the first shielding electrode SHE1-B, and the second shielding electrode SHE2 overlaps the peripheral trace PW-B and the first shielding electrode SHE1-B to strengthen the electric field shielding of the peripheral trace PW-B. For example, the second shielding electrode SHE2 may be formed on the second metal layer ML2-B as the source electrode SE, the drain electrode DE, and the data line DL. The second shielding electrode SHE2 may have the same potential as the first shielding electrode SHE1-B, but is not limited thereto. For example, the second shielding electrode SHE2 may have a ground potential with the first shielding electrode SHE1-B, but is not limited thereto.

In the present embodiment, at least a portion of the peripheral trace PW-B overlaps the second shielding electrode SHE2, i.e. at least a portion of the orthographic projection of the peripheral trace PW-B on the first substrate 101 overlaps the orthographic projection of the second shielding electrode SHE2 on the first substrate 101. In FIG. 7, the peripheral trace PW-B and the second shielding electrode SHE2 are shown overlapping each other with PW-B/SHE 2. In addition, at least a portion of the second shielding electrode SHE2 overlaps the first shielding electrode SHE1-B, i.e., at least a portion of the orthographic projection of the second shielding electrode SHE2 onto the first substrate 101 overlaps the orthographic projection of the first shielding electrode SHE1-B onto the first substrate 101. In the present embodiment, the orthographic projection of the second shielding electrode SHE2 on the first substrate 101 is located within the orthographic projection of the first shielding electrode SHE1-B on the first substrate 101, but is not limited thereto. In other embodiments, a portion of the orthographic projection of the second shielding electrode SHE2 onto the first substrate 101 is located within the orthographic projection of the first shielding electrode SHE1-B onto the first substrate 101.

In summary, the peripheral trace PW-B overlaps the first shielding electrode SHE1-B and the second shielding electrode SHE2, i.e., the front projection of the peripheral trace PW-B on the first substrate 101 overlaps the front projection of the first shielding electrode SHE1-B on the first substrate 101 and the front projection of the second shielding electrode SHE2 on the first substrate 101. In addition, since the first shielding electrode SHE1-B and the second shielding electrode SHE2 disposed on the overlapped peripheral wire PW-B have the same potential (e.g., the ground potential), the electric field of the peripheral wire PW-B can be effectively shielded to avoid charges accumulated on the pixel electrode PE of the edge pixel structure due to the bias effect of the peripheral wire PW-B, so as to solve the light leakage phenomenon of the display panel 20 at the edge of the display area DA after the reliability test (e.g., under long-time operation) and improve the display quality of the display panel 20.

In fig. 7, the peripheral wiring PW-B of the first metal layer ML1-a is shown to be disposed around the display area DA, but is not limited thereto. In other embodiments, the peripheral traces of the first metal layer may be located only in the peripheral area PA on opposite sides of the display area DA.

Fig. 10 is a schematic top view of a display panel according to a modified embodiment of the third embodiment of the present invention. Referring to fig. 10, the display panel 20A of the present embodiment is different from the display panel 20 of fig. 7 to 9 in that: the peripheral wiring, the first shielding electrode and the second shielding electrode are arranged in different manners. Specifically, in the present embodiment, the gate driving circuit GDC of the display panel 20A is disposed in the peripheral area PA on the left and right sides of the display area DA, and the peripheral traces (not shown) in the trace area WA of the gate driving circuit GDC are overlapped with the first shielding electrode SHE1-B 'and the second shielding electrode SHE2'. In fig. 10, the second shielding electrode SHE2 'and the peripheral wiring located in the wiring area WA of the gate driving circuit GDC are shown as WA (GDC)/SHE 2' overlapped with each other. For example, the peripheral trace in the trace area WA of the gate driving circuit GDC may be a gate signal line electrically connected to a scan line (not shown) in the display area DA, and transmits the gate driving signal generated by the gate driving circuit GDC to the corresponding scan line, but is not limited thereto. In this embodiment, the peripheral wiring in the wiring area WA of the gate driving circuit GDC is formed on the first metal layer in the same manner as the scanning line.

In the present embodiment, the first shielding electrode SHE1-B 'is disposed in the peripheral area PA located at the left and right sides of the display area DA, the second shielding electrode SHE2' is disposed in the peripheral area PA located at the left and right sides of the display area DA, and the first shielding electrode SHE1-B 'and the second shielding electrode SHE2' overlap a portion of the gate driving circuit GDC. Specifically, the first shielding electrode SHE1-B 'and the second shielding electrode SHE2' overlap the peripheral trace in the trace area WA of the gate driving circuit GDC to shield the electric field of the peripheral trace in the trace area WA of the gate driving circuit GDC, thereby avoiding charge accumulation on the pixel electrode PE of the edge pixel structure, solving the problem of light leakage at the edge of the display area DA after the reliability test (e.g. long-time operation) of the display panel 20A and improving the display quality of the display panel 20A. The schematic cross-sectional view of the partial region Z3' of the display panel 20A of the present modified embodiment can refer to fig. 9, and the rest of the same parts will not be repeated.

Fig. 11 is a schematic top view of a display panel according to a fourth embodiment of the present invention. Fig. 12 is an enlarged schematic view of a partial region Z4 of the display panel of fig. 10. Fig. 13 is a schematic cross-sectional view of the display panel of fig. 12 along section line D-D'. For clarity of presentation, fig. 11 omits the illustration of the scan lines GL and the data lines DL in fig. 12, and fig. 12 omits the illustration of the second substrate 102, the gate insulating layer 110, the light shielding pattern layer 170, and the liquid crystal layer 150 in fig. 13.

Referring to fig. 11 to 13, the display panel 30 of the present embodiment is different from the display panel 20 of fig. 7 to 9 in that: the first shielding electrodes are arranged in different manners. Specifically, in the present embodiment, the first shielding electrode SHE1 of the display panel 30 is configured in a similar manner to the first shielding electrode SHE1 of fig. 1 to 3. That is, the first shielding electrode SHE1 of the display panel 30 extends from the common electrode layer CEL at one side of the edge of the display area DA and overlaps the peripheral trace PW-B. In addition, the first shielding electrode SHE1 is also overlapped with the second shielding electrode SHE2.

The first shielding electrode SHE1 and the second shielding electrode SHE2 of the present embodiment may have the same potential, but are not limited thereto. Note in particular that, unlike the first shielding electrode SHE1-B and the second shielding electrode SHE2 of fig. 7 to 9, which have the ground potential, the first shielding electrode SHE1 and the second shielding electrode SHE2 of the present embodiment may have the same common potential as the common electrode layer CEL.

From another point of view, compared with the display panel 10 of fig. 1 to 3, since the second shielding electrode SHE2 is further disposed between the first shielding electrode SHE1 and the peripheral trace PW-B in the present embodiment, the shielding effect on the electric field of the peripheral trace PW-B closest to the display area DA can be further improved, so as to avoid the accumulation of charges on the pixel electrode PE of the edge pixel structure due to the bias effect of the peripheral trace PW-B, thereby solving the light leakage phenomenon at the edge of the display area DA after the reliability test (e.g. under long-time operation) of the display panel 30 and improving the display quality of the display panel 30.

In the present embodiment, the first shielding electrode SHE1 overlaps at least a portion of the peripheral trace PW-B, i.e. the front projection of the first shielding electrode SHE1 on the first substrate 101 overlaps at least a portion of the front projection of the peripheral trace PW-B on the first substrate 101, but is not limited thereto. In a variation of the present embodiment, the first shielding electrode may not overlap the peripheral trace PW-B, and a ratio of a width of the first shielding electrode to a width of the stripe electrode STE may be greater than or equal to 1 and less than or equal to 2. The first shielding electrode SHE1 in fig. 13 may be replaced with the first shielding electrode SHE1-a of the second embodiment.

In addition, the shielding manner (e.g., fig. 13) of the peripheral trace PW-B by the first shielding electrode SHE1 and the second shielding electrode SHE2 in the present embodiment can also be applied to the modified embodiment of fig. 10, and the same parts are not repeated.

In the embodiments of fig. 7 to 13, the common electrode of each pixel structure is located between the first substrate and the pixel electrode, the peripheral trace is formed on the first metal layer, the second shielding electrode is formed on the second metal layer, the common electrode and the first shielding electrode are formed on the first transparent conductive layer, the pixel electrode is formed on the second transparent conductive layer, the first shielding electrode is located between the peripheral trace and the pixel electrode of the edge pixel structure, and the second shielding electrode is located between the peripheral trace and the first shielding electrode, so that the first shielding electrode of the first transparent conductive layer and the second shielding electrode of the second metal layer located between the first metal layer and the second transparent conductive layer can shield the electric field of the peripheral trace. In addition, the first shielding electrode and the second shielding electrode may have the same potential (e.g., both have a ground potential or both have a common potential) to further enhance the shielding effect on the peripheral wiring.

In summary, in the display panel according to an embodiment of the invention, a plurality of pixel structures are disposed in the display area, and a peripheral trace is disposed in a peripheral area outside the display area. The peripheral trace is disposed adjacent to the display area. By arranging the shielding electrode between the peripheral wiring and the display area, charges can be effectively prevented from accumulating on the pixel electrode of the pixel structure adjacent to the peripheral area due to the influence of the bias voltage of the peripheral wiring, so that the light leakage phenomenon of the display panel at the edge of the display area after the reliability test is solved.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.

Claims

1. A display panel, comprising:

The display device comprises a first substrate, a second substrate and a first display unit, wherein the first substrate is provided with a display area and a peripheral area outside the display area;

A plurality of scan lines disposed on the first substrate;

A plurality of data lines arranged on the first substrate, and intersecting the plurality of scanning lines and the plurality of data lines to define a plurality of pixel regions;

The pixel structures are respectively arranged in the pixel areas and respectively comprise an active element and a pixel electrode which are electrically connected with each other;

The common electrode layer is arranged in the display area and comprises a plurality of common electrodes, the plurality of common electrodes are arranged to overlap a plurality of pixel electrodes of the plurality of pixel structures, and each common electrode is positioned between the first substrate and the corresponding pixel electrode;

The peripheral wiring is arranged in the peripheral area; and

The first shielding electrode is arranged in the peripheral area, is positioned between the peripheral wiring and the pixel electrode, and is formed on the first transparent conductive layer with the common electrode layer.

2. The display panel of claim 1, wherein the perimeter trace is formed in a metal layer between the first substrate and the first transparent conductive layer.

3. The display panel of claim 2, wherein the plurality of data lines or the plurality of scan lines are formed on the metal layer.

4. The display panel of claim 1, wherein the peripheral trace is a common electrode line or a trace of a gate driving circuit.

5. The display panel of claim 1, wherein the first shielding electrode extends from the common electrode layer, and the first shielding electrode and the common electrode layer are electrically connected to each other.

6. The display panel of claim 1, wherein the first shielding electrode is electrically independent of the common electrode layer.

7. The display panel of claim 5 or 6, wherein the first shielding electrode overlaps the peripheral trace.

8. The display panel according to claim 5 or 6, further comprising:

The second shielding electrode is arranged in the peripheral area and overlapped with the peripheral wiring, and the second shielding electrode is positioned between the peripheral wiring and the first shielding electrode.

9. The display panel of claim 8, wherein the peripheral trace is formed on a first metal layer, the second shielding electrode is formed on a second metal layer, the first metal layer is located between the first substrate and the second metal layer, and the second metal layer is located between the first metal layer and the first transparent conductive layer.

10. The display panel according to claim 8, wherein a potential of the first shielding electrode is the same as a potential of the second shielding electrode.

11. The display panel according to claim 10, wherein a potential of the first shielding electrode is a common potential or a ground potential.

12. The display panel of claim 1, wherein the display panel is an in-cell touch display panel.