CN118138493A - Circuit for identifying Ethernet auto-negotiation frame content - Google Patents

Abstract

The application relates to the technical field of integrated circuits, and discloses a circuit for identifying the content of an Ethernet auto-negotiation frame, which comprises the following components: a first computing module for receiving an input signal from a SerDes receiver and identifying respective locations of high and low levels from the input signal; the signal edge detection module is used for identifying the position where the high-low level jump occurs for the first time in each sampling period according to the identified respective positions of the high level and the low level, and marking the jump position where the high level jumps to the high level firstly when the low level is continuously identified and the jump position where the low level jumps to the low level when the low level is continuously identified in each sampling period; the judgment adding and deleting module is used for determining whether to perform adding judgment and deleting judgment according to whether the jump position changes or not; and the second calculation and judgment output module is used for calculating a middle position according to the jump position and the addition judgment and deletion judgment and outputting the middle position as a judgment result. The application can correctly identify the content of the auto-negotiation frame.

Description

Circuit for identifying Ethernet auto-negotiation frame content

Technical Field

The application relates to the technical field of integrated circuits, in particular to a circuit for identifying the content of an Ethernet auto-negotiation frame.

Background

Auto-Negotiation (Auto-Negotiation) refers to the ability of network devices to automatically exchange information and determine optimal communication parameters, including speed, duplex mode, and other relevant characteristics, in an ethernet connection. This process allows the devices to negotiate the parameters best suited for communication between them at the time of connection, thereby enabling more efficient data transfer. During auto-negotiation, when two devices are first connected or when the network configuration changes, they exchange a series of special frames to negotiate communication parameters. These frames contain the speed and duplex mode options supported by the device, as well as other relevant characteristics. The devices communicate with each other according to their capabilities and preferences, and the optimal communication parameters are finally determined.

Auto-negotiation can effectively ensure compatibility between devices and automatically adjust communication parameters without manual intervention when network configuration changes. In this way, the network administrator can manage the network more easily while ensuring optimal performance and reliability between network devices, which makes high demands on the identification of auto-negotiated frame content, and whether the frame content can be correctly identified within the required time is a key to the problem.

IEEE802.3 CL73, etc. specifies the format of an Auto-negotiation frame (Auto-Negotiation frames), the main content being to specify that each bit (bit) has a duration of 3.2ns (312.5 Mbps) to enable the peer device to communicate freely without negotiating the result, which requires that the SerDes be able to send and receive signals at 312.5Mbps no matter what rate it is operating at. Because the clock frequency of the local equipment works on different crystal oscillators, the clock frequency of the local equipment and the clock frequency of the opposite-end equipment certainly have frequency deviation. It is now common practice to fix the local clock to an integer multiple of 312.5M (e.g. SerDes operates at 10.3125g, 33 times 312.5M) and then lock the local clock to the input data using Bang-Bang Clock Data Recovery (CDR) to make a correct decision. There are three problems with this approach. The problem is that Inter Symbol Interference (ISI) due to long 0 or long 1 affects where the 0/1 handover corresponds to cause decision errors in the handover (e.g., serDes may jump back and forth in 0/1 handover). The second problem is that CDR performance is stable in operation, and the condition of losing lock cannot occur in the working process, because the occurrence of missing bit or multiple bits can cause direct error in the judgment of frame content. The third problem is that for high speed SerDes, a relatively low rate is also supported for auto-negotiation, which can be an additional cost, and a rate switch is required before and after auto-negotiation to operate the SerDes in normal rate mode. The invention provides a circuit for automatically negotiating high identification rate of frames, which can correctly identify the content of the frames by 100% under normal conditions.

This section is intended to provide a background or context to the embodiments of the application that are recited in the claims. The description herein is not admitted to be prior art by inclusion in this section.

Disclosure of Invention

The application aims to provide a circuit for identifying the content of an Ethernet auto-negotiation frame, which can accurately identify the content of the auto-negotiation frame.

The application discloses a circuit for identifying the content of an Ethernet auto-negotiation frame, which comprises:

a first computing module for receiving an input signal from a SerDes receiver and identifying respective locations of high and low levels from the input signal;

the signal edge detection module is used for identifying the position where the high-low level jump occurs for the first time in each sampling period according to the identified respective positions of the high level and the low level, and marking the jump position where the high level jumps to the high level firstly when the low level is continuously identified and the jump position where the low level jumps to the low level when the low level is continuously identified in each sampling period;

The judgment adding and deleting module is used for determining whether to perform adding judgment and deleting judgment according to whether the jump position changes or not; and

And the second calculation and judgment output module is used for calculating a middle position according to the jump position and the addition judgment and deletion judgment and outputting the middle position as a judgment result.

In a preferred embodiment, the clock of the SerDes receiving end is M times of the clock of the SerDes sending end, and the intermediate position is a position of pushing floor (1/2*M) or floor (1/2*M) +1 bits back from the current jump position, where M is a positive integer.

In a preferred embodiment, M is 33.

In a preferred embodiment, if no high-low level transition occurs in the current sampling period, the signal edge detection module keeps the transition position of the last sampling period as the transition position of the current period.

In a preferred embodiment, the deletion decision comprises deleting an intermediate position within the current sampling period that is derived from the transition position of the previous sampling period if the difference of the transition position of the current sampling period minus the transition position of the previous sampling period is greater than a first predetermined value.

In a preferred embodiment, the first predetermined value is 20.

In a preferred embodiment, the decision adding/deleting module determines to make a deletion decision if the jump position changes from 0 to a maximum value, the deletion decision including deleting an intermediate position estimated from the jump position of 0.

In a preferred embodiment, if the difference between the jump position of the current sampling period and the jump position of the last sampling period is smaller than the second predetermined value, the decision adding/deleting module determines to make an adding decision, where the adding decision includes adding an intermediate position to the jump position of the current sampling period by the position of floor (1/2*M) or floor (1/2*M) +1 bit, where M is a multiple of the clock of the SerDes receiving end relative to the clock of the SerDes transmitting end.

In a preferred embodiment, the second predetermined value is-20.

In a preferred embodiment, if the jump position changes from the maximum value to 0, the decision adding/deleting module determines to make an increase decision, where the increase decision includes pushing the floor (1/2*M) or floor (1/2*M) +1 bits back at the jump position of the maximum value by an intermediate position, where M is a multiple of the clock of the SerDes receiving end relative to the clock of the SerDes transmitting end.

In the embodiment of the application, the position of the 0/1 jump is detected instead of the position of the long 0 (low level) or the long 1 (high level), the intermediate position is calculated according to the oversampling multiple by utilizing the jump position, and the identification result of the intermediate position is used as the judgment result of the signal. Because there is sufficient margin available for over-sampling, the problem of inter-symbol interference is avoided, enabling 100% correct identification of auto-negotiation frame content.

The numerous technical features described in the description of the present application are distributed among the various technical solutions, which can make the description too lengthy if all possible combinations of technical features of the present application (i.e., technical solutions) are to be listed. In order to avoid this problem, the technical features disclosed in the above summary of the application, the technical features disclosed in the following embodiments and examples, and the technical features disclosed in the drawings may be freely combined with each other to constitute various new technical solutions (which should be regarded as having been described in the present specification) unless such a combination of technical features is technically impossible. For example, in one example, feature a+b+c is disclosed, in another example, feature a+b+d+e is disclosed, and features C and D are equivalent technical means that perform the same function, technically only by alternative use, and may not be adopted simultaneously, feature E may be technically combined with feature C, and then the solution of a+b+c+d should not be considered as already described because of technical impossibility, and the solution of a+b+c+e should be considered as already described.

Drawings

Fig. 1 is a block diagram schematic diagram of a circuit for identifying ethernet auto-negotiation frame content in accordance with one embodiment of the present application.

FIG. 2 is a schematic diagram of a SerDes output in accordance with one embodiment of the application.

Fig. 3 is a schematic diagram of a delete decision in accordance with an embodiment of the present application.

Fig. 4 is a schematic diagram of an increase decision in one embodiment according to the application.

In the drawings, each is indicated as follows:

101-a first computing module;

102-a signal edge detection module;

103-judging an adding and deleting module;

104-a second calculation and decision output module;

105-SerDes receiver.

Detailed Description

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. It will be understood by those skilled in the art that the claimed application may be practiced without these specific details and with various changes and modifications from the embodiments that follow.

Description of the partial concepts:

SerDes is an acronym for english SERializer/DESerializer. It is a mainstream Time Division Multiplexing (TDM), point-to-point (P2P) serial communication technology. The multi-path low-speed parallel signals are converted into high-speed serial signals at the transmitting end, and finally the high-speed serial signals are converted into low-speed parallel signals at the receiving end through a transmission medium (an optical cable or a copper wire). The point-to-point serial communication technology fully utilizes the channel capacity of a transmission medium, reduces the number of required transmission channels and device pins, and improves the transmission speed of signals, thereby greatly reducing the communication cost.

The SerDes (sequencer/Deserializer) receiver is a component for receiving a serial data stream from a remote device and converting it into parallel data. The SerDes (sequencer/Deserializer) sender is a component for converting parallel data into a serial data stream and transmitting. In high-speed serial communications, serDes transmitters are commonly used to convert parallel data into a serial signal suitable for transmission, such as in network devices, storage systems, and communication systems.

The floor () function rounds one real number down to the integer closest to it and is no greater than the original real number.

The cell () function rounds one real number up to the integer closest to it and is not smaller than the original real number.

For the purpose of making the objects, technical solutions and advantages of the present application more apparent, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

One embodiment of the present application relates to a circuit for identifying the content of an ethernet auto-negotiation frame, the block diagram of which is shown in fig. 1, and the circuit includes a first calculation module 101, a signal edge detection module 102, a decision adding/deleting module 103, and a second calculation and decision output module 104. An input of the first calculation module 101 is coupled to a SerDes Receiver (RX) 105. An output of the first calculation module 101 is coupled to a signal edge detection module 102 and a second calculation and decision output module 104. The output of the signal edge detection block 102 is coupled to a decision adding/deleting block 103. The output of the decision adding/deleting module 103 is coupled to a second calculation and decision output module 104.

The first calculation module 101 is configured to receive an input signal from a SerDes receiving terminal (RX) 105 and identify respective positions of a high level (denoted as "1") and a low level (denoted as "0") from the input signal. In one embodiment, the SerDes RX 105 operates with a sampling clock 33 times the operating clock of the SerDes transmitter (not shown). For example, the transmit-side operating clock is 312.5MHz, while SerDes RX operates at a frequency of 10.3125GHz, which is 33 times 312.5M. When the voltage value of the input signal received by the first computing module 101 from the SerDes RX 105 is higher than the preset threshold, the corresponding input signal is considered to be 1, and when the voltage value of the input signal received by the first computing module 101 from the SerDes RX 105 is lower than the preset threshold, the corresponding input signal is considered to be 0, and accordingly, the first computing module 101 identifies the input signal received from the SerDes RX 105 and determines the positions of the 1 and 0 respectively.

In one embodiment, the clock at the SerDes receiver is M times the clock at the SerDes sender, where M is a positive integer. In one embodiment, M is 33. It should be understood that M is taken as 33 in the present application and that M is not limited by this value, and may be set to any other positive integer, for example, any integer between 20 and 100 in other embodiments of the present application.

Fig. 2 is a schematic diagram of SerDes inputs and outputs according to an embodiment of the application, where the sender sends a "010" signal (signal a in fig. 2) to SerDes RX 105 at 312.5MHz, for example, with the ideal sampling and outputs of SerDes RX 105 being 330 s, 33 1 s and 330 s, as shown by signal b in fig. 2. However, due to intersymbol interference, a transition occurs when switching between 0 and 1. The signal edge detection module 102 is configured to identify, from the input signal, a position at which a transition of a high level and a low level occurs in each sampling period (or called beat) according to the identified respective positions of the high level and the low level, and further identify, from the positions of 1 and 0 identified by the first calculation module 101, a position at which a transition of 1 and 0 occurs, for example, a position at which a transition from 1 to 0 or a position at which a transition from 0 to 1 occurs. The transition position that transitions from low to high first when the continuous signal is recognized as low and the transition position that transitions from high to low first when the continuous signal is recognized as high (denoted as p 1) are marked. For example, referring to signal c of fig. 2, as indicated by the marked dashed boxes, where more than one 0 to 1,1 to 0 transitions, respectively, occur, whereas in this embodiment only the locations where the first 0 to 1 or 1 to 1 transitions occur in each sampling period are marked. When the first calculation module 101 continuously recognizes 0, the signal edge detection module 102 marks the position where the first transition from 0 to 1 occurs, and when the first calculation module 101 continuously recognizes 1, the signal edge detection module 102 marks the position where the first transition from 1 to 0 occurs, and both are marked as p1.

It should be appreciated that the term "transition position p1" indicates the position at which the transition occurs for the current sampling period corresponds to the bit sequence number. The transition position p1 is dynamically changed. For a "010" signal, one p1 transition position occurs every one sample period. It should be noted that only the first position of the transition is marked in each sampling period, i.e. each sampling period has only one transition position p1.

In one embodiment, the signal edge detection module maintains the transition position of the last sampling period as the transition position of the current period if no high-low level transition occurs within the current sampling period (i.e., no p1 position is identified). For example, if the jump position p1=0 of the previous sampling period does not occur in the current sampling period, the jump position of the current sampling period defaults to a position p1=0, and the value of the jump position p1 is stored in the register and does not change.

The second calculation and decision output module 104 calculates an intermediate position (denoted as p 2) from the jump position p1 and outputs the intermediate position as a decision result. The middle position p2 is the position of the current jump position p1 pushing back floor (1/2*M) or floor (1/2*M) +1 bits. Wherein floor () represents a rounding down. Taking 33 as an example, each week comprises 33 bits, e.g., in order from bit 32 to bit 0. floor (1/2×33) =16. It should be appreciated that the intermediate position p2 is the position of the current transition position p1 pushed back by cell (1/2*M) or cell (1/2*M) +1 bits. Where cell () represents a round-up. For example, the intermediate position p2 is a current jump position p1, which is pushed back by floor (1/2*M) bits (i.e. 16 bits), when the current jump position corresponds to the 0 th bit, the intermediate position may select a position corresponding to the 16 th bit of the next period, and when the current jump position corresponds to the 31 st bit, the intermediate position may select a position corresponding to the 15 th bit of the current period. It should be noted that there is only one intermediate position p2 within each sampling period.

With continued reference to fig. 1, the decision adding/deleting module 103 is configured to determine whether to perform an adding decision and a deleting decision according to whether the jump position changes, and the second calculating and decision outputting module 104 further calculates an intermediate position (denoted as p 2) according to the jump position and the adding decision and the deleting decision, and outputs the intermediate position as a decision result. Wherein adding a decision means adding an intermediate position and deleting a decision means deleting an intermediate position. And when the jump position p1 changes, the frequency deviation exists between the clock of the SerDes receiving end and the clock of the SerDes transmitting end.

Specifically, if the difference of the jump position of the current sampling period minus the jump position of the last sampling period is greater than a first preset value, the decision adding and deleting module determines to perform deleting decision, and deleting decision includes deleting the intermediate position calculated according to the last sampling period in the current sampling period. In one embodiment, the first predetermined value may be 20. It should be appreciated that in other embodiments of the present application, the first predetermined value is not limited to this value, and may be set to any other positive integer, for example, any integer between 15 and M-1 (e.g., 32). If the difference of the jump position of the current sampling period minus the jump position of the last sampling period is larger than a first preset value (for example, 20), the forward shift of the data of the current period is indicated, and the intermediate position calculated according to the last sampling period should be discarded.

In one embodiment, the decision adding/subtracting module determines to make an increase decision if the difference of the transition position of the current sampling period minus the transition position of the previous sampling period is less than a second predetermined value, the increase decision comprising pushing the floor (1/2*M) or floor (1/2*M) +1 bit forward at the transition position of the current sampling period by an intermediate position, where M is a multiple of the clock at the SerDes receiver relative to the clock at the SerDes sender. In one embodiment, the second predetermined value may be-20. It should be appreciated that in other embodiments of the application, the second predetermined value is not limited to this value, but may be set to any other positive integer, such as any integer between-15 and- (M-1) (e.g., -32). If the difference between the jump position of the current sampling period and the jump position of the last sampling period is smaller than a second preset value (for example, -20), the data of the current period is indicated to be negatively shifted, the current sampling period is short of an intermediate position, and the intermediate position needs to be calculated in a complementary mode.

In a particular embodiment, the decision adding/deleting module determines to make a deletion decision if the jump position changes from 0 to a maximum value, the deletion decision comprising deleting an intermediate position derived from the jump position of 0.

In a specific embodiment, if the transition position changes from maximum to 0, the decision adding/deleting module determines to make an increase decision, where the increase decision includes pushing the floor (1/2*M) or floor (1/2*M) +1 bit forward at the transition position of 0 by an intermediate position, where M is a multiple of the clock at the SerDes receiver relative to the clock at the SerDes transmitter.

It should be noted that the order of sampling per cycle is from bit 32 to bit 0, the term "push-back" means that the calculation is made from bit 32 to bit 0 of the current cycle in order, and possibly the next cycle. The term "push forward" means that the calculation is made sequentially from the 0 th bit to the 32 nd bit of the current cycle, and it is possible to calculate the previous cycle.

Fig. 3 is a schematic diagram of a delete decision in accordance with an embodiment of the present application. The recognition results of the high and low levels and their transition positions for 4 sampling periods are shown, respectively. In the first period, a transition occurs in bit 0, and p1=0. In the second period, the intermediate position estimated from p1=0 in the first period is the position of the 16 th bit, p2=16. In addition, the second period is 1, and no jump position occurs, so the jump position of the first period is kept unchanged, that is, p1=0. In the third period, the intermediate position estimated from p1=0 in the second period is the position of the 16 th bit, p2=16, and if a 1/0 transition occurs in the 31 st bit, p1=31 is present, and therefore the intermediate position estimated from p1=31 is the position of the 15 th bit, p2=15. In the fourth period, since p1=30 is present when the 30 th bit is hopped, the intermediate position estimated from p1=30 is the 14 th bit position, and p2=14. It can be found that in the third cycle two intermediate positions p2 are calculated, the correct intermediate position should be the position p2=15 calculated from the actual occurrence of the 1/0 jump, and thus the intermediate position p2=16 calculated from p1=0 in the second cycle is deleted, as indicated by the deletion line in fig. 3.

Fig. 4 is a schematic diagram of an increase decision in one embodiment according to the application. The recognition results of the high and low levels and their transition positions for 4 sampling periods are shown, respectively. In the first period, when a transition occurs in the 31 st bit, p1=31 and the intermediate position estimated from the transition is the 15 th bit position, p2=15. The second period is similar to the first period. In the third cycle, when a transition occurs in the 0 th bit, p1=0, and the intermediate position estimated from this transition is the 16 th bit position in the next cycle (fourth cycle). In the fourth period, when the 0 th bit jumps, p1=0 is present, and therefore, the intermediate position of the next period is presumed to be the 16 th bit position (not shown) from p1=0. It can be found that one intermediate position p2 is absent in the third period, and therefore the position p1=0 in the transition position of the third period is pushed forward by 16 bits to increase by one intermediate position p2=16, as indicated by the dashed box in fig. 4.

For the problem one, the idea of the above circuit structure is to detect not the position of length 0 or length 1 (p 2 in fig. 2), but the position of the first 0/1 change (p 1 in fig. 2), and to use this position to push back by 1/2 bits (p 2 in fig. 2) of the sampling multiple as the decision result of this signal. Assuming that SerDes operates at 10.3125g,33 times oversampling, then a 16 bit backward decision after finding the 0/1 change point is the desired decision result, which is that the exact position of the 0/1 change point need not be found, since the 33 times oversampling later has enough margin available to circumvent the inter-symbol interference problem presented above.

For the second problem, the invention adds frequency offset detection and processing, and the position p1 of the 0/1 jump is always detected in the processing process, when the position of p1 in the parallel data is detected to change, the frequency offset exists between the input signal and the sampling clock, and the positive and negative of the frequency offset can be judged from the increase or the decrease of the position. If the position of p1 is within one data parallelism, this beat of data needs to be thrown away when p1 jumps from 0 to maximum illustrating a1 beat of data offset (shown in fig. 3), whereas if p1 jumps from maximum to 0 (shown in fig. 4) illustrates that there is a1 beat of additional data needs to be decided (p2=14 in fig. 4 needs to be additionally supplemented).

Problem three comparison, the circuit structure of the present application can be fully adapted by calculating an oversampling rate based on the clock frequency of the SerDes receiver and 312.5M.

It should be noted that in the present patent application, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. In the present patent application, if it is mentioned that an action is performed according to an element, it means that the action is performed at least according to the element, and two cases are included: the act is performed solely on the basis of the element and is performed on the basis of the element and other elements. Multiple, etc. expressions include 2, 2 times, 2, and 2 or more, 2 or more times, 2 or more.

The term "coupled to" and its derivatives may be used herein. "coupled" may mean that two or more elements are in direct physical or electrical contact. However, "coupled" may also mean that two or more elements are in indirect contact with each other, but still cooperate or interact with each other, and may mean that one or more other elements are coupled or connected between elements that are referred to as being coupled to each other.

This specification includes combinations of the various embodiments described herein. Separate references to embodiments (e.g., "one embodiment" or "some embodiments" or "preferred embodiments") do not necessarily refer to the same embodiment; however, unless indicated as mutually exclusive or as would be apparent to one of skill in the art, the embodiments are not mutually exclusive. It should be noted that the term "or" is used in this specification in a non-exclusive sense unless the context clearly indicates otherwise or requires otherwise.

All references mentioned in this specification are to be considered as being included in the disclosure of the application in its entirety so as to be applicable as a basis for modification when necessary. Furthermore, it should be understood that the foregoing description is only of the preferred embodiments of the present application and is not intended to limit the scope of the present application. Any modification, equivalent replacement, improvement, or the like, which is within the spirit and principles of one or more embodiments of the present disclosure, is intended to be included within the scope of one or more embodiments of the present disclosure.

Claims (8)

1. A circuit for identifying the content of an ethernet auto-negotiation frame, comprising:

a first computing module for receiving an input signal from a SerDes receiver and identifying respective locations of high and low levels from the input signal;

the signal edge detection module is used for identifying the position where the high-low level jump occurs for the first time in each sampling period according to the identified respective positions of the high level and the low level, and marking the jump position where the high level jumps to the high level firstly when the low level is continuously identified and the jump position where the low level jumps to the low level when the low level is continuously identified in each sampling period;

The judgment adding and deleting module is used for determining whether to perform adding judgment and deleting judgment according to whether the jump position changes or not; and

And the second calculation and judgment output module is used for calculating a middle position according to the jump position and the addition judgment and deletion judgment and outputting the middle position as a judgment result.

2. The circuit of claim 1, wherein the clock at the SerDes receiver is M times the clock at the SerDes transmitter, and the intermediate position is a position where the current transition position is pushed backward by floor (1/2*M) or floor (1/2*M) +1 bits, where M is a positive integer.

3. The circuit of claim 1 wherein M is 33.

4. The circuit of claim 1, wherein the signal edge detection module maintains a transition position of a previous sampling period as the transition position of the current period if no high-low level transition occurs within the current sampling period.

5. The circuit of claim 1, wherein the decision adding/subtracting module determines to make a deletion decision if a difference of the transition position of the current sampling period minus the transition position of the previous sampling period is greater than a first predetermined value, the deletion decision comprising deleting an intermediate position within the current sampling period that is inferred from the transition position of the previous sampling period.

6. The circuit of claim 5 wherein said first predetermined value is 20.

7. The circuit of claim 1, wherein the decision adding/subtracting module determines to make an increase decision if the difference of the transition position of the current sampling period minus the transition position of the previous sampling period is less than a second predetermined value, the increase decision comprising increasing the transition position of the current sampling period by one intermediate position forward of the floor (1/2*M) or floor (1/2*M) +1 bit, where M is a multiple of the clock of the SerDes receiver relative to the clock of the SerDes transmitter.

8. The circuit of claim 7 wherein said second predetermined value is-20.