CN118138046A - Active interpolation circuit structure applied to high-speed folding interpolation ADC - Google Patents
Active interpolation circuit structure applied to high-speed folding interpolation ADC Download PDFInfo
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Abstract
The application relates to the technical field of integrated circuits, and provides an active interpolation circuit structure applied to a high-speed folding interpolation ADC, which comprises the following components: n two-input differential operational amplifiers are used for receiving n groups of differential signals output by the folding circuit of the high-speed folding interpolation ADC and outputting n groups of interpolation signals; n four-input differential operational amplifiers alternately parallel to the n two-input differential operational amplifiers, the n four-input differential operational amplifiers being configured to receive n sets of differential signals and output n sets of interpolation signals; a fixed phase difference exists between every two adjacent differential signals; each two-input differential operational amplifier corresponds to a group of differential signals respectively; n-1 four-input differential operational amplifiers respectively correspond to two groups of adjacent differential signals, 1 four-input differential operational amplifier corresponds to a first group of differential signals and a last group of differential signals, and n is more than or equal to 2. The scheme of the application can improve the linearity and accuracy of the output signal of the active interpolation circuit structure.
Description
Technical Field
The application relates to the technical field of integrated circuits, in particular to an active interpolation circuit structure applied to a high-speed folding interpolation ADC.
Background
In a high-speed folding interpolation ADC (analog-to-digital converter), the interpolation technology and the folding technology are the core of the ADC circuit design, and the interpolation circuit is usually used as a later stage of the folding circuit, and has the function of generating zero crossing points required by the ADC, and the number of generated zero crossing points is multiplied by the interpolation coefficient. The current circuit structure for realizing interpolation technology is mainly divided into three types of passive interpolation, active interpolation and current interpolation, wherein the active interpolation is a method for generating interpolation signals by interpolation operation and discharge circuits from adjacent signals with different phases, and the interpolation factor is 2.
For a folding interpolation ADC with the resolution of N bits, the number of zero crossing points required is 2N, the method for increasing the number of zero crossing points is an interpolation technology, and passive interpolation is most commonly used at present. But is limited by the effect of passive interpolation boundaries, whose interpolation factor is typically no more than 4, the number of zero crossings required is multiplied by cascading multiple stages of passive interpolation. With the improvement of the resolution of the folding interpolation ADC, the increase of the number of cascade layers of the passive interpolation circuit can lead to the attenuation of the effective interval of the signal, and the circuit performance is seriously reduced. The bandwidth of the signal can be increased through the active interpolation circuit, the effective establishment of the signal is quickened, and the driving capability of the output signal is improved, so that the performance of the folding interpolation ADC is improved.
The traditional active interpolation circuit structure only uses one positive and one negative of two groups of differential adjacent signals, obtains interpolation signals through a differential operational amplifier, and can generate more accurate output signals for ideal input signals. However, as the cascade level of the folding interpolation ADC increases, the signal frequency increases, and the actual input signal has a certain offset error and amplitude gain error after being subjected to multi-stage processing, which results in reduced linearity and accuracy of the output signal when the signal is processed by the conventional active interpolation circuit structure, resulting in reduced performance of the integral folding interpolation ADC.
Therefore, how to improve the linearity and accuracy of the output signal of the active interpolation circuit structure is a problem to be solved.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present application is to provide an active interpolation circuit structure applied to a high-speed folded interpolation ADC, which is used for solving the problem of how to improve the linearity and accuracy of the output signal of the active interpolation circuit structure in the prior art.
To achieve the above and other related objects, the present application provides an active interpolation circuit structure applied to a high-speed folding interpolation ADC, the structure comprising:
n two-input differential operational amplifiers are used for receiving n groups of differential signals output by the folding circuit of the high-speed folding interpolation ADC and outputting n groups of interpolation signals;
n four-input differential operational amplifiers alternately parallel to the n two-input differential operational amplifiers, wherein the n four-input differential operational amplifiers are used for receiving the n groups of differential signals and outputting n groups of interpolation signals; wherein,
A fixed phase difference exists between every two adjacent groups of differential signals;
Each two-input differential operational amplifier corresponds to one group of differential signals respectively;
n-1 four-input differential operational amplifiers respectively correspond to two groups of adjacent differential signals, 1 four-input differential operational amplifier corresponds to a first group of differential signals and a last group of differential signals, and n is more than or equal to 2.
In an embodiment of the present application, when values of a set of adjacent differential signals input to the two-input differential operational amplifiers are the same, a phase difference between zero crossings of the two-input differential operational amplifiers and zero crossings of the four-input differential operational amplifiers input to the adjacent differential signals is half of the fixed phase difference.
In one embodiment of the present application, the two-input differential operational amplifier includes:
the first common-emitter differential operational amplifier module is used for receiving the differential signals;
the emitter follower module is used for outputting the interpolation signal;
The power supply end is connected with one end of the first common-emitter differential operational amplifier module, and one end of the emitter follower module is connected with the power supply end;
the other end of the first common-emitter differential operational amplifier module is connected with the grounding end, and the other end of the emitter follower module is connected with the grounding end.
In an embodiment of the application, the first common-emitter differential operational amplifier module includes:
A first input and a second input for receiving the differential signal;
A first npn transistor and a second npn transistor, the first input terminal being connected to a base of the first npn transistor and the second input terminal being connected to a base of the second npn transistor;
a seventh npn transistor, an emitter of the first npn transistor and an emitter of the second npn transistor being connected to a collector of the seventh npn transistor;
The base electrode of the seventh npn transistor is connected with the bias voltage end;
An emitter of the seventh npn transistor is connected to one end of the fourth resistor, and the other end of the fourth resistor is connected to the ground terminal;
a second resistor and a third resistor, the collector of the first npn transistor being connected to one end of the second resistor, the collector of the second npn transistor being connected to one end of the third resistor;
and the other end of the second resistor and the other end of the third resistor are connected with one end of the first resistor, and the other end of the first resistor is connected with the power supply end.
In one embodiment of the present application, the emitter follower module includes:
A base electrode of the third npn transistor is connected with a collector electrode of the first npn transistor, a base electrode of the fourth npn transistor is connected with a collector electrode of the second npn transistor, and a collector electrode of the third npn transistor and a collector electrode of the fourth npn transistor are connected with the power supply terminal;
A fifth npn transistor having an emitter connected to a collector of the fifth npn transistor, an emitter connected to a collector of the sixth npn transistor, a collector connected to a base of the fifth npn transistor, and a collector connected to a base of the sixth npn transistor;
An eighth npn transistor and a ninth npn transistor, an emitter of the fifth npn transistor being connected to a collector of the eighth npn transistor, an emitter of the sixth npn transistor being connected to a collector of the ninth npn transistor, a base of the eighth npn transistor and a base of the ninth npn transistor being connected to the bias voltage terminal;
A fifth resistor and a sixth resistor, an emitter of the eighth npn transistor being connected to one end of the fifth resistor, the ninth npn transistor being connected to one end of the sixth resistor, the other end of the fifth resistor and the other end of the sixth resistor being connected to the ground terminal;
The first output end and the second output end are used for outputting the interpolation signals, the first output end is connected with the emitter of the third npn transistor and the collector of the fifth npn transistor, and the second output end is connected with the emitter of the fourth npn transistor and the collector of the sixth npn transistor.
In one embodiment of the present application, the four-input differential operational amplifier includes:
the second common-emitter differential operational amplifier module is used for receiving the differential signals;
the emitter follower module is used for outputting the interpolation signal;
the power end is connected with one end of the second common-emitter differential operational amplifier module, and one end of the emitter follower module is connected with the power end;
The other end of the second common-emitter differential operational amplifier module is connected with the grounding end, and the other end of the emitter follower module is connected with the grounding end.
In an embodiment of the application, the second common-stage differential operational amplifier module includes:
The first input end, the second input end, the third input end and the fourth input end are used for receiving the differential signals;
A first npn transistor and a second npn transistor, the first input terminal being connected to a base of the first npn transistor and the second input terminal being connected to a base of the second npn transistor;
a seventh npn transistor, an emitter of the first npn transistor and an emitter of the second npn transistor being connected to a collector of the seventh npn transistor;
The base electrode of the seventh npn transistor is connected with the bias voltage end;
An emitter of the seventh npn transistor is connected to one end of the fourth resistor, and the other end of the fourth resistor is connected to the ground terminal;
a second resistor and a third resistor, the collector of the first npn transistor being connected to one end of the second resistor, the collector of the second npn transistor being connected to one end of the third resistor;
the other end of the second resistor and the other end of the third resistor are connected with one end of the first resistor, and the other end of the first resistor is connected with the power supply end;
a tenth npn transistor and an eleventh npn transistor, wherein the third input terminal is connected to the base of the tenth npn transistor, the fourth input terminal is connected to the base of the eleventh npn transistor, the collector of the tenth npn transistor is connected to the collector of the first npn transistor and one end of the second resistor, the collector of the eleventh npn transistor is connected to the collector of the second npn transistor and one end of the third resistor, and the emitter of the tenth npn transistor and the emitter of the eleventh npn transistor are connected to the collector of the seventh npn transistor.
In an embodiment of the present application, the tail currents of the first npn transistor and the second npn transistor are represented by:
The representation of the collector current flowing through the first npn transistor includes:
the representation of the collector current flowing through the second npn transistor includes:
wherein I TALL is the tail current, V bias is the bias voltage, For the voltage of the seventh npn transistor, R 4 is the resistance of the fourth resistor, α F1 is the characteristic parameter of the first npn transistor, α F2 is the characteristic parameter of the second npn transistor, α F1＝αF2,VT is the temperature parameter, vinpl is the input voltage of the first input terminal, vinn1 is the input voltage of the second input terminal.
In an embodiment of the application, the parameters of the second resistor are the same as the parameters of the third resistor;
The parameters of the third npn transistor are the same as the parameters of the fourth npn transistor;
the parameters of the fifth npn transistor are the same as those of the sixth npn transistor;
The parameters of the eighth npn transistor are the same as those of the ninth npn transistor;
The parameters of the fifth resistor are the same as those of the sixth resistor.
In an embodiment of the present application, parameters of the first npn transistor, the second npn transistor, the tenth npn transistor, and the eleventh npn transistor are the same.
The invention has the beneficial effects that:
The active interpolation circuit structure applied to the high-speed folding interpolation ADC in the invention comprises: n two-input differential operational amplifiers are used for receiving n groups of differential signals output by the folding circuit of the high-speed folding interpolation ADC and outputting n groups of interpolation signals; n four-input differential operational amplifiers alternately parallel to the n two-input differential operational amplifiers, wherein the n four-input differential operational amplifiers are used for receiving the n groups of differential signals and outputting n groups of interpolation signals; wherein a fixed phase difference exists between every two adjacent groups of differential signals; each two-input differential operational amplifier corresponds to one group of differential signals respectively; n-1 four-input differential operational amplifiers respectively correspond to two groups of adjacent differential signals, 1 four-input differential operational amplifier corresponds to a first group of differential signals and a last group of differential signals, and n is more than or equal to 2. Compared with a passive interpolation circuit, the active interpolation circuit structure can effectively reduce the amplitude of signal attenuation, increase the bandwidth of signals, improve the driving capability of output signals, accelerate the effective establishment of signals and improve the performance of a folding interpolation ADC; compared with the traditional active interpolation circuit, the active interpolation circuit has better inhibition effect on offset errors, amplitude gain errors and the like, and can improve linearity and interpolation accuracy of output signals.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application as claimed.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application. It is evident that the drawings in the following description are only some embodiments of the present application and that other drawings may be obtained from these drawings without inventive effort for a person of ordinary skill in the art. In the drawings:
fig. 1 is a schematic diagram of an active interpolation circuit structure according to an exemplary embodiment of the present application;
FIG. 2 is a schematic diagram of a two-input differential operational amplifier according to an exemplary embodiment of the present application;
Fig. 3 is a schematic diagram of a four-input differential operational amplifier according to an exemplary embodiment of the present application;
fig. 4 is a schematic diagram of the structure of an active interpolation circuit according to another exemplary embodiment of the present application.
Detailed Description
Further advantages and effects of the present invention will become readily apparent to those skilled in the art from the disclosure herein, by referring to the accompanying drawings and the preferred embodiments. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention. It should be understood that the preferred embodiments are presented by way of illustration only and not by way of limitation.
It should be noted that the illustrations provided in the following embodiments merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complicated.
In the following description, numerous details are set forth in order to provide a more thorough explanation of embodiments of the present invention, it will be apparent, however, to one skilled in the art that embodiments of the present invention may be practiced without these specific details, in other embodiments, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the embodiments of the present invention.
In an embodiment of the present application, in order to solve the problem of how to improve the linearity and accuracy of the output signal of the active interpolation circuit structure, an active interpolation circuit structure applied to a high-speed folded interpolation ADC is provided, where the active interpolation circuit structure includes:
n two-input differential operational amplifiers are used for receiving n groups of differential signals output by the folding circuit of the high-speed folding interpolation ADC and outputting n groups of interpolation signals;
n four-input differential operational amplifiers alternately parallel to the n two-input differential operational amplifiers, wherein the n four-input differential operational amplifiers are used for receiving the n groups of differential signals and outputting n groups of interpolation signals; wherein,
A fixed phase difference exists between every two adjacent groups of differential signals;
Each two-input differential operational amplifier corresponds to one group of differential signals respectively;
n-1 four-input differential operational amplifiers respectively correspond to two groups of adjacent differential signals, 1 four-input differential operational amplifier corresponds to a first group of differential signals and a last group of differential signals, and n is more than or equal to 2.
In an embodiment of the present application, when values of a set of adjacent differential signals input to the two-input differential operational amplifier are the same, a phase difference between zero crossings of the two-input differential operational amplifier and zero crossings of the four-input differential operational amplifier input to the adjacent differential signal is half of the fixed phase difference.
Referring to fig. 1, for example, fig. 1 is a schematic diagram of an active interpolation circuit structure according to an exemplary embodiment of the present application. The active interpolation circuit structure in fig. 1 is applied to the middle and later stages in the high-frequency high-precision folding interpolation ADC, can be used in cascade with the active interpolation or passive interpolation structure, and is suitable for the differential signals of n groups of inputs. In fig. 1, n two-input differential operational amplifiers AMP1 and n four-input differential operational amplifiers AMP2 are alternately parallel, and n groups of differential signals output from the folding circuit can be subjected to active interpolation. The active interpolation structure can effectively reduce the amplitude of signal attenuation, increase the bandwidth of signals, improve the driving capability of output signals, accelerate the effective establishment of signals and improve the performance of a circuit.
Between every two adjacent sets of differential signals there is a fixed phase difference (the fixed phase difference may be, for example, pi/n). The front-stage folding circuit outputs n groups of adjacent differential signals VP1 and VM1; VP2, VM2; … … VPn, VMn, generating 2n groups of differential signals VOP1, VOM1 by n two-input differential operational amplifiers and n four-input differential operational amplifiers of the active interpolation circuit; VOP2, VOM2; VOP3, VOM3; VOP4, VOM4 … … VOP2n-1, VOM2n-1; VOP2n, VOM2n. Wherein the differential signal pair VPn and VMn (n=1, 2,3 … … n) generates interpolation signals VOP2n-1 and VOM2n-1 (n=1, 2,3 … … n) through the two-input differential operational amplifier AMP 1; adjacent differential signal pairs VPn-1, VMn-1 and VPn, VMn (n=1, 2,3 … … n) generate interpolation signals VOP2n-2 and VOM2n-2 (n=1, 2,3 … … n) through a four-input differential operational amplifier AMP 2; and the last group of differential signals VPn, VMn and VP1, VM1 generates interpolation signals VOP2n and VOM2n through the four-input differential operational amplifier AMP 2.
The phase difference between adjacent differential input signals is known as pi/n, and an input differential signal pair Vp1=sin (x), vm1= -sin (x), VPn-1=sin [ x- (n-2) pi/n ], VMn-1= -sin [ x- (n-2) pi/n ], and adjacent signals VPn=sin [ x- (n-1) pi/n ], VMn= -sin [ x- (n-1) pi/n ]. When the two-input differential operational amplifier inputs a differential signal pair VPn-1=vmn-1, the zero crossing point is x= (n-2) pi/n; when four-input differential operational amplifiers input adjacent signals VPn-1, VMn-1 and VPn, VMn, zero-crossing points are x '= (2 n-3) pi/2 n, and the phase difference of the two zero-crossing points is dx=x-x' =pi/2 n, which is half of the phase difference between the adjacent signals. The linearity of the input signal and the performance of the operational amplifier are important to the accuracy of the interpolation signal, so the operational amplifier is the core of the active interpolation circuit structure.
In one embodiment of the present application, the two-input differential operational amplifier includes:
the first common-emitter differential operational amplifier module is used for receiving the differential signals;
the emitter follower module is used for outputting the interpolation signal;
The power supply end is connected with one end of the first common-emitter differential operational amplifier module, and one end of the emitter follower module is connected with the power supply end;
the other end of the first common-emitter differential operational amplifier module is connected with the grounding end, and the other end of the emitter follower module is connected with the grounding end.
Illustratively, the operational amplifiers AMP1 and AMP2 proposed by the present invention are each constructed using npn transistors and resistors. The input stages of AMP1 and AMP2 are first common-emitter differential operational amplifier modules, the output stage is an emitter follower module, the power supply voltage is VCC, the bias voltage is V bias, and the ground voltage is GND.
In an embodiment of the present application, the first common-stage differential operational amplifier module includes:
A first input and a second input for receiving the differential signal;
A first npn transistor and a second npn transistor, the first input terminal being connected to a base of the first npn transistor and the second input terminal being connected to a base of the second npn transistor;
a seventh npn transistor, an emitter of the first npn transistor and an emitter of the second npn transistor being connected to a collector of the seventh npn transistor;
The base electrode of the seventh npn transistor is connected with the bias voltage end;
An emitter of the seventh npn transistor is connected to one end of the fourth resistor, and the other end of the fourth resistor is connected to the ground terminal;
a second resistor and a third resistor, the collector of the first npn transistor being connected to one end of the second resistor, the collector of the second npn transistor being connected to one end of the third resistor;
and the other end of the second resistor and the other end of the third resistor are connected with one end of the first resistor, and the other end of the first resistor is connected with the power supply end.
In one embodiment of the present application, the emitter follower module includes:
A base electrode of the third npn transistor is connected with a collector electrode of the first npn transistor, a base electrode of the fourth npn transistor is connected with a collector electrode of the second npn transistor, and a collector electrode of the third npn transistor and a collector electrode of the fourth npn transistor are connected with the power supply terminal;
A fifth npn transistor having an emitter connected to a collector of the fifth npn transistor, an emitter connected to a collector of the sixth npn transistor, a collector connected to a base of the fifth npn transistor, and a collector connected to a base of the sixth npn transistor;
An eighth npn transistor and a ninth npn transistor, an emitter of the fifth npn transistor being connected to a collector of the eighth npn transistor, an emitter of the sixth npn transistor being connected to a collector of the ninth npn transistor, a base of the eighth npn transistor and a base of the ninth npn transistor being connected to the bias voltage terminal;
A fifth resistor and a sixth resistor, an emitter of the eighth npn transistor being connected to one end of the fifth resistor, the ninth npn transistor being connected to one end of the sixth resistor, the other end of the fifth resistor and the other end of the sixth resistor being connected to the ground terminal;
The first output end and the second output end are used for outputting the interpolation signals, the first output end is connected with the emitter of the third npn transistor and the collector of the fifth npn transistor, and the second output end is connected with the emitter of the fourth npn transistor and the collector of the sixth npn transistor.
Referring to fig. 2, fig. 2 is a schematic diagram illustrating a two-input differential operational amplifier according to an exemplary embodiment of the present application. As shown in fig. 2, the first input Vinp1 and the second input Vinn1 are connected to the bases of the first npn transistor Q1 and the second npn transistor Q2, respectively; the emitters of Q1 and Q2 are connected together with the collector of a seventh npn transistor Q7, the base of Q7 receiving a bias voltage V bias; the emitter of Q7 is connected to one end of a fourth resistor R4, the other end GND of R4 being grounded. The collectors of Q1 and Q2 are connected to a second resistor R2 and a third resistor R3 for the load, respectively, the other ends of R2 and R3 are connected together to one end of a first resistor R1, and the other end of R1 receives a power supply VCC. The bases of the third npn transistor Q3 and the fourth npn transistor Q4 are connected to the collectors of Q1 and Q2, respectively, the collectors of Q3 and Q4 receive the power supply voltage VCC, the emitters of Q3 and Q4 are connected to the collectors of the fifth npn transistor Q5 and the sixth npn transistor Q6, respectively, the collectors of Q5 and Q6 are connected to the respective bases, the emitters of Q5 and Q6 are connected to the collectors of the eighth npn transistor Q8 and the ninth npn transistor Q9, respectively, the bases of Q8 and Q9 receive the bias voltage V bias, the emitters of Q8 and Q9 are connected to one ends of the fifth resistor R5 and the sixth resistor R6, respectively, and the other ends GND of R5 and R6 are grounded. The first output terminal Voutn is connected to the emitter of Q3 and the collector and base of Q5, and the second output terminal Voutp is connected to the emitter of Q4 and the collector and base of Q6.
In one embodiment of the present application, the four-input differential operational amplifier includes:
the second common-emitter differential operational amplifier module is used for receiving the differential signals;
the emitter follower module is used for outputting the interpolation signal;
the power end is connected with one end of the second common-emitter differential operational amplifier module, and one end of the emitter follower module is connected with the power end;
The other end of the second common-emitter differential operational amplifier module is connected with the grounding end, and the other end of the emitter follower module is connected with the grounding end.
In an embodiment of the present application, the second common-stage differential operational amplifier module includes:
The first input end, the second input end, the third input end and the fourth input end are used for receiving the differential signals;
A first npn transistor and a second npn transistor, the first input terminal being connected to a base of the first npn transistor and the second input terminal being connected to a base of the second npn transistor;
a seventh npn transistor, an emitter of the first npn transistor and an emitter of the second npn transistor being connected to a collector of the seventh npn transistor;
The base electrode of the seventh npn transistor is connected with the bias voltage end;
An emitter of the seventh npn transistor is connected to one end of the fourth resistor, and the other end of the fourth resistor is connected to the ground terminal;
a second resistor and a third resistor, the collector of the first npn transistor being connected to one end of the second resistor, the collector of the second npn transistor being connected to one end of the third resistor;
the other end of the second resistor and the other end of the third resistor are connected with one end of the first resistor, and the other end of the first resistor is connected with the power supply end;
a tenth npn transistor and an eleventh npn transistor, wherein the third input terminal is connected to the base of the tenth npn transistor, the fourth input terminal is connected to the base of the eleventh npn transistor, the collector of the tenth npn transistor is connected to the collector of the first npn transistor and one end of the second resistor, the collector of the eleventh npn transistor is connected to the collector of the second npn transistor and one end of the third resistor, and the emitter of the tenth npn transistor and the emitter of the eleventh npn transistor are connected to the collector of the seventh npn transistor.
Referring to fig. 3, for example, fig. 3 is a schematic diagram of a four-input differential operational amplifier according to an exemplary embodiment of the present application. As shown in fig. 3, the four-input differential operational amplifier has a circuit structure of a two-input differential operational amplifier, in which a tenth npn transistor Q10 and an eleventh npn transistor Q11 are added, a newly added third input terminal Vinp2 is connected to the base of Q10, and a newly added fourth input terminal Vinn2 is connected to the base of Q11. The collector of Q10 is connected to the collector of Q1 and one end of R2, and the collector of Q11 is connected to the collector of Q2 and one end of R3. The emitters of Q10 and Q11 are connected together with the emitters of Q1 and Q2 and the collector of Q7. The other circuit structures of the four-input differential operational amplifier are identical to those of the two-input differential operational amplifier, and the description of the embodiment is omitted.
In one embodiment of the application, the method is characterized by:
the representation of the tail currents of the first npn transistor and the second npn transistor includes:
The representation of the collector current flowing through the first npn transistor includes:
the representation of the collector current flowing through the second npn transistor includes:
wherein I TALL is the tail current, V bias is the bias voltage, For the voltage of the seventh npn transistor, R 4 is the resistance of the fourth resistor, α F1 is the characteristic parameter of the first npn transistor, α F2 is the characteristic parameter of the second npn transistor, α F1＝αF2,VT is the temperature parameter, vinpl is the input voltage of the first input terminal, vinn1 is the input voltage of the second input terminal.
For a two-input differential operational amplifier, the input cascode differential pair transistors Q1 and Q2, tail current source I TALL is determined by Q7, R4 and bias voltage V bias, V T being approximately equal to 26mV at room temperature, for example. As is known from the representation of the collector current of the first npn transistor and the collector current of the second npn transistor, the collector current is exponentially related to the input differential voltage, and when I (Vinp) - (Vinn) I >3V T, one of the crystals is completely turned off and all the current I TALL flows to the other npn transistor.
In an embodiment of the application, the parameters of the second resistor are the same as the parameters of the third resistor;
The parameters of the third npn transistor are the same as the parameters of the fourth npn transistor;
the parameters of the fifth npn transistor are the same as those of the sixth npn transistor;
The parameters of the eighth npn transistor are the same as those of the ninth npn transistor;
The parameters of the fifth resistor are the same as those of the sixth resistor.
Illustratively, in the circuit design, resistor R2 is consistent with the R3 parameter, r2=r3=r. The voltage values of the output voltages vo1 and vo2 of the first common-emitter differential operational amplifier module are vo1=vcc-r1×i TALL-R2*ICQ1,vo2＝VCC-R1*ITALL-R3*ICQ2, respectively. In the circuit design, Q3 and Q4 are identical, and npn transistors Q5 and Q6 are identical in diode connection, so that output voltage voutn=vcc-r1×i TALL-R2*ICQ1-Vbe3,Voutp＝VCC-R1*ITALL-R3*ICQ2-Vbe4 of the emitter follower module is identical. In the circuit design, the Q8 and Q9 parameters that produce the output bias current are identical, and the resistor R5 is identical to the R6 parameter.
In an embodiment of the present application, parameters of the first npn transistor, the second npn transistor, the tenth npn transistor, and the eleventh npn transistor are the same.
Illustratively, for a four-input differential operational amplifier, the Q1, Q2, Q10, and Q11 parameters are exactly identical in circuit design. Collector currents ICQ1, ICQ2, ICQ10 and ICQ11 flowing through differential pair transistors Q1, Q2, Q10 and Q11 are determined by input voltages Vinp1, vinn1, vinp2, vinn 2. The four input voltage values are sequentially ordered from large to small to obtain voltage values V1> V2> V3> V4, when the difference between the maximum voltage V1 and the second maximum voltage V2 exceeds 3VT, the other 3 crystals are completely cut off, and all current I TALL flows to an npn transistor with the largest input voltage.
Referring to fig. 4 for an exemplary illustration, fig. 4 is a schematic diagram of an active interpolation circuit structure according to another exemplary embodiment of the present application. Fig. 4 is a schematic structural diagram of an active interpolation circuit structure when n is 4, and as shown in fig. 4, the front stage folding circuit outputs 4 sets of adjacent differential signals VP1, VM1; VP2, VM2; VP3, VM3; VP4, VM4, the phase difference between adjacent differential signals is pi/4, the common mode voltage of the differential signals is Vcm, the amplitude of the differential signals is a, and then the expression of 4 groups of adjacent differential signals is as follows:
VP1＝Vcm+a*sinx，VM1＝Vcm-a*sinx；
VP2＝Vcm+a*sin(x-π/4)，VM2＝Vcm-a*sin(x-π/4)；
VP3＝Vcm+a*sin(x-2π/4)，VM3＝Vcm-a*sin(x-2π/4)；
VP4＝Vcm+a*sin(x-3π/4)，VM4＝Vcm-a*sin(x-3π/4)。
Generating 8 sets of adjacent interpolation signals VOP1, VOM1 by 4 two-input differential operational amplifiers AMP1 and 4 four-input differential operational amplifiers AMP2 of the active interpolation circuit; VOP2, VOM2; … … VOP8, VOM8. Wherein the differential signal pair VP1 and VM1 generates output signals VOP1 and VOM1 through a two-input differential operational amplifier AMP 1; adjacent differential signals VP1, VM1 and VP2, VM2 generate interpolation signals VOP2 and VOM2 through a four-input differential operational amplifier AMP 2; the differential signals VP2 and VM2 generate interpolation signals VOP3 and VOM3 through a two-input differential operational amplifier AMP 1; adjacent differential signal pairs VP2, VM2 and VP3, VM3 generate interpolation signals VOP4 and VOM4 through a four-input differential operational amplifier AMP 2; the differential signals VP3 and VM3 are operated and amplified through a two-input differential operational amplifier AMP1 to generate interpolation signals VOP5 and VMO5; adjacent differential signals VP3, VM3 and VP4, VM4 generate interpolation signals VOP6 and VMO6 through a four-input differential operational amplifier AMP 2; the differential signals VP4 and VM4 are operated and amplified through a two-input differential operational amplifier AMP1 to generate VOP7 and VOM7; the differential signals VP4, VM4 and VP1, VM1 generate interpolation signals VOP8 and VOM8 through a four-input differential operational amplifier AMP 2.
Therefore, based on the above embodiment, compared with the passive interpolation circuit, the active interpolation circuit structure of the invention can effectively reduce the amplitude of signal attenuation, increase the bandwidth of signals, improve the driving capability of output signals, accelerate the effective establishment of signals and improve the performance of the folding interpolation ADC; compared with the traditional active interpolation circuit, the active interpolation circuit has better inhibition effect on offset errors, amplitude gain errors and the like, and can improve linearity and interpolation accuracy of output signals.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. It is therefore intended that all equivalent modifications and changes made by those skilled in the art without departing from the spirit and technical spirit of the present invention shall be covered by the appended claims.
Claims (10)
1. An active interpolation circuit architecture for a high-speed folded interpolation ADC, the architecture comprising:
n two-input differential operational amplifiers are used for receiving n groups of differential signals output by the folding circuit of the high-speed folding interpolation ADC and outputting n groups of interpolation signals;
n four-input differential operational amplifiers alternately parallel to the n two-input differential operational amplifiers, wherein the n four-input differential operational amplifiers are used for receiving the n groups of differential signals and outputting n groups of interpolation signals; wherein,
A fixed phase difference exists between every two adjacent groups of differential signals;
Each two-input differential operational amplifier corresponds to one group of differential signals respectively;
n-1 four-input differential operational amplifiers respectively correspond to two groups of adjacent differential signals, 1 four-input differential operational amplifier corresponds to a first group of differential signals and a last group of differential signals, and n is more than or equal to 2.
2. The active interpolation circuit architecture for a high-speed folded interpolation ADC of claim 1, wherein:
When the values of a group of adjacent differential signals input to the two-input differential operational amplifier are the same, the phase difference between the zero crossing point of the two-input differential operational amplifier and the zero crossing point of the four-input differential operational amplifier input to the adjacent differential signal is half of the fixed phase difference.
3. The active interpolation circuit structure applied to a high-speed folded interpolation ADC according to claim 1, wherein the two-input differential operational amplifier comprises:
the first common-emitter differential operational amplifier module is used for receiving the differential signals;
the emitter follower module is used for outputting the interpolation signal;
The power supply end is connected with one end of the first common-emitter differential operational amplifier module, and one end of the emitter follower module is connected with the power supply end;
the other end of the first common-emitter differential operational amplifier module is connected with the grounding end, and the other end of the emitter follower module is connected with the grounding end.
4. The active interpolation circuit architecture for a high-speed folded interpolation ADC of claim 3, wherein the first common-stage differential op-amp module comprises:
A first input and a second input for receiving the differential signal;
A first npn transistor and a second npn transistor, the first input terminal being connected to a base of the first npn transistor and the second input terminal being connected to a base of the second npn transistor;
a seventh npn transistor, an emitter of the first npn transistor and an emitter of the second npn transistor being connected to a collector of the seventh npn transistor;
The base electrode of the seventh npn transistor is connected with the bias voltage end;
An emitter of the seventh npn transistor is connected to one end of the fourth resistor, and the other end of the fourth resistor is connected to the ground terminal;
a second resistor and a third resistor, the collector of the first npn transistor being connected to one end of the second resistor, the collector of the second npn transistor being connected to one end of the third resistor;
and the other end of the second resistor and the other end of the third resistor are connected with one end of the first resistor, and the other end of the first resistor is connected with the power supply end.
5. The active interpolation circuit architecture for a high-speed folded interpolation ADC of claim 4, wherein the stage follower module comprises:
A base electrode of the third npn transistor is connected with a collector electrode of the first npn transistor, a base electrode of the fourth npn transistor is connected with a collector electrode of the second npn transistor, and a collector electrode of the third npn transistor and a collector electrode of the fourth npn transistor are connected with the power supply terminal;
A fifth npn transistor having an emitter connected to a collector of the fifth npn transistor, an emitter connected to a collector of the sixth npn transistor, a collector connected to a base of the fifth npn transistor, and a collector connected to a base of the sixth npn transistor;
An eighth npn transistor and a ninth npn transistor, an emitter of the fifth npn transistor being connected to a collector of the eighth npn transistor, an emitter of the sixth npn transistor being connected to a collector of the ninth npn transistor, a base of the eighth npn transistor and a base of the ninth npn transistor being connected to the bias voltage terminal;
A fifth resistor and a sixth resistor, an emitter of the eighth npn transistor being connected to one end of the fifth resistor, the ninth npn transistor being connected to one end of the sixth resistor, the other end of the fifth resistor and the other end of the sixth resistor being connected to the ground terminal;
The first output end and the second output end are used for outputting the interpolation signals, the first output end is connected with the emitter of the third npn transistor and the collector of the fifth npn transistor, and the second output end is connected with the emitter of the fourth npn transistor and the collector of the sixth npn transistor.
6. The active interpolation circuit configuration applied to a high-speed folded interpolation ADC according to claim 5, wherein the four-input differential operational amplifier comprises:
the second common-emitter differential operational amplifier module is used for receiving the differential signals;
the emitter follower module is used for outputting the interpolation signal;
the power end is connected with one end of the second common-emitter differential operational amplifier module, and one end of the emitter follower module is connected with the power end;
The other end of the second common-emitter differential operational amplifier module is connected with the grounding end, and the other end of the emitter follower module is connected with the grounding end.
7. The active interpolation circuit architecture for a high-speed folded interpolation ADC of claim 6, wherein the second common-stage differential op-amp module comprises:
The first input end, the second input end, the third input end and the fourth input end are used for receiving the differential signals;
A first npn transistor and a second npn transistor, the first input terminal being connected to a base of the first npn transistor and the second input terminal being connected to a base of the second npn transistor;
a seventh npn transistor, an emitter of the first npn transistor and an emitter of the second npn transistor being connected to a collector of the seventh npn transistor;
The base electrode of the seventh npn transistor is connected with the bias voltage end;
An emitter of the seventh npn transistor is connected to one end of the fourth resistor, and the other end of the fourth resistor is connected to the ground terminal;
a second resistor and a third resistor, the collector of the first npn transistor being connected to one end of the second resistor, the collector of the second npn transistor being connected to one end of the third resistor;
the other end of the second resistor and the other end of the third resistor are connected with one end of the first resistor, and the other end of the first resistor is connected with the power supply end;
a tenth npn transistor and an eleventh npn transistor, wherein the third input terminal is connected to the base of the tenth npn transistor, the fourth input terminal is connected to the base of the eleventh npn transistor, the collector of the tenth npn transistor is connected to the collector of the first npn transistor and one end of the second resistor, the collector of the eleventh npn transistor is connected to the collector of the second npn transistor and one end of the third resistor, and the emitter of the tenth npn transistor and the emitter of the eleventh npn transistor are connected to the collector of the seventh npn transistor.
8. The active interpolation circuit architecture for a high-speed folded interpolation ADC of claim 7, wherein:
the representation of the tail currents of the first npn transistor and the second npn transistor includes:
The representation of the collector current flowing through the first npn transistor includes:
the representation of the collector current flowing through the second npn transistor includes:
wherein I TALL is the tail current, V bias is the bias voltage, As the voltage of the seventh npn transistor, R 4 is the voltage of the fourth resistor, α F1 is the characteristic parameter of the first npn transistor, α F2 is the characteristic parameter of the second npn transistor, α F1＝αF2,VT is the temperature parameter, vinpl is the input voltage of the first input terminal, vinn1 is the input voltage of the second input terminal.
9. The active interpolation circuit architecture for a high-speed folded interpolation ADC of claim 8, wherein:
the parameters of the second resistor are the same as the parameters of the third resistor;
The parameters of the third npn transistor are the same as the parameters of the fourth npn transistor;
the parameters of the fifth npn transistor are the same as those of the sixth npn transistor;
The parameters of the eighth npn transistor are the same as those of the ninth npn transistor;
The parameters of the fifth resistor are the same as those of the sixth resistor.
10. The active interpolation circuit architecture for a high-speed folded interpolation ADC of claim 9, wherein:
the parameters of the first npn transistor, the second npn transistor, the tenth npn transistor and the eleventh npn transistor are the same.
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