CN118136067A - Word line decoding circuit, memory chip, and word line decoding control method - Google Patents
Word line decoding circuit, memory chip, and word line decoding control method Download PDFInfo
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Abstract
The embodiment of the invention provides a word line decoding circuit, a memory chip and a word line decoding control method, which relate to the technical field of semiconductors. Under the condition that the word line overturning speed is unchanged, the size of the transistor in the word line driving module can be reduced by increasing the driving force of the transistor in the word line driving module, so that the area of a word line decoding circuit is reduced, and the cost for manufacturing the memory chip is reduced.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a word line decoding circuit, a memory chip and a word line decoding control method.
Background
With the advancement of technology, the capacity demand of memories is increasing, and the speed demand of data processing is also increasing. In a large-capacity memory chip design, the area of the memory chip is mainly determined by the area of the memory cell array and the word line decoding circuit.
In the prior art, the area of a word line decoding circuit in a mass storage chip is relatively large, resulting in high manufacturing cost.
Disclosure of Invention
The invention aims to provide a word line decoding circuit, a memory chip and a word line decoding control method, which are used for solving the problem of high manufacturing cost caused by large area of the word line decoding circuit in a large-capacity memory chip.
In a first aspect, the present invention provides a word line decoding circuit, the word line decoding circuit comprising a pre-decoding module, a global decoding module, a selection decoding module, a word line driving module, a power module, and a control module; the pre-decoding module is electrically connected with the global decoding module and the selective decoding module, the global decoding module and the selective decoding module are electrically connected with the word line driving module, and the word line driving module is electrically connected with the memory cell array; the power module is electrically connected with the pre-decoding module, the global decoding module, the selective decoding module and the control module;
The power supply module is used for providing operation voltages for the global decoding module and the selective decoding module respectively;
The control module is used for controlling the power supply module to adjust the operation voltage input to the selection decoding module when the memory cell array is subjected to the reading operation, so as to adjust the voltage of the output signal of the selection decoding module, and further increase the driving force of the transistor in the word line driving module.
In a second aspect, the present invention provides a memory chip comprising a memory cell array and a word line decoding circuit according to any one of the preceding embodiments.
In a third aspect, the present invention provides a word line decoding control method applied to the memory chip described in the foregoing embodiment, the method including:
when the control module receives a read operation instruction aiming at the storage unit array, a voltage regulating signal is output to the power supply module;
The power supply module adjusts the operation voltage input to the selection decoding module according to the voltage adjusting signal, and then adjusts the voltage of the output signal of the selection decoding module so as to increase the driving force of the transistor in the word line driving module.
The word line decoding circuit comprises a pre-decoding module, a global decoding module, a selection decoding module, a word line driving module, a power module and a control module, wherein the pre-decoding module is electrically connected with the global decoding module and the selection decoding module, the global decoding module and the selection decoding module are electrically connected with the word line driving module, the word line driving module is electrically connected with the memory cell array, the power module is electrically connected with the pre-decoding module, the global decoding module, the selection decoding module and the control module, the power module is used for providing operation voltages for the global decoding module and the selection decoding module respectively, and the control module is used for controlling the power module to adjust the operation voltage input to the selection decoding module when the memory cell array is subjected to read operation, so as to adjust the voltage of output signals of the selection decoding module, and increase the driving force of transistors in the word line driving module. Under the condition that the word line overturning speed is unchanged, the size of the transistor in the word line driving module can be reduced by increasing the driving force of the transistor in the word line driving module, so that the area of the word line decoding circuit is reduced, and the cost for manufacturing the word line decoding circuit is reduced.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a word line decoding circuit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a word line decoding circuit according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a word line decoding circuit according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a truth table corresponding to a prior art word line decoding circuit;
FIG. 5 is a schematic diagram of a truth table corresponding to a word line decoding circuit according to an embodiment of the present invention;
FIG. 6 is another schematic diagram of a truth table corresponding to a word line decoding circuit according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of a truth table corresponding to a word line decoding circuit according to an embodiment of the present invention;
fig. 8 is a schematic flow chart of a word line decoding control method according to an embodiment of the invention.
Icon: 100-word line decoding circuitry; 110-a pre-decoding module; 120-global decoding module; 121-a global decoding unit; 1211-a first logic circuit; 1212-a first level shifter circuit; 130-select a decoding module; 131-selecting a decoding unit; 1311-a second logic circuit; 1312-a second level shifter circuit; 140-word line driving module; 141-word line driving units; 150-a power module; 160-a control module; 200-an array of memory cells; 210-a memory cell; MN 1-a first transistor; MN 2-second transistor; MP 1-third transistor; MP 0-fourth transistor; MN 0-fifth transistor.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. The components of the embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the invention, as presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It is noted that relational terms such as "first" and "second", and the like, are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises an element.
Referring to fig. 1, fig. 1 is a schematic diagram of a word line decoding circuit according to an embodiment of the invention. The word line decoding circuit 100 includes a pre-decoding module 110, a global decoding module 120, a selection decoding module 130, a word line driving module 140, a power supply module 150, and a control module 160; the pre-decoding module 110 is electrically connected to the global decoding module 120 and the selective decoding module 130, the global decoding module 120 and the selective decoding module 130 are electrically connected to the word line driving module 140, the word line driving module 140 is electrically connected to the memory cell array 200, and the power module 150 is electrically connected to the pre-decoding module 110, the global decoding module 120, the selective decoding module 130 and the control module 160.
The power module 150 is configured to provide operating voltages to the global decoding module 120 and the selective decoding module 130, respectively.
The power module 150 may also be used to provide a base operating voltage for the pre-decode module 110, the global decode module 120, the select decode module 130, and the control module 160.
The control module 160 is used for controlling the power module 150 to adjust the operating voltage input to the selection decoding module 130 when the memory cell array 200 is read, and further adjust the voltage of the output signal of the selection decoding module 130 to increase the driving force of the transistors in the word line driving module 140.
In the process of turning over the word line, the driving force of the transistor in the word line decoding circuit 100 affects the turning over speed of the word line, which affects the data reading performance. In the large-capacity memory chip design, the area of the memory chip is mainly determined by the areas of the memory cell array 200 and the word line decoding circuit 100, and the number of transistors of the word line driving module 140 in the word line decoding circuit 100 is large, so that the size of the transistors in the word line driving module 140 can be reduced effectively to reduce the area of the word line decoding circuit 100, thereby reducing the area of the memory chip.
In the word line decoding circuit provided by the embodiment of the invention, the control module is used for controlling the power supply module to adjust the operation voltage input to the selection decoding module when the memory cell array is subjected to the reading operation, so as to adjust the voltage of the output signal of the selection decoding module, thereby increasing the driving force of the transistor in the word line driving module. Under the condition that the word line overturning speed is unchanged, the size of the transistor in the word line driving module can be reduced by increasing the driving force of the transistor in the word line driving module, so that the area of a word line decoding circuit is reduced, and the cost for manufacturing the memory chip is reduced.
In some embodiments, referring to fig. 2 (the pre-decoding module 110 is not shown), the word line driving module 140 includes a plurality of word line driving units 141, the memory cell array 200 includes a plurality of memory cells 210, and the word line driving units 141 are electrically connected to the memory cells 210 in a one-to-one correspondence.
The pre-decoding module 110 is configured to pre-decode the received signal to be decoded to generate a pre-decoded signal, and transmit the pre-decoded signal to the global decoding module 120 and the selective decoding module 130.
The global decoding module 120 is configured to decode the pre-decoded signal to generate a global word line signal, and transmit the global word line signal to the word line driving module 140.
The selection decoding module 130 is used for decoding the pre-decoding signal to generate a word line selection signal, and transmitting the word line selection signal to the word line driving module 140.
The word line driving module 140 is configured to select the memory cell 210 corresponding to one of the word line driving units 141 according to the global word line signal and the word line selection signal.
In some embodiments, the global decoding module 120 includes a plurality of global decoding units, and the selection decoding module 130 includes a plurality of selection decoding units, and each word line driving unit is electrically connected to one global decoding unit and one selection decoding unit, respectively.
The number m of global decoding units and the number n of selective decoding units may be designed according to the number (m×n) of word lines. Referring to fig. 3, the global decoding unit 121 includes a first logic circuit 1211, a first level shifter 1212, a fourth transistor MP0, and a fifth transistor MN0. The selection decoding unit 131 includes a second logic circuit 1311 and a second level shift circuit 1312. The first logic circuit 1211 and the second logic circuit 1311 are designed by logic gates according to different decoding logics.
In fig. 3, VCC, VPP, VPP, VNN, and VNN2 are all provided by power module 150; wherein VCC is the basic operation voltage, the second operation high voltage input to the global decoding unit 121 by the power module 150 is VPP, and the second operation low voltage input to the global decoding unit 121 is VNN; the power module 150 inputs the first operation high voltage VPP2 to the selection decoding unit 131 and the first operation low voltage VNN2 to the selection decoding unit 131; the voltage input to the source of the second transistor MN2 by the power module 150 is VNN.
The fourth transistor MP0 may be a P-channel MOS transistor, and the fifth transistor MN0 may be an N-channel MOS transistor. The different global decoding units 121 decode the pre-decoded signal using different first logic circuits 1211, and the different selective decoding units 131 decode the pre-decoded signal using different second logic circuits 1311. The global word line signal includes a signal GWL obtained by decoding the pre-decode signal by each global decoding unit 121, and the word line selection signal includes signals (i.e., ss and ssb) obtained by decoding the pre-decode signal by each selection decoding unit.
The first level shift circuit 1212 is configured to level shift a signal obtained by decoding the pre-decoded signal by the first logic circuit 1211.
The second level shift circuit 1312 is configured to level shift a signal obtained by decoding the pre-decoded signal by the second logic circuit 1311.
With continued reference to fig. 3, each word line driving unit 141 includes a first transistor MN1, a second transistor MN2, and a third transistor MP1; each selection decoding unit 131 includes a first output terminal and a second output terminal.
Wherein, the first output terminal of the selection decoding unit 131 outputs the first signal ss, and the second output terminal of the selection decoding unit 131 outputs the second signal ssb. That is, each of the selection decoding units 131 decodes the pre-decoded signal to obtain a signal including a first signal ss and a second signal ssb, and the first signal ss and the second signal ssb are two opposite signals. The first transistor MN1 and the second transistor MN2 may be N-channel MOS transistors, and the third transistor MP1 may be a P-channel MOS transistor.
The gate of the first transistor MN1 is electrically connected to the first output terminal of the corresponding selection decoding unit 131, the source of the first transistor MN1 is electrically connected to the corresponding memory unit 210, and the drain of the first transistor MN1 is electrically connected to the output terminal of the corresponding global decoding unit 121.
The gate of the second transistor MN2 is electrically connected to the second output terminal of the corresponding selection decoding unit 131, the source of the second transistor MN2 is electrically connected to the power module 150, and the drain of the second transistor MN2 is electrically connected to the corresponding memory unit 210.
The gate of the third transistor MP1 is electrically connected to the second output terminal of the corresponding selection decoding unit 131, the source of the third transistor MP1 is electrically connected to the output terminal of the corresponding global decoding unit 121, and the drain of the third transistor MP1 is electrically connected to the corresponding memory unit 210.
The operation voltages input to the global decoding module 120 by the power module 150 include a second operation high voltage VPP and a second operation low voltage VNN, wherein the second operation high voltage VPP is a set high voltage and the second operation low voltage VNN is a set low voltage.
The operation voltages input to the selection decoding module 130 by the power supply module 150 include a first operation high voltage VPP2 and a first operation low voltage VNN2. When the first operation high voltage is higher than the set high voltage, the first operation low voltage is lower than or equal to the set low voltage; when the first operation high voltage is equal to the set high voltage, the first operation low voltage is lower than the set low voltage.
In a read operation of the memory cell array 200, the selected memory cell 210 needs to be applied with a read high voltage, and the unselected word line is applied with 0V. Wherein, the read high pressure is generally 5-6V.
In the case of writing to the memory cell array 200, the selected memory cell 210 needs to be written with a high voltage, and the unselected memory cell 210 needs to be written with a negative voltage. The writing high voltage can be 9-10V, and the writing negative voltage can be-1 to-2V.
When the memory cell array 200 is erased, the selected memory cells 210 need to have an erase negative voltage, and the unselected memory cells 210 need to have an erase limit voltage, wherein the erase negative voltage may be-9V to-10V, and the erase limit voltage may be 2V.
Take a global decoding unit 121, a selection decoding unit 131 and a word line driving unit 141 as an example.
Referring to fig. 3 and 4, fig. 4 is a truth table corresponding to the word line decoding circuit 100 in the prior art. In the prior art, the control module 160 controls the power module 150 to adjust the first and second operation high voltages VPP2 and VPP inputted to the selection decoding unit 131 to be set to be high voltages, and the first and second operation low voltages VNN2 and VNN are set to be low voltages.
For the read/write operation of the memory cell array 200, when the signal GWL output by the global decoding unit 121 connected to the word line driving unit 141 is a read high voltage (or a write high voltage), the first signal ss output by the selection decoding unit 131 connected to the word line driving unit 141 is a read high voltage (or a write high voltage), and the second signal ssb is 0V (or a write negative voltage), the signal GWL output by the global decoding unit 121 is applied to the memory cell 210 corresponding to the word line driving unit 141 through the pull-up third transistor MP1, and the memory cell 210 corresponding to the word line driving unit 141 is selected. When the first signal ss outputted from the selection decoding unit 131 connected to the word line driving unit 141 is 0V (or writing negative pressure) and the second signal ssb is reading high voltage (or writing high voltage), the second transistor MN2 is turned on, and VNN (0V or writing negative pressure) is applied to the corresponding unselected memory cell 210. When the signal GWL output from the global decoding unit 121 connected to the word line driving unit 141 is 0V (or a write negative voltage), the first signal ss output from the selection decoding unit 131 connected to the word line driving unit 141 is a read high voltage (or a write high voltage), and the second signal ssb is 0V (or a write negative voltage), the signal GWL (0V or write negative voltage) output from the global decoding unit 121 is applied to the corresponding unselected memory cell 210 through the first transistor MN 1.
When the global decoding unit 121 connected to the word line driving unit 141 outputs a signal GWL of an erase restriction voltage and the first signal ss and the second signal ssb outputted from the selection decoding unit 131 connected to the word line driving unit 141 are the erase negative voltage and the erase restriction voltage, respectively, the word line corresponding to the word line driving unit 141 is selected, and a VNN (erase negative voltage) signal is applied to the selected memory cell 210 through the second transistor MN 2; when the first signal ss output from the selection decoding unit 131 connected to the word line driving unit 141 is an erase limit voltage and the second signal ssb is an erase negative voltage, the signal GWL (erase limit voltage) output from the global decoding unit 121 connected to the word line driving unit 141 is applied to the unselected memory cell 210 through the third transistor MP 1.
It is understood that the driving capability of the first transistor MN1, the second transistor MN2, the third transistor MP1, the fourth transistor MP0, and the fifth transistor MN0 affects the flip speed of the word line during the flip process of the word line. Particularly in read operations, the flip speed of the word line has a critical effect on the performance of data reading. Since the number of the global decoding units 121 is generally small, the fourth transistor MP0 and the fifth transistor MN0 may have a large size and have little influence on the area of the word line decoding circuit 100, while the sizes of the first transistor MN1, the second transistor MN2 and the third transistor MP1 of the word line driving unit 141 have a significant influence on the area of the entire word line decoding circuit 100, and reducing the sizes of the first transistor MN1, the second transistor MN2 and the third transistor MP1 of the word line driving unit 141 may effectively reduce the area of the entire word line decoding circuit 100, thereby reducing the area of the entire memory chip.
Based on this, in the present embodiment, referring to fig. 3 and 5, when performing a read operation on the memory cell array 200, the control module 160 controls the power module 150 to adjust the first operating high voltage VPP2 input to the selection decoding unit 131 to a second read high voltage, the second read high voltage is higher than the set high voltage (the read high voltage), the first operating low voltage VNN2 is equal to the set low voltage (0V), and further adjusts the voltages of the first signal ss and the second signal ssb of the selection decoding module 130 to increase the driving force of the transistors in the word line driving module 140.
Specifically, at the time of performing a read operation on the memory cell array 200, the high voltage applied to the gate of the first transistor MN1 or the second transistor MN2 is a first operation high voltage (second read high voltage), wherein the first operation high voltage (second read high voltage) > set high voltage (read high voltage); since the voltage of the gate electrode of the first transistor MN1 or the second transistor MN2 is the first operation high voltage (the second read high voltage) and is higher than the set high voltage (the read high voltage), the first transistor MN1 or the second transistor MN2 has a stronger driving capability and can transmit the set high voltage, and thus the size of the first transistor MN1 or the second transistor MN2 can be smaller than the size of the first transistor MN1 or the second transistor MN2 in the prior art under the condition that the same inversion speed is required, and the size of the third transistor MP1 can be reduced, thereby reducing the area of the word line decoding circuit 100.
In this embodiment, referring to fig. 3 and 6, during the read operation of the memory cell array 200, the control module 160 controls the power module 150 to adjust the first operating high voltage VPP2 input to the selection decoding unit 131 to be equal to the set high voltage (read high voltage), the first operating low voltage VNN2 to be the read negative voltage (lower than the set low voltage), the first operating low voltage VNN2 to be lower than the set low voltage (0V), and further adjust the voltages of the first signal ss and the second signal ssb of the selection decoding module 130 to increase the driving force of the transistors in the word line driving module 140.
The negative reading pressure may be-1V, -2V, etc., and is not limited herein.
Specifically, when the memory cell array 200 is subjected to a read operation, the power module 150 adjusts the first high voltage VPP2 input to the selection decoding unit 131 to be a read high voltage, and the first low voltage VNN2 to be a read negative voltage, so that the second signal ssb is a read negative voltage when the first signal ss output by the selection decoding unit 131 is a read high voltage, or the second signal ssb is a read high voltage when the first signal ss output by the selection decoding unit 131 is a read negative voltage; the gate voltage of the third transistor MP1 is a read negative voltage, which is lower than the set low voltage, so that the driving capability of the third transistor MP1 is enhanced and the 0V voltage can be transmitted, and the sizes of the third transistor MP1 and the first transistor MN1 can be reduced under the same inversion speed requirement, thereby reducing the area of the word line decoding circuit 100.
In this embodiment, referring to fig. 3 and fig. 7, when the memory cell array 200 is read, the control module 160 controls the power module 150 to adjust the first operation high voltage VPP2 input to the selection decoding unit 131 to be a second read high voltage, the second read high voltage is higher than the set high voltage (read high voltage), the first operation low voltage VNN2 is a read negative voltage, and the read negative voltage is lower than the set low voltage (0V), so that the second signal ssb is a read negative voltage when the first signal ss output by the selection decoding unit 131 is a second read high voltage, or the second signal ssb is a second read high voltage when the first signal ss output by the selection decoding unit 131 is a read negative voltage, the gate voltage when the first transistor MN1 and the second transistor MN2 are turned on is a second read high voltage, and the gate voltage when the third transistor MP1 is turned on is a read negative voltage, thereby increasing the driving force of the first transistor MN1, the second transistor MN2, and the third transistor MP1, and reducing the driving force of the first transistor MN1 and the second transistor MP 2 by a size of the second transistor MP1 and a size of the second transistor MP 2, which is smaller than the first transistor MN1 and the third transistor MN1 in the prior art.
The embodiment of the invention also provides a memory chip which comprises a memory cell array and the word line decoding circuit.
In some embodiments, the memory chip may be disposed in a memory, among other things. The memory may include a solid state disk, a usb disk, and the like, which are not limited herein.
In this embodiment, by increasing the driving force of the transistors in the word line driving module, the area of the word line decoding circuit is reduced, thereby reducing the area of the memory chip and reducing the cost of manufacturing the memory chip.
Referring to fig. 8, fig. 8 is a flow chart illustrating a word line decoding control method according to an embodiment of the invention. The word line decoding control method can be applied to a memory chip, and a specific flow of this embodiment will be described below by taking the memory chip as an example. As described in detail below with respect to the flowchart shown in fig. 8, the word line decoding control may specifically include the following steps:
Step S110: when the control module receives a read operation instruction for the memory cell array, a voltage regulating signal is output to the power supply module.
Step S120: the power module adjusts the operation voltage input to the selection decoding module according to the voltage adjusting signal, and then adjusts the voltage of the output signal of the selection decoding module so as to increase the driving force of the transistor in the word line driving module.
As one embodiment, the power module adjusts the first operation high voltage input to the selection decoding module to be higher than the set high voltage and the first operation low voltage input to the selection decoding module to be lower than or equal to the set low voltage according to the voltage adjustment signal.
As another embodiment, the power module adjusts the first operation high voltage input to the selection decoding module to be equal to the set high voltage and the first operation low voltage input to the selection decoding module to be lower than the set low voltage according to the voltage adjustment signal.
According to the word line decoding control method provided by the embodiment of the invention, under the condition that the word line overturning speed is unchanged, the size of the transistor in the word line driving module can be reduced by increasing the driving force of the transistor in the word line driving module, so that the area of a word line decoding circuit is reduced, and the cost for manufacturing a memory chip is reduced.
In the several embodiments provided in the present invention, it should be understood that the disclosed apparatus and method may be implemented in other manners. The apparatus embodiments described above are merely illustrative, for example, of the flowcharts and block diagrams in the figures that illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored on a computer readable storage medium. Based on this understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) to perform all or part of the steps of the method of the embodiments of the present invention. And the aforementioned storage medium includes: a usb disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
The above is only a preferred embodiment of the present invention, and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. The word line decoding circuit is characterized by comprising a pre-decoding module, a global decoding module, a selection decoding module, a word line driving module, a power supply module and a control module; the pre-decoding module is electrically connected with the global decoding module and the selective decoding module, the global decoding module and the selective decoding module are electrically connected with the word line driving module, and the word line driving module is electrically connected with the memory cell array; the power module is electrically connected with the pre-decoding module, the global decoding module, the selective decoding module and the control module;
The power supply module is used for providing operation voltages for the global decoding module and the selective decoding module respectively;
The control module is used for controlling the power supply module to adjust the operation voltage input to the selection decoding module when the memory cell array is subjected to the reading operation, so as to adjust the voltage of the output signal of the selection decoding module, and further increase the driving force of the transistor in the word line driving module.
2. The circuit of claim 1, wherein the operating voltage input to the select decode module by the power supply module comprises a first operating high voltage and a first operating low voltage;
when the first operation high voltage is higher than a set high voltage, the first operation low voltage is lower than or equal to the set low voltage;
when the first operation high voltage is equal to the set high voltage, the first operation low voltage is lower than the set low voltage.
3. The circuit of claim 2, wherein the operating voltage input to the global decoding module by the power module comprises a second operating high voltage and a second operating low voltage, the second operating high voltage being the set high voltage and the second operating low voltage being the set low voltage.
4. The circuit of claim 1, wherein the word line driving module comprises a plurality of word line driving units, the memory cell array comprises a plurality of memory cells, and the word line driving units are electrically connected to the memory cells in a one-to-one correspondence.
5. The circuit of claim 4, wherein the pre-decoding module is configured to pre-decode a received signal to be decoded to generate a pre-decoded signal, and transmit the pre-decoded signal to the global decoding module and the selective decoding module;
the global decoding module is used for decoding the pre-decoding signal to generate a global word line signal and transmitting the global word line signal to the word line driving module;
the selection decoding module is used for decoding the pre-decoding signal to generate a word line selection signal and transmitting the word line selection signal to the word line driving module;
the word line driving module is used for selecting a storage unit corresponding to one word line driving unit according to the global word line signal and the word line selection signal.
6. The circuit of claim 5, wherein the global decoding module comprises a plurality of global decoding units, the select decoding module comprises a plurality of select decoding units, each of the word line driving units is electrically connected to one of the global decoding units and one of the select decoding units, respectively; wherein different global decoding units decode the pre-decoded signal by adopting different first logic circuits, and different selective decoding units decode the pre-decoded signal by adopting different second logic circuits; the global word line signals include signals obtained by decoding the pre-decoding signals by the global decoding units, and the word line selection signals include signals obtained by decoding the pre-decoding signals by the selection decoding units.
7. The circuit of claim 6, wherein each of the word line driving units includes a first transistor, a second transistor, and a third transistor; each of the selective decoding units comprises a first output end and a second output end;
The grid electrode of the first transistor is electrically connected with the first output end of the corresponding selective decoding unit, the source electrode of the first transistor is electrically connected with the corresponding storage unit, and the drain electrode of the first transistor is electrically connected with the output end of the corresponding global decoding unit;
The grid electrode of the second transistor is electrically connected with the second output end of the corresponding selective decoding unit, the source electrode of the second transistor is electrically connected with the power supply module, and the drain electrode of the second transistor is electrically connected with the corresponding storage unit;
The grid electrode of the third transistor is electrically connected with the second output end of the corresponding selective decoding unit, the source electrode of the third transistor is electrically connected with the output end of the corresponding global decoding unit, and the drain electrode of the third transistor is electrically connected with the corresponding storage unit.
8. A memory chip comprising an array of memory cells and the wordline decoding circuit of any of claims 1-7.
9. A word line decoding control method applied to the memory chip of claim 8, the method comprising:
when the control module receives a read operation instruction aiming at the storage unit array, a voltage regulating signal is output to the power supply module;
The power supply module adjusts the operation voltage input to the selection decoding module according to the voltage adjusting signal, and then adjusts the voltage of the output signal of the selection decoding module so as to increase the driving force of the transistor in the word line driving module.
10. The word line decoding control method of claim 9, wherein the operation voltage input to the selection decoding module by the power supply module includes a first operation high voltage and a first operation low voltage; the power module adjusts the operation voltage input to the selection decoding module according to the voltage adjustment signal, and the power module comprises:
The power supply module adjusts the first operation high voltage input to the selection decoding module to be higher than the set high voltage according to the voltage adjusting signal, and the first operation low voltage input to the selection decoding module is lower than or equal to the set low voltage; or the power supply module adjusts the first operation high voltage input to the selection decoding module to be equal to the set high voltage according to the voltage adjusting signal, and the first operation low voltage input to the selection decoding module is lower than the set low voltage.
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