CN118131863A

CN118131863A - Bus level switching mainboard and electronic equipment

Info

Publication number: CN118131863A
Application number: CN202410132908.1A
Authority: CN
Inventors: 李祝军; 袁斌; 刘舰
Original assignee: Shenzhen Weibu Information Co Ltd
Current assignee: Shenzhen Weibu Information Co Ltd
Priority date: 2024-01-31
Filing date: 2024-01-31
Publication date: 2024-06-04

Abstract

The embodiment of the invention discloses a bus level switching main board and electronic equipment, wherein the bus level switching main board comprises an interface module, a central processing unit, an interface module, a level conversion module and a switching compatible module, wherein the interface module is connected with peripheral equipment; the central processing unit outputs a first-level processing bus, and the level conversion module converts the first-level processing bus into a second-level conversion bus after detecting power-on; and the switching compatible module selects a processing bus of a first level and/or a conversion bus of a second level to be transmitted to the corresponding peripheral through the interface module according to a level path formed by the welded electronic components. Different levels can be provided for the peripheral equipment, and the problem that the level of the existing SMBUS cannot be switched is solved.

Description

Bus level switching mainboard and electronic equipment

Technical Field

The present invention relates to the field of electronic technologies, and in particular, to a motherboard with bus level switching and an electronic device.

Background

With the continuous development of technology, people have an increasing demand for functions of electronic devices. When a novel main board is designed, different peripheral equipment is needed by a customer, and temperature monitoring, information reading, power supply information management and the like are needed for the peripheral equipment; at this time, it is necessary to exchange and manage information for the peripheral devices using an SMBUS (system management bus) bus.

SMBUS is applied to low-rate communication in mobile PCs (personal computers) and desktop PC systems, which controls devices on a motherboard and gathers corresponding information through an inexpensive and powerful bus (consisting of two lines). The SMBUS provides a control bus for the tasks of system and power management, and the system using the SMBUS is used for sending and receiving messages between devices through the SMBUS instead of using a separate control line, so that the pin number of the devices can be saved. Using the SMBUS, the device may also provide its production information, tell the system its model, part number, etc., save its status for a hang event, report different types of errors, receive control parameters, and return its status, etc. The SMBUS device exists in the first 3 layers of the existing 7-layer OSI (Open System Interconnection) network model, namely the physical layer, the data link layer, and the network layer.

In order to meet market requirements, when designing a PCIE slot (an expansion slot based on a PCI local bus (PERIPHERAL COMPONENT INTERCONNECTION) element expansion interface) or an m.2 interface (a host interface scheme, which can be compatible with multiple communication protocols), an SMBUS is designed into the interface for temperature monitoring, vendor information reading, power information management, and the like. However, the levels that the SMBUS needs to use are different for different peripherals, which requires level switching by the SMBUS. At present, a 3.3V SMBUS is commonly used, and a scheme for switching the level of the SMBUS is not available, so that the required bus level cannot be provided for different peripheral devices.

Disclosure of Invention

Aiming at the technical problems, the embodiment of the invention provides a bus level switching mainboard and electronic equipment, which are used for solving the problem that the level of the existing SMBUS bus cannot be switched.

The embodiment of the invention provides a bus level switching main board, which comprises an interface module and a connecting peripheral, wherein a central processing unit, the interface module, a level conversion module and a switching compatible module are also arranged on the main board;

The central processing unit outputs a first-level processing bus, and the level conversion module converts the first-level processing bus into a second-level conversion bus after detecting power-on;

And the switching compatible module selects a processing bus of a first level and/or a conversion bus of a second level to be transmitted to the corresponding peripheral through the interface module according to a level path formed by the welded electronic components.

Optionally, in the bus level switching motherboard, the interface module includes a first interface and a second interface, where the first interface is an m.2 interface, and the second interface is a pcie x8 interface.

Optionally, in the bus level switching motherboard, the level switching module includes a first switching tube, a second switching tube, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor and a sixth resistor;

The grid electrode of the first switching tube is connected with the grid electrode of the second switching tube, one end of the first resistor and one end of the second resistor; the other end of the first resistor and the first power end, the other end of the second resistor is grounded, the drain electrode of the first switch tube is connected with the CT31 pin of the central processing unit and one end of the third resistor, the other end of the third resistor is connected with one end of the fourth resistor and the first power end, the source electrode of the first switch tube is connected with one end of the fifth resistor and the switching compatible module, the other end of the fifth resistor is connected with one end of the sixth resistor R6 and the second power end, the drain electrode of the second switch tube is connected with the other end of the fourth resistor and the CP31 pin of the central processing unit, and the source electrode of the second switch tube is connected with the other end of the sixth resistor and the switching compatible module.

Optionally, in the bus level switching motherboard, the switching compatible module includes a first welding bit, a second welding bit, a third welding bit, a fourth welding bit, a fifth welding bit, a sixth welding bit, a seventh welding bit, an eighth welding bit, a first compatible welding bit, and a second compatible welding bit;

One end of the first welding position is connected with one end of the third welding position and a source electrode of the first switching tube, one end of the second welding position is connected with one end of the fourth welding position and the source electrode of the second switching tube, the other end of the first welding position is connected with one end of the fifth welding position and an NC9 pin of the first interface, the other end of the second welding position is connected with one end of the sixth welding position and an NC8 pin of the first interface, the other end of the third welding position is connected with one end of the seventh welding position and an SMCLK pin of the second interface, the other end of the fourth welding position is connected with one end of the eighth welding position and an SMDAT pin of the second interface, the other end of the fifth welding position is connected with a first welding pad of the second compatible welding position and the other end of the eighth welding position, a common welding pad of the first compatible welding position is connected with a CT pin of the central processing unit, and a common welding pad of the second compatible welding position is connected with a CP31 pin of the central processing unit.

Optionally, in the bus level switching motherboard, the first compatible solder bit and the second compatible solder bit are composed of a first pad, a second pad and a common pad. Two ends of the element are welded on the first bonding pad and the common bonding pad to form a transmission path, and two ends of the element are welded on the second bonding pad and the common bonding pad to form another transmission path.

Optionally, in the bus level switching motherboard, when the first welding bit and the second welding bit respectively weld a 0 ohm resistor, a 1.8V conversion clock bus and a conversion data bus output by the level conversion module are connected to an m.2 interface;

and when the third welding bit and the fourth welding bit are respectively welded with a 0 ohm resistor, a 1.8V conversion clock bus and a conversion data bus which are output by the level conversion module are connected to the PCIEX8 interface.

Optionally, in the bus level switching motherboard, when the fifth welding bit to the eighth welding bit are respectively provided with a 0 ohm resistor, and the first bonding pad and the common bonding pad of the two compatible welding bits are respectively provided with a 0 ohm resistor, a 3.3V processing data bus and a processing clock bus output by the central processing unit are converted into SMBUS interface buses of corresponding interfaces through resistors, and are connected to the m.2 interface and the pcie x8 interface.

Optionally, in the bus level switching main board, a level output module is further arranged on the main board; the central processing unit controls channel switching in the level output module according to channel selection, and the SMBUS interface bus outputting the corresponding level is transmitted to the corresponding peripheral through the interface module.

Optionally, in the bus level switching motherboard, the level output module includes a switch chip, a fifteenth resistor, a sixteenth resistor, a seventeenth resistor, an eighteenth resistor, a nineteenth resistor, a twentieth resistor, a twenty first resistor, and a twenty second resistor;

The VDD pin of the switch chip is connected with a fifth power end, the SDA pin of the switch chip is connected with a second bonding pad of a second compatible bonding position, the SCL pin of the switch chip is connected with the second bonding pad of a first compatible bonding position, the VSS pin of the switch chip is grounded, the SC0 pin of the switch chip is connected with one end of a fifteenth resistor and the NC9 pin of a first interface, the SC1 pin of the switch chip is connected with one end of a nineteenth resistor and the NC9 pin of the first interface, the SC2 pin of the switch chip is connected with one end of a seventeenth resistor and the B5 pin of a second interface, the SC3 pin of the switch chip is connected with one end of a twenty-first resistor and the NC8 pin of the first interface, the SD1 pin of the switch chip is connected with one end of a twentieth resistor and the B6 pin of the second interface, and the SD3 pin of the switch chip is connected with one end of a twenty-second resistor and the B6 pin of the second interface; the other ends of the fifteenth resistor, the sixteenth resistor, the seventeenth resistor and the eighteenth resistor are all connected with a third power supply end; the other ends of the nineteenth resistor, the twentieth resistor, the twenty first resistor and the twenty second resistor are all connected with a fourth power supply terminal.

The second aspect of the embodiment of the invention provides an electronic device, which comprises a shell, wherein the shell is internally provided with a main board for bus level switching;

And the main board outputs a bus with a corresponding level to the connected equipment according to the type of the peripheral equipment.

In the technical scheme provided by the embodiment of the invention, the main board for bus level switching comprises an interface module, a central processing unit, an interface module, a level conversion module and a switching compatible module, wherein the interface module is connected with peripheral equipment; the central processing unit outputs a first-level processing bus, and the level conversion module converts the first-level processing bus into a second-level conversion bus after detecting power-on; and the switching compatible module selects a processing bus of a first level and/or a conversion bus of a second level to be transmitted to the corresponding peripheral through the interface module according to a level path formed by the welded electronic components. Different levels can be provided for the peripheral equipment, and the problem that the level of the existing SMBUS cannot be switched is solved.

Drawings

Fig. 1 is a block diagram of a bus level switching motherboard according to an embodiment of the present invention.

Fig. 2 is a circuit diagram of a cpu according to an embodiment of the invention.

Fig. 3 is a circuit diagram of a first interface according to an embodiment of the invention.

Fig. 4 is a circuit diagram of a second interface according to an embodiment of the invention.

Fig. 5 is a circuit diagram of a level shift module according to an embodiment of the invention.

Fig. 6 is a circuit diagram of a switching compatible module according to an embodiment of the invention.

Fig. 7 is a schematic circuit diagram of a switching compatible module according to an embodiment of the present invention.

Fig. 8 is a circuit diagram of a level output module according to an embodiment of the invention.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. Embodiments of the present invention are intended to be within the scope of the present invention as defined by the appended claims.

Referring to fig. 1 to 8, an electronic device provided in an embodiment of the present invention includes a housing, a display screen (for displaying a BIOS interface described below) is disposed on the housing, a motherboard for bus level switching is disposed in the housing, and the motherboard outputs a bus with a corresponding level to a connected device according to a type of a peripheral device.

The motherboard is provided with a central processing unit 10, an interface module 20, a level conversion module 30 and a switching compatibility module 40. The central processing unit 10 outputs a processing bus (including a processing data bus soc_ SMBSDA _1 and a processing clock bus soc_smbclk_1) of a first level (3.3V), and the interface module 20 is connected to different types of peripheral devices; the level conversion module 30 detects a conversion bus that converts a processing bus of a first level (3.3V) into a second level (1.8V) after power-up.

The switching compatible module 40 may perform bus level switching by selecting a manual welding switching mode or a software controlled switching mode. When the manual welding switching mode of the upper part is selected, corresponding level paths are formed by welding corresponding electronic elements in the switching compatible module 40 according to the level requirements of the peripheral equipment, and a processing bus of a first level (3.3V) and/or a conversion bus of a second level (1.8V) are selected to be connected with the corresponding peripheral equipment through an interface module.

When the software control switching mode is selected, the main board is also provided with a level output module 50, the central processing unit 10 controls the channel switching in the level output module according to the channel selection, and the SMBUS interface bus outputting the corresponding level is transmitted to the corresponding peripheral through the interface module.

The embodiment can well complete SMBUS level switching, and is switched to different level outputs aiming at different types of interfaces and peripherals, so that different switching level schemes are configured for different use requirements.

In this embodiment, two interfaces are disposed in the interface module 20, and the first interface J1 and the second interface J2 are different in peripheral type. When the processing bus of the first level (3.3V) and/or the conversion bus of the second level (1.8V) are connected with the corresponding peripheral through the interface module, 4 situations are included, namely, the first interface J1 and the second interface J2 output the first level (3.3V) to different peripheral; the first interface J1 outputs a first level (3.3V) to the connected peripheral, and the second interface J outputs a second level (1.8V) to the connected peripheral; the first interface J1 outputs a second level (1.8V) to the connected peripheral, and the second interface J outputs a first level (3.3V) to the connected peripheral; both the first interface J1 and the second interface J2 output the second level (1.8V) to different peripherals.

As shown in fig. 2, the CT31 pin (i.e., the gpp_c6/SML1CLK pin) and the CP31 pin (i.e., the gpp_c7/SML1DATA pin) of the central processing unit (i.e., the CPU, such as the processor N100) are connected to the level conversion module, and the CT31 pin and the CP31 pin are connected to the power supply terminal (providing the power supply voltage +v3p3a_pch) through a resistor, respectively. Based on the supply voltage +v3p3a_pch of the CPU side being 3.3V, the level of the SMBUS bus of the CPU side including the processing data bus soc_ SMBSDA _1 and the processing clock bus soc_smbclk_1 is also set to 3.3V.

The interface module is in the prior art, and the corresponding SMBUS is illustrated by taking the first interface J1 shown in fig. 3 as an m.2 interface and the second interface J2 shown in fig. 4 as a pcie x8 interface as an example.

The m.2 interface can be compatible with communication protocols including ：SATA(Serial Advanced Technology Attachment)、PCIe(peripheral component interconnect express)、USB、HSIC(High-Speed Inter-Chip)、UART(Universal Asynchronous Receiver/Transmitter)、SMBUS, etc. The SMBUS interface bus of the first interface J1 includes: the NC9 pin of the first interface J1 transmits the hard disk interface clock bus smb_clk_ssd1, and the NC8 pin transmits the hard disk interface DATA bus smb_data_ssd1.

The PCIEX8 interface is also called PCIEX8 slot, and is mainly used for display cards, RAID array cards, M.2SSD, M.2 wireless network cards or other M.2 interface devices, etc. The PCIEX8 slot has excellent compatibility and can be downward compatible with x1/x 4-level equipment; is a universal slot for PCI-E. PCIex8 slots are commonly used for display cards and are directly communicated with a central processing unit and are directly close to the CPU in physical position, so that data exchange between the display cards and the central processing unit can reduce delay and the performance of the system can be fully exerted. The SMBUS interface bus of the second interface J2 includes: the B5 pin of the second interface J2 transfers the slot clock bus pciex16_smb_clk, and the B6 pin transfers the slot DATA bus pciex16_smb_data.

It should be understood that only elements and signals related to the SMBUS in the interface are shown herein, and other elements and lines are connected in the prior art, which is not described in detail herein. In implementations, other interfaces may be used, and the pins and signal names of the SMBUS correspondingly change. Different interfaces connect different peripherals, and the bus levels required by the different peripherals are different, so that the switching needs to be performed automatically according to the bus level requirements of the connected peripherals.

In this embodiment, two modes may be used to switch bus levels, one is by selecting a manual welding switching mode for the upper member, and the other is by software control, so as to select different switching modes for different customer groups.

The first approach may be used when the customer is fixed with a device attached to an interface. The level shift module 30 includes a first switching tube Q1, a second switching tube Q2, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6 as shown in fig. 5; the grid electrode of the first switching tube Q1 is connected with the grid electrode of the second switching tube Q2, one end of the first resistor R1 and one end of the second resistor R2; the other end of the first resistor R1 and the first power end (providing a first voltage + V3.3S), the other end of the second resistor R2 is grounded, the drain electrode of the first switch tube Q1 is connected with the CT31 pin of the central processing unit and one end of the third resistor R3, the other end of the third resistor R3 is connected with one end of the fourth resistor R4 and the first power end, the source electrode of the first switch tube Q1 is connected with one end of the fifth resistor R5 and the switching compatible module, the other end of the fifth resistor R5 is connected with one end of the sixth resistor R6 and the second power end (providing a second voltage +1P8VS), the drain electrode of the second switch tube Q2 is connected with the other end of the fourth resistor R4 and the CP31 pin of the central processing unit, and the source electrode of the second switch tube Q2 is connected with the other end of the sixth resistor R6 and the switching compatible module.

The first voltage + V3.3S is 3.3V, and the second voltage +1p8vs is 1.8V. The first switching tube Q1 and the second switching tube Q2 are NMOS tubes with the model of 2SK3018, the switching frequency can reach 1Mhz, and the transmission speed of the SMBUS can be completely met. The partial pressures of R1 (resistance value is preferably 1KΩ) and R2 (resistance value is preferably 3.3KΩ) control Q1 and Q2 to be on. The processing clock bus soc_smbclk_1 is switched from 3.3V to 1.8V by the first switching transistor Q1, and the switching clock bus smbclk_1.8V is output. The processing DATA bus soc_ SMBSDA _1 is switched to a level of 1.8V by the second switching transistor Q2, and the output switching DATA bus smb_data_1.8V is outputted.

Referring to fig. 6, the switching compatible module 40 includes a first welding bit P1, a second welding bit P2, a third welding bit P3, a fourth welding bit P4, a fifth welding bit P5, a sixth welding bit P6, a seventh welding bit P7, an eighth welding bit P8, a first compatible welding bit P9, and a second compatible welding bit P10; one end of the first welding position P1 is connected with one end of the third welding position P3 and the source electrode of the first switching tube Q1, one end of the second welding position P2 is connected with one end of the fourth welding position P4 and the source electrode of the second switching tube Q2, the other end of the first welding position P1 is connected with one end of the fifth welding position P5 and the NC9 pin of the first interface J1, the other end of the second welding position P2 is connected with one end of the sixth welding position P6 and the NC8 pin of the first interface J1, the other end of the third welding position P3 is connected with one end of the seventh welding position P7 and the SMCLK pin of the second interface J2, the other end of the fourth welding position P4 is connected with one end of the eighth welding position P8 and SMDAT pins of the second interface J2, the other end of the fifth welding position P5 is connected with the first welding pad 1 of the first compatible welding position P9 and the other end of the seventh welding position P7, the other end of the sixth welding position P6 is connected with the first welding pad 1 of the second compatible welding position P10 and the other end of the eighth welding position P8, the public welding pad 3 of the first compatible welding position P9 is connected with the CT31 pin of the central processor, and the public welding pad 3 of the second compatible welding position P10 is connected with the CP31 pin of the central processor.

The bond site is comprised of two bond pads, one bond pad representing one end of the bond site and the other bond pad representing the other end of the bond site. The first compatible bonding bit P9 and the second compatible bonding bit P10 are each composed of a first pad 1, a second pad 2, and a common pad 3. Two ends of the element are welded on the first bonding pad and the common bonding pad to form a transmission path, and two ends of the element are welded on the second bonding pad and the common bonding pad to form another transmission path; thus, different circuit connection relations can be formed by the welding mode on the compatible welding position.

When the first welding bit and the second welding bit are respectively welded with a 0 ohm resistor, a 1.8V conversion clock bus and a conversion data bus which are output by the level conversion module are connected to an M.2 interface; and when the third welding bit and the fourth welding bit are respectively welded with a 0 ohm resistor, a 1.8V conversion clock bus and a conversion data bus which are output by the level conversion module are connected to the PCIEX8 interface. When the P1 to P4 are respectively provided with a 0 ohm resistor, the 1.8V conversion clock bus SMB_CLK_1.8V and the conversion DATA bus SMB_DATA_1.8V output by the level conversion module are respectively connected to the M.2 interface and the PCIEX8 interface through four resistors to detect the use equipment. When P5 to P8 are respectively provided with a 0 ohm resistor, and the first bonding pad of two compatible welding bits and the common bonding pad are provided with a 0 ohm resistor, a 3.3V processing data bus SOC_ SMBSDA _1 and a processing clock bus SOC_SMBCLK_1 output by the central processing unit are respectively connected to an M.2 interface and a PCIEX8 interface through six resistors to detect the using equipment.

When the main board is produced in a factory, BOM (bill of materials) is used for controlling the loading state of each welding position, so that the connection requirements of different clients can be met. For example, if the customer needs an m.2 interface to connect to a device having an SMBUS bus of 1.8V level and a pcie x8 interface to connect to a device having an SMBUS bus of 3.3V level, as shown in fig. 7, the first welding bit P1, the second welding bit P2, the seventh welding bit P7 to the tenth welding bit P10 may be selected for loading, and P2 to P6 may not be loaded. The switching compatible module further includes a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, and a fourteenth resistor R14; the ninth resistor R9 is welded on the first welding position P1, the tenth resistor R10 is welded on the second welding position P2, the eleventh resistor R11 is welded on the seventh welding position P7, and the twelfth resistor R12 is welded on the eighth welding position P8. The thirteenth resistor R13 is soldered to the first pad and the common pad of the first compatible solder bit P9, and the fourteenth resistor R14 is soldered to the first pad and the common pad of the second compatible solder bit P10.

The 1.8V conversion clock bus SMB_CLK_1.8V and the conversion DATA bus SMB_DATA_1.8V are respectively transmitted to the M.2 interface through R9 and R10, so that the M.2 interface can be externally connected with 1.8V level equipment. 3.3V of processing data buses SOC_ SMBSDA _1 are sequentially transmitted to the PCIEX8 interface through R7 and R11; 3.3V of processing clock bus SOC_SMBCLK_1 is transmitted to the PCIEX8 interface through R8 and R12 in sequence; the PCIEX8 interface can be externally connected with 3.3V level equipment.

The second software-controlled switching mode is used when the customer is not sure of what level of equipment to use at the interface. The software is a BIOS system in the central processing unit, and the BIOS system can access the bottom layer interface of the central processing unit and can control signal output and input. A level output module 50 is added on the basis of the first mode of selecting the manual welding switching of the upper part, and the upper part of the bonding pads of the first compatible welding position P9 and the second compatible welding position P10 is controlled by the BOM to select between two modes.

Referring to fig. 8, the level output module 50 includes a switch chip U1, a fifteenth resistor R15, a sixteenth resistor R16, a seventeenth resistor R17, an eighteenth resistor R18, a nineteenth resistor R19, a twentieth resistor R20, a twenty first resistor R21, and a twenty second resistor R22; the VDD pin of the switch chip U1 is connected to the fifth power supply terminal (providing the fifth voltage +v3p3a), the SDA pin of the switch chip U1 is connected to the second pad of the second compatible solder bit P10, the SCL pin of the switch chip U1 is connected to the second pad of the first compatible solder bit P9, the VSS pin of the switch chip U1 is grounded, the SC0 pin of the switch chip U1 is connected to one end of the fifteenth resistor R15 and the NC9 pin of the first interface J1, the SC1 pin of the switch chip U1 is connected to one end of the nineteenth resistor R19 and the NC9 pin of the first interface J1, the SC2 pin of the switch chip U1 is connected to one end of the seventeenth resistor R17 and the B5 pin of the second interface J2, the SC3 pin of the switch chip U1 is connected to one end of the twenty first resistor R21 and the B5 pin of the second interface J2, the SD0 pin of the switch chip U1 is connected to one end of the sixteenth resistor R16 and the NC8 pin of the first interface J1, the SD1 pin of the switch chip U1 is connected to one end of the twenty resistor R20 and the NC9 pin of the first interface J1, and the SD1 pin of the second interface J2 is connected to the first end of the twenty-first resistor R2J 2 and the second interface J2; the other ends of the fifteenth resistor R15, the sixteenth resistor R16, the seventeenth resistor R17 and the eighteenth resistor R18 are all connected with a third power supply end; the other ends of the nineteenth resistor R19, the twentieth resistor R20, the twenty first resistor R21 and the twenty second resistor R22 are all connected to the fourth power supply terminal.

In the second mode, two resistors are welded on two compatible welding positions to connect the level output module 50 with the central processing unit, and the motherboard further comprises a twenty-third resistor R23 and a twenty-fourth resistor R24; the twenty-third resistor R23 is soldered on the second pad and the common pad of the second compatible soldering bit P10, and the twenty-fourth resistor R24 is soldered on the second pad and the common pad of the first compatible soldering bit P9.

The switch chip U1 is preferably a one-way four-way bidirectional I2C chip with the model of NCA9546, wherein SD represents data channels, and 4 data channels are transmitted by SD0 pins to SD3 pins; SC represents clock channels, and 4 are transmitted by SC0 pin to SC3 pin; the SD0 pin and the SC0 pin are connected with a peripheral needing 3.3V power supply through a first interface J1 (M.2 interface), the SD1 pin and the SC1 pin are connected with a peripheral needing 1.8V power supply through the first interface J1 (M.2 interface), the SD2 pin and the SC2 pin are connected with a peripheral needing 3.3V power supply through a second interface J2 (PCIEX 8 interface), and the SD3 pin and the SC3 pin are connected with a peripheral needing 1.8V power supply through the second interface J2 (PCIEX 8 interface).

The switch chip U1 is internally integrated with an 8-bit control register, and the on-off (on or off) of each channel is controlled by the 4 least significant bits in the register. The SDA pin and the SCL pin of the U1 are connected with the central processing unit end of the main equipment, and the central processing unit writes data streams into registers in the U1 through a processing data bus SOC_ SMBSDA _1 and a processing clock bus SOC_SMBCLK_1, so that the on-off of each channel can be controlled.

And R15-R22 are pull-up resistors with the resistance value of preferably 4.7 Kohm at the output port of the switch chip U1, and can be connected with different pull-up levels to control the output SMBUS level. In fig. 8, the third voltage + V3.3AL is 3.3V, the fourth voltage +v1p8a is 1.8v, and the SC0 and SC1 channels are connected to the m.2 interface, but as seen from the pull-up level, the level of the SC0 channel is 3.3V and the level of the SC1 channel is 1.8V. The SC2 and SC3 channels are connected to the pcie x8 interface, and from the pull-up level, the level of the SC2 channel is 3.3V, and the level of the SC3 channel is 1.8V.

Suppose that when a customer wants to replace an m.2 interface device with an SMBUS bus of 3.3V with an m.2 interface device with an SMBUS bus of 1.8V. The BIOS engineer can modify BIOS bit, the options of independently opening or closing the four groups of channels SC0/SD0, SC1/SD1, SC2/SD2 and SC3/SD3 are displayed under the BIOS interface, the channels SC0 and SD0 are closed under the BIOS interface, the channels SC1 and SD1 are opened, corresponding DATA streams are generated after the hooks are checked, the DATA streams are written into a register in U1 through a processing DATA bus SOC_ SMBSDA _1 and a processing clock bus SOC_SMBCK1, namely the channels SC0 and SD0 are closed, the channels SC1 and SD1 are opened, and the levels of a hard disk interface clock bus SMB_CLK_SSD1 and a hard disk interface DATA bus SMB_DATA_SSD1 are changed to 1.8V. The PCIEX8 interface device in the same way can also be switched in this way.

Assume again that the customer's usage scenario requires access to an SSD of 3.3V power requirements and a graphics card of 1.8V power requirements. The BIOS engineer modifies BIOS bit, displays the options of independently opening or closing four groups of channels SC0/SD0, SC1/SD1, SC2/SD2 and SC3/SD3 under the BIOS interface, opens the channels SC0, SD0, SC3 and SD3, closes the channels SC1, SD1, SC2 and SD2, generates the data stream of XXXX1001 after the checking, and writes the data stream into the register in U1 through the processing data bus SOC_ SMBSDA _1 and the processing clock bus SOC_SMBCLK_1, thereby realizing the opening of the channels SC0, SD0, SC3 and SD3 and the closing of the channels SC1, SD1, SC2 and SD 2. The levels of the hard disk interface clock bus smb_clk_ssd1 and the hard disk interface DATA bus smb_data_ssd1 become 3.3V, and the levels of the slot clock bus pciex16_smb_clk and the slot DATA bus pciex16_smb_data become 1.8V.

Preferably, the level output module 50 further includes a first capacitor C1, a second capacitor C2, a twenty-fifth resistor R25, and a twenty-sixth resistor R26; the VDD pin of the switch chip U1 is grounded through a first capacitor C1; switch chip U1The pin is connected with one end of the second capacitor C2, one end of the twenty-fifth resistor R25 and one end of the twenty-sixth resistor R26, the other end of the twenty-fifth resistor R25 is grounded, and the other end of the twenty-sixth resistor R26 is connected with the third power supply end.

Wherein C1 is used to filter the supply on the VDD pin of U1. And C2, R25 and R26 form a reset circuit for automatically resetting U1 when power is supplied.

In the implementation, the pin A0, the pin A1, and the pin A2 of the switch chip U1 may be grounded through a resistor, or connected to the fifth power terminal through a resistor, respectively, for setting parameters of U1. The two switching modes are not only suitable for level switching of the SMBUS, but also suitable for level switching of other low-speed signals; the method is not limited to two interfaces, and the number of the switch chips can be increased for level switching of multiple interfaces.

In summary, according to the bus level switching motherboard and the electronic device provided by the invention, corresponding welding bits, compatible welding bits and level output modules are arranged on the motherboard aiming at different bus level switching modes; the bonding pad connection mode compatible with the welding position realizes the switching of the hardware circuit and the software control switching mode, the loading modes on different welding positions can realize the output of different bus levels, the level output module can also output different bus levels according to the data flow output by the central processing unit, the bus level switching mode is various, the different peripheral power supply requirements of customers can be met, and the switching mode is flexible and changeable and the operation is convenient.

The above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. The main board for bus level switching comprises an interface module and a connecting peripheral device, and is characterized in that a central processing unit, the interface module, a level conversion module and a switching compatible module are also arranged on the main board;

2. The bus-level-switching motherboard of claim 1, wherein the interface module comprises a first interface and a second interface, the first interface being an m.2 interface, the second interface being a pcie x8 interface.

3. The bus level-switched motherboard of claim 2, wherein the level-switching module comprises a first switching tube, a second switching tube, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, and a sixth resistor;

4. The bus level-switched motherboard of claim 3, wherein said switch compatibility module comprises a first solder bit, a second solder bit, a third solder bit, a fourth solder bit, a fifth solder bit, a sixth solder bit, a seventh solder bit, an eighth solder bit, a first compatible solder bit, and a second compatible solder bit;

5. The bus level switched motherboard of claim 4, wherein said first and second compatible solder bits consist of a first pad, a second pad, and a common pad. Two ends of the element are welded on the first bonding pad and the common bonding pad to form a transmission path, and two ends of the element are welded on the second bonding pad and the common bonding pad to form another transmission path.

6. The bus-level-switching motherboard of claim 4, wherein when the first welding bit and the second welding bit respectively weld a 0 ohm resistor, a 1.8V conversion clock bus and a conversion data bus output by the level conversion module are connected to the m.2 interface;

7. The bus-level-switching motherboard of claim 6, wherein when the fifth to eighth bonding bits are respectively connected to a 0 ohm resistor, and the first bonding pads and the common bonding pads of the two compatible bonding bits are respectively connected to a 0 ohm resistor, a 3.3V processing data bus and a processing clock bus output by the central processing unit are converted into SMBUS interface buses of corresponding interfaces through resistors, and are connected to an m.2 interface and a pcie x8 interface.

8. The bus level-switching motherboard of claim 4, further comprising a level output module; the central processing unit controls channel switching in the level output module according to channel selection, and the SMBUS interface bus outputting the corresponding level is transmitted to the corresponding peripheral through the interface module.

9. The bus level-switched motherboard of claim 8, wherein said level output module comprises a switch chip, a fifteenth resistor, a sixteenth resistor, a seventeenth resistor, an eighteenth resistor, a nineteenth resistor, a twentieth resistor, a twenty first resistor, and a twenty second resistor;

10. An electronic device comprising a housing, wherein a motherboard for bus level switching according to any one of claims 1 to 9 is provided in the housing;