CN118118260A

CN118118260A - Method, circuit, chip and electronic equipment for scrambling and descrambling address

Info

Publication number: CN118118260A
Application number: CN202410381326.7A
Authority: CN
Inventors: 方献更
Original assignee: Haiguang Information Technology Co Ltd
Current assignee: Haiguang Information Technology Co Ltd
Priority date: 2024-03-29
Filing date: 2024-03-29
Publication date: 2024-05-31

Abstract

The present disclosure provides methods, circuits, chips, and electronic devices for scrambling and descrambling addresses. The method for scrambling the address comprises the following steps: receiving a first request message from a processing unit, wherein the first request message contains a data address; performing address scrambling operation on the to-be-processed address packet to obtain a scrambling address, wherein the length of the scrambling address is greater than or equal to that of the data address, and the to-be-processed address is the data address or an intermediate address in the address scrambling operation period; and sending a second request message containing the scrambling address to the link layer, wherein the second request message corresponds to the first request message and is a transaction layer data packet. By the method, scrambling and descrambling of the address can be realized on the basis of CXL protocol, and safety of data transmission can be improved.

Description

Method, circuit, chip and electronic equipment for scrambling and descrambling address

Technical Field

Embodiments of the present disclosure relate to a method, a circuit, a chip, and an electronic device for scrambling and descrambling an address, and more particularly, to a method, a circuit, a chip, and an electronic device for scrambling an address.

Background

The Compute Express Link (CXL) protocol is a cache coherence interconnect protocol for processors, memory extensions, and accelerators. The CXL protocol is based on PCIe (PERIPHERAL COMPONENTINTERCONNECT EXPRESS, peripheral component interconnect protocol) and extends and optimizes memory consistency and high-speed data exchange capability by adding a new protocol layer.

Security of data transmission between a Host (Host) and a Device (Device) supporting the CXL protocol is important. In PCIe, encryption and address scrambling are generally used to ensure security of data transmission, but in CXL protocol, there is no corresponding provision and implementation of address scrambling, so how to implement address scrambling based on CXL protocol is a technical problem that needs to be solved at present.

Disclosure of Invention

In order to solve the technical problems, embodiments of the present disclosure provide a method for scrambling an address, a method for descrambling an address, a circuit, a chip, and an electronic device, which implement scrambling and descrambling of an address based on a CXL protocol, thereby improving security of data transmission.

In a first aspect, at least one embodiment of the present disclosure provides a method of scrambling an address, comprising: receiving a first request message from a processing unit, wherein the first request message contains a data address; performing address scrambling operation on the address to be processed packet to obtain a scrambling address, wherein the length of the scrambling address is greater than or equal to that of the data address, and the address to be processed is the data address or an intermediate address in the address scrambling operation period; and sending a second request message containing the scrambling address to the link layer, wherein the second request message corresponds to the first request message and is a transaction layer data packet.

For example, in a method of scrambling an address provided by an embodiment of the present disclosure, the address scrambling operation includes at least one of: doping the address to be processed according to the identification information in the first request message; according to the pseudo-random number characteristics, carrying out pseudo-random exchange operation on the address to be processed according to a preset length; according to the pseudo-random number characteristic, carrying out pseudo-random sequence adjustment operation on the grouping sequence of the addresses to be processed; wherein the address to be processed is a data address or an intermediate address during an address scrambling operation.

For example, in a method of scrambling an address provided in an embodiment of the present disclosure, before address scrambling is performed on a pending address packet, the method further includes: and determining whether the address scrambling is enabled or not and the operation included when the address scrambling is enabled according to the configuration information in the first request message.

For example, in a method of scrambling an address provided in an embodiment of the present disclosure, when an address scrambling operation includes at least two operations of a doping operation, a switching operation, and a sequential adjustment operation, the address scrambling operation is performed in order of sequentially performing the doping operation, the switching operation, and the sequential adjustment operation.

For example, in a method of scrambling an address provided in an embodiment of the present disclosure, before performing an address scrambling operation on a pending address packet, the method further includes: the data addresses are divided into N groups according to the positions of the data addresses in the first request message, wherein N is an integer greater than or equal to 2.

For example, in a method for scrambling an address provided in an embodiment of the present disclosure, when an address scrambling operation includes a doping operation, performing an address scrambling operation for an address packet to be processed to obtain a scrambled address, including: dividing the identification information into N groups according to the position of the identification information in the first request message; doping the N groups of identification information with the N groups of addresses to be processed respectively according to a preset arrangement mode to obtain N groups of virtual addresses, wherein the preset arrangement mode indicates the relative position relationship between the addresses to be processed and the identification information in each group of virtual addresses, and the relative position relationship corresponding to the N groups of virtual addresses is at least partially different.

For example, in a method for scrambling an address provided in an embodiment of the present disclosure, when an address scrambling operation includes a switching operation, performing the address scrambling operation for an address packet to be processed, includes: acquiring a first pseudo-random number; and respectively controlling the switching modes of the N switch arrays by using the first pseudo-random numbers so that the N switch arrays respectively exchange positions in the N groups of addresses to be processed according to preset lengths.

For example, in a method for scrambling an address provided in an embodiment of the present disclosure, when an address scrambling operation includes a sequence adjustment operation, performing the address scrambling operation for an address packet to be processed, includes: acquiring a second pseudo-random number; and taking the second pseudo-random number as a control sequence, and adjusting the grouping sequence of N groups of addresses to be processed according to a preset adjustment rule of the control sequence and the grouping sequence.

For example, in a method for scrambling addresses provided in an embodiment of the present disclosure, when the lengths of N groups of addresses to be processed are different, a default value is used to fill in N groups of virtual addresses, so that the lengths of N groups of virtual addresses are the same.

For example, in a method of scrambling an address provided by an embodiment of the present disclosure, obtaining a first pseudorandom number includes: generating a pseudo-random number in response to receiving the clock signal, wherein each clock cycle in the clock signal corresponds to one of the pseudo-random numbers, and not generating the pseudo-random number in response to ceasing to receive the clock signal; and acquiring a pseudo random number corresponding to the last clock period in the received clock signal as a first pseudo random number.

In a second aspect, at least one embodiment of the present disclosure provides a method of descrambling an address, comprising: receiving a third request message from the link layer, wherein the third request message is a read request message or a write request message, and the third request message is a transaction layer data packet and contains a scrambling address; when the address descrambling is started, address descrambling operation is carried out on the address packet to be scrambled so as to acquire a data address, wherein the length of the data address is smaller than or equal to that of the scrambling address, and the address to be scrambled is a scrambling address or an intermediate address in the address descrambling operation period; and sending a fourth request message containing the data address to the processing unit, wherein the fourth request message corresponds to the third request message.

For example, in a method of descrambling an address provided by an embodiment of the present disclosure, the address descrambling operation includes at least one of the following operations: carrying out a dedoping operation on the address to be processed according to the identification information in the third request message; according to the pseudo-random number characteristics, performing pseudo-random reverse exchange operation on the address to be processed according to a preset length; according to the pseudo-random number characteristic, carrying out pseudo-random reverse order adjustment operation on the grouping order of the addresses to be processed; wherein the address to be processed is a scrambling address or an intermediate address during an address descrambling operation.

For example, in a method for descrambling an address provided in an embodiment of the present disclosure, before performing an address descrambling operation for a pending address packet, the method further includes: and determining whether address descrambling is enabled or not and the operation included when the address descrambling is enabled according to the configuration information in the third request message.

For example, in a method of descrambling an address provided in an embodiment of the present disclosure, when an address descrambling operation includes at least two operations of a de-doping operation, a reverse switching operation, and a reverse order adjustment operation, the address descrambling operation is performed in an order in which the reverse order adjustment, the reverse switching operation, and the de-doping operation are sequentially performed.

For example, in a method for descrambling an address provided in an embodiment of the present disclosure, before performing an address descrambling operation for a pending address packet, the method further includes: the scrambling address is divided into N groups according to the position of the scrambling address in the third request message, wherein N is an integer greater than or equal to 2.

For example, in a method for descrambling an address provided in an embodiment of the present disclosure, when an address descrambling operation includes a dedoping operation, performing an address descrambling operation on an address packet to be processed, including removing N sets of identification information from N sets of addresses to be processed according to a preset arrangement manner, to obtain N sets of data addresses; the preset arrangement mode indicates the relative position relationship between the data addresses and the identification information in each group of addresses to be processed, and the relative position relationship corresponding to the N groups of addresses to be processed is at least partially different.

For example, in a method for descrambling an address provided in an embodiment of the present disclosure, when an address descrambling operation includes a reverse switching operation, performing an address descrambling operation for an address packet to be processed, including: acquiring a first pseudo-random number; and inverting the first pseudo-random number, and respectively controlling the switching modes of the N switch arrays by utilizing the inversion result of the first pseudo-random number, so that the N switch arrays respectively perform position reverse exchange in the N groups of addresses to be processed according to the preset length.

For example, in a method for descrambling an address provided in an embodiment of the present disclosure, when an address descrambling operation includes a reverse order adjustment operation, performing an address descrambling operation for an address packet to be processed, includes: acquiring a second pseudo-random number; and taking the second pseudo-random number as a control sequence, and reversely adjusting the grouping sequence of N groups of addresses to be processed according to a preset adjustment rule of the control sequence and the grouping sequence.

For example, in a method for descrambling addresses provided in an embodiment of the present disclosure, when a default value is included in N groups of addresses to be processed, the method further includes: and removing the default value from the N groups of addresses to be processed to obtain N groups of data addresses.

For example, in a method for descrambling an address provided in an embodiment of the present disclosure, obtaining a first pseudo-random number includes: generating a pseudo-random number in response to receiving the clock signal, wherein each clock cycle in the clock signal corresponds to one of the pseudo-random numbers, and not generating the pseudo-random number in response to ceasing to receive the clock signal; and acquiring a pseudo random number corresponding to the last clock period in the received clock signal as a first pseudo random number.

In a third aspect, at least one embodiment of the present disclosure provides a circuit for scrambling an address, comprising: a receiving module configured to receive a first request message from the processing unit, wherein the first request message contains a data address; the address scrambling module is connected with the receiving module and is configured to perform address scrambling operation on the address packet to be processed so as to obtain a scrambling address, the length of the scrambling address is greater than or equal to that of the data address, and the address to be processed is the data address or an intermediate address in the address scrambling operation period; and the sending module is connected with the address scrambling module and is configured to send a second request message containing the scrambling address to the link layer, wherein the second request message corresponds to the first request message and is a transaction layer data packet.

For example, in one embodiment of the present disclosure provides a circuit for scrambling an address, an address scrambling module includes: the doping unit is configured to dope the address to be processed according to the identification information in the first request message; the switching unit is configured to perform pseudo-random switching operation on the address to be processed according to the pseudo-random number characteristic and the preset length; and a sequence adjustment unit configured to perform a pseudo-random sequence adjustment operation on the packet sequence of the address to be processed according to the pseudo-random number characteristic; wherein the address scrambling operation includes at least one of a doping operation, a swapping operation, and a sequence adjustment operation.

For example, in one embodiment of the present disclosure provides a circuit for scrambling an address, the circuit further comprising: the detection module is connected with the receiving module and the address scrambling module, and is configured to determine whether the address scrambling is started or not and the units started in the address scrambling module according to the configuration information in the first request message, and start at least one unit in the address scrambling module when the address scrambling is started.

For example, in a circuit for scrambling an address provided by an embodiment of the present disclosure, the detection module is further configured to disable the address scrambling module upon determining that address scrambling is disabled.

For example, in a circuit for scrambling an address provided in an embodiment of the present disclosure, when at least two of a doping unit, a switching unit, and a sequential adjustment unit are enabled, an address scrambling module is configured to perform an address scrambling operation on the data address in the order of the doping unit, the switching unit, and the sequential adjustment unit.

For example, in an embodiment of the present disclosure that provides for scrambling an address, the address scrambling module further includes: the grouping unit is connected with the receiving module, the doping unit, the switching unit and the sequence adjusting unit and is configured to divide the data address into N groups according to the position of the data address in the first request message before performing address scrambling operation on the address grouping to be processed, wherein N is an integer greater than or equal to 2.

For example, in a circuit for scrambling an address provided by an embodiment of the present disclosure, a doping unit is configured to: dividing the identification information into N groups according to the position of the identification information in the first request message; doping the N groups of identification information with the N groups of addresses to be processed respectively according to a preset arrangement mode to obtain N groups of virtual addresses, wherein the preset arrangement mode indicates the relative position relationship between the addresses to be processed and the identification information in each group of virtual addresses, and the relative position relationship corresponding to the N groups of virtual addresses is at least partially different.

For example, in one embodiment of the present disclosure provides a circuit for scrambling an address, a switching unit is configured to: acquiring a first pseudo-random number; and respectively controlling the switching modes of the N switch arrays by using the first pseudo-random numbers so that the N switch arrays respectively exchange positions in the N groups of addresses to be processed according to preset lengths.

For example, in a circuit for scrambling addresses provided by an embodiment of the present disclosure, a sequential adjustment unit is configured to: acquiring a second pseudo-random number; and taking the second pseudo-random number as a control sequence, and adjusting the grouping sequence of N groups of addresses to be processed according to a preset adjustment rule of the control sequence and the grouping sequence.

For example, in a circuit for scrambling addresses provided in an embodiment of the present disclosure, the doping unit is further configured to fill in N sets of virtual addresses with a default value when the lengths of N sets of addresses to be processed are different, so that the lengths of N sets of virtual addresses are the same.

For example, in one embodiment of the present disclosure provides a circuit for scrambling an address, a switching unit includes: a linear feedback shift register configured to generate a first pseudo-random number; and N switch arrays, wherein each switch array comprises a plurality of multi-control switches, and each switch array is configured to control the on or off of the plurality of multi-control switches according to a switching mode corresponding to the first pseudo-random number so as to enable a group of addresses to be processed, which are input into one switch array, to be subjected to position exchange in the transmission process of one switch array.

For example, in a circuit providing scrambling of addresses in an embodiment of the present disclosure, a linear feedback shift register is configured to: generating a pseudo-random number in response to receiving the clock signal, wherein each clock cycle in the clock signal corresponds to one of the pseudo-random numbers, and not generating the pseudo-random number in response to ceasing to receive the clock signal; and taking the pseudo random number corresponding to the last clock period in the received clock signal as a first pseudo random number.

For example, in a circuit for scrambling an address provided by an embodiment of the present disclosure, the switching unit further includes: and the clock gating is connected with the linear feedback shift register and is configured to control the input of a clock signal of the linear feedback shift register.

In a fourth aspect, at least one embodiment of the present disclosure provides a circuit for descrambling an address, comprising: a receiving module configured to receive a third request message from the link layer, wherein the third request message is a transaction layer packet and includes a scrambling address; the address descrambling module is connected with the receiving module and is configured to perform address descrambling operation on the address packet to be processed so as to acquire a data address, the length of the data address is smaller than or equal to that of the scrambling address, and the address to be processed is a scrambling address or an intermediate address in the address descrambling operation period; and the sending module is connected with the address descrambling module and is used for sending a fourth request message containing the data address to the processing unit, and the fourth request message corresponds to the third request message.

For example, in one embodiment of the present disclosure provides a circuit for descrambling an address, an address descrambling module includes: the dedoping unit is configured to carry out the dedoping operation on the address to be processed according to the identification information in the third request message; the reverse exchange unit is configured to perform pseudo-random reverse exchange operation on the address to be processed according to the pseudo-random number characteristic and the preset length; and a reverse order adjustment unit configured to perform a pseudo-random reverse order adjustment operation on the packet order of the addresses to be processed according to the pseudo-random number characteristic; wherein the address descrambling operation comprises at least one of a de-doping operation, a reverse switching operation and a reverse order adjustment operation.

For example, in one embodiment of the present disclosure provides a circuit for descrambling an address, the circuit further comprises: the detection module is connected with the receiving module and the address descrambling module and is configured to determine whether the address descrambling is started or not and the units started in the address descrambling module according to the configuration information in the third request message, and at least one unit in the address descrambling module is started when the address descrambling is started.

For example, in a circuit for descrambling an address provided by an embodiment of the present disclosure, the detection module is further configured to disable the address descrambling module when determining that address descrambling is disabled.

For example, in a circuit for descrambling an address provided in an embodiment of the present disclosure, when at least two units of a dedoping unit, a reverse switching unit, and a reverse order adjustment unit are enabled, an address descrambling module is configured to perform an address descrambling operation on a scrambled address in the order of the reverse order adjustment unit, the reverse switching unit, and the dedoping unit.

For example, in an embodiment of the present disclosure that provides for descrambling an address, the address descrambling module further comprises: and the grouping unit is connected with the receiving module, the dedoping unit, the reverse switching unit and the reverse sequence adjusting unit and is configured to divide the scrambling address into N groups according to the position of the scrambling address in the third request message, wherein N is an integer greater than or equal to 2.

For example, in a circuit for descrambling an address provided by an embodiment of the present disclosure, a dedoping unit is configured to: according to a preset arrangement mode, removing N groups of identification information from N groups of addresses to be processed respectively to obtain N groups of data addresses; the preset arrangement mode indicates the relative position relationship between the data addresses and the identification information in each group of addresses to be processed, and the relative position relationship corresponding to the N groups of addresses to be processed is at least partially different.

For example, in a circuit for descrambling an address provided by an embodiment of the present disclosure, a reverse switching unit is configured to: acquiring a first pseudo-random number; and inverting the first pseudo-random number, and respectively controlling the switching modes of the N switch arrays by utilizing the inversion result of the first pseudo-random number, so that the N switch arrays respectively perform position reverse exchange in the N groups of addresses to be processed according to the preset length.

For example, in a circuit for descrambling addresses provided by an embodiment of the present disclosure, a reverse order adjustment unit is configured to: acquiring a second pseudo-random number; and taking the second pseudo-random number as a control sequence, and reversely adjusting the grouping sequence of N groups of addresses to be processed according to a preset adjustment rule of the control sequence and the grouping sequence.

For example, in a circuit providing descrambling of addresses in an embodiment of the present disclosure, the dedoping unit is further configured to: and when the N groups of addresses to be processed comprise default values, removing the default values from the N groups of addresses to be processed to obtain N groups of data addresses.

For example, in a circuit providing descrambling of addresses in one embodiment of the present disclosure, a linear feedback shift register is configured to: generating a pseudo-random number in response to receiving the clock signal, wherein each clock cycle in the clock signal corresponds to one of the pseudo-random numbers, and not generating the pseudo-random number in response to ceasing to receive the clock signal; and taking the pseudo random number corresponding to the last clock period in the received clock signal as a first pseudo random number.

For example, in a circuit for descrambling an address provided in an embodiment of the present disclosure, the switching unit further includes: and the clock gating is connected with the linear feedback shift register and is configured to control the input of a clock signal of the linear feedback shift register.

In a fifth aspect, at least one embodiment of the present disclosure provides a chip, a circuit for scrambling an address as in any of the above third aspects, and/or a circuit for descrambling an address as in any of the above fourth aspects.

In a sixth aspect, at least one embodiment of the present disclosure provides an electronic device, including the chip of the fifth aspect.

In a seventh aspect, at least one embodiment of the present disclosure provides an electronic device comprising a processor and a memory having stored therein computer executable instructions that are executed by the processor to implement a method as in the first aspect and/or any of the second aspects described above.

In an eighth aspect, at least one embodiment of the present disclosure provides a computer-readable storage medium having instructions stored thereon, wherein the instructions are loaded and executed by a processor to implement a method as in the first aspect and/or any of the second aspects described above.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure, not to limit the present disclosure.

FIG. 1 illustrates a flow chart of a method of scrambling an address provided in accordance with an embodiment of the present disclosure;

FIG. 2 illustrates a flow chart of a method of descrambling an address provided in accordance with an embodiment of the present disclosure;

FIG. 3a shows a schematic diagram of a circuit for scrambling addresses provided in accordance with an embodiment of the present disclosure;

FIG. 3b shows a schematic diagram of a circuit for scrambling addresses provided in accordance with an embodiment of the present disclosure;

FIG. 4 shows a schematic diagram of a multi-control switch provided in accordance with an embodiment of the present disclosure;

FIG. 5 shows a schematic diagram of a switch array provided in accordance with an embodiment of the present disclosure;

FIG. 6a shows a schematic diagram providing a linear feedback shift register according to an embodiment of the present disclosure;

Fig. 6b shows a schematic diagram providing a switching unit according to an embodiment of the present disclosure.

FIG. 7a shows a schematic diagram of a circuit for descrambling an address provided in accordance with an embodiment of the present disclosure;

FIG. 7b shows a schematic diagram of yet another circuit for descrambling an address provided in accordance with an embodiment of the present disclosure;

FIG. 7c shows a schematic diagram of another circuit for descrambling an address provided in accordance with an embodiment of the present disclosure;

FIG. 8 shows a schematic diagram of yet another switch array provided in accordance with an embodiment of the present disclosure;

Fig. 9 shows a schematic diagram of a reverse switching unit provided in accordance with an embodiment of the present disclosure;

Fig. 10 shows a schematic diagram of an electronic device provided according to an embodiment of the present disclosure.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. It will be apparent that the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments, which can be made by one of ordinary skill in the art without the need for inventive faculty, are within the scope of the present disclosure, based on the described embodiments of the present disclosure.

Unless defined otherwise, technical or scientific terms used in this disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first," "second," and the like, as used in this disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. Likewise, the terms "a," "an," or "the" and similar terms do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", etc. are used merely to indicate relative positional relationships, which may also be changed when the absolute position of the object to be described is changed.

There is a relevant provision for an address scrambling mechanism starting from PCIe 1.0, for example, an exclusive or operation is performed on the address by using a pseudo-random number, so that the signal capability can be distributed more dispersedly in the whole energy spectrum, and the anti-interference capability is increased. In the evolution of PCIe, the role of address scrambling has also changed from just increasing the immunity to interference, to also improving the security of data transmissions.

Although the CXL protocol is based on PCIe, unlike PCIe, there is no description in the CXL protocol of any content of address scrambling, and thus it is important to implement address scrambling adapted to the CXL protocol.

Based on the above, at least one embodiment of the present disclosure provides a method for scrambling an address, a method for descrambling an address, a circuit, a chip, and an electronic device, which implement scrambling and descrambling of an address based on the CXL protocol, thereby improving security of data transmission.

The CXL protocol includes a CXL.mem sub-protocol and a CXL.cache sub-protocol. Among the CXL.mem sub-protocols are RWD and REQ channels, among the CXL.cache sub-protocols are H2D (Host to Device) Request, H2D Response, H2D Data, D2H (Device to Host) Request, D2H Response and D2H Data channels, the RWD, REQ and H2D Request channels among these channels are related to the transmission of addresses. The application scenario of the embodiments of the present disclosure mainly relates to RWD, REQ, and H2D Request channels. REQ may also be denoted as M2S (Masterto Subordinate, master-to-slave) Request or REQ, RWD may also be denoted as M2S Requestwith Data or RwD, different representations of the same meaning being interchangeable in this disclosure. In the present disclosure, host corresponds to Device and Master corresponds to Subordinate. Host is, for example, a controller supporting the CXL protocol, e.g., host is a CPU (Central Processing Unit ), and Device is a Device supporting the CXL protocol, e.g., a memory connected to the CPU. Master and Subordinate are then interchangeable, e.g., CXL controller is connected to memory, master can be understood as the request initiator, subordinate is the corresponding request processor, so CXL controller can be Master or Subordinate, memory can also be Master or Subordinate.

Fig. 1 shows a flow chart of a method of scrambling an address provided in accordance with an embodiment of the present disclosure.

As shown in fig. 1, a method 100 of scrambling an address includes the steps of:

Step S101, a first request message is received from a processing unit, wherein the first request message contains a data address.

Step S102, address scrambling operation is performed on the address packet to be processed to obtain a scrambling address, wherein the length of the scrambling address is greater than or equal to the length of the data address, and the address to be processed is the data address or an intermediate address during the address scrambling operation.

Step S103, a second request message containing the scrambling address is sent to the link layer, the second request message corresponds to the first request message and the second request message is a transaction layer data packet.

Upon execution of step S101, a first Request message is received from the processing unit, which may be RWD, REQ, and H2D Request messages including a read Request message or a write Request message, e.g. H2D Request may be a host-to-device read Request or a write Request. The processing unit is, for example, a CPU or a controller.

Optionally, it may also be determined whether address scrambling is enabled before performing step S102. For example, based on configuration information in the first request message, it is determined whether address scrambling is enabled and the operations included when address scrambling is enabled. For example, there are reserved fields in RWD, REQ, and H2D Request messages, also referred to as RSVD fields, in which configuration information indicating whether address scrambling is enabled and which operations are specifically included when address scrambling is enabled may be added. For example, the address scrambling operations include a doping operation, a swapping operation, and a sequence adjustment operation, which may be enabled alone or in combination. For example, when the configuration information indicates that the address scrambling operation is disabled, then all operations included in the address scrambling operation are disabled, and when the configuration information indicates that the address scrambling operation is enabled, at least one of the doping operation, the switching operation, and the sequence adjustment operation is enabled.

For example, RSVD [5:2] in the reservation field is configuration information, RSVD [2] indicates whether address scrambling operations are enabled, RSVD [3] indicates whether doping operations are enabled, RSVD [4] indicates whether switching operations are enabled, and RSVD [5] indicates whether sequence adjustment operations are enabled. RSVD x is 0 for disabled and 1 for enabled, with x being equal to 2,3, 4 and 5. It will be appreciated that RSVD [ x ] may also be set to a value of 0 to represent an enable operation and a value of 1 to represent a disable operation. In addition, which bits in the reserved field are set as the configuration information may also be set according to the requirement, and the configuration information may also be represented by RSVD [11:8] in the reserved field, for example, without limitation. The position of the "word" in the reserved field indicating the above operations may also be set arbitrarily in the reserved field, for example, RSVD 2 corresponds to the switch operation, RSVD 3 indicates the doping operation.

Alternatively, whether the address scrambling operation is enabled may be indicated by configuration information of the doping operation, the switching operation, and the sequence adjustment operation instead of setting whether the address scrambling operation is enabled. For example, RSVD [5:3] in the reserved field is configuration information, RSVD [3] indicates whether the doping operation is enabled, RSVD [4] indicates whether the switching operation is enabled, RSVD [5] indicates whether the sequence adjustment operation is enabled, implicitly indicates that the address scrambling operation is disabled when the doping operation, switching operation and sequence adjustment operation are all disabled, and indicates that the address scrambling operation is enabled when at least one of the doping operation, switching operation and sequence adjustment operation is enabled.

Disabling of various operations in this embodiment may also be understood as bypassing. Through setting configuration information, the specific operation contained in the address scrambling operation can be selected more flexibly, so that the use requirements in different scenes are met. For example, in a scenario with high security requirements, three of doping operation, switching operation, and sequence adjustment operation may be selected to be enabled. In a scenario with low security requirements, one or both of the doping operation, the switching operation, and the sequence adjustment operation may be performed. When there is no scrambling requirement, the address scrambling operation may be selected to be disabled as a whole. For example, when a Host is connected to a type3 device in the CXL protocol, address scrambling can be performed on the Host side if it is desired that the data be stored in an out-of-order manner in memory. For another example, when the memory has an address boundary for out-of-order storage, the doping operation and the sequence adjustment operation may be disabled, and only the switching operation may be enabled, so that the scrambled address may be in a smaller range to meet the address boundary requirement.

Optionally, the address scrambling operation may also be configured to be enabled or disabled by default. For example, the first request message may be set to contain no configuration information and the address scrambling operation may be set to an enabled state, thereby enabling the address scrambling operation by default. For another example, setting the address scrambling operation to a disabled state, the address scrambling operation is disabled by default.

Step S102 is executed, when the address scrambling is enabled, address scrambling operation is performed on the address packet to be processed to obtain a scrambled address, and the length of the scrambled address is greater than or equal to the length of the data address.

Optionally, the address scrambling operation includes at least one of: doping the address to be processed according to the identification information in the first request message; according to the pseudo-random number characteristics, carrying out pseudo-random exchange operation on the address to be processed according to a preset length; according to the pseudo-random number characteristic, carrying out pseudo-random sequence adjustment operation on the grouping sequence of the addresses to be processed; wherein the address to be processed is a data address or an intermediate address during an address scrambling operation.

For example, since the address scrambling operation may include one or more operations, the data address and the intermediate address obtained during the address scrambling operation are collectively referred to as the pending address. The doping operation is to dope the address to be processed and the identification information carried by the first request message, and the address length after doping is increased. The doping operation may also be referred to as a haze operation. The exchange operation is to exchange the addresses to be processed pseudo-randomly in the group, for example, with a length of "1 bit", and the address length after the exchange operation is unchanged. The order adjustment operation is an adjustment of the packet order of the addresses to be processed, and may also be regarded as a position exchange operation performed in units of groups. The sequence adjustment operation affects the location of the address packets in the message and thus the order in which the address packets are transmitted.

The data address in this embodiment may be a physical address or a logical address. For example, when the first request message is a RWD message, the data address has a length of 46 bits; when the first request message is a REQ message, the length of the data address is 47 bits; when the first Request message is an H2D Request message, the data address has a length of 46 bits.

Optionally, before performing the address scrambling operation on the address packet to be processed, the method further comprises: the data addresses are divided into N groups according to the positions of the data addresses in the first request message, wherein N is an integer greater than or equal to 2. For example, the data addresses are unevenly divided into 8 groups according to the low order to the high order, such as 4-7 bits in length of each group of data addresses. Alternatively, the process of dividing the data address into N groups is not performed, but in the address scrambling operation, the address scrambling operation of the data address packet is directly performed according to the location of the data address in the first request message and a preset packet rule.

In this embodiment, after the data addresses are grouped, all the addresses to be processed are processed according to the grouping of the data addresses, and the intermediate addresses during the address scrambling operation do not need to be repeatedly subjected to the grouping processing.

Optionally, when the address scrambling operation includes a doping operation, performing the address scrambling operation on the address packet to be processed to obtain a scrambled address, including: dividing the identification information into N groups according to the position of the identification information in the first request message; doping the N groups of identification information with the N groups of addresses to be processed respectively according to a preset arrangement mode to obtain N groups of virtual addresses, wherein the preset arrangement mode indicates the relative position relationship between the addresses to be processed and the identification information in each group of virtual addresses, and the relative position relationship corresponding to the N groups of virtual addresses is at least partially different.

When the first request message is a RWD message or a REQ message, the identification information is a tag, and the length is 16 bits. When the first Request message is an H2D Request, the identification information is UQID and the length is 12 bits. The identification information may be unevenly divided into N groups according to its position in the first request message, e.g. from low order to high order. Each group of identification information may be 0-2 bits in length.

In this embodiment, the doping of the identification information and the address to be processed is implemented according to a preset arrangement mode, and when the first request message is different, the preset arrangement mode may be different. The following illustrates the manner of performing the doping operation for the RWD message, the REQ message, and the H2D Request message, respectively.

For example, when the first request message is an RWD message, the RWD message has a total length of 87 bits, wherein the data address is address [51:6], the identification information tag occupies 16 bits, and the RSVD occupies 6 bits. The data address and the identification information are divided into 8 groups, and 8 groups of virtual addresses can be obtained after doping. The 8 sets of virtual addresses are denoted as Group0 to Group7, and the following doping schemes are used for Group0 to Group 3:

1) Each Group is composed of 2-bit identification information and 6-bit data address;

2) The upper 4 bits and the lower 4 bits of each Group are respectively doped with 1 bit of identification information;

3) The position of the identification information in the virtual address is shifted from low order to high order by 1 bit each time according to the number of the packet.

The following doping schemes are used for Group4 to Group 7:

1) Each Group is composed of 2 bits of identification information and 6 bits of data address, wherein when the data address is insufficient, the data address is filled by a default value, and the default value is usually 0;

2) 2 bits of identification information in each Group are connected;

According to the doping scheme described above, 8 sets of virtual addresses can be obtained as follows:

Group0{vir_address[7:0]}＝{address[11:9],tag[1],address[8:6],tag[0]}；

Group1{vir_addr[15:8]}＝{address[17:16],tag[3],address[15:13],tag[2],address[12]}；

Group2{vir_addr[23:16]}＝{address[23],tag[5],address[22:20],tag[4],address[19:18]}；

Group3{vir_addr[31:24]}＝{tag[7],address[29:27],tag[6],address[26:24]}；

Group4{vir_addr[39:32]}＝{address[35:30],tag[9:8]}；

Group5{vir_addr[47:40]}＝{address[41:37],tag[11:10],address[36]}；

Group6{vir_addr[55:48]}＝{address[47:44],tag[13:12],address[43:42]}；

Group7{vir_addr[63:56]}＝{2’b00,address[51],tag[15:14],address[50:48]}。

Wherein vir_addr represents a virtual address, address represents a data address, tag represents representing information, and 2' b00 represents a value of 0 which is two bits higher. address [ ] represents the location of the data address in the RWD message, tag [ ] represents the location of the identification information in the RWD message, and vir_addr [ ] represents the location of the obtained virtual address.

For example, when the first request message is a REQ message, the total length of the REQ message is 87 bits, where the data address is address [51:7], the identification information tag occupies 16 bits, and RSVD occupies 6 bits. The data address and the identification information are divided into 8 groups, and 8 groups of virtual addresses can be obtained after doping. The 8 sets of virtual addresses are denoted as Group0 to Group7, and the following doping schemes are used for Group0 to Group 3:

The following doping schemes are used for Group4 to Group 7:

2) 2 bits of identification information in each Group are connected;

Group0{vir_address[7:0]}＝{address[12:10],tag[1],address[9:7],tag[0]}；

Group1{vir_addr[15:8]}＝{address[18:17],tag[3],address[16:14],tag[2],address[13]}；

Group2{vir_addr[23:16]}＝{address[24],tag[5],address[23:21],tag[4],address[20:19]}；

Group3{vir_addr[31:24]}＝{tag[7],address[30:28],tag[6],address[27:25]}；

Group4{vir_addr[39:32]}＝{address[36:31],tag[9:8]}；

Group5{vir_addr[47:40]}＝{address[42:38],tag[11:10],address[37]}；

Group6{vir_addr[55:48]}＝{address[48:45],tag[13:12],address[44:43]}；

Group7{vir_addr[63:56]}＝{3’b00,tag[15:14],address[51:49]}。

wherein vir_addr represents a virtual address, address represents a data address, tag represents representing information, and 3' b00 represents a value of 0 which is 3 bits higher. The address [ ] indicates the position of the data address in the REQ message, the tag [ ] indicates the position of the identification information in the REQ message, and vir_addr [ ] indicates the position of the obtained virtual address.

For example, when the first Request message is an H2D Request message, the H2D Request message has a total length of 64 bits, where the data address is address [51:6], the identification information UQID occupies 12 bits, and the RSVD occupies 6 bits. The data address and the identification information are divided into 8 groups, and 8 groups of virtual addresses can be obtained after doping. The 8 groups of virtual addresses are expressed as groups 0 to 7, doping operation is carried out for groups 0 to 5, a one-to-one mapping relation is kept for groups 6 to 7, and if the data address length is insufficient, the virtual addresses are filled with default values.

The following doping schemes are used for Group0 to Group 3:

The following doping schemes are used for Group4 to Group 5:

2) 2 bits of identification information in each Group are connected;

Group0{vir_addr[7:0]}＝{address[11:9],UQID[1],address[8:6],UQID[0]}；

Group1{vir_addr15:8]}＝{address[17:16],UQID[3],address[15:13],UQID[2],address[12]}；

Group2{vir_addr[23:16]}＝{address[23],UQID[5],address[22:20],UQID[4],address[19:18]}；

Group3{vir_addr[31:24]}＝{UQID[7],address[29:27],UQID[6],address[26:24]}；

Group4{vir_addr[39:32]}＝{address[35:30],UQID[9:8]}；

Group5{vir_addr[47:40]}＝{address[41:37],UQID[11:10],address[36]}；

Group6{vir_addr[55:48]}＝{address[49:42]}；

Group7{vir_addr[63:56]}＝{4‘b000，address[51:50]}。

Wherein vir_addr represents a virtual address, address represents a data address, tag represents representing information, and 4' b00 represents a value of 0 higher than 4 bits. address [ ] represents the location of the data address in the H2D Request message, tag [ ] represents the location of the identification information in the H2D Request message, and vir_addr [ ] represents the location of the obtained virtual address.

Optionally, when the address scrambling operation includes a switching operation, performing the address scrambling operation for the address packet to be processed, including: acquiring a first pseudo-random number; and respectively controlling the switching modes of the N switch arrays by using the first pseudo-random numbers so that the N switch arrays respectively exchange positions in the N groups of addresses to be processed according to preset lengths.

For example, the address to be processed has 8 packets, each packet corresponding to 1 switch array, the 8 switch arrays being controlled by the first pseudo-random number. The first pseudo-random number may consist of only 1 and 0, more adapted to the control of the switch. For example, the first pseudorandom number is 1011100011010001, 16 bits in length, each of which controls a switch. For example, the switch may be a multi-control switch, whereby the conduction path of the switch may be selected with only 0 and 1. For example, a group of addresses to be processed is "abcdefg", and "ahbdfecg" is obtained after the position exchange in the group according to the preset length of 1 bit. Alternatively, the N switch arrays may be controlled with a first pseudo-random number, in which case the intra-group switching of each group of addresses to be processed is the same. In another alternative implementation, the N switch arrays may be controlled with a plurality of first pseudo-random numbers, e.g., the N switch arrays may be controlled with N first pseudo-random numbers, in which case the intra-group switching patterns of the different groups of pending addresses may be different or the same.

Optionally, the obtaining the first pseudo random number includes: generating a pseudo-random number in response to receiving the clock signal, wherein each clock cycle in the clock signal corresponds to one of the pseudo-random numbers, and not generating the pseudo-random number in response to ceasing to receive the clock signal; and acquiring a pseudo random number corresponding to the last clock period in the received clock signal as a first pseudo random number.

In this embodiment, the generation of the pseudo-random number may be triggered by the clock signal, e.g., a rising edge of a clock cycle in the clock signal is used to trigger the generation of the pseudo-random number such that one pseudo-random number is generated per clock cycle. When the reception of the clock signal is stopped, i.e. no new clock cycle is received, no pseudo random number is generated. Each time a pseudo-random number is generated may be used as the first pseudo-random number, and thus the first pseudo-random number is updated following a clock cycle. When the clock signal is stopped being received, the pseudo random number corresponding to the last clock period is used as a first pseudo random number, and the first pseudo random number is kept unchanged until the clock signal is received again. By the scheme of the embodiment, the randomness of the first pseudo random number can be increased, so that the safety of data transmission is improved.

Optionally, when the address scrambling operation includes a sequence adjustment operation, performing the address scrambling operation for the address packet to be processed includes: acquiring a second pseudo-random number; and taking the second pseudo-random number as a control sequence, and adjusting the grouping sequence of N groups of addresses to be processed according to a preset adjustment rule of the control sequence and the grouping sequence.

In this embodiment, the second pseudorandom number has a length smaller than that of the first pseudorandom number, and may be acquired alone, or after the first pseudorandom number is acquired, a part of the digits may be selected as the second pseudorandom number from the first pseudorandom number. For example, bits 3, 7, and 9 of the first pseudorandom number are selected as the second pseudorandom number. The manner of separately obtaining the second pseudo random number may refer to the manner of obtaining the first pseudo random number, which is not described herein.

For example, the N groups of addresses to be processed are virtual addresses Group0 to Group7 in the above, and the second pseudo-random number control adjusts the order of Group0 to Group 7. The preset adjustment rule in this embodiment may indicate a sequential adjustment manner of N groups of addresses to be processed, for example, the sequential adjustment manner includes forward movement, backward movement, position exchange, and the like. For example, the original order of Group0 to Group7 is Group0, group1, … …, group7, and the order after the forward shift is Group1, group2, … …, group7, group0.

Optionally, when the lengths of the N groups of addresses to be processed are different, filling the N groups of virtual addresses with a default value so that the lengths of the N groups of virtual addresses are the same.

In this embodiment, the length of the data address before the address scrambling may not be equally divided into N groups, for example, the length of the data address is 46 bits, and may not be equally divided into 8 groups. By filling N groups of addresses to be processed to be the same in length, the same address scrambling operation can be performed on the N groups of addresses to be processed, so that the complexity of the processing process can be reduced.

Optionally, when the address scrambling operation includes at least two operations of a doping operation, a switching operation, and a sequential adjustment operation, the address scrambling operation is performed in order of sequentially performing the doping operation, the switching operation, and the sequential adjustment operation.

In the present embodiment, the address scrambling operation may include a doping operation, a swapping operation, and a sequence adjustment operation, or include a doping operation and a swapping operation, include a doping operation and a sequence adjustment operation, and include a swapping operation and a sequence adjustment operation. Where the address scrambling operation includes at least two operations, the at least two operations included may be performed in any order. For example, the doping operation is performed first, then the switching operation is performed, and finally the sequence adjustment operation is performed. For another example, the switching operation is performed first, then the doping operation is performed, and finally the sequence adjustment operation is performed. For another example, the sequence adjustment operation is first performed, then the exchange operation is performed, and finally the doping operation is performed.

Step S103 is executed to send a second request message containing the scrambling address to the link layer, where the second request message corresponds to the first request message and the second request message is a transaction layer packet.

After step S102 is performed, a scrambling address may be obtained, and the transaction layer packet including the scrambling address may be further sent to the link layer to complete the subsequent data transmission. In this embodiment, the first request message is received from an upper layer of the transaction layer, so that the information to be transmitted needs to be packaged into a transaction layer data packet and further transmitted to the link layer.

In the CXL protocol, the location of the data address in various messages is fixed, so that an attacker can intercept the power consumption curve of the address field by using the characteristics of address distribution in different messages or channels, and crack the address information by using a means of analyzing the power consumption. The doping operation can dope the address by means of other fields carried by the message, such as identification information, so as to reduce the regularity of address distribution. The exchange operation ensures that addresses in messages sent in a certain time period have different scrambling modes by means of the characteristics of random numbers, so that the regularity of address distribution is greatly reduced, an attacker cannot find the regularity by analyzing the address power consumption and other modes, and the safety of data transmission is remarkably improved. The sequential switching operation can further disturb the address distribution and reduce the regularity of the address distribution.

By the address scrambling method provided by the embodiment of the disclosure, at least one of doping, exchanging and sequential adjusting operation of the data address can be realized, so that the method is more suitable for CXL protocol, can cope with more scenes, ensures the safety of data transmission and improves the flexibility of the scheme.

Fig. 2 shows a flow chart of a method of descrambling an address provided in accordance with an embodiment of the present disclosure.

As shown in fig. 2, a method 200 of descrambling an address includes the steps of:

Step S201, a third request message is received from the link layer, wherein the third request message is a transaction layer packet and includes a scrambling address.

In step S202, an address descrambling operation is performed on the address packet to be processed to obtain a data address, where the length of the data address is less than or equal to the length of the scrambling address, and the address to be processed is the scrambling address or an intermediate address during the address descrambling operation.

In step S203, a fourth request message including the data address is sent to the processing unit, where the fourth request message corresponds to the third request message.

The method for descrambling the address provided in this embodiment corresponds to the method for scrambling the address described above, and descrambling the address is the reverse operation of address scrambling. In the present disclosure, the method 100 of scrambling an address may be performed by an electronic device or an electronic apparatus supporting the CXL protocol, such as a chip, a processor, a controller, or the like, and the method 200 of descrambling an address may be performed by an electronic device or an electronic apparatus supporting the CXL protocol, such as a memory, a chip, a processor, a controller, or the like. The method 100 of scrambling an address and the method 200 of descrambling an address may be implemented in the same device, may be implemented in different devices connected to each other, or may be implemented separately.

Step S201 is performed, in which a third request message is received from the link layer, wherein the third request message is a transaction layer packet and includes a scrambling address.

In this embodiment, the third request message is a message from the link layer, which may be a link layer packet or a transaction layer packet obtained from the link layer packet. The third request message may have the same format as the second request message. The third request message is a read request message or a write request message and includes a scrambling address. The third Request message may be RWD, REQ, and H2D Request messages.

Optionally, before performing step S202, it may also be determined whether address descrambling is enabled. For example, according to the configuration information in the third request message, it is determined whether address descrambling is enabled and the operations included when address descrambling is enabled.

In an alternative implementation, similar to the configuration information in the first request message described above, the same configuration information may be used to indicate both whether address scrambling is enabled and whether address descrambling is enabled. For example, when the configuration information indicates that address scrambling is enabled, address descrambling is correspondingly enabled.

For example, RSVD [5:2] in the reservation field is configuration information, RSVD [2] indicates whether address scrambling and address descrambling operations are enabled, RSVD [3] indicates whether doping and de-doping operations are enabled, RSVD [4] indicates whether switching operations and reverse switching operations are enabled, RSVD [5] indicates whether sequence adjustment operations and reverse sequence adjustment operations are enabled. RSVD x is 0 for disabled and 1 for enabled, with x being equal to 2, 3, 4 and 5. It will be appreciated that RSVD [ x ] may also be set to a value of 0 to represent an enable operation and a value of 1 to represent a disable operation.

In yet another alternative implementation, different configuration information may be used to indicate whether address scrambling is enabled and whether address descrambling is enabled. For example, RSVD [5:2] in the reservation field is configuration information of address scrambling, RSVD [9:6] in the reservation field is configuration information of address descrambling, RSVD [2] indicates whether address scrambling is enabled, RSVD [3] indicates whether doping operation is enabled, RSVD [4] indicates whether switching operation is enabled, RSVD [5] indicates whether sequence adjustment operation is enabled, RSVD [6] indicates whether address descrambling operation is enabled, RSVD [7] indicates whether de-doping operation is enabled, RSVD [8] indicates whether reverse switching operation is enabled, and RSVD [9] indicates whether reverse sequence adjustment operation is enabled.

Alternatively, whether the address descrambling operation is enabled may be indicated by configuration information of the dedoping operation, the reverse switching operation, and the reverse order adjustment operation instead of setting whether the address descrambling operation is enabled. For example, RSVD [5:3] in the reserved field is configuration information for address descrambling, RSVD [3] indicates whether a de-doping operation is enabled, RSVD [4] indicates whether a reverse switching operation is enabled, RSVD [5] indicates whether a reverse order adjustment operation is enabled, implicitly indicates that the address descrambling operation is disabled when the de-doping operation, the reverse switching operation and the reverse order adjustment operation are all disabled, and indicates that the address descrambling operation is enabled when at least one of the de-doping operation, the reverse switching operation and the reverse order adjustment operation is enabled.

In this embodiment, for the case of requiring data to be stored out of order in the memory, the address descrambling function may be selectively disabled, thereby improving the flexibility of the scheme.

Optionally, the address descrambling operation may also be configured to be enabled or disabled by default. For example, the third request message may be set to contain no configuration information and the address descrambling operation may be configured to an enabled state, thereby enabling the address descrambling operation by default. For another example, setting the address descrambling operation to a disabled state, the address descrambling operation is disabled by default.

Step S202 is executed, when address descrambling is enabled, address descrambling operation is performed on the address packet to be processed to obtain a data address, wherein the length of the data address is smaller than or equal to the length of the scrambling address.

Optionally, the address descrambling operation comprises at least one of the following operations: carrying out a dedoping operation on the address to be processed according to the identification information in the third request message; according to the pseudo-random number characteristics, performing pseudo-random reverse exchange operation on the address to be processed according to a preset length; and performing pseudo-random reverse order adjustment operation on the grouping order of the addresses to be processed according to the pseudo-random number characteristics.

The address descrambling operation in this embodiment is the reverse operation of the address scrambling operation in the above embodiment, where the de-doping operation is to remove the identification information in the address to be processed and retain the address information. The reverse exchange operation is to restore the exchange operation to obtain the address information which is not exchanged. The reverse order adjustment operation is to restore the packet order of the addresses to be processed to the initial state, and obtain the original packet order.

Optionally, before performing the address descrambling operation for the address packet to be processed, the method further comprises: the scrambling address is divided into N groups according to the position of the scrambling address in the third request message, wherein N is an integer greater than or equal to 2.

The scrambled addresses are addresses scrambled via at least one of the above-described doping operation, switching operation, and sequential adjustment operation, and the length of the scrambled addresses can be generally divided into N groups on average, so that the scrambled addresses can be divided into N groups on average directly from the lower order to the upper order. If the length of the scrambling address cannot be divided into N groups on average, in this case, there will be a specific packet indication in the third request message, so that the scrambling address is grouped according to the packet indication.

Alternatively, the process of dividing the scrambling address into N groups is not performed, but in the address descrambling operation, the address descrambling operation is directly performed on the scrambling address packet according to the position of the scrambling address in the third request message and the preset packet rule.

Optionally, when the address descrambling operation includes a de-doping operation, performing the address descrambling operation for the address packet to be processed, including: according to a preset arrangement mode, removing N groups of identification information from N groups of addresses to be processed respectively to obtain N groups of data addresses; the preset arrangement mode indicates the relative position relationship between the data addresses and the identification information in each group of addresses to be processed, and the relative position relationship corresponding to the N groups of addresses to be processed is at least partially different.

Unlike the doping operation, the third request message has no area carrying the identification information alone, which has been doped with the address. The dedoping operation is to remove the N groups of identification information from the N groups of addresses to be processed according to a preset arrangement mode, so as to obtain N groups of data addresses.

For example, when the third request message is a RWD message, the 8 sets of pending addresses are:

Group0{vir_address[7:0]}＝{address[11:9],tag[1],address[8:6],tag[0]}；

Group3{vir_addr[31:24]}＝{tag[7],address[29:27],tag[6],address[26:24]}；

Group4{vir_addr[39:32]}＝{address[35:30],tag[9:8]}；

Group5{vir_addr[47:40]}＝{address[41:37],tag[11:10],address[36]}；

Group6{vir_addr[55:48]}＝{address[47:44],tag[13:12],address[43:42]}；

Group7{vir_addr[63:56]}＝{2’b00,address[51],tag[15:14],address[50:48]}。

Removing default values and identification information, and independently extracting data addresses to obtain:

Address[51:6]＝{vir_addr[61],vir_addr[58:56],vir_addr[55:52],vir_addr[49:48],vir_addr[47:43],vir_addr[40],vir_addr[39:34]vir_addr[30:28],vir_addr[26:24],vir_addr[23],vir_addr[21:19],vir_addr[17:16],vir_addr[15:14],vir_addr[12:10],vir_addr[8],vir_addr[7:5],vir_addr[3:1]}.

For another example, when the third Request message is an H2D Request message, the 8 sets of pending addresses are:

Group0{vir_addr[7:0]}＝{address[11:9],UQID[1],address[8:6],UQID[0]}；

Group3{vir_addr[31:24]}＝{UQID[7],address[29:27],UQID[6],address[26:24]}；

Group4{vir_addr[39:32]}＝{address[35:30],UQID[9:8]}；

Group5{vir_addr[47:40]}＝{address[41:37],UQID[11:10],address[36]}；

Group6{vir_addr[55:48]}＝{address[49:42]}；

Group7{vir_addr[63:56]}＝{4‘b000，address[51:50]}。

Address[51:6]＝{vir_addr[58:56],vir_addr[55:48],vir_addr[47:43],vir_addr[40],vir_addr[39:34],vir_addr[30:28],vir_addr[26:24],vir_addr[23],vir_addr[21:19],vir_addr[17:16],vir_addr[15:14],vir_addr[12:10],vir_addr[8],vir_addr[7:5],vir_addr[3:1]}.

optionally, when the address descrambling operation includes a reverse switching operation, performing the address descrambling operation for the address packet to be processed, including: acquiring a first pseudo-random number; and inverting the first pseudo-random number, and respectively controlling the switching modes of the N switch arrays by utilizing the inversion result of the first pseudo-random number, so that the N switch arrays respectively perform position reverse exchange in the N groups of addresses to be processed according to the preset length.

The reverse exchange operation corresponds to the exchange operation above, for example, a group of addresses to be processed is "ahbdfecg", and according to a preset length of 1 bit, after the positions in the group are exchanged reversely, an "abcdefg" is obtained, and the "abcdefg" is the state before the exchange operation is performed. The first pseudo random number in this embodiment is the same as the first pseudo random number in the above, so that the exchange operation and the reverse exchange operation can be guaranteed to correspond. After the first pseudo-random number is obtained, it is inverted to obtain the control sequence for the reverse switching operation. The inversion of the first pseudo-random number in this embodiment is related to the structure of the switch array, for example, may be packet inversion, for example, the first pseudo-random number is "0010,1100,1011,0100,0101", the first pseudo-random number is divided into 5 groups, each group controls 4 switches, and there are 5 layers of switches, and the inverted first pseudo-random number is "0101,0100,1011,1100,0010".

Optionally, when the address descrambling operation includes a reverse order adjustment operation, performing the address descrambling operation for the address packet to be processed includes: acquiring a second pseudo-random number; and taking the second pseudo-random number as a control sequence, and reversely adjusting the grouping sequence of N groups of addresses to be processed according to a preset adjustment rule of the control sequence and the grouping sequence.

In this embodiment, the second pseudorandom number has a length smaller than that of the first pseudorandom number, and may be acquired alone, or after the first pseudorandom number is acquired, a part of the digits may be selected as the second pseudorandom number from the first pseudorandom number. For example, bits 3, 7, and 17 of the first pseudorandom number are selected as the second pseudorandom number. The manner of separately obtaining the second pseudo random number may refer to the manner of obtaining the first pseudo random number, which is not described herein.

The preset adjustment rule in this embodiment may indicate a sequential adjustment manner of N groups of addresses to be processed, such as a reverse sequential adjustment manner including forward movement, backward movement, position exchange, and the like. For example, group1, group2, … …, group7, group0 of groups 0 to 7 are back-shifted to reverse the adjustment to obtain the original order Group0, group1, … …, group7.

Optionally, when the default value is included in the N groups of addresses to be processed, the method further includes: and removing the default value from the N groups of addresses to be processed to obtain N groups of data addresses. The default values are typically filled in the highest or lowest bits of each set of addresses to be processed, and can be easily removed.

Optionally, when the address descrambling operation includes at least two operations of a de-doping operation, a reverse switching operation, and a reverse order adjustment operation, the address descrambling operation is performed in an order in which the reverse order adjustment, the reverse switching operation, and the de-doping operation are sequentially performed.

In the present embodiment, the order of the address descrambling operations is related to the order of the address scrambling operations, which needs to be completely opposite to the order of the address scrambling operations. For example, when the order of the address scrambling operation is to sequentially perform the doping operation, the switching operation, and the order adjustment operation, the order of the address descrambling operation is to sequentially reverse the order adjustment operation, the reverse switching operation, and the de-doping operation.

Step S203 is executed to send a fourth request message containing the data address to the processing unit, where the fourth request message corresponds to the third request message.

After performing step S202, the data address may be obtained, thereby continuing to send a message containing the data address back to the processing unit. For example via a bus to a processing unit. The format of the fourth request message may be the same as the format of the first request message.

Fig. 3a shows a schematic diagram of a circuit for scrambling an address provided in accordance with an embodiment of the present disclosure.

As shown in fig. 3a, a circuit 300 for scrambling an address includes: a receiving module 310, an address scrambling module 320, and a transmitting module 330. The receiving module 310 is connected to the processing unit, for example directly to the processing unit or via a bus. The address scrambling module 320 is connected to the receiving module 310 and the transmitting module 330. The transmission module 330 is connected to the link layer. The circuit 300 in this embodiment is disposed in the transaction layer, and the distance between the transaction layer and the physical layer is further than the link layer, so that the likelihood of an attacker analyzing the acquired address is further reduced.

The receiving module 310 is configured to receive a first request message from the processing unit, wherein the first request message comprises a data address.

The address scrambling module 320 is configured to perform an address scrambling operation on the address packet to be processed to obtain a scrambled address, where the length of the scrambled address is greater than or equal to the length of the data address, and the address to be processed is the data address or an intermediate address during the address scrambling operation.

The sending module 330 is configured to send a second request message containing the scrambling address to the link layer, where the second request message corresponds to the first request message and the second request message is a transaction layer packet.

Optionally, the address scrambling module 320 includes: a doping unit 321 configured to perform doping operation on the address to be processed according to the identification information in the first request message;

a switching unit 322 configured to perform a pseudo-random switching operation on the address to be processed according to a predetermined length according to the pseudo-random number characteristic; and

The sequence adjustment unit 323 is configured to perform a pseudo random sequence adjustment operation on the packet sequence of the addresses to be processed according to the pseudo random number characteristic.

In this embodiment, the address scrambling operation includes at least one of a doping operation, a switching operation, and a sequence adjustment operation.

The connection inside the address scrambling module 320 is not shown in fig. 3a, since there may be various ways of connecting inside the address scrambling module 320. When the doping unit 321, the switching unit 322 and the sequence adjustment unit 323 are all enabled, there are 6 connection modes, including: (1) The device comprises a receiving module 310, a doping unit 321, a switching unit 322, a sequence adjusting unit 323 and a transmitting module 330; (2) The device comprises a receiving module 310, a doping unit 321, a sequence adjusting unit 323, a switching unit 322 and a transmitting module 330; (3) The device comprises a receiving module 310, a switching unit 322, a doping unit 321, a sequence adjusting unit 323 and a transmitting module 330; (4) The device comprises a receiving module 310, a switching unit 322, a sequence adjusting unit 323, a doping unit 321 and a transmitting module 330; (5) The receiving module 310, the sequence adjusting unit 323, the doping unit 321, the exchanging unit 322 and the transmitting module 330; (6) The receiving module 310, the sequence adjusting unit 323, the exchanging unit 322, the doping unit 321 and the transmitting module 330.

When the doping unit 321 and the switching unit 322 are enabled, there are 2 connection modes, that is, (1) the receiving module 310→the doping unit 321→the switching unit 322→the transmitting module 330; (2) The receiving module 310, the switching unit 322, the doping unit 321 and the transmitting module 330. Similarly, there are 2 connection modes each when the doping unit 321 and the sequence adjustment unit 323 are enabled, or when the switching unit 322 and the sequence adjustment unit 323 are enabled. When only one of the doping unit 321, the switching unit 322, and the sequence adjusting unit 323 is enabled, then the receiving module 310 is connected to the enabled unit and to the transmitting module 330.

Fig. 3b shows a schematic diagram of a circuit for scrambling an address provided in accordance with an embodiment of the present disclosure.

As shown in fig. 3b, the circuit 300' for scrambling an address includes a receiving module 310, an address scrambling module 320, and a transmitting module 330. The receiving module 310, the address scrambling module 320 and the transmitting module 330 are the same as those in fig. 3a, and are not described here again. The circuit 300' for scrambling an address further includes: the detection module 340 is connected to the receiving module 310 and the address scrambling module 320, and is configured to determine, according to the configuration information in the first request message, whether the address scrambling is enabled and the enabled units in the address scrambling module 320, and enable at least one unit in the address scrambling module 320 when determining that the address scrambling is enabled.

For example, the detection module 340 may be connected between the reception module 310 and the address scrambling module 320, and the address scrambling module 320 may enable corresponding units, such as the switching unit 322 and the order adjustment unit 323, according to an instruction of the detection module. In yet another implementation, the detection module may be a module inside the address scrambling module 320, in which case the detection module is connected to the doping unit 321, the switching unit 322, and the sequence adjustment unit 323, and enables the corresponding units according to the detection result.

Optionally, the detection module 340 is further configured to disable the address scrambling module upon determining that address scrambling is disabled. The detection module may disable the entire address scrambling module, so that the received first request message is directly sent to the link layer after being packaged into a transaction layer packet without undergoing address scrambling.

Optionally, when at least two units of the doping unit, the switching unit and the sequential adjustment unit are enabled, the address scrambling module is configured to perform an address scrambling operation on the data address in the order of the doping unit, the switching unit and the sequential adjustment unit.

The doping unit 321, the switching unit 322, and the sequence adjustment unit 323 in the present embodiment correspondingly perform doping operation, switching operation, and sequence adjustment operation, and the specific implementation manner may be referred to the above description and will not be repeated herein. Various ways of connecting the units within the address scrambling module 320 have been described above, with the order of the address scrambling operations being fixed in the event that the connection is fixed.

Optionally, the address scrambling module 320 further includes: the grouping unit 324 is connected to the receiving module 310, the doping unit 321, the switching unit 322 and the sequence adjusting unit 323, and is configured to divide the data address into N groups according to the position of the data address in the first request message before performing the address scrambling operation on the address packet to be processed, where N is an integer greater than or equal to 2.

In this embodiment, the grouping unit 324 may be connected to the receiving module 310 and further connected to the doping unit 321, the switching unit 322 and the sequence adjusting unit 323, and the grouping unit 324 selectively sends the data address after grouping to one of the doping unit 321, the switching unit 322 and the sequence adjusting unit 323 according to the enabled units and the connection modes.

Optionally, the doping unit 321 is configured to: dividing the identification information into N groups according to the position of the identification information in the first request message; doping the N groups of identification information with the N groups of addresses to be processed respectively according to a preset arrangement mode to obtain N groups of virtual addresses, wherein the preset arrangement mode indicates the relative position relationship between the addresses to be processed and the identification information in each group of virtual addresses, and the relative position relationship corresponding to the N groups of virtual addresses is at least partially different.

In this embodiment, the doping unit 321 performs doping on the identification information and the address to be processed according to the description of the method embodiment described above, which is not described herein again.

Optionally, the switching unit 322 is configured to: acquiring a first pseudo-random number; and respectively controlling the switching modes of the N switch arrays by using the first pseudo-random numbers so that the N switch arrays respectively exchange positions in the N groups of addresses to be processed according to preset lengths.

Fig. 4 shows a schematic diagram of a multi-control switch provided in accordance with an embodiment of the present disclosure.

Fig. 4 shows two connection states of the multi-control switch, namely a through state and an intersecting state, and the through state and the intersecting state are both in an on state, and the switch is not discussed in this embodiment.

The multi-control switch 401 and the multi-control switch 402 each have 4 ports, port a and port b being input ports and port c and port d being output ports. The multi-control switch 401 is in a pass-through state, port a is connected to port c and port b is connected to port d. The multi-control switch 420 is in a crossed state, port a being connected to port d and port b being connected to port c. The multi-control switch is switched between a through state and an intersecting state, for example, the through state and the intersecting state are indicated by "0" and "1", when the control indication of the multi-control switch is "0", the multi-control switch is controlled to be in the through state, and when the control indication is "1", the multi-control switch is controlled to be in the intersecting state.

Alternatively, instead of the multi-control switch shown in fig. 4, other types of switches may be used to connect and switch between the pass-through state and the switch state. For example, the function of the multi-control switch may be implemented by using 2 single pole double throw switches, the input ports of the 2 single pole double throw switches are the port a and the port b, respectively, and the 2 single pole double throw switches are connected to the port c and the port d, but the control manner of the 2 single pole double throw switches is opposite, and the "0" may be used to control one single pole double throw switch to be connected to the port c while controlling the other single pole double throw switch to be connected to the port d, so that the function of the multi-control switch as shown in fig. 4 may be implemented.

Fig. 5 shows a schematic diagram of a switch array provided in accordance with an embodiment of the present disclosure.

As shown in fig. 5, the switch array 500 includes 20 switches in total of 4 rows by 5 columns, and the switches that make up the switch array 500 may be multi-controlled switches as shown in fig. 4.

The switch array 500 includes 5 columns of switches, each column including 4 switches, having 8 input ports and 8 input ports, which can process addresses to be processed that are 8 bits in length. The "columns" in the switch array 500 may also be referred to as "layers," i.e., there are 5 layers of switches.

In fig. 5, L0, L1, L2, L3, and L4 are switching coefficients, and each control a column of switches. The switching coefficient may be derived from a first pseudo-random number. For example, the length of the first pseudo random number is 20 bits, and the first pseudo random number is divided into 5 groups, i.e., L0 to L4. For example, the first pseudo random number is "01101100101101000101", the switching coefficient L0 is "0101", L1 is "1100", L2 is "1011", L3 is "0100", and L4 is "0101". In this example, the "0" control switch assumes a cross state and the "1" control switch assumes a pass-through state. It should be noted that the switching coefficient only controls the conduction mode inside the switch, such as pass-through or cross-over, and the switching coefficient does not affect the connection mode between the switches. Fig. 5 shows only one possible switch array and connection between switches, and there are many ways of connecting switches in each column, which will not be listed here. Even if all switches in the switch array 500 are in a pass-through or cross-over state, the connection of each column of switches in the switch array 500 is itself already capable of switching the input address.

Referring to the switch array 500 and the conduction mode of each switch shown in fig. 5, assuming that the input address is "abcdefgh", the switching mode of each column of switches is as follows:

abcdefgh is routed through L0 to achieve bacdefhg; bacdefhg is routed through L1 to obtain bcehdagf; bcehdagf is routed through L2 to yield behcdgaf; behcdgaf is routed through L3 to obtain hbecadfg; hbecadfg is routed through L4 to yield ahbdfecg.

The switch array 500 shown in fig. 5 is only capable of switching a set of addresses to be processed having a length of 8 bits, and requires N switch arrays when there are N sets of addresses to be processed. For example, if there are 8 sets of addresses to be processed, 8 switch arrays are required, all of the 8 switch arrays may employ switch array 500, and all of the 8 switch arrays may employ different switch arrays. Accordingly, the N switch arrays may each use the same first pseudo-random number as the switch coefficient, or may generate N first pseudo-random numbers for the N switch arrays, respectively.

In one implementation, the same switch array may be multiplexed for N groups of addresses to be processed, e.g., N groups of addresses to be processed are input into the switch array in time order, and the addresses exchanged in N groups may be obtained. The method and the device can reduce the number of the required switch arrays and save hardware resources.

Fig. 6a shows a schematic diagram providing a linear feedback shift register according to an embodiment of the present disclosure.

In fig. 6a, the linear feedback shift register 600 is a 6 tap 20 bit linear feedback shift register, where the tap positions may be set as desired, without limitation. The linear feedback shift register 600 outputs a pseudo-random number of 20 bits in length. Reg [ m ] in fig. 6a represents registers, m equals 0-19, and each register in fig. 6a may be a register composed of D flip-flops. The input to the linear feedback shift register 600 is a CLOCK signal CLOCK, and the rising or falling edge of a CLOCK cycle may trigger the generation of a new pseudo-random number.

Optionally, the switching unit comprises: a linear feedback shift register configured to generate a first pseudo-random number; and N switch arrays, wherein each switch array comprises a plurality of multi-control switches, and each switch array is configured to control the on or off of the plurality of multi-control switches according to a switching mode corresponding to the first pseudo-random number so as to enable a group of addresses to be processed, which are input into one switch array, to be subjected to position exchange in the transmission process of one switch array.

For example, the switching unit 322 may include a linear feedback shift register 600 and N switch arrays 500, and the first pseudo-random number outputted by the linear feedback shift register 600 controls the conduction mode of the switches in the N switch arrays.

In this embodiment, the switching unit includes a linear feedback shift register whose output pseudo-random number length depends on the number of switches in the switch array. For example, if the switch array includes 20 switches, a pseudorandom number of 20 bits in length is required, and if the switch array includes 16 switches, a pseudorandom number of 16 bits in length is required.

Optionally, the linear feedback shift register is configured to: generating a pseudo-random number in response to receiving the clock signal, wherein each clock cycle in the clock signal corresponds to one of the pseudo-random numbers, and not generating the pseudo-random number in response to ceasing to receive the clock signal; and taking the pseudo random number corresponding to the last clock period in the received clock signal as a first pseudo random number.

In this embodiment, the linear feedback shift register is triggered by the clock signal, so that when no clock signal is input, the generation of a new pseudo random number is stopped, and the properties of the register can store the last generated pseudo random number, so that when the first pseudo random number is acquired, the pseudo random number can always be acquired as the first pseudo random number.

Optionally, the exchange unit further comprises: and the clock gating is connected with the linear feedback shift register and is configured to control the input of a clock signal of the linear feedback shift register.

Fig. 6b shows a schematic diagram of a switching unit provided according to an embodiment of the present disclosure.

In fig. 6b, the switching unit 610 comprises a linear feedback shift register 611 and N switch arrays 612 and clock gating 613. The clock gating 613 is connected to a linear feedback shift register 611, and the linear feedback shift register 611 is connected to N switch arrays 612.

The input of clock gating 613 is a clock signal, and clock gating 613 controls the clock signal input to linear feedback shift register 611. The linear feedback shift register 611 generates a pseudo-random number according to a clock signal, and outputs the pseudo-random number to the N switch arrays 612 as a control signal, and the N switch arrays 612 control on and off of switches inside each switch array 612 according to a switching manner corresponding to the pseudo-random number. For example, the linear feedback shift register 611 may be the linear feedback shift register 600 shown in fig. 6a and the switch array 612 may be the switch array 500 shown in fig. 5.

For example, the switching unit 322 may be implemented using the switching unit 610 of fig. 6 b.

In this embodiment, clock gating may be added, which is connected between the clock signal and the linear feedback shift register, for controlling the on or off of the clock signal. Setting clock gating can further increase the randomness of switching operation, thereby improving the security of data transmission.

Optionally, the order adjustment unit is configured to: acquiring a second pseudo-random number; and taking the second pseudo-random number as a control sequence, and adjusting the grouping sequence of N groups of addresses to be processed according to a preset adjustment rule of the control sequence and the grouping sequence.

In this embodiment, the adjustment manner of the address packet sequence is simpler than the switching operation, and several digits in the first pseudo random number can be selected to form the second pseudo random number. For example, 3-bit data of 3, 9, and 17 taps shown in fig. 6a is selected as the second pseudo random number.

The control sequence may be set to trngctl= { reg [3], reg [9], reg [17] }. The order adjustment may be performed according to the following rule:

1) Trng_ctl [2:0] =1, shift left by 1bit per Group cycle; i.e. Group0 becomes Group1, … …, group6 becomes Group7;

2) Trng_ctl [2:0] =2, shift left by 2 bits per Group cycle; i.e. Group0 becomes Group2, … …, group6 becomes Group0;

3) Trngctl [2:0] =3, shift left by 3 bits per Group cycle; i.e. Group0 becomes Group3, … …, group6 becomes Group1;

4) Trngctl [2:0] =4, exchanging adjacent groups, i.e. Group0 with Group1, group2 with Group3, group4 with Group5, and Group6 with Group 7.

Optionally, the doping unit is further configured to fill in the N groups of virtual addresses with a default value when the lengths of the N groups of addresses to be processed are different, so that the lengths of the N groups of virtual addresses are the same.

In this embodiment, in order to facilitate implementation of the address scrambling operation, the addresses to be processed may be filled such that the length of each group of addresses to be processed is the same. In addition to the doping unit, both the switching unit and the ordering unit may be configured to fill in N sets of addresses to be processed, the default value typically being "0" or "1". For example, if the length of the data address cannot be equally divided into N groups when only the switching unit is enabled, the filling of the default value may be first performed, and the same address length may make the switching operation easier to implement than if the address lengths of each group are different.

Fig. 7a shows a schematic diagram of a circuit for descrambling an address provided in accordance with an embodiment of the present disclosure.

As shown in fig. 7a, the circuit 700a for descrambling an address includes a receiving module 710, an address descrambling module 720 and a transmitting module 730. The receiving module 710 is connected to the link layer. The address scrambling module 720 is connected to the receiving module 710 and the transmitting module 730. The transmission module 730 is connected to the processing unit, for example directly to the processing unit or via a bus.

The receiving module 710 is configured to receive a third request message from the link layer, wherein the third request message is a transaction layer packet and includes a scrambling address.

The address descrambling module 720 is configured to perform an address descrambling operation on the address packet to be processed when the address descrambling is enabled, so as to obtain a data address, where the length of the data address is less than or equal to the length of the scrambling address, and the address to be processed is a scrambling address or an intermediate address during the address descrambling operation.

And a sending module 730, connected to the address descrambling module, for sending a fourth request message containing the data address to the processing unit, where the fourth request message corresponds to the third request message.

Optionally, the address descrambling module 720 comprises the following units:

a dedoping unit 721 configured to perform a dedoping operation on the address to be processed according to the identification information in the third request message;

a reverse exchange unit 722 configured to perform a pseudo random reverse exchange operation on the address to be processed according to a predetermined length according to the pseudo random number characteristic; and

The reverse order adjustment unit 733 is configured to perform a pseudo random reverse order adjustment operation on the packet order of the addresses to be processed according to the pseudo random number characteristic.

The address descrambling operation in this embodiment includes at least one of a dedoping operation, a reverse switching operation, and a reverse order adjustment operation.

Fig. 7a does not show the connection relationship inside the address descrambling module 720, similar to the address scrambling module 320, and there may be various connection manners in the address descrambling module 720, and the specific connection manner is opposite to that of the address scrambling module 320, and no expansion is performed here.

Optionally, the circuit 700b for descrambling an address further comprises: the detection module 740 is connected to the receiving module 710 and the address descrambling module 720, and is configured to determine, according to the configuration information in the third request message, whether the address descrambling is enabled and the enabled units in the address descrambling module, and enable at least one unit in the address descrambling module when determining that the address descrambling is enabled.

For example, the detection module 740 may be connected between the reception module 710 and the address descrambling module 720, and the address descrambling module 720 may enable a corresponding unit, such as the reverse switching unit 722, according to an instruction of the detection module 740.

Fig. 7b shows a schematic diagram of a circuit for descrambling an address provided in accordance with an embodiment of the present disclosure.

As shown in fig. 7b, the circuit 700b for descrambling an address includes a receiving module 710, an address descrambling module 720, a transmitting module 730 and a detecting module 740. The receiving module 710 and the transmitting module 730 are the same as those shown in fig. 7a, and will not be described again.

The detection module 740 is connected between the receiving module 710 and the address scrambling module 720, and determines whether the address descrambling is enabled and the enabled units in the address descrambling module 720 according to the configuration information in the third request message, and when the address descrambling is enabled, indicates to the address descrambling module 720 that the address descrambling and the corresponding enabled units are enabled.

In yet another implementation, the detection module may be implemented as a module inside the address descrambling module, in which case the detection module is connected to the dedoping unit, the reverse switching unit and the reverse order adjustment unit, and enables the corresponding units according to the detection result.

Fig. 7c shows a schematic diagram of a circuit for descrambling an address provided in accordance with an embodiment of the present disclosure.

As shown in fig. 7b, the circuit 700c for descrambling an address includes a receiving module 710, an address descrambling module 720 and a transmitting module 730. The receiving module 710 and the transmitting module 730 are the same as those shown in fig. 7a, and will not be described again.

The detection module 724 is connected to the dedoping unit 321, the reverse switching unit 322 and the reverse order adjustment unit 323, and enables the corresponding units according to the detection result.

Optionally, the detection module is further configured to disable the address descrambling module upon determining that address descrambling is disabled. The detection module may disable the entire address descrambling module such that the received third request message is unpacked and sent directly to the processing unit without experiencing address descrambling.

Optionally, when at least two units of the de-doping unit, the reverse switching unit and the reverse order adjustment unit are enabled, the address descrambling module is configured to perform an address descrambling operation on the scrambled address in the order of the reverse order adjustment unit, the reverse switching unit and the de-doping unit.

Optionally, the address descrambling module further comprises: and the grouping unit is connected with the receiving module, the dedoping unit, the reverse switching unit and the reverse sequence adjusting unit and is configured to divide the scrambling address into N groups according to the position of the scrambling address in the third request message, wherein N is an integer greater than or equal to 2. For example, as shown in fig. 7b and 7c, the grouping unit 724 is connected to the receiving module 710, the dedoping unit 721, the reverse switching unit 722, and the reverse order adjustment unit 723.

In this embodiment, the grouping unit 724 may be connected to the receiving module 710 and further connected to the doping unit 721, the switching unit 722 and the sequence adjusting unit 723, and selectively sends the data address after grouping to one of the doping unit 721, the switching unit 722 and the sequence adjusting unit 723 according to the enabled units and the connection modes.

Optionally, the undoped unit is configured to: according to a preset arrangement mode, removing N groups of identification information from N groups of addresses to be processed respectively to obtain N groups of data addresses; the preset arrangement mode indicates the relative position relationship between the data addresses and the identification information in each group of addresses to be processed, and the relative position relationship corresponding to the N groups of addresses to be processed is at least partially different. In this embodiment, the manner in which the undoped unit 721 performs the address undoped operation can be referred to the description of the method embodiment, and the description thereof is omitted herein

Optionally, the reverse switching unit is configured to: acquiring a first pseudo-random number; and inverting the first pseudo-random number, and respectively controlling the switching modes of the N switch arrays by utilizing the inversion result of the first pseudo-random number, so that the N switch arrays respectively perform position reverse exchange in the N groups of addresses to be processed according to the preset length.

Fig. 8 shows a schematic diagram of yet another switch array provided in accordance with an embodiment of the present disclosure.

The manner of connection between the switches in the switch array 800 is the same as the manner of connection between the switches in the switch array 500, but the manner of conduction of the switches is different from that shown in the switch array 500. In this example, the first pseudorandom number is "01101100101101000101", and the first pseudorandom number is subjected to packet inversion to obtain a switching coefficient L0 of "0101", L1 of "0100", L2 of "1011", L3 of "1100", and L4 of "0110". The address of the input switch array 800 is "ahbdfecg", and the address after the reverse switching is "abcdefgh".

Optionally, the reverse order adjustment unit is configured to: acquiring a second pseudo-random number; and taking the second pseudo-random number as a control sequence, and reversely adjusting the grouping sequence of N groups of addresses to be processed according to a preset adjustment rule of the control sequence and the grouping sequence.

Optionally, the undoped unit is further configured to: and when the N groups of addresses to be processed comprise default values, removing the default values from the N groups of addresses to be processed to obtain N groups of data addresses.

Fig. 9 shows a schematic diagram of a reverse switching unit provided according to an embodiment of the present disclosure.

In fig. 9, the reverse switching unit 910 includes a linear feedback shift register 911 and N switch arrays 912 and clock gating 913. The clock gating 913 is connected to the linear feedback shift register 911, and the linear feedback shift register 911 is connected to the N switch arrays 912.

The input of clock gating 913 is a clock signal, and clock gating 913 controls the clock signal input to linear feedback shift register 911. The linear feedback shift register 911 generates a pseudo-random number according to a clock signal, and outputs the pseudo-random number to the N switch arrays 912 as a control signal, and the N switch arrays 912 control on and off of the switches inside each switch array 912 according to a switching pattern corresponding to the pseudo-random number. For example, the linear feedback shift register 911 may be the linear feedback shift register 600 shown in fig. 6a and the switch array 912 may be the switch array 800 shown in fig. 8.

The linear feedback shift register in this embodiment needs to be adopted to be consistent with the linear feedback shift register in the switching unit so that the generated random numbers are kept consistent.

Optionally, at least one embodiment of the present disclosure provides an electronic device, including a processor and a memory, the memory having stored therein computer executable instructions that are executed by the processor to implement a method as in any of the first method embodiment and/or the second method embodiment described above.

Fig. 10 is a schematic structural diagram of an electronic device according to at least one embodiment of the present disclosure.

As shown in fig. 10, the electronic device 1000 includes a processor 1001 and a memory 1002, the memory 1002 storing computer executable instructions, which when executed by the processor 1001, implement the method in the above-described embodiments.

The terminal devices in the embodiments of the present disclosure may include, but are not limited to, mobile terminals such as mobile phones, notebook computers, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), in-vehicle terminals (e.g., in-vehicle navigation terminals), and the like, and stationary terminals such as digital TVs, desktop computers, and the like. The electronic device shown in fig. 10 is merely an example and should not be construed to limit the functionality and scope of use of the disclosed embodiments.

For example, according to embodiments of the present disclosure, the processes described above with reference to flowcharts may be implemented as computer software programs. For example, embodiments of the present disclosure include a computer program product comprising a computer program embodied on a non-transitory computer readable medium, the computer program comprising program code for performing the method shown in the flow chart.

Optionally, at least one embodiment of the present disclosure provides a computer-readable storage medium having instructions stored thereon, wherein the instructions are loaded and executed by a processor to implement a method as in any of the first method embodiment and/or the second method embodiment described above.

It should be noted that the computer readable medium described in the present disclosure may be a computer readable signal medium or a computer readable storage medium, or any combination of the two. The computer readable storage medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples of the computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In an embodiment of the present disclosure, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. Whereas in embodiments of the present disclosure, the computer-readable signal medium may comprise a data signal propagated in baseband or as part of a carrier wave, with computer-readable program code embodied therein. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination of the foregoing. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to: electrical wires, fiber optic cables, RF (radio frequency), and the like, or any suitable combination of the foregoing.

The computer readable medium may be contained in the electronic device; or may exist alone without being incorporated into the electronic device.

At least one embodiment of the present disclosure also provides a chip, a circuit for scrambling an address as in any of the above embodiments, and/or a circuit for descrambling an address as in any of the above embodiments.

For example, the chip may include circuitry to scramble the address, circuitry to descramble the address, or both. For example, a controller in memory may include only circuitry to descramble an address.

At least one embodiment of the present disclosure provides an electronic device, including the chip described in the foregoing embodiment. The electronic device may be any device having a computing function, such as a computer, a server, a smart phone, a tablet computer, etc., to which embodiments of the present disclosure are not limited.

The basic principles of the present application have been described above in connection with specific embodiments, but it should be noted that the advantages, benefits, effects, etc. mentioned in the present application are merely examples and not intended to be limiting, and these advantages, benefits, effects, etc. are not to be construed as necessarily possessed by the various embodiments of the application. Furthermore, the specific details disclosed herein are for purposes of illustration and understanding only, and are not intended to be limiting, as the application is not necessarily limited to practice with the above described specific details.

It is noted that the step flow diagrams in the present application and the above method descriptions are merely illustrative examples and are not intended to require or imply that the steps of the various embodiments must be performed in the order presented, and that certain steps may be performed in parallel, independently of each other, or in any other suitable order. In addition, words such as "next," "then," "next," etc. are not intended to limit the order of the steps; these words are simply used to guide the reader through the description of these methods.

The block diagrams of the devices, apparatuses, devices, systems referred to in the present application are only illustrative examples and are not intended to require or imply that the connections, arrangements, configurations must be made in the manner shown in the block diagrams. It is also noted that in the apparatus and method of the present application, the components or steps may be disassembled and/or assembled. Such decomposition and/or recombination should be considered as equivalent aspects of the present application.

The following points need to be described: (1) The drawings of the embodiments of the present disclosure relate only to the structures to which the embodiments of the present disclosure relate, and reference may be made to the general design for other structures. (2) The embodiments of the present disclosure and features in the embodiments may be combined with each other to arrive at a new embodiment without conflict. The foregoing is merely specific embodiments of the disclosure, but the scope of the disclosure is not limited thereto, and the scope of the disclosure should be determined by the claims.

Claims

1. A method of scrambling an address, comprising:

receiving a first request message from a processing unit, wherein the first request message contains a data address;

Performing address scrambling operation on an address packet to be processed to obtain a scrambling address, wherein the length of the scrambling address is greater than or equal to that of the data address, and the address to be processed is the data address or an intermediate address in the address scrambling operation period;

And sending a second request message containing the scrambling address to a link layer, wherein the second request message corresponds to the first request message and is a transaction layer data packet.

2. The method of claim 1, wherein the address scrambling operation comprises at least one of:

doping the address to be processed according to the identification information in the first request message;

according to the pseudo-random number characteristics, carrying out pseudo-random exchange operation on the address to be processed according to a preset length; and

And according to the pseudo-random number characteristic, carrying out pseudo-random sequence adjustment operation on the grouping sequence of the addresses to be processed.

3. The method of claim 1, wherein prior to address scrambling for the data address packet, the method further comprises:

and determining whether the address scrambling is started or not and the operation included when the address scrambling is started according to the configuration information in the first request message.

4. The method of claim 1, wherein the address scrambling operation is performed in an order in which the doping operation, the swapping operation, and the sequence adjustment operation are sequentially performed when the address scrambling operation includes at least two operations of the doping operation, the swapping operation, and the sequence adjustment operation.

5. The method of claim 2, wherein prior to performing an address scrambling operation on the pending address packet, the method further comprises:

dividing the data address into N groups according to the position of the data address in the first request message, wherein N is an integer greater than or equal to 2.

6. The method of claim 5, wherein, when the address scrambling operation includes the doping operation, the performing an address scrambling operation on the pending address packet to obtain a scrambled address includes:

Dividing the identification information into N groups according to the position of the identification information in the first request message;

Doping N groups of identification information with N groups of addresses to be processed respectively according to a preset arrangement mode to obtain N groups of virtual addresses, wherein the preset arrangement mode indicates the relative position relationship between the addresses to be processed in each group of virtual addresses and the identification information, and the relative position relationship corresponding to the N groups of virtual addresses is at least partially different.

7. The method of claim 5, wherein, when the address scrambling operation comprises the switching operation, the performing an address scrambling operation on the pending address packet comprises:

Acquiring a first pseudo-random number;

And respectively controlling the switching modes of the N switch arrays by using the first pseudo-random numbers so that the N switch arrays respectively exchange positions in the N groups of addresses to be processed according to the preset length.

8. The method of any of claims 5-7, wherein, when the address scrambling operation comprises the order adjustment operation, the performing an address scrambling operation on the pending address packet comprises:

acquiring a second pseudo-random number;

and taking the second pseudo-random number as a control sequence, and adjusting the grouping sequence of N groups of addresses to be processed according to a preset adjustment rule of the control sequence and the grouping sequence.

9. The method of claim 6, wherein when the N groups of addresses to be processed are different in length, filling the N groups of virtual addresses with a default value such that the N groups of virtual addresses are the same in length.

10. The method of claim 7, wherein the obtaining a first pseudo-random number comprises:

generating a pseudo-random number in response to receiving a clock signal, wherein each clock cycle in the clock signal corresponds to a pseudo-random number, and not generating the pseudo-random number in response to ceasing to receive the clock signal;

And acquiring a pseudo random number corresponding to the last clock period in the received clock signal as the first pseudo random number.

11. A method of descrambling an address, comprising:

receiving a third request message from a link layer, wherein the third request message is a transaction layer data packet and includes a scrambling address;

Address descrambling operation is carried out on the address to be processed packet so as to obtain a data address, wherein the length of the data address is smaller than or equal to that of the scrambling address, and the address to be processed is the scrambling address or an intermediate address in the address descrambling operation period;

and sending a fourth request message containing the data address to a processing unit, wherein the fourth request message corresponds to the third request message.

12. The method of claim 11, wherein the address descrambling operation comprises at least one of:

carrying out a dedoping operation on the address to be processed according to the identification information in the third request message;

According to the pseudo-random number characteristics, carrying out pseudo-random reverse exchange operation on the address to be processed according to a preset length; and

And according to the pseudo-random number characteristic, carrying out pseudo-random reverse order adjustment operation on the grouping order of the addresses to be processed.

13. The method of claim 11, wherein prior to performing an address descrambling operation for the pending address packet, the method further comprises:

And determining whether address descrambling is enabled or not and the operation included when the address descrambling is enabled according to the configuration information in the third request message.

14. The method of claim 12, wherein the address descrambling operation is performed in an order in which the reverse order adjustment, the reverse exchange operation, and the de-doping operation are sequentially performed when the address descrambling operation includes at least two operations of the de-doping operation, the reverse exchange operation, and the reverse order adjustment operation.

15. The method of claim 12, wherein prior to performing an address descrambling operation for the pending address packet, the method further comprises:

and dividing the scrambling address into N groups according to the position of the scrambling address in the third request message, wherein N is an integer greater than or equal to 2.

16. The method of claim 15, wherein, when the address descrambling operation comprises the de-doping operation, the performing an address descrambling operation for the pending address packet comprises:

According to a preset arrangement mode, removing N groups of identification information from N groups of addresses to be processed respectively to obtain N groups of data addresses;

The preset arrangement mode indicates the relative position relationship between the data addresses and the identification information in each group of addresses to be processed, and the relative position relationship corresponding to the N groups of addresses to be processed is at least partially different.

17. The method of claim 15, wherein the performing an address descrambling operation for the pending address packet when the address descrambling operation comprises the reverse switching operation comprises:

Acquiring a first pseudo-random number;

And inverting the first pseudo-random number, and respectively controlling the switching modes of N switch arrays by utilizing the inversion result of the first pseudo-random number, so that the N switch arrays respectively perform position reverse exchange in the N groups of addresses to be processed according to the preset length.

18. The method of any of claims 15-17, wherein, when the address descrambling operation comprises the reverse order adjustment operation, the performing an address descrambling operation for the pending address packet comprises:

acquiring a second pseudo-random number;

and taking the second pseudo-random number as a control sequence, and reversely adjusting the grouping sequence of N groups of addresses to be processed according to a preset adjustment rule of the control sequence and the grouping sequence.

19. The method of claim 16, wherein when a default value is included in the N sets of pending addresses, the method further comprises:

And removing the default value from the N groups of addresses to be processed to obtain N groups of data addresses.

20. The method of claim 17, wherein the obtaining a first pseudo-random number comprises:

21. A circuit for scrambling an address, comprising:

A receiving module configured to receive a first request message from a processing unit, wherein the first request message contains a data address;

The address scrambling module is connected with the receiving module and is configured to perform address scrambling operation on an address packet to be processed so as to obtain a scrambling address, the length of the scrambling address is greater than or equal to that of the data address, and the address to be processed is the data address or an intermediate address during the address scrambling operation;

and the sending module is connected with the address scrambling module and is configured to send a second request message containing the scrambling address to a link layer, wherein the second request message corresponds to the first request message and is a transaction layer data packet.

22. The circuit of claim 21, wherein the address scrambling module comprises:

the doping unit is configured to carry out doping operation on the address to be processed according to the identification information in the first request message;

The exchange unit is configured to perform pseudo-random exchange operation on the address to be processed according to the pseudo-random number characteristic and the preset length; and

A sequence adjustment unit configured to perform a pseudo-random sequence adjustment operation on the grouping sequence of the addresses to be processed according to the pseudo-random number characteristic;

wherein the address scrambling operation includes at least one of the doping operation, the swapping operation, and the order adjustment operation.

23. The circuit of claim 21, wherein the circuit further comprises:

And the detection module is connected with the receiving module and the address scrambling module, and is configured to determine whether address scrambling is started or not and the units started in the address scrambling module according to the configuration information in the first request message, and start at least one unit in the address scrambling module when determining that the address scrambling is started.

24. The circuit of claim 23, wherein the detection module is further configured to disable the address scrambling module upon determining that address scrambling is disabled.

25. The circuit of claim 22, wherein, when at least two of the doping unit, the switching unit, and the order adjustment unit are enabled, the address scrambling module is configured to perform the address scrambling operation on the data address in an order of the doping unit, the switching unit, and the order adjustment unit.

26. The circuit of claim 22, wherein the address scrambling module further comprises:

And the grouping unit is connected with the receiving module, the doping unit, the switching unit and the sequence adjusting unit and is configured to divide the data address into N groups according to the position of the data address in the first request message before performing address scrambling operation on the address grouping to be processed, wherein N is an integer greater than or equal to 2.

27. The circuit of claim 26, wherein the doping unit is configured to:

28. The circuit of claim 26, wherein the switching unit is configured to:

Acquiring a first pseudo-random number;

29. The circuit of claim 26, wherein the order adjustment unit is configured to:

acquiring a second pseudo-random number;

30. The circuit of claim 27, wherein the doping unit is further configured to fill the N sets of virtual addresses with a default value to make the lengths of the N sets of virtual addresses the same when the lengths of the N sets of pending addresses are different.

31. The circuit of claim 28, wherein the switching unit comprises:

a linear feedback shift register configured to generate the first pseudo-random number;

And N switch arrays, wherein each switch array comprises a plurality of multi-control switches, and each switch array is configured to control the on or off of the plurality of multi-control switches according to the switching mode corresponding to the first pseudo random number so as to enable a group of addresses to be processed, which are input into one switch array, to be subjected to position exchange in the transmission process of the one switch array.

32. The circuit of claim 31, wherein the linear feedback shift register is configured to:

And taking the pseudo random number corresponding to the last clock period in the received clock signal as the first pseudo random number.

33. The circuit of claim 32, wherein the switching unit further comprises:

And the clock gating is connected with the linear feedback shift register and is configured to control the input of a clock signal of the linear feedback shift register.

34. A circuit for descrambling an address, comprising:

A receiving module configured to receive a third request message from a link layer, wherein the third request message is a transaction layer packet and contains a scrambling address;

the address descrambling module is connected with the receiving module and is configured to perform address descrambling operation on an address packet to be processed so as to acquire a data address, the length of the data address is smaller than or equal to that of the scrambling address, and the address to be processed is the scrambling address or an intermediate address during the address descrambling operation;

And the sending module is connected with the address descrambling module and is used for sending a fourth request message containing the data address to the processing unit, and the fourth request message corresponds to the third request message.

35. The circuit of claim 34, wherein the address descrambling module comprises:

The dedoping unit is configured to carry out a dedoping operation on the address to be processed according to the identification information in the third request message;

The reverse exchange unit is configured to perform pseudo-random reverse exchange operation on the address to be processed according to the pseudo-random number characteristic and a preset length; and

A reverse order adjustment unit configured to perform a pseudo-random reverse order adjustment operation on the packet order of the addresses to be processed according to the pseudo-random number characteristic;

Wherein the address descrambling operation comprises at least one of the de-doping operation, the reverse switching operation and the reverse order adjustment operation.

36. The circuit of claim 34, wherein the circuit further comprises:

And the detection module is connected with the receiving module and the address descrambling module and is configured to determine whether address descrambling is started or not and the units started in the address descrambling module according to the configuration information in the third request message, and start at least one unit in the address descrambling module when determining that the address descrambling is started.

37. The circuit of claim 36, wherein the detection module is further configured to disable the address descrambling module upon determining that address descrambling is disabled.

38. The circuit of claim 35, wherein, when at least two of the de-doping unit, the reverse switching unit, and the reverse order adjustment unit are enabled, the address descrambling module is configured to perform the address descrambling operation on the scrambled address in the order of the reverse order adjustment unit, the reverse switching unit, and the de-doping unit.

39. The circuit of claim 36, wherein the address descrambling module further comprises:

And the grouping unit is connected with the receiving module, the dedoping unit, the reverse switching unit and the reverse sequence adjusting unit and is configured to divide the scrambling address into N groups according to the position of the scrambling address in the third request message, wherein N is an integer greater than or equal to 2.

40. The circuit of claim 39, wherein the undoped unit is configured to:

41. The circuit of claim 39, wherein the reverse switching unit is configured to:

Acquiring a first pseudo-random number;

42. The circuit of any one of claims 39-41, wherein the reverse order adjustment unit is configured to:

acquiring a second pseudo-random number;

43. The circuit of claim 40, wherein the undoped unit is further configured to:

And when the N groups of addresses to be processed comprise default values, removing the default values from the N groups of addresses to be processed to obtain N groups of data addresses.

44. The circuit of claim 41, wherein the linear feedback shift register is configured to:

45. The circuit of claim 3454, wherein the switching unit further comprises:

46. A chip, a circuit for scrambling an address as claimed in any of claims 22 to 33 and/or a circuit for descrambling an address as claimed in any of claims 34 to 45.

47. An electronic device comprising a chip as claimed in claim 46.