CN118116450A - Memory internal voltage testing system and method - Google Patents
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
- G11C2029/5004—Voltage
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The embodiment of the disclosure provides a system and a method for testing internal voltage of a memory, comprising the following steps: the device comprises a selection enabling signal output module, a voltage selection module, a voltage generation module and an output module, wherein the selection enabling signal output module outputs a first selection signal to the voltage selection module when receiving a test indication signal, and the test indication signal comprises a preset test voltage; the voltage generation module is used for determining a test voltage according to the working voltage of the memory and outputting the test voltage to the voltage selection module; the voltage selection module is used for selecting a target test voltage from the test voltages according to the first selection signal output by the selection enabling signal output module and outputting the target test voltage to the output module; the output module outputs the target test voltage to the comparison module under the action of the enabling signal; and the comparison module is used for determining whether the target test voltage generated by the memory meets the requirement according to the relation between the target test voltage and the preset test voltage, so as to realize the test of a plurality of test voltages generated by the memory.
Description
Technical Field
Embodiments of the present disclosure relate to the field of memory technology and related technology, and in particular, to a system and method for testing internal voltages of a memory.
Background
The dynamic random access memory (Dynamic Random Access Memory, DRAM) is a semiconductor memory.
In the prior art, when the dynamic random access memory is applied in different scenes, the required voltages are different, so that the dynamic random access memory needs to meet different voltage outputs.
Therefore, a method for testing the output voltage of the dynamic random access memory is needed to ensure the accuracy of the output voltage of the dynamic random access memory in different application scenarios.
Disclosure of Invention
Embodiments described herein provide a memory internal voltage testing system and method that solve the problems of the prior art.
According to a first aspect of the present disclosure, there is provided a memory internal voltage test system including: the device comprises a selection enabling signal output module, a voltage generation module, a voltage selection module, an output module and a comparison module;
the selection enabling signal output module is configured to output a first selection signal to the voltage selection module and output an enabling signal to the voltage generation module and the output module when receiving a test indication signal, wherein the test indication signal comprises a preset test voltage;
the voltage generation module is configured to determine a test voltage according to the working voltage of the memory and output the test voltage to the voltage selection module, wherein the test voltage comprises N different test voltages;
the voltage selection module is configured to select a target test voltage from the test voltages according to a first selection signal output by the selection enable signal output module and output the target test voltage to the output module;
the output module is configured to output the target test voltage to the comparison module under the action of the enabling signal;
The comparison module is configured to determine whether the target test voltage generated by the memory meets requirements according to the relation between the target test voltage and the preset test voltage.
In some embodiments of the present disclosure, the comparing module is further configured to output a trimming signal to the voltage generating module according to a relationship between the target test voltage and the preset test voltage;
The voltage generation module is further configured to adjust the output target test voltage according to the trimming signal.
In some embodiments of the present disclosure, a cache module is further included;
The buffer module is configured to receive the target test voltage output by the voltage selection module and output the target test voltage to the output module.
In some embodiments of the present disclosure, the system further comprises a decoding module and a switching module;
The selection enabling signal output module is further configured to output a second selection signal to the decoding module when receiving a test indication signal;
The voltage generation module is further configured to determine test voltages corresponding to memory layers of the memory according to the working voltage of the memory, and output the test voltages corresponding to the memory layers of the memory to the voltage selection module, wherein the test voltages corresponding to one memory layer of the memory comprise a plurality of different voltage values, the number of the test voltages included in the different memory layers of the memory is the same, and the test voltages included in the different memory layers of the memory are the same;
the voltage selection module is further configured to select a target test voltage from the test voltages corresponding to the memory layers of the memory according to the first selection signal output by the selection enable signal output module and send the selected target test voltage of the memory layers of the memory to the switch module;
The decoding module is configured to output a control signal to the switch module according to the second selection signal;
The switch module is configured to determine a conducting state according to the control signal output by the decoding module so as to send the target test voltage of the target memory layer to the output module.
In some embodiments of the present disclosure, the switching module includes a plurality of switching units, the number of the switching units is the same as the number of the memory layers included in the memory, and the switching units include a first transistor, a second transistor, and an inverter;
the control end of the first transistor and the first end of the inverter receive the control signal output by the decoding module, the first end of the first transistor and the first end of the second transistor respectively receive the target test voltage of a memory layer of the memory output by the voltage selection module, the second end of the first transistor and the second end of the second transistor are electrically connected with the output module, and the second end of the inverter is electrically connected with the control end of the second transistor.
In some embodiments of the present disclosure, the voltage generating module includes N resistors, a third transistor and N switches sequentially connected in series, a second end of the last resistor is electrically connected to a first end of the next resistor and a first end of the first switch, a first end of the first resistor is electrically connected to a power supply voltage node, a second end of the last resistor is electrically connected to a first end of the third transistor and a first end of the last switch, a second end of the third transistor is electrically connected to a ground node, a control terminal of the third transistor is connected to an enable signal output by the selection enable signal output module, and a second end of each switch outputs a test voltage.
According to a second aspect of the present disclosure, there is provided a memory internal voltage testing method including:
Determining a first selection signal and an enable signal in response to the received test indication signal;
Determining a test voltage according to the working voltage of the memory, wherein the test voltage comprises N different test voltages;
Selecting a target test voltage from the test voltages according to the first selection signal and the enable signal and outputting the target test voltage;
and determining whether the target test voltage generated by the memory meets the requirement according to the relation between the target test voltage and a preset test voltage.
In some embodiments of the present disclosure, the determining whether the target test voltage generated by the memory meets a requirement according to a relationship between the target test voltage and a preset test voltage includes:
when the absolute value of the difference value between the target test voltage and the preset test voltage is larger than or equal to a preset threshold value, determining that the target test voltage generated by the memory does not meet the requirement;
And when the absolute value of the difference value between the target test voltage and the preset test voltage is smaller than a preset threshold value, determining that the target test voltage generated by the memory meets the requirement.
In some embodiments of the present disclosure, the method further comprises:
and when the absolute value of the difference value between the target test voltage and the preset test voltage is larger than or equal to a preset threshold value, regulating and outputting the size of the target test voltage.
In some embodiments of the present disclosure, when determining the first selection signal and the enable signal in response to the received test indication signal, the method further includes:
Determining a second selection signal in response to the received test indication signal;
Determining test voltages corresponding to all memory layers of the memory according to the working voltage of the memory, wherein the test voltages corresponding to one memory layer of the memory comprise a plurality of different voltage values, the number of the test voltages included in the different memory layers of the memory is the same, and the test voltages included in the different memory layers of the memory are the same;
selecting a target test voltage from the test voltages corresponding to the memory layers of the memory according to the first selection signal and the enabling signal, and outputting the target test voltage;
and outputting a target test voltage of the target memory layer according to the second selection signal.
According to the system and the method for testing the internal voltage of the memory, the system for testing the internal voltage of the memory comprises the selection enabling signal output module, the voltage generation module, the voltage selection module, the output module and the comparison module, one target test voltage is selected from N test voltages generated by the voltage generation module to be output based on the first selection signal output by the selection enabling signal output module, the comparison module is used for comparing the relationship between the output target test voltage and the preset test voltage, whether the target test voltage of the tested memory meets the design requirement is determined, the test of a plurality of test voltages generated by the memory is achieved, and the reliability and the stability of the memory in practical application are improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following brief description of the drawings of the embodiments will be given, it being understood that the drawings described below relate only to some embodiments of the present disclosure, not to limitations of the present disclosure, in which:
FIG. 1 is a schematic diagram of a memory internal voltage testing system according to an embodiment of the present disclosure;
FIG. 2 is a schematic diagram of another memory internal voltage testing system provided by an embodiment of the present disclosure;
FIG. 3 is a schematic diagram of a further memory internal voltage testing system provided by an embodiment of the present disclosure;
FIG. 4 is a schematic diagram of a three-dimensional stacked memory provided by an embodiment of the present disclosure;
FIG. 5 is a schematic diagram of a further memory internal voltage testing system provided by embodiments of the present disclosure;
FIG. 6 is a schematic diagram of a voltage generation module in a memory internal voltage test system according to an embodiment of the disclosure;
fig. 7 is a flowchart of a method for testing internal voltages of a memory according to an embodiment of the disclosure.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings. It will be apparent that the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments, which can be made by those skilled in the art based on the described embodiments of the present disclosure without the need for creative efforts, are also within the scope of the protection of the present disclosure.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the presently disclosed subject matter belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the specification and relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. As used herein, a statement that two or more parts are "connected" or "coupled" together shall mean that the parts are joined together either directly or joined through one or more intermediate parts.
In all embodiments of the present disclosure, terms such as "first" and "second" are used merely to distinguish one component (or portion of a component) from another component (or portion of a component).
As used herein and in the appended claims, the singular forms of words include the plural and vice versa, unless the context clearly dictates otherwise. Thus, when referring to the singular, the plural of the corresponding term is generally included. Similarly, the terms "comprising" and "including" are to be construed as being inclusive rather than exclusive. Likewise, the terms "comprising" and "or" should be interpreted as inclusive, unless such an interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it follows a set of terms, the "example" is merely exemplary and illustrative and should not be considered exclusive or broad.
Based on the problems existing in the prior art, an embodiment of the present disclosure provides a memory internal voltage testing system, and fig. 1 is a schematic structural diagram of the memory internal voltage testing system provided in the embodiment of the present disclosure, as shown in fig. 1, the memory internal voltage testing system includes: a selection enable signal output module 10, a voltage generation module 20, a voltage selection module 30, an output module 40, and a comparison module 50; wherein the selection enable signal output module 10 is configured to output a first selection signal to the voltage selection module 30 and output an enable signal to the voltage generation module 20 and the output module 40 when receiving a test indication signal, the test indication signal including a preset test voltage; a voltage generation module 20 configured to determine a test voltage according to an operating voltage of the memory, and output the test voltage to the voltage selection module 30, the test voltage including N different test voltages; a voltage selection module 30 configured to select a target test voltage from among the test voltages and output the target test voltage to the output module 40 according to the first selection signal output from the selection enable signal output module 10; an output module 40 configured to output a target test voltage to the comparison module 50 under the action of the enable signal; the comparison module 50 is configured to determine whether the target test voltage generated by the memory meets the requirement according to the relationship between the target test voltage and the preset test voltage.
In a specific embodiment, the selection enable signal output module 10 outputs a first selection signal to the voltage selection module 30, outputs an enable signal to the voltage generation module 20 and the output module 40, when the voltage generation module 20 receives the enable signal, outputs N test voltages to the voltage selection module 30, the voltage selection module 30 selects one target test voltage from the N test voltages output by the voltage generation module 20 according to the first selection signal output by the selection enable signal output module 10, and outputs the target test voltage to the output module 40, the output module 40 outputs the target test voltage under the effect of the enable signal, and the comparison module 50 determines whether the target test voltage generated by the memory meets the requirement by comparing the relationship between the target test voltage output by the output module 40 and a preset test voltage.
It should be noted that, the first selection signal output by the selection enable signal output module 10 is used to select one target test voltage from the N different test voltages generated by the voltage generating module for outputting. The enable signal output from the selection enable signal output module 10 to the voltage generation module 20 is used to control the voltage generation module 20 to output N different test voltages, and the enable signal output from the selection enable signal output module 20 to the output module 40 is used to instruct the output port of the memory to output the test signal at this time, and not to receive the data signal and transmit the data signal.
According to the memory internal voltage testing system provided by the embodiment of the disclosure, the memory internal voltage testing system comprises the selection enabling signal output module, the voltage generation module, the voltage selection module, the output module and the comparison module, one target testing voltage is selected from N testing voltages generated by the voltage generation module to be output based on the first selection signal output by the selection enabling signal output module, the comparison module is used for comparing the relation between the output target testing voltage and the preset testing voltage, whether the target testing voltage of the tested memory meets the design requirement is determined, testing of a plurality of testing voltages generated by the memory is achieved, and the reliability and stability of the memory in practical application are improved.
In a specific embodiment, the comparing module 50 is further configured to output the trimming signal to the voltage generating module 20 according to the relationship between the target test voltage and the preset test voltage; the voltage generating module 20 is further configured to adjust the magnitude of the output target test voltage according to the trimming signal.
Specifically, when the absolute value of the difference between the target test voltage and the preset test voltage is smaller than the preset threshold, the design in the memory generates the target test voltage to meet the design requirement, and when the absolute value of the difference between the target test voltage and the preset test voltage is larger than or equal to the preset threshold, the design in the memory generates the target test voltage to not meet the design requirement, so that the voltage generation module needs to output the trimming signal to the voltage generation module, so that the voltage generation module adjusts and outputs the target test voltage according to the trimming signal.
The voltage generation module is configured to output a trimming signal to the voltage generation module if the absolute value of the difference between the target test voltage and the preset test voltage is greater than or equal to a preset threshold value and the target test voltage is greater than the preset test voltage, reduce the output target test voltage according to the trimming signal, and output the trimming signal to the voltage generation module if the absolute value of the difference between the target test voltage and the preset test voltage is greater than or equal to the preset threshold value and the target test voltage is less than the preset test voltage and the voltage generation module increases the output target test voltage according to the trimming signal.
On the basis of the above embodiment, fig. 2 is a schematic structural diagram of another internal voltage testing system of a memory according to an embodiment of the disclosure, where, as shown in fig. 2, the internal voltage testing system of a memory further includes a buffer module; the buffer module 60 is configured to receive the target test voltage output by the voltage selection module 30 and output the target test voltage to the output module 40.
By arranging the buffer module 60 between the voltage selection module 30 and the output module 40, the output impedance of the output module 40 is reduced based on the buffer module 60, the influence of the load on the target test voltage output by the output module 40 is reduced, and the accuracy of the target test voltage output by the output module 40 is improved.
On the basis of the above embodiments, fig. 3 is a schematic structural diagram of still another internal voltage testing system for memory according to an embodiment of the disclosure, where, as shown in fig. 3, the internal voltage testing system for memory further includes: a decoding module 70 and a switching module 80; the selection enable signal output module 10 is further configured to output a second selection signal to the decoding module 70 when receiving the test indication signal; the voltage generating module 20 is further configured to determine a test voltage corresponding to each memory layer of the memory according to the working voltage of the memory, and output the test voltage corresponding to each memory layer of the memory to the voltage selecting module 30, where the test voltage corresponding to one memory layer of the memory includes a plurality of different voltage values, the number of test voltages included in different memory layers of the memory is the same, and the test voltages included in different memory layers of the memory are all the same; the voltage selecting module 30 is further configured to select a target test voltage from the test voltages corresponding to the memory layers of the memory according to the first selection signal output by the selection enable signal output module 10 and send the target test voltage of the memory layers of the selected memory to the switching module 80; a decoding module 70 configured to output a control signal to the switching module 80 according to the second selection signal; the switch module 80 is configured to determine the on state according to the control signal output by the decoding module 70, so as to send the target test voltage of the target memory layer to the output module 40.
In a specific embodiment, when the memory is a three-dimensional stacked memory, as shown in fig. 4, the three-dimensional stacked memory includes different memory layers, and each of the different memory layers includes a voltage generating module and a voltage selecting module, so that when the internal voltage test is performed on the three-dimensional stacked memory, the test voltage generated by each layer needs to be tested, and therefore, by designing the internal voltage test system of the memory, the decoding module and the switch module are further included, when the voltage generating module determines the test voltages corresponding to each memory layer of the memory and outputs the test voltages corresponding to each memory layer of the memory to the voltage selecting module, the voltage selecting module selects a target test voltage from the test voltages corresponding to each memory layer of the memory based on the first selection signal, that is, the switch module receives a target test voltage of each memory layer in the memory, and at this time, the target test voltage of one target memory layer in the memory is selected and sent to the output module is realized through the decoding module and the switch module.
The three-dimensional stacked memory is a structure which is realized by connecting a plurality of memory layer Die through TSV (Through Silicon Via) technology, wherein a logic layer Die is arranged on the last layer as a substrate, and pins of a Die chip of each memory layer Die are connected together through TSVs and connected to the logic layer Die.
In a specific implementation manner, the decoding module 70 receives the second selection signal output by the selection enable signal output module 10, decodes the second selection signal, outputs a control signal to the switch module 80, and controls the on state of the switch module 80 to send the target test voltage of one target memory layer in the memory to the output module.
Specifically, as shown in fig. 5, the switch module 80 includes a plurality of switch units, the number of the switch units is the same as the number of memory layers included in the storage device, and the switch units include a first transistor NMOS1, a second transistor PMOS and an inverter NOT; the control terminal of the first transistor NMOS1 and the first terminal of the inverter NOT receive the control signal output by the decoding module 70, the first terminal of the first transistor NMOS1 and the first terminal of the second transistor PMOS receive the target test voltage of a memory layer of the memory output by the voltage selection module 30, respectively, the second terminal of the first transistor NMOS1 and the second terminal of the second transistor PMOS are electrically connected to the output module 40, and the second terminal of the inverter NOT is electrically connected to the control terminal of the second transistor PMOS.
By setting the switching unit to include a first transistor NMOS1 and a second transistor PMOS, where the first transistor is an NMOS transistor, the second transistor is a PMOS transistor, and the second selection signal output by the selection enable signal output module 10 is 00, the control signal output after the decoding module 70 decodes the second selection signal is 0001, at this time, the control end of the first transistor NMOS1 in the first switching unit receives the high-level signal, the control end of the second transistor PMOS receives the low-level signal output through the inverter NOT, the first switching unit is turned on, and the voltage selection module 30 outputs the target test voltage of the first memory layer of the memory to the output module 40 through the first switching unit, so as to further implement the test of the target test voltage of the first memory layer of the memory.
Specifically, by setting the switching unit to include the first transistor and the second transistor, when the decoding module outputs the high-level control signal to the first switching unit, the first transistor and the second transistor of the first switching unit are both in the on state, so that the accuracy of the output target test voltage is prevented from being influenced due to the fact that the NMOS transmits the high-level with the pre-loss value and the PMOS transmits the low-level with the pre-loss value, and the accuracy of the internal voltage test of the memory is prevented from being influenced.
For example, if the memory includes 4 memory layers, the switching module 80 includes 4 switching units, and each switching unit includes a first transistor, a second transistor, and an inverter. The second selection signal output by the selection enable signal output module 10 may be a two-bit selection signal, and after decoding by the decoding module 70, the gating of any one of the four switch units may be implemented.
Specifically, if it is desired to output the target test voltage of the first memory layer of the memory, the second selection signal output by the selection enable signal output module 10 is 00, the control signal output after the decoding module 70 decodes the second selection signal is 0001, that is, at this time, the first switch unit is controlled to be turned on, so as to send the target test voltage of the first memory layer of the memory to the output module through the first switch unit.
According to the memory internal voltage testing system provided by the embodiment of the disclosure, the memory internal voltage testing system further comprises the decoding module and the switch module, when the memory is a three-dimensional stacked memory and testing is required to be performed on the testing voltage generated by each layer of the three-dimensional stacked memory, the decoding module receives the second selection signal output by the selection enabling signal output module, decodes the second selection signal, outputs the control signal to the switch module, and controls the conduction state of the switch module so as to achieve that the target testing voltage of one target memory layer in the memory is sent to the output module.
In a specific embodiment, as shown in fig. 6, the voltage generating module includes N resistors R, a third transistor NMOS2 and N switches K sequentially connected in series, the second end of the last resistor is electrically connected to the first end of the next resistor and the first end of the first switch, the first end of the first resistor is electrically connected to the power supply voltage node, the second end of the last resistor is electrically connected to the first end of the third transistor NMOS2 and the first end of the last switch, the second end of the third transistor NMOS2 is electrically connected to the ground node, the control terminal of the third transistor NMOS receives the enable signal output by the selection enable signal output module 10, and the second end of each switch outputs a test voltage.
If the voltage generating module 20 needs to output N different test voltages, the voltage generating module 20 includes N resistors and N switches sequentially connected in series, the second end of each resistor is electrically connected with the first end of one switch, the second end of each switch outputs a test voltage, and the switch is controlled to be turned on by setting the resistance value of the resistor, so as to output N test voltages.
In addition, each resistor can be set as an adjustable resistor, and when the absolute value of the difference value between the target test voltage and the preset test voltage is larger than or equal to a preset threshold value, the size of the output target test voltage is further adjusted by adjusting the resistance value of the adjustable resistor in the branch corresponding to the output target test voltage.
On the basis of the above embodiments, fig. 7 is a schematic flow chart of a method for testing internal voltage of a memory according to an embodiment of the disclosure, and as shown in fig. 7, the method for testing internal voltage of a memory includes:
s110, responding to the received test indication signal, and determining a first selection signal and an enabling signal.
Wherein the first selection signal is used for selecting one target test voltage from N different test voltages to output, and the enable signal is used for indicating the output port of the memory to output the test signal at the moment, and the data signal is not received and transmitted
S120, determining a test voltage according to the working voltage of the memory.
Wherein the test voltages comprise N different test voltages.
S130, selecting a target test voltage from the test voltages according to the first selection signal and the enable signal and outputting the target test voltage.
Under the action of a first selection signal, selecting one target test voltage from N different test voltages, and under the action of an enabling signal, outputting the target test voltage selected and output by an output port of the memory.
S140, determining whether the target test voltage generated by the memory meets the requirement according to the relation between the target test voltage and the preset test voltage.
According to the relation between the target test voltage and the preset test voltage, determining whether the target test voltage generated by the memory meets the requirement or not includes:
When the absolute value of the difference value between the target test voltage and the preset test voltage is larger than or equal to a preset threshold value, determining that the target test voltage generated by the memory does not meet the requirement; and when the absolute value of the difference value between the target test voltage and the preset test voltage is smaller than the preset threshold value, determining that the target test voltage generated by the memory meets the requirement.
In addition, when the absolute value of the difference value between the target test voltage and the preset test voltage is greater than or equal to a preset threshold value, the magnitude of the output target test voltage is regulated.
According to the method for testing the internal voltage of the memory, provided by the embodiment of the disclosure, one target test voltage is selected from N test voltages generated by the voltage generation module to output based on the first selection signal, and the relation between the output target test voltage and the preset test voltage is compared through the comparison module to determine whether the target test voltage of the tested memory meets the design requirement, so that the test of a plurality of test voltages generated by the memory is realized, and the reliability and the stability of the memory in practical application are improved.
In addition, on the basis of the above embodiment, the method for testing the internal voltage of the memory according to the embodiment of the present disclosure further includes: determining a second selection signal in response to the received test indication signal; determining test voltages corresponding to all memory layers of the memory according to the working voltage of the memory, wherein the test voltages corresponding to one memory layer of the memory comprise a plurality of different voltage values, the number of the test voltages contained in the different memory layers of the memory is the same, and the test voltages contained in the different memory layers of the memory are the same; selecting a target test voltage from the test voltages corresponding to the memory layers of the storage according to the first selection signal and the enabling signal, and outputting the target test voltage; and outputting the target test voltage of the target memory layer according to the second selection signal.
When the memory is a three-dimensional stacked memory, the three-dimensional stacked memory comprises different memory layers, each memory layer comprises a voltage generation module and a voltage selection module, therefore, when the three-dimensional stacked memory is subjected to internal voltage test, test voltages generated by each layer need to be tested, when test indication signals are received, through determining second selection signals, after test voltages corresponding to the memory layers of the memory and test voltages corresponding to the memory layers of the memory are output to the voltage selection module, a target test voltage is selected from the test voltages corresponding to the memory layers of the memory according to first selection signals and enabling signals and is output, and then the target test voltage of one target memory layer in the memory is selected through the second selection signals and is sent to the output module.
According to the method for testing the internal voltage of the memory, when the memory is a three-dimensional stacked memory and the test voltage generated by each layer of the three-dimensional stacked memory is required to be tested, the target test voltage of one target memory layer in the memory is sent to the output module through the second selection signal.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of exemplary embodiments according to the present application. As used herein, the singular is also intended to include the plural unless the context clearly indicates otherwise, and furthermore, it is to be understood that the terms "comprises" and/or "comprising" when used in this specification are taken to specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof.
It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present application. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that, in various embodiments of the present application, the sequence number of each step/process described above does not mean that the execution sequence of each step/process should be determined by its functions and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present application. Moreover, the foregoing description of the embodiments of the application is provided for the purpose of illustration only, and does not represent the advantages or disadvantages of the embodiments.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that embodiments of the application described herein may be capable of being practiced otherwise than as specifically illustrated and described. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
The foregoing description of the preferred embodiments of the present disclosure is provided only and not intended to limit the disclosure so that various modifications and changes may be made to the present disclosure by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure should be included in the protection scope of the present disclosure.
Claims (10)
1. A memory internal voltage testing system, comprising: the device comprises a selection enabling signal output module, a voltage generation module, a voltage selection module, an output module and a comparison module;
the selection enabling signal output module is configured to output a first selection signal to the voltage selection module and output an enabling signal to the voltage generation module and the output module when receiving a test indication signal, wherein the test indication signal comprises a preset test voltage;
the voltage generation module is configured to determine a test voltage according to the working voltage of the memory and output the test voltage to the voltage selection module, wherein the test voltage comprises N different test voltages;
the voltage selection module is configured to select a target test voltage from the test voltages according to a first selection signal output by the selection enable signal output module and output the target test voltage to the output module;
the output module is configured to output the target test voltage to the comparison module under the action of the enabling signal;
The comparison module is configured to determine whether the target test voltage generated by the memory meets requirements according to the relation between the target test voltage and the preset test voltage.
2. The system of claim 1, wherein the comparison module is further configured to output a trimming signal to the voltage generation module according to a relationship of the target test voltage and the preset test voltage;
The voltage generation module is further configured to adjust the output target test voltage according to the trimming signal.
3. The system of claim 1, further comprising a cache module;
The buffer module is configured to receive the target test voltage output by the voltage selection module and output the target test voltage to the output module.
4. The system of claim 1, further comprising a decoding module and a switching module;
The selection enabling signal output module is further configured to output a second selection signal to the decoding module when receiving a test indication signal;
The voltage generation module is further configured to determine test voltages corresponding to memory layers of the memory according to the working voltage of the memory, and output the test voltages corresponding to the memory layers of the memory to the voltage selection module, wherein the test voltages corresponding to one memory layer of the memory comprise a plurality of different voltage values, the number of the test voltages included in the different memory layers of the memory is the same, and the test voltages included in the different memory layers of the memory are the same;
the voltage selection module is further configured to select a target test voltage from the test voltages corresponding to the memory layers of the memory according to the first selection signal output by the selection enable signal output module and send the selected target test voltage of the memory layers of the memory to the switch module;
The decoding module is configured to output a control signal to the switch module according to the second selection signal;
The switch module is configured to determine a conducting state according to the control signal output by the decoding module so as to send the target test voltage of the target memory layer to the output module.
5. The system of claim 4, wherein the switching module comprises a plurality of switching units, the number of switching units being the same as the number of memory layers comprised by the memory, the switching units comprising a first transistor, a second transistor, and an inverter;
the control end of the first transistor and the first end of the inverter receive the control signal output by the decoding module, the first end of the first transistor and the first end of the second transistor respectively receive the target test voltage of a memory layer of the memory output by the voltage selection module, the second end of the first transistor and the second end of the second transistor are electrically connected with the output module, and the second end of the inverter is electrically connected with the control end of the second transistor.
6. The system of claim 1, wherein the voltage generating module comprises N resistors, a third transistor and N switches connected in series in sequence, the second terminal of the last resistor is electrically connected to the first terminal of the next resistor and the first terminal of the first switch, the first terminal of the first resistor is electrically connected to the power supply voltage node, the second terminal of the last resistor is electrically connected to the first terminal of the third transistor and the first terminal of the last switch, the second terminal of the third transistor is electrically connected to the ground node, the control terminal of the third transistor is connected to the enable signal output by the selection enable signal output module, and the second terminal of each switch outputs a test voltage.
7. A method for testing internal voltage of a memory, comprising:
Determining a first selection signal and an enable signal in response to the received test indication signal;
Determining a test voltage according to the working voltage of the memory, wherein the test voltage comprises N different test voltages;
Selecting a target test voltage from the test voltages according to the first selection signal and the enable signal and outputting the target test voltage;
and determining whether the target test voltage generated by the memory meets the requirement according to the relation between the target test voltage and a preset test voltage.
8. The method of claim 7, wherein determining whether the target test voltage generated by the memory meets a requirement according to a relationship between the target test voltage and a preset test voltage comprises:
when the absolute value of the difference value between the target test voltage and the preset test voltage is larger than or equal to a preset threshold value, determining that the target test voltage generated by the memory does not meet the requirement;
And when the absolute value of the difference value between the target test voltage and the preset test voltage is smaller than a preset threshold value, determining that the target test voltage generated by the memory meets the requirement.
9. The method of claim 8, wherein the method further comprises:
and when the absolute value of the difference value between the target test voltage and the preset test voltage is larger than or equal to a preset threshold value, regulating and outputting the size of the target test voltage.
10. The method of claim 7, wherein determining the first select signal and the enable signal in response to the received test indication signal further comprises:
Determining a second selection signal in response to the received test indication signal;
Determining test voltages corresponding to all memory layers of the memory according to the working voltage of the memory, wherein the test voltages corresponding to one memory layer of the memory comprise a plurality of different voltage values, the number of the test voltages included in the different memory layers of the memory is the same, and the test voltages included in the different memory layers of the memory are the same;
selecting a target test voltage from the test voltages corresponding to the memory layers of the memory according to the first selection signal and the enabling signal, and outputting the target test voltage;
and outputting a target test voltage of the target memory layer according to the second selection signal.
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