CN118115038A

CN118115038A - LED chip defect detection method, device, equipment and storage medium

Info

Publication number: CN118115038A
Application number: CN202410280926.4A
Authority: CN
Inventors: 古乐野
Original assignee: Shenzhen Pengle Intelligent System Co ltd
Current assignee: Shenzhen Pengle Intelligent System Co ltd
Priority date: 2024-03-12
Filing date: 2024-03-12
Publication date: 2024-05-31

Abstract

The invention provides a method, a device, equipment and a storage medium for detecting defects of an LED chip, wherein the method comprises the following steps: selecting a plurality of corresponding chip process detection models according to a plurality of equipment nodes respectively, and inputting chip process data of each equipment node in a target time period into the corresponding chip process detection models respectively to obtain corresponding process yield; calculating the process passing rate of the target LED chip produced in the target time period based on the weight data corresponding to each equipment node and the corresponding process yield; judging whether the product grade of the target LED chip is a preset defective grade or not based on the process passing rate; and carrying out chip electrical detection on the target LED chips with defective product grades to obtain chip defect detection results. The method uses the process data in different process steps before the electrical detection of the LED chip, predicts the shipment quality and grade of the product, only performs electrical measurement on the bad product, reduces the electrical measurement cost, and can reduce the secondary bad rate caused by the electrical measurement of the product.

Description

LED chip defect detection method, device, equipment and storage medium

Technical Field

The present invention relates to the field of defect detection, and in particular, to a method, an apparatus, a device, and a storage medium for detecting defects of an LED chip.

Background

An LED (LIGHT EMITTING Diode) chip is an important semiconductor device and is widely applied to the fields of illumination, display, communication and the like. In order to ensure stable quality and performance of the LED chip, electrical detection becomes an indispensable link in the LED production process. However, the electrical measurement is the operation flow with the lowest efficiency in the led manufacturing process and the largest equipment number and occupied area. Along with the great increase of the mini and micro display requirements, the geometrical size of the electrode is smaller and smaller, the electrode is more and more difficult to prick, and the proportion of pricked products is higher and higher.

Disclosure of Invention

The invention mainly aims to solve the technical problem that the number of pricked products is increased due to the fact that the existing electrical detection is used for detecting defects of an LED chip.

The invention provides an LED chip defect detection method, which is applied to an LED chip production system, wherein the LED chip production system comprises a plurality of equipment nodes corresponding to a plurality of process sections of an LED chip in the process; the LED chip defect detection method comprises the following steps:

Acquiring chip process data of each equipment node in the LED chip production system in a target time period;

Selecting a plurality of corresponding chip process detection models according to the plurality of equipment nodes, and respectively inputting the chip process data into the corresponding chip process detection models to obtain the process yield of the corresponding equipment nodes in the target time period;

calculating the process passing rate of the target LED chip produced in the target time period based on the weight data corresponding to each equipment node and the corresponding process yield;

Determining the product grade of the target LED chip produced in the target time period based on the process passing rate, and judging whether the product grade is a preset defective grade or not;

If yes, the chip electrical detection is carried out on the target LED chip produced in the target time period, and a chip defect detection result is obtained.

Optionally, in a first implementation manner of the first aspect of the present invention, the chip process data includes chip process parameters and/or a three-dimensional topography detection image;

the step of respectively selecting a plurality of corresponding chip process detection models according to the plurality of equipment nodes, respectively inputting the chip process data into the corresponding chip process detection models, and obtaining the process yield of the equipment nodes corresponding to the target time period comprises the following steps:

Respectively selecting a plurality of corresponding chip process detection models according to the plurality of equipment nodes, and determining whether a process section corresponding to the corresponding equipment nodes is an image detection process section according to the equipment types of the plurality of equipment nodes;

If yes, acquiring a three-dimensional morphology detection image in the image detection processing section, preprocessing the three-dimensional morphology detection image and the chip processing parameters, and inputting the preprocessed three-dimensional morphology detection image and the preprocessed chip processing parameters into a corresponding chip processing detection model to obtain the processing yield of the corresponding equipment node in the target time section;

if not, the chip process parameters are preprocessed and then respectively input into corresponding chip process detection models, and the process yield of the corresponding equipment nodes in the target time period is obtained.

Optionally, in a second implementation manner of the first aspect of the present invention, the preprocessing the chip process parameter and then inputting the preprocessed chip process parameter into a corresponding chip process detection model, so as to obtain a process yield of the corresponding equipment node in the target time period includes:

the chip process parameters are preprocessed and then respectively input into corresponding chip process detection models, wherein the chip process detection models comprise an input layer, a cross layer, a depth layer, a combination layer and an output layer;

performing data preprocessing and data feature extraction on the chip process parameters through the input layer to obtain a plurality of data features;

Performing first feature association processing on the plurality of data features through the cross layer to obtain first association features, and performing second feature association processing on the plurality of data features through the depth layer to obtain second association features;

and connecting the first association feature and the second association feature through the combination layer, and calculating the process yield of the corresponding equipment node in the target time period through an activation function by using the connected feature vector.

Optionally, in a third implementation manner of the first aspect of the present invention, the performing, by the input layer, data preprocessing and data feature extraction on the chip process parameter, where obtaining the data feature includes:

Performing feature extraction on the chip process parameters through the input layer to obtain first feature data;

generating an adjacency matrix according to the first characteristic data, and calculating a corresponding Laplace matrix based on the adjacency matrix;

Performing eigenvalue decomposition on the Laplace matrix to obtain a plurality of eigenvectors and corresponding eigenvalues, and screening the eigenvectors according to the eigenvalue sizes to obtain corresponding eigenvalue subspaces;

And acquiring second characteristic data based on the characteristic subspace, and carrying out iterative processing on the second characteristic data according to a particle swarm algorithm to obtain data characteristics.

Optionally, in a fourth implementation manner of the first aspect of the present invention, the obtaining a three-dimensional feature detection image in the image detection process segment, preprocessing the three-dimensional feature detection image and the chip process parameter, and inputting the preprocessed three-dimensional feature detection image and the preprocessed chip process parameter into a corresponding chip process detection model, so as to obtain a process yield corresponding to the corresponding equipment node in the target time segment includes:

Acquiring a three-dimensional morphology detection image in the image detection processing section, preprocessing the three-dimensional morphology detection image and the chip processing parameters, and inputting the preprocessed three-dimensional morphology detection image and the preprocessed three-dimensional morphology detection image into a corresponding chip processing detection model, wherein the chip processing detection model comprises an input layer, an attention mechanism layer, a feature fusion layer, a classification layer and an output layer;

Performing data preprocessing and data feature extraction on the chip process parameters through the input layer to obtain data features, and performing image preprocessing and image feature extraction on the three-dimensional morphology detection image to obtain image features;

Calculating attention weight vectors of the data features and the image features through the attention mechanism layer respectively;

The feature fusion layer carries out weighted fusion on the data features and the image features according to the weight vector to obtain a fusion feature vector;

And calculating the process yield of the corresponding equipment node in the target time period according to the fusion feature vector through the classification layer, and outputting the process yield through the output layer.

Optionally, in a fifth implementation manner of the first aspect of the present invention, before the acquiring the three-dimensional morphology detection image in the image detection process segment and preprocessing the three-dimensional morphology detection image and the chip process parameter, inputting the preprocessed three-dimensional morphology detection image and the preprocessed chip process parameter into a corresponding chip process detection model, the method further includes:

the method comprises the steps of obtaining the resolution of optical lens equipment corresponding to each image processing section, and calculating the number of scanning layers corresponding to each image processing section according to a preset super-depth-of-field synthetic imaging algorithm and the resolution;

The optical lens equipment of the corresponding image processing section is controlled based on the scanning layer number to perform three-dimensional morphology detection on the target chip produced in the target time section, so that depth images of different scanning layers of each image processing section are obtained;

And combining the depth images of the different scanning layers to generate three-dimensional morphology detection images of each image processing section.

Optionally, in a sixth implementation manner of the first aspect of the present invention, the calculating, by the classification layer, a process yield of the corresponding device node in the target time period according to the fusion feature vector, and outputting, by the output layer, the process yield includes:

Mapping the fusion feature vector to a high-dimensional feature space through the classification layer in a linear transformation way to obtain a linear transformation result;

nonlinear transformation is carried out on the linear transformation result through a preset activation function, and a nonlinear transformation result is obtained;

Calculating the probability of the corresponding equipment node in the process yield interval corresponding to the target time period according to the nonlinear transformation result through a full-connection layer in the classification layer;

and taking the process yield interval with the highest probability as the process yield corresponding to the corresponding equipment node in the target time period, and outputting the process yield through the output layer.

The second aspect of the invention provides an LED chip defect detection device, which is applied to an LED chip production system, wherein the LED chip production system comprises a plurality of equipment nodes corresponding to a plurality of process sections of an LED chip in the process; the LED chip defect detection device comprises:

the acquisition module is used for acquiring chip process data of each equipment node in the LED chip production system in a target time period;

The yield calculation module is used for respectively selecting a plurality of corresponding chip process detection models according to the plurality of equipment nodes, and respectively inputting the chip process data into the corresponding chip process detection models to obtain the process yield of the corresponding equipment nodes in the target time period;

The passing rate calculation module is used for calculating the process passing rate of the target LED chip produced in the target time period based on the weight data corresponding to each equipment node and the corresponding process yield;

The judging module is used for determining the product grade of the target LED chip produced in the target time period based on the process passing rate and judging whether the product grade is a preset defective grade or not;

And the electric detection module is used for carrying out chip electric detection on the target LED chip produced in the target time period if the product grade is a defective grade, so as to obtain a chip defect detection result.

A third aspect of the present invention provides an LED chip defect detection apparatus, including: a memory and at least one processor, the memory having instructions stored therein, the memory and the at least one processor being interconnected by a line; the at least one processor invokes the instructions in the memory to cause the LED chip defect detection apparatus to perform the steps of the LED chip defect detection method described above.

A fourth aspect of the present invention provides a computer readable storage medium having instructions stored therein which, when run on a computer, cause the computer to perform the steps of the LED chip defect detection method described above.

According to the LED chip defect detection method, the device, the equipment and the storage medium, the corresponding multiple chip process detection models are selected according to the multiple equipment nodes, and the chip process data of the equipment nodes in the target time period are respectively input into the corresponding chip process detection models, so that the corresponding process yield is obtained; calculating the process passing rate of the target LED chip produced in the target time period based on the weight data corresponding to each equipment node and the corresponding process yield; judging whether the product grade of the target LED chip is a preset defective grade or not based on the process passing rate; and carrying out chip electrical detection on the target LED chips with defective product grades to obtain chip defect detection results. The method uses the process data in different process steps before the electrical detection of the LED chip, predicts the shipment quality and grade of the product, only performs electrical measurement on the bad product, reduces the electrical measurement cost, and can reduce the secondary bad rate caused by the electrical measurement of the product.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

In order to make the above objects, features and advantages of the present invention more comprehensible, preferred embodiments accompanied with figures are described in detail below.

Drawings

FIG. 1 is a schematic diagram of an embodiment of a method for detecting defects of an LED chip according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of an embodiment of an LED chip defect detection apparatus according to an embodiment of the present invention;

fig. 3 is a schematic diagram of an embodiment of an apparatus for detecting defects of an LED chip according to an embodiment of the present invention.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

The terms "comprising" and "having" and any variations thereof, as used in the embodiments of the present invention, are intended to cover non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed but may optionally include other steps or elements not listed or inherent to such process, method, article, or apparatus.

For the sake of understanding the present embodiment, first, a detailed description will be given of an LED chip defect detection method disclosed in the present embodiment, where the LED chip defect detection method is applied to an LED chip production system, and the LED chip production system includes a plurality of equipment nodes corresponding to a plurality of process segments in a process of manufacturing an LED chip. As shown in fig. 1, the method for detecting defects of the LED chip includes the following steps:

101. Acquiring chip process data of each equipment node in an LED chip production system in a target time period;

In one embodiment of the invention, the LED chip production system comprises a plurality of equipment nodes, such as wafer processing equipment, deposition equipment, photolithography equipment, etching equipment, metallization equipment, packaging equipment, and the like, wherein the wafer processing equipment comprises wafer cleaners, dicing machines, polishing machines, and the like. These devices are used to process the raw wafer of LED chips, and the process data provided may include wafer size, dicing quality, uniformity of polishing, etc., deposition devices such as Chemical Vapor Deposition (CVD) devices, physical Vapor Deposition (PVD) devices, etc. These devices are used to deposit materials on wafers and process data may relate to deposition rates, film quality, interface characteristics, etc. The lithographic apparatus is used to transfer the pattern on the photoresist layer onto the wafer. The process data may include exposure time, alignment accuracy, exposure dose, etc. Etching equipment is used to remove unwanted material from the wafer. The process data may include etch depth, etch rate, surface quality, etc. Metallization equipment such as vacuum evaporation machines, electroplating equipment, and the like. These devices are used to form metal electrodes or wires on a wafer. The process data may include film thickness, resistance, metal bonding, etc. Packaging equipment such as packaging machines, soldering equipment, etc. These devices are used to package LED chips into end products. The process data may relate to package quality, solder joint reliability, package speed, etc.

102. Selecting a plurality of corresponding chip process detection models according to the plurality of equipment nodes respectively, and inputting chip process data into the corresponding chip process detection models respectively to obtain the process yield of the corresponding equipment nodes in the target time period;

In one embodiment of the invention, the chip process data includes chip process parameters and/or three-dimensional topography detection images; the step of respectively selecting a plurality of corresponding chip process detection models according to the plurality of equipment nodes, respectively inputting the chip process data into the corresponding chip process detection models, and obtaining the process yield of the equipment nodes corresponding to the target time period comprises the following steps: respectively selecting a plurality of corresponding chip process detection models according to the plurality of equipment nodes, and determining whether a process section corresponding to the corresponding equipment nodes is an image detection process section according to the equipment types of the plurality of equipment nodes; if yes, acquiring a three-dimensional morphology detection image in the image detection processing section, preprocessing the three-dimensional morphology detection image and the chip processing parameters, and inputting the preprocessed three-dimensional morphology detection image and the preprocessed chip processing parameters into a corresponding chip processing detection model to obtain the processing yield of the corresponding equipment node in the target time section; if not, the chip process parameters are preprocessed and then respectively input into corresponding chip process detection models, and the process yield of the corresponding equipment nodes in the target time period is obtained.

Specifically, the chip process data further includes a three-dimensional morphology detection image, which is an image for observing and analyzing the morphology and structure of the chip surface. It provides detailed information about the geometry and microstructure of the chip surface. Typically, three-dimensional topography detection images of the chip are acquired using high resolution surface scanning techniques, such as Atomic Force Microscopy (AFM), scanning Electron Microscopy (SEM), or white light interferometers. In the production process of the LED chip, three-dimensional shape detection is generally applied to the following process sections of equipment nodes, including wafer processing equipment, deposition equipment, etching equipment and metallization equipment, and can be used for evaluating the surface flatness and quality of the chip in the wafer cutting and polishing processes so as to ensure that the size and shape of the chip meet the requirements. Deposition apparatus such as Chemical Vapor Deposition (CVD) apparatus and Physical Vapor Deposition (PVD) apparatus are used to deposit materials on wafers to form structures of different levels. At this stage, three-dimensional topography detection can help assess film thickness, uniformity, and surface quality. The etching apparatus is used to remove unwanted material from the wafer to form the desired pattern and structure. During etching, three-dimensional topography detection can be used to detect etch depth, sidewall quality, and structural morphology. The metallization equipment is used for forming metal electrodes or wires on the wafer, and the thickness, the flatness and the connection quality of the metal film can be evaluated through three-dimensional morphology detection. In addition, the three-dimensional morphology detection can be directly carried out in the last step of the process to obtain a three-dimensional morphology image, and for the process section without the three-dimensional morphology detection, the yield prediction is directly carried out according to the chip process parameters, and the yield prediction is carried out by combining the chip process parameters and the three-dimensional morphology detection image in the process section corresponding to the process section for operating the three-dimensional morphology detection.

Further, the preprocessing the chip process parameters and then inputting the preprocessed chip process parameters into corresponding chip process detection models respectively, and obtaining the process yield of the corresponding equipment node in the target time period comprises the following steps: the chip process parameters are preprocessed and then respectively input into corresponding chip process detection models, wherein the chip process detection models comprise an input layer, a cross layer, a depth layer, a combination layer and an output layer; performing data preprocessing and data feature extraction on the chip process parameters through the input layer to obtain a plurality of data features; performing first feature association processing on the plurality of data features through the cross layer to obtain first association features, and performing second feature association processing on the plurality of data features through the depth layer to obtain second association features; and connecting the first association feature and the second association feature through the combination layer, and calculating the process yield of the corresponding equipment node in the target time period through an activation function by using the connected feature vector.

Specifically, after pretreatment, the chip process parameters are respectively input into the corresponding chip process detection models. The model includes an input layer, a cross layer, a depth layer, a combination layer, and an output layer. Firstly, the input layer performs data preprocessing and feature extraction on chip process parameters to obtain a plurality of data features. These features may include chip size, material properties, process parameters, etc. Next, the cross-layer performs a first feature correlation process on the plurality of data features. It combines different features, for example by multiplication or addition, to obtain a new feature representation. These new features capture the correlation information between the original features and have a higher dimension of expressive power. These first correlation features provide a linear relationship between the different features. The depth layer then performs a second feature correlation process on the plurality of data features. Through the plurality of hidden layers, the model learns the nonlinear relationship between different features. By means of the back propagation algorithm, gradient descent and other optimization methods, the depth layer can automatically learn the complex relation between the features and generate a second correlation feature. These features represent a more abstract association between the original features in a high-dimensional space. Then, the combination layer connects the first association feature and the second association feature to form a new feature vector. The connection mode can be series connection, parallel connection or jump connection. By means of the connection, the information of the first and second associated features is integrated into a richer feature representation. This concatenated feature vector is passed to the output layer. And finally, calculating the connected feature vector by the output layer by using an activation function to obtain the process yield of the corresponding equipment node in the target time period. The activation function can be selected according to specific requirements, and common functions include sigmoid function, reLU function and the like. This process maps feature vectors to a range between 0 and 1 to represent process yields for the device nodes.

Further, the data preprocessing and the data feature extraction are performed on the chip process parameters through the input layer, and the obtaining the data features includes: performing feature extraction on the chip process parameters through the input layer to obtain first feature data; generating an adjacency matrix according to the first characteristic data, and calculating a corresponding Laplace matrix based on the adjacency matrix; performing eigenvalue decomposition on the Laplace matrix to obtain a plurality of eigenvectors and corresponding eigenvalues, and screening the eigenvectors according to the eigenvalue sizes to obtain corresponding eigenvalue subspaces; and acquiring second characteristic data based on the characteristic subspace, and carrying out iterative processing on the second characteristic data according to a particle swarm algorithm to obtain data characteristics.

Specifically, for a given feature data set, an adjacency matrix is first constructed to describe the degree of association between features. The adjacency matrix may be constructed using a measure of similarity or correlation between features. Based on the adjacency matrix, a laplace matrix can be calculated, and the laplace matrix is usually in different forms such as a standard laplace matrix, a symmetric normalized laplace matrix and the like. These matrices are capable of capturing the structure and associated information within the data. And decomposing the eigenvalue of the Laplace matrix to obtain the eigenvalue and the corresponding eigenvector. The eigenvalues corresponding to the eigenvectors may provide important information about the data structure, where the eigenvectors corresponding to smaller eigenvalues typically contain noise or irrelevant information. And selecting the first k corresponding feature vectors as final feature subspaces according to the magnitude of the feature values. Typically, feature vectors with larger feature values are selected, as their corresponding feature information is more important.

Further, the obtaining the three-dimensional morphology detection image in the image detection process section, preprocessing the three-dimensional morphology detection image and the chip process parameters, and inputting the preprocessed three-dimensional morphology detection image and the preprocessed chip process parameters into a corresponding chip process detection model, and obtaining the process yield of the corresponding equipment node in the target time section comprises the following steps: acquiring a three-dimensional morphology detection image in the image detection processing section, preprocessing the three-dimensional morphology detection image and the chip processing parameters, and inputting the preprocessed three-dimensional morphology detection image and the preprocessed three-dimensional morphology detection image into a corresponding chip processing detection model, wherein the chip processing detection model comprises an input layer, an attention mechanism layer, a feature fusion layer, a classification layer and an output layer; performing data preprocessing and data feature extraction on the chip process parameters through the input layer to obtain data features, and performing image preprocessing and image feature extraction on the three-dimensional morphology detection image to obtain image features; calculating attention weight vectors of the data features and the image features through the attention mechanism layer respectively; the feature fusion layer carries out weighted fusion on the data features and the image features according to the weight vector to obtain a fusion feature vector; and calculating the process yield of the corresponding equipment node in the target time period according to the fusion feature vector through the classification layer, and outputting the process yield through the output layer.

Specifically, in practical application, because the data such as the chip process parameters are numerical data and the three-dimensional morphology detection image is image data, the neural network model fusing various types of characteristics can be used for processing the numerical data and the image data, and the neural network model fusing various types of characteristics can use a multi-input model, a deep fusion model or an attention fusion model, wherein the multi-input model can respectively take the numerical data and the image data as different input layers and combine the numerical data and the image data into one model through a connecting layer. This approach may use a common convolutional neural network, such as ResNet, efficientNet, or the like, or a visual transducer to process image data and a fully connected layer to process numerical data. The deep fusion model can respectively send numerical data and image data into respective neural networks for feature extraction and classification prediction, and connect the outputs of the numerical data and the image data into a full-connection layer for comprehensive learning and classification prediction. This approach may use multiple neural network models, such as a convolutional neural network and a fully-connected neural network, to handle different types of features. While this embodiment mainly uses an attention fusion model that uses an attention mechanism to weight fuse different types of features. The method can respectively perform characteristic extraction on the digital data and the image data.

Specifically, the input layer performs data preprocessing and data feature extraction on the digital data to obtain data features, and the three-dimensional shape detection image is used for performing image feature extraction on the image data to obtain image features, wherein the digital data is used as neurons of the input layer, the digital data is subjected to feature extraction and conversion through a plurality of full-connection layers to obtain a digital feature vector with a dimension d, and the image feature extraction can use a visual transducer (such as ViT) to process the image data and extract the image features. It is assumed that an image feature vector of dimension d is obtained and then the attention mechanism is used at the attention mechanism layer to weight the fused numerical feature and the image feature. The importance weight of each feature can be calculated by using a self-attention mechanism (self-attention), so as to obtain attention weight vectors of the numerical feature and the image feature, then the numerical feature vector and the image feature vector are weighted and fused according to the attention weight, so as to obtain a final fusion feature vector, and finally the fusion feature vector is input into a full-connection layer for classification prediction. This layer may include multiple fully connected layers, activation functions, and loss functions for training and optimization of the model.

Further, before the three-dimensional morphology detection image in the image detection process section is obtained, the three-dimensional morphology detection image and the chip process parameters are preprocessed and then input into the corresponding chip process detection model, the method further comprises the steps of: the method comprises the steps of obtaining the resolution of optical lens equipment corresponding to each image processing section, and calculating the number of scanning layers corresponding to each image processing section according to a preset super-depth-of-field synthetic imaging algorithm and the resolution; the optical lens equipment of the corresponding image processing section is controlled based on the scanning layer number to perform three-dimensional morphology detection on the target chip produced in the target time section, so that depth images of different scanning layers of each image processing section are obtained; and combining the depth images of the different scanning layers to generate three-dimensional morphology detection images of each image processing section.

Specifically, it is first necessary to know the resolution of the optical lens device used, i.e., the details of the image that can be captured and the pixel density. This is an important parameter for calculating the number of scan layers. According to a preset super-depth-of-field synthetic imaging algorithm and the resolution of the optical lens device, the number of scanning layers required by each image processing section can be calculated. The super depth of field synthetic imaging algorithm can extend the clear area of an image by multiple focalizations or superposition of multiple images. And according to the calculated scanning layer number, detecting the three-dimensional morphology of the target chip by using corresponding optical lens equipment. The depth information of each image processing section can be obtained through the scanning of different scanning layers. And finally, splicing and merging the depth images of different scanning layers to generate a final three-dimensional morphology detection image. Thus, the complete three-dimensional morphology information of each image processing section can be obtained. For each image processing section, three-dimensional morphology detection is performed first, and depth images of different scanning layers are obtained. Ensuring that each depth image is aligned with the same coordinate system and has the same size and image format. Since there may be a slight positional deviation of different scan layers, an image alignment operation is required. Each pair of adjacent depth images may be aligned to have consistent features in the same region using a particular image registration algorithm, such as feature matching, phase correlation, mutual information, etc. And fusing the aligned depth images to generate a final three-dimensional morphology detection image. Common fusion methods include weighted averaging, image fusion algorithms (e.g., poisson reconstruction), multi-view stereo matching, and the like. In the fusion process, the weights of the images with different depths can be adjusted according to actual requirements so as to control the contribution degrees of different scanning layers. Finally, according to the requirements, further post-processing operations such as denoising, smoothing, edge enhancement and the like can be carried out on the fused image so as to improve the image quality and definition and obtain a three-dimensional morphology detection image.

Further, the calculating, by the classification layer, the process yield of the corresponding device node in the target time period according to the fusion feature vector, and outputting, by the output layer, the process yield includes: mapping the fusion feature vector to a high-dimensional feature space through the classification layer in a linear transformation way to obtain a linear transformation result; nonlinear transformation is carried out on the linear transformation result through a preset activation function, and a nonlinear transformation result is obtained; calculating the probability of the corresponding equipment node in the process yield interval corresponding to the target time period according to the nonlinear transformation result through a full-connection layer in the classification layer; and taking the process yield interval with the highest probability as the process yield corresponding to the corresponding equipment node in the target time period, and outputting the process yield through the output layer.

Specifically, the obtained fusion feature vector is used as the input of the full connection layer, and the fusion feature vector is mapped to a feature space with higher dimension through linear transformation. This linear transformation is typically a fully connected layer, which contains a plurality of neurons (nodes), each connected to each element of the fused feature vector. And carrying out nonlinear transformation on the result of the linear transformation, and introducing nonlinear relation to increase the expression capacity of the model. Common activation functions include ReLU, sigmoid, tanh, etc. The choice of activation function depends on the specific task and model design. The design of the output layer may also vary depending on the task. For example, for a classification task, a neuron may be used and a sigmoid activation function applied to output a probability value between 0 and 1; for multi-class tasks, multiple neurons may be used and a softmax activation function applied to output the probability distribution for each class. And obtaining the corresponding process yield of the corresponding equipment node in the target time period according to the result of the output layer.

103. Calculating the process passing rate of the target LED chip produced in the target time period based on the weight data corresponding to each equipment node and the corresponding process yield;

In one embodiment of the invention, the weights of the different device nodes may be determined according to their degree of impact on the chip process. For example, for critical nodes such as lithographic and etching equipment, the weights may be higher, as they have a decisive role for the pattern and structural morphology of the chip; while the weight for the nodes such as wafer processing equipment and deposition equipment may be somewhat lower because they have a relatively small degree of impact on the surface topography and material properties of the chip. When the process passing rate of the target LED chip produced in the target time period is calculated, the weight of each equipment node and the process yield can be combined for use. For example, for a process flow consisting of 5 equipment nodes, the weights of the process flow are set to be w1, w2, w3, w4, w5, and the corresponding process yields are r1, r2, r3, r4, r5, respectively, and then the overall process yield of the process flow can be calculated as:

Integrated process yield = w1×r1+w2×r2+w3×r3+w4×r4+w5×r5

Finally, according to the calculated comprehensive process yield, the process passing rate of the target LED chip produced in the target time period can be predicted. If the overall process yield is high, the predicted process throughput will be correspondingly increased, and vice versa. In addition, in actual production, the process can be adjusted and optimized according to the real-time monitoring data so as to further improve the process passing rate.

104. Determining the product grade of the target LED chip produced in the target time period based on the process passing rate, and judging whether the product grade is a preset defective grade or not;

in one embodiment of the present invention, the process throughput is an important indicator for evaluating the quality of the chip during the production of the LED chip. When determining the product grade of the target LED chip produced in the target time period, whether the quality of the chip meets the expectations or not can be judged according to the process passing rate, and the chips are classified into different grades. Generally, the higher the process throughput, the higher the quality of the chip. Therefore, at high process throughput, the chips produced may be classified as high-grade products. For example, chips with process pass rates above 90% may be classified as class a products, chips with process pass rates between 80% and 90% may be classified as class B products, and chips below 80% may be classified as class C products. In addition, it is also necessary to determine whether the chip is defective or not while determining the product grade. Generally, for a predetermined defective grade, only chips with a process pass rate lower than a certain value (e.g., 20%) are identified as defective. If the process pass rate of the chip is above the threshold, then even if some defects or flaws are present, it may be considered a good product. In actual production, specific product grades and defective product grades can be formulated according to actual conditions and market demands of enterprises. In order to ensure that the quality of the produced chips meets the requirements of clients, enterprises need to strengthen management in the aspects of process control, equipment maintenance and the like, the process passing rate is continuously improved, and the grading standard is timely adjusted to adapt to market demand changes.

105. If yes, the chip electrical detection is carried out on the target LED chip produced in the target time period, and a chip defect detection result is obtained.

In one embodiment of the present invention, the secondary inspection of the product identified as defective in the previous step, i.e., the electrical inspection, requires the connection of the chip pins to the test instrument in order to electrically test the chip. The wiring scheme is carefully planned to ensure the correct transmission and collection of the test signals, and electrode alignment is required in the process, namely, the accurate contact is performed on the pins of the chip by using metal pins or probes so as to ensure the reliability of the transmission of the test signals and the accuracy of the test results. In chip electrical testing, electrode alignment is a very important step, which relates to the accuracy of test data and the reliability of test results. Because the pitch of the pins of a chip is small, sometimes tens of microns or even less, and the number of pins is typically large, electrode alignment requires high precision equipment and techniques to achieve. In general, electrode alignment requires the use of special needles or probes with very small diameters and high precision tips that can be easily positioned precisely and in contact with the chip pins. It should be noted that the relevant safety regulations and operation procedures should be followed when performing electrode pricking so as not to damage the chip or the test instrument, while also protecting the needle or the probe from affecting the test result. In addition, before electrode alignment, related calibration of test instruments and programming of test programs are required to ensure the accuracy and reliability of test results.

In this embodiment, a plurality of corresponding chip process detection models are selected according to a plurality of equipment nodes, and chip process data of each equipment node in a target time period are respectively input into the corresponding chip process detection models, so as to obtain corresponding process yield; calculating the process passing rate of the target LED chip produced in the target time period based on the weight data corresponding to each equipment node and the corresponding process yield; judging whether the product grade of the target LED chip is a preset defective grade or not based on the process passing rate; and carrying out chip electrical detection on the target LED chips with defective product grades to obtain chip defect detection results. The method uses the process data in different process steps before the electrical detection of the LED chip, predicts the shipment quality and grade of the product, only performs electrical measurement on the bad product, reduces the electrical measurement cost, and can reduce the secondary bad rate caused by the electrical measurement of the product.

The method for detecting the defects of the LED chip in the embodiment of the present invention is described above, and the following describes an apparatus for detecting the defects of the LED chip in the embodiment of the present invention, where the apparatus for detecting the defects of the LED chip is applied to an LED chip production system, and the LED chip production system includes a plurality of equipment nodes corresponding to a plurality of process segments in the process of manufacturing the LED chip, referring to fig. 2, and one embodiment of the apparatus for detecting the defects of the LED chip in the embodiment of the present invention includes:

An obtaining module 201, configured to obtain chip process data of each equipment node in the LED chip production system in a target time period;

The yield calculation module 202 is configured to select a plurality of corresponding chip process detection models according to the plurality of equipment nodes, and input the chip process data into the corresponding chip process detection models, respectively, to obtain a process yield corresponding to the target time period by the corresponding equipment nodes;

The passing rate calculation module 203 is configured to calculate a process passing rate of the target LED chip produced in the target time period based on the weight data corresponding to each equipment node and the corresponding process yield;

a judging module 204, configured to determine a product level of a target LED chip produced in the target time period based on the process passing rate, and judge whether the product level is a preset defective product level;

And the electrical inspection module 205 is configured to perform chip electrical inspection on the target LED chip produced in the target time period if the product grade is a defective grade, so as to obtain a chip defect detection result.

In the embodiment of the invention, the LED chip defect detection device runs the LED chip defect detection method, and the LED chip defect detection device obtains the corresponding process yield by respectively selecting a plurality of corresponding chip process detection models according to a plurality of equipment nodes and respectively inputting the chip process data of each equipment node in a target time period into the corresponding chip process detection models; calculating the process passing rate of the target LED chip produced in the target time period based on the weight data corresponding to each equipment node and the corresponding process yield; judging whether the product grade of the target LED chip is a preset defective grade or not based on the process passing rate; and carrying out chip electrical detection on the target LED chips with defective product grades to obtain chip defect detection results. The method uses the process data in different process steps before the electrical detection of the LED chip, predicts the shipment quality and grade of the product, only performs electrical measurement on the bad product, reduces the electrical measurement cost, and can reduce the secondary bad rate caused by the electrical measurement of the product.

The above-mentioned fig. 2 describes the device for detecting defects of a middle LED chip in the embodiment of the present invention in detail from the point of view of modularized functional entities, and the following describes the device for detecting defects of a LED chip in the embodiment of the present invention in detail from the point of view of hardware processing.

Fig. 3 is a schematic structural diagram of an LED chip defect detection apparatus according to an embodiment of the present invention, where the LED chip defect detection apparatus 300 may have a relatively large difference due to different configurations or performances, and may include one or more processors (central processing units, CPU) 310 (e.g., one or more processors) and a memory 320, and one or more storage mediums 330 (e.g., one or more mass storage devices) storing application programs 333 or data 332. Wherein memory 320 and storage medium 330 may be transitory or persistent storage. The program stored in the storage medium 330 may include one or more modules (not shown), each of which may include a series of instruction operations in the LED chip defect detection apparatus 300. Still further, the processor 310 may be configured to communicate with the storage medium 330 and execute a series of instruction operations in the storage medium 330 on the LED chip defect detection apparatus 300 to implement the steps of the LED chip defect detection method described above.

The LED chip defect detection apparatus 300 may also include one or more power supplies 340, one or more wired or wireless network interfaces 350, one or more input/output interfaces 360, and/or one or more operating systems 331, such as Windows Serve, mac OS X, unix, linux, freeBSD, and the like. It will be appreciated by those skilled in the art that the configuration of the LED chip defect detection apparatus shown in fig. 3 is not limiting of the LED chip defect detection apparatus provided by the present invention, and may include more or fewer components than shown, or may combine certain components, or may be arranged in different components.

The present invention also provides a computer readable storage medium, which may be a non-volatile computer readable storage medium, and may also be a volatile computer readable storage medium, where instructions are stored in the computer readable storage medium, when the instructions are executed on a computer, cause the computer to perform the steps of the LED chip defect detection method.

It will be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working process of the system or apparatus and unit described above may refer to the corresponding process in the foregoing method embodiment, which is not repeated herein.

The integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied essentially or in part or all of the technical solution or in part in the form of a software product stored in a storage medium, including instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a read-only memory (ROM), a random access memory (random access memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.

The above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. The LED chip defect detection method is characterized by being applied to an LED chip production system, wherein the LED chip production system comprises a plurality of equipment nodes corresponding to a plurality of process sections of an LED chip in the process; the LED chip defect detection method comprises the following steps:

2. The method of claim 1, wherein the chip process data comprises chip process parameters and/or three-dimensional topography detection images;

3. The method for detecting defects of an LED chip according to claim 2, wherein said preprocessing the chip process parameters and then inputting the preprocessed chip process parameters into corresponding chip process detection models, respectively, to obtain the process yield of the corresponding equipment node corresponding to the target time period comprises:

4. The method for detecting defects of an LED chip according to claim 3, wherein said performing data preprocessing and data feature extraction on said chip process parameters through said input layer, obtaining data features comprises:

5. The method of claim 2, wherein the obtaining a three-dimensional feature detection image in the image detection process segment, preprocessing the three-dimensional feature detection image and the chip process parameters, and inputting the preprocessed three-dimensional feature detection image and the preprocessed chip process parameters into a corresponding chip process detection model, and obtaining a process yield corresponding to the corresponding equipment node in the target time segment comprises:

6. The method of claim 5, further comprising, before the step of obtaining the three-dimensional topography detection image in the image detection process section and preprocessing the three-dimensional topography detection image and the chip process parameters and inputting the preprocessed three-dimensional topography detection image and the chip process parameters into a corresponding chip process detection model:

7. The method of claim 5, wherein the calculating, by the classification layer, a process yield of the corresponding device node in the target period according to the fusion feature vector, and outputting, by the output layer, the process yield comprises:

8. The LED chip defect detection device is characterized by being applied to an LED chip production system, wherein the LED chip production system comprises a plurality of equipment nodes corresponding to a plurality of process sections of an LED chip in the process; the LED chip defect detection device comprises:

9. An LED chip defect detection apparatus, characterized in that the LED chip defect detection apparatus comprises: a memory and at least one processor, the memory having instructions stored therein;

The at least one processor invokes the instructions in the memory to cause the LED chip defect detection apparatus to perform the steps of the LED chip defect detection method according to any one of claims 1-7.

10. A computer readable storage medium having instructions stored thereon, which when executed by a processor, implement the steps of the LED chip defect detection method according to any of claims 1-7.