CN118102729A

CN118102729A - Three-dimensional memory device and method of forming the same

Info

Publication number: CN118102729A
Application number: CN202211502869.7A
Authority: CN
Inventors: 吴林春; 张坤; 周文犀; 吴双双; 夏志良; 霍宗亮
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2022-11-28
Filing date: 2022-11-28
Publication date: 2024-05-28

Abstract

A three-dimensional (3D) memory device comprising: a stacked structure including staggered first conductive layers and first dielectric layers; a channel structure extending through the stack structure in a first direction, the channel structure being in contact with the first semiconductor layer at a bottom portion of the channel structure; and a slit structure extending through the stacked structure in a first direction. The slot structure includes a slot core, and a second dielectric layer surrounding the slot core. The first width of the second dielectric layer proximate the first semiconductor layer is greater than the second width of the second dielectric layer distal the first semiconductor layer.

Description

Three-dimensional memory device and method of forming the same

Background

The present disclosure relates to three-dimensional (3D) memory devices and methods of making the same.

Planar memory cells have been scaled down to smaller dimensions by improving process technology, circuit design, programming algorithms, and fabrication processes. But planar processing and fabrication techniques become challenging and costly as the feature size of the memory cell approaches the lower limit. Therefore, the storage density of the planar memory cell approaches the upper limit. As the number of 3D memory layers continues to increase, control of the channel profile becomes increasingly difficult.

Disclosure of Invention

In one aspect, a 3D memory device is disclosed. The 3D memory device includes: a stacked structure including staggered first conductive layers and first dielectric layers; a channel structure extending through the stack structure in a first direction, the channel structure being in contact with the first semiconductor layer at a bottom portion of the channel structure; and a slit structure extending through the stacked structure in the first direction. The slot structure includes a slot core and a second dielectric layer surrounding the slot core. The first width of the second dielectric layer proximate the first semiconductor layer is greater than the second width of the second dielectric layer distal the first semiconductor layer.

In some embodiments, the channel structure includes a semiconductor channel and a memory film over the semiconductor channel. The semiconductor channel includes an angled (angled) structure, and a third width of the semiconductor channel at a bottom portion of the channel structure that is below the angled structure is less than a fourth width of the semiconductor channel at an upper portion of the channel structure that is above the angled structure.

In some implementations, the 3D memory device further includes a second semiconductor layer located under the stacked structure. The second semiconductor layer is located below a bottom surface of the second dielectric layer.

In some embodiments, the second semiconductor layer is located below a bottom surface of the semiconductor channel, and a top surface of the second semiconductor layer is treated with ammonia (NH ₃).

In some embodiments, the second semiconductor layer comprises a p-type doped polysilicon layer.

In some implementations, the 3D memory device further includes a third semiconductor layer located between the second semiconductor layer and the stacked structure. The top surface of the third semiconductor layer is coplanar with the bottom surface of the second dielectric layer.

In some embodiments, the third semiconductor layer includes an undoped polysilicon layer, and a top surface of the third semiconductor layer is treated with ammonia (NH ₃).

In another aspect, a 3D memory device is disclosed. The 3D memory device includes: a first stacked structure including a first semiconductor layer, a second semiconductor layer over the first semiconductor layer, and a third semiconductor layer surrounding the first semiconductor layer and the second semiconductor layer; a second stack structure located above the first stack structure, the second stack structure including staggered first conductive layers and first dielectric layers; and a channel structure extending through the second stack structure in the first direction, the channel structure being in contact with the third semiconductor layer at a bottom portion of the channel structure.

In some implementations, the 3D memory device further includes a slit structure extending through the second stack structure in the first direction. The slot structure includes a slot core extending through the second stack structure in the first direction and in contact with the third semiconductor layer, and a second dielectric layer surrounding the slot core. The first width of the second dielectric layer contacting the third semiconductor layer is greater than the second width of the second dielectric layer away from the third semiconductor layer.

In some embodiments, the channel structure includes a semiconductor channel and a memory film over the semiconductor channel. The semiconductor channel includes an angled structure, and a third width of the semiconductor channel at a bottom portion of the channel structure below the angled structure is less than a fourth width of the semiconductor channel at an upper portion of the channel structure above the angled structure.

In some embodiments, the first semiconductor layer comprises a p-type doped polysilicon layer and the second semiconductor layer comprises an undoped polysilicon layer.

In yet another aspect, a method for forming a 3D memory device is disclosed. A first semiconductor layer, a first dielectric layer, and a second semiconductor layer are formed on a substrate. A second dielectric layer is formed extending through the second semiconductor layer, the first dielectric layer and the first semiconductor layer and in contact with the substrate. A dielectric stack including staggered third and fourth dielectric layers is formed over the second semiconductor layer and the second dielectric layer. A channel hole is formed through the dielectric stack, the second semiconductor layer, the first dielectric layer, and the first semiconductor layer to expose the substrate. An oxidation operation is performed to form a fifth dielectric layer on the first semiconductor layer exposed through the sidewall of the channel hole. A channel structure is formed in the channel hole. The substrate, the fifth dielectric layer, and a bottom portion of the channel structure are removed. A third semiconductor layer is formed over the channel structure.

In some embodiments, a trench is formed extending through the second semiconductor layer, the first dielectric layer, and the first semiconductor layer to expose the substrate, and the second dielectric layer is formed in the trench.

In some embodiments, an ammonia (NH ₃) treatment is performed on top surfaces of the first semiconductor layer and the second semiconductor layer.

In some embodiments, a gate line slit opening is formed extending through the dielectric stack and the second dielectric layer. The first semiconductor layer and the gate line slit opening are separated by the second dielectric layer.

In some embodiments, the fourth dielectric layer is replaced with a first conductive layer through the gate line slit opening, and a slit structure is formed in the gate line slit opening.

In some embodiments, a planarization operation is performed to remove the substrate, the bottom portion of the channel structure, and the bottom portion of the slit structure, and to remove portions of the second dielectric layer and the fifth dielectric layer.

In some embodiments, the etching operation is performed using the second semiconductor layer as a stop layer.

In some embodiments, the channel structure includes a semiconductor channel and a memory film over the semiconductor channel, and a bottom portion of the memory film is removed to expose the semiconductor channel.

In some embodiments, the semiconductor channel is formed over the first semiconductor layer in the channel hole.

Drawings

The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate various aspects of the present disclosure and, together with the description, further serve to explain the disclosure and to enable a person skilled in the pertinent art to make and use the disclosure.

Fig. 1 illustrates a cross-sectional view of an exemplary 3D memory device, according to some aspects of the present disclosure.

Fig. 2 illustrates a cross-sectional view of a bottom portion of a channel structure, in accordance with some aspects of the present disclosure.

Fig. 3-14 illustrate cross-sectional views of an exemplary 3D memory device at various stages of a fabrication process, in accordance with aspects of the present disclosure.

Fig. 15 illustrates a flow chart of an exemplary method for forming a 3D memory device, according to some aspects of the present disclosure.

Fig. 16 illustrates a block diagram of an exemplary system having a memory device, in accordance with aspects of the present disclosure.

Fig. 17A illustrates a view of an exemplary memory card having a memory device, in accordance with some aspects of the present disclosure.

Fig. 17B illustrates a view of an exemplary solid-state drive (SSD) with a memory device, according to some aspects of the present disclosure.

The present disclosure will be described with reference to the accompanying drawings.

Detailed Description

While specific configurations and arrangements are discussed, it should be understood that this discussion is for illustrative purposes only. As such, other configurations and arrangements may be used without departing from the scope of this disclosure. Moreover, the present disclosure may also be employed in a wide variety of other applications. The functional and structural features described in the present disclosure may be combined, adjusted, and modified with each other in a manner not specifically shown in the drawings so that they are within the scope of the present disclosure.

Generally, terms may be understood, at least in part, by use in the context. For example, the term "one or more" as used herein may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe a combination of features, structures, or characteristics in a plural sense, at least in part depending on the context. Similarly, terms such as "a," "an," or "the" may also be construed as conveying either singular usage or plural usage, depending at least in part on the context. Furthermore, the term "based on" may be understood as not necessarily intended to convey an exclusive set of factors, but rather may allow for the presence of additional factors that may not be explicitly stated, again depending at least in part on the context.

It should be readily understood that the meanings of "on … …", "over … …" and "over … …" in this disclosure should be interpreted in the broadest sense so that "on … …" means not only directly on something but also includes meaning that something is "on" with intermediate features or layers therebetween, and "over … …" or "over … …" means not only the meaning that something is "over" or "over" but also can include the meaning that something is "over" or "over" with no intermediate features or layers therebetween (i.e., directly on something).

Furthermore, spatially relative terms, such as "below," "lower," "above," "upper," and the like, may be used herein for ease of description to describe one element or feature's relationship to one or more additional elements or features as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

As used herein, the term "layer" refers to a portion of material that includes regions having a certain thickness. The layer may extend over the entire underlying or overlying structure, or may have a range that is less than the range of the underlying or overlying structure. Furthermore, the layer may be a region in a homogeneous or heterogeneous continuous structure, the thickness of the region being less than the thickness of the continuous structure. For example, the layers may be located between any pair of horizontal planes between the top and bottom surfaces of the continuous structure, or at the top and bottom surfaces of the continuous structure. The layers may extend horizontally, vertically, and/or along a tapered surface. The substrate may be a layer, may include one or more layers therein, and/or may have one or more layers located thereon, and/or thereunder. The layer may comprise a plurality of layers. For example, the interconnect layer may include one or more conductors and contact layers (in which interconnect lines and/or via contacts are formed) and one or more dielectric layers.

As used herein, the term "substrate" refers to a material to which subsequent layers of material are added. The substrate itself can be patterned. The material added atop the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be composed of a non-conductive material such as glass, plastic, or sapphire wafer.

As used herein, the term "3D memory device" refers to a semiconductor device having vertically oriented strings of memory cell transistors (referred to herein as "memory strings", e.g., NAND memory strings) located on a laterally oriented substrate such that the memory strings extend in a vertical direction relative to the substrate. As used herein, the term "vertically" refers to a lateral surface nominally perpendicular to a substrate.

The 3D semiconductor device may be formed by stacking semiconductor wafers or dies and vertically interconnecting them such that the resulting structure functions as a single device, thereby achieving improved performance with reduced power and smaller footprint than conventional planar processes. However, as the number of 3D memory layers continues to increase, control of the channel profile becomes increasingly difficult.

Fig. 1 illustrates a cross-sectional view of an exemplary 3D memory device 100 in accordance with some aspects of the present disclosure. As shown in fig. 1, the 3D memory device 100 includes a stack structure 111, a channel structure 118 extending through the stack structure 111 in the z-direction, and a channel structure 119 also extending through the stack structure 111 in the z-direction. In some embodiments, channel structure 118 and channel structure 119 extend vertically through stacked structure 111 in the z-direction. The stacked structure 111 may include alternating conductive layers 113 and dielectric layers 107, and these stacked conductive/dielectric layer pairs are also referred to as memory stacks. In some embodiments, the dielectric layer 107 may comprise a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some embodiments, the conductive layer 113 may form a word line and may include a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof.

Channel structure 118 and channel structure 119 may extend through stack structure 111, and the bottoms of channel structure 118 and channel structure 119 may contact the source of 3D memory device 100. In some implementations, the channel structure 118 can include a semiconductor channel 132 and a memory film 125 formed over the semiconductor channel 132. The meaning of "over" here should be interpreted as being "over" something from the top side or from the lateral side, in addition to having the explanation set forth above. In some embodiments, the channel structure 118 may further include a dielectric core 129 located at the center of the channel structure 118. In some implementations, the memory film 125 can include a tunneling layer 130 over the semiconductor channel 132, a storage layer 128 over the tunneling layer 130, and a barrier layer 126 over the storage layer 128.

According to some embodiments, the dielectric core 129, the semiconductor channel 132, the tunneling layer 130, the memory layer 128, and the barrier layer 126 are arranged radially from the center of the channel structure 118 to the outer surface in this order. In some implementations, the tunneling layer 130 may include silicon oxide, silicon oxynitride, or any combination thereof. In some embodiments, the memory layer 128 may include silicon nitride, silicon oxynitride, silicon, or any combination thereof. In some implementations, the barrier layer 126 may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory film may include a silicon oxide/silicon oxynitride (or silicon nitride)/silicon oxide (ONO) composite layer.

As shown in fig. 1, the channel structure 118 and the channel structure 119 may have similar structures, but the bottom portions of the channel structure 118 and the channel structure 119 are different. The bottom portion of channel structure 118 includes semiconductor channel 132 that extends into semiconductor layer 136, and the bottom portion of channel structure 119 includes semiconductor channel 132 that does not extend into semiconductor layer 136. The differences between channel structure 118 and channel structure 119 will be discussed further below in fig. 2.

As shown in fig. 1, a dummy channel structure 124 extending in the z-direction may be formed in the stacked structure 111. In some embodiments, contact structures 134 extending in the z-direction may be formed in the stacked structure 111. It should be appreciated that in an actual structure, the stacked structure 111 and the stair-step structure (including the dummy channel structure 124 and/or the contact structure 134) may not be visible in the same cross-sectional view. For better description of the present disclosure, cross-sectional views of the stacked structure 111 and the stepped region are shown in the same drawing in the present disclosure, and coordinates in x-direction and y-direction are labeled in fig. 1 to show verticality of the cross-sectional views of the stacked structure 111 and the stepped region.

As shown in fig. 1, a gate line slit 133 extending in the z-direction may be formed in the stacked structure 111. In some embodiments, gate line slit 133 may include dielectric layer 135, dielectric layer 139, and a slit core, e.g., conductive layer 141. In some embodiments, dielectric layer 135 and dielectric layer 139 may surround conductive layer 141. In some embodiments, the conductive layer 141 may further include one or more conductive layers, such as polysilicon, tungsten (W), or a combination of polysilicon and W. As shown in fig. 1, dielectric layer 135 and dielectric layer 139 may have different widths in the cross-sectional view of 3D memory device 100. In some embodiments, the width of dielectric layer 135 may be greater than the width of dielectric layer 139 in a cross-sectional view of 3D memory device 100. In other words, in a cross-sectional view of 3D memory device 100, the width of dielectric layer 135 proximate to the source of 3D memory device 100 may be greater than the width of dielectric layer 139 distal from the source of 3D memory device 100.

In some implementations, a peripheral device may be formed above or below the 3D memory device 100, and the conductive path formed by the contact structures 134 may be used to connect the peripheral device. For example, the source terminal of the 3D memory device 100 may be connected to a peripheral device through a conductive path formed by one or more contact structures 134, and thus the peripheral device may control the operation of the 3D memory device 100. In some implementations, the conductive path formed by the contact structures 134 may be used to connect other devices disposed above, below, or beside the 3D memory device 100. In some implementations, the peripheral device may include one or more peripheral circuits. In some implementations, peripheral circuitry may be electrically connected to 3D memory device 100 through conductive lines (e.g., redistribution layers).

Fig. 2 illustrates a cross-sectional view of a bottom portion of channel structure 118 and channel structure 119 of 3D memory device 100, according to some aspects of the present disclosure. As shown in fig. 2, the bottom portions of channel structure 118 and channel structure 119 may include a folded structure of semiconductor channel 132, tunneling layer 130, and memory layer 128. As shown in fig. 1 and 2, the semiconductor layer 136 may be disposed under the stack structure 111. In some embodiments, the semiconductor layer 136 may be a conductive layer. In some embodiments, the semiconductor layer 136 may be a polysilicon layer. In some embodiments, semiconductor layer 136 is in direct contact with semiconductor channel 132. In some embodiments, the semiconductor layer 136 is in direct contact with a bottom surface of the semiconductor channel 132 and a portion of a side surface of the semiconductor channel 132 at a bottom portion of the channel structure 118. In some implementations, the bottom surface of the memory film 125, including the barrier layer 126, the storage layer 128, and the tunneling layer 130, is located above the bottom surface of the semiconductor channel 132, as shown in fig. 2.

The difference between channel structure 118 and channel structure 119 is the bottom of the channel structure. In some embodiments, the difference between channel structure 118 and channel structure 119 is a bottom portion of semiconductor channel 132. A bottom portion of semiconductor channel 132 of channel structure 118 may extend into semiconductor layer 136, while a bottom portion of semiconductor channel 132 of channel structure 119 may not extend into semiconductor layer 136. In some embodiments, channel structure 118 and channel structure 119 may have the same structure.

In some embodiments, each of the channel structure 118 and the channel structure 119 may have a circular structure in a plan view of the 3D memory device 100. In some embodiments, dielectric core 129, semiconductor channel 132, tunneling layer 130, memory layer 128, and barrier layer 126 are disposed radially from the center of channel structure 118 and channel structure 119 to the outer surface. As shown in fig. 2, the semiconductor channel 132 at the bottom portion of the channel structure 118 and the channel structure 119 may have a different diameter than the semiconductor channel 132 at the upper portion of the channel structure 118 and the channel structure 119. In some embodiments, in a plan view of the 3D memory device 100, the semiconductor channels 132 at the bottom portions of the channel structures 118 and 119 may have an outside diameter or outside width W1, and the semiconductor channels 132 at the upper portions of the channel structures 118 and 119 may have an outside diameter or outside width W2, and W1 is less than W2. Here, upper portions of the channel structures 118 and 119 refer to the channel structures 118 and 119 located above the bent structures, and bottom portions of the channel structures 118 and 119 refer to the channel structures 118 and 119 located below the bent structures, as shown in fig. 2.

In some embodiments, the bent structures of channel structure 118 and channel structure 119 may be formed as angled structures in the cross-sectional views of channel structure 118 and channel structure 119. For example, as shown in fig. 2, the semiconductor channel 132 may be formed as two right angle mechanisms. In some embodiments, the semiconductor channel 132 may be formed as obtuse angle structures, acute angle structures, right angle structures, radian angle structures, or any combination of these angled structures. The outside diameter W1 of the semiconductor channel 132 at the bottom portion of the channel structure 118 and the channel structure 119 located below the angled structure is smaller than the outside diameter W2 of the semiconductor channel 132 at the upper portion of the channel structure 118 and the channel structure 119 located above the angled structure.

In some embodiments, as shown in fig. 1, a semiconductor layer 106 (e.g., a first semiconductor layer) may be formed under the stack structure 111. In some embodiments, semiconductor layer 106 may be formed below a bottom surface of dielectric layer 135. In some embodiments, the semiconductor layer 106 may be formed below a bottom surface of the semiconductor channel 132 of the channel structure 119. In some embodiments, the semiconductor layer 106 may be a p-type doped (p-doped) polysilicon layer.

In some embodiments, the semiconductor layer 110 (e.g., a second semiconductor layer) may be formed between the semiconductor layer 136 and the stack structure 111. In some embodiments, a dielectric layer 116 may be formed between the semiconductor layer 110 and the channel structure 118. In other words, the dielectric layer 116 insulates the channel structure 118 from the semiconductor layer 110. Note that in some embodiments, dielectric layer 116 and barrier layer 126 may be formed of the same material (e.g., silicon oxide), and that in a cross-sectional view of 3D memory device 100, semiconductor layer 110 may be in contact with channel structure 118 through dielectric layer 116.

In some embodiments, the semiconductor layer 110 may be formed between the semiconductor layer 106 and the stacked structure 111. In some embodiments, the top surface of semiconductor layer 110 is coplanar with the bottom surface of dielectric layer 135. In some embodiments, the semiconductor layer 110 may be an undoped polysilicon layer.

Fig. 3-14 illustrate cross-sectional views of a 3D memory device 100 at different stages of a manufacturing process, according to some aspects of the present disclosure. Fig. 15 illustrates a flow chart of an exemplary method 1500 for forming a 3D memory device 100 in accordance with some aspects of the present disclosure. To better describe the present disclosure, cross-sectional views of the 3D memory device 100 in fig. 3-14 are discussed with the method 1500 in fig. 15. It should be understood that the operations shown in method 1500 are not exclusive and that other operations may be performed before, after, or between any of the operations shown. Further, some of these operations may be performed simultaneously, or may be performed in a different order than shown in fig. 3-14 and 15.

As shown in fig. 3 and operation 1502 in fig. 15, a dielectric layer 104, a semiconductor layer 106, a dielectric layer 108, a semiconductor layer 110, a dielectric layer 117, a dielectric layer 121, and a dielectric layer 123 may be sequentially formed on a substrate 102.

In some embodiments, the substrate 102 may be a doped or undoped semiconductor layer. In some embodiments, the dielectric layer 104 may be a silicon oxide layer. In some embodiments, the semiconductor layer 106 may be a p-type doped (p-doped) polysilicon layer. In some embodiments, the dielectric layer 108 may be a silicon oxide layer. In some embodiments, the semiconductor layer 110 may be an undoped polysilicon layer. In some embodiments, dielectric layer 117 may be a silicon oxide layer. In some embodiments, dielectric layer 121 may be a silicon nitride layer. In some embodiments, the dielectric layer 123 may be a silicon oxide layer. In some embodiments, dielectric layer 104, semiconductor layer 106, dielectric layer 108, semiconductor layer 110, dielectric layer 117, dielectric layer 121, and dielectric layer 123 may be deposited sequentially by one or more thin film deposition processes including, but not limited to, chemical vapor deposition (chemical vapor deposition, CVD), physical vapor deposition (physical vapor deposition, PVD), atomic layer deposition (atomic layer deposition, ALD), or combinations thereof.

In some embodiments, semiconductor layer 106 may have an oxidation rate that is higher than an oxidation rate of semiconductor layer 110. In some embodiments, after the semiconductor layer 106 and the semiconductor layer 110 are formed, ammonia (NH ₃) treatment may be performed on the semiconductor layer 106 and the semiconductor layer 110. In some embodiments, NH ₃ treatment may be performed on top surfaces of semiconductor layer 106 and semiconductor layer 110. In some embodiments, NH ₃ treatment of the top surfaces of semiconductor layer 106 and semiconductor layer 110 may prevent formation of an oxide layer along the top surfaces of semiconductor layer 106 and semiconductor layer 110 in a later oxidation process. In some embodiments, the thickness of semiconductor layer 106 is greater than the thickness of semiconductor layer 110.

As shown in fig. 4 and 5, and operation 1504 in fig. 15, a dielectric layer 135 may be formed that extends through dielectric layer 117, semiconductor layer 110, dielectric layer 108, semiconductor layer 106, and dielectric layer 104 and contacts substrate 102. In some embodiments, an opening 127 may be first formed in the dielectric layer 104, the semiconductor layer 106, the dielectric layer 108, the semiconductor layer 110, the dielectric layer 117, the dielectric layer 121, and the dielectric layer 123 to expose the substrate 102, as shown in fig. 4. In some embodiments, the opening 127 may be formed by employing dry etching, wet etching, or other suitable process. Thereafter, a dielectric layer 135 may be formed in the opening 127, and a planarization operation (e.g., a Chemical Mechanical Polishing (CMP) process) may be performed to remove portions of the dielectric layer 135, the dielectric layer 121, and the dielectric layer 123, as shown in fig. 5.

In some embodiments, dielectric layer 135 may be used as a barrier in a later oxidation operation, thereby restricting the oxidation operation of semiconductor layer 106 to be performed in a predefined region. In some implementations, dielectric layer 135 may be used to limit oxidation of semiconductor layer 106 in the core region of 3D memory device 100. Since the thickness of the semiconductor layer 106 will become different after the oxidation operation, the dielectric layer 135 can prevent the occurrence of the non-uniformity of the semiconductor layer 106 in the stepped region.

As shown in fig. 6 and operation 1506 in fig. 15, a dielectric stack 103 including staggered dielectric layers 107 and 109 may be formed on semiconductor layer 110 and dielectric layer 135. In some embodiments, dielectric stack 103 is formed on dielectric layer 117, semiconductor layer 110, dielectric layer 108, semiconductor layer 106, dielectric layer 104, and dielectric layer 135. In some embodiments, the dielectric layer 109 may be a sacrificial layer and will be removed in a later operation. In some embodiments, each dielectric layer 107 may comprise a layer of silicon oxide, and each dielectric layer 109 may comprise a layer of silicon nitride. In some embodiments, the dielectric stack 103 may be formed by one or more thin film deposition processes (including, but not limited to CVD, PVD, ALD, or any combination thereof).

As shown in fig. 7, and in operation 1508 of fig. 15, one or more channel holes 112 may be formed through the dielectric stack 103, the semiconductor layer 110, and the semiconductor layer 106 to expose the substrate 102. In some embodiments, the channel holes 112 may be vertically formed. In some embodiments, a channel hole 112 extending in the z-direction may be formed. As shown in fig. 7, the semiconductor layer 110 and the semiconductor layer 106 are exposed through the sidewalls of the channel hole 112. In some embodiments, the fabrication process for forming the channel holes 112 may include wet etching and/or dry etching, for example, deep reactive ion etching (DEEP REACTIVE ion etching, DRIE).

As shown in fig. 8 and operation 1510 in fig. 15, an oxidation operation may be performed such that a dielectric layer 114 is formed on the semiconductor layer 106 exposed through the sidewalls of the channel holes 112 and a dielectric layer 116 is formed on the semiconductor layer 110 exposed through the sidewalls of the channel holes 112.

Since semiconductor layer 106 is a p-doped polysilicon layer and semiconductor layer 110 is an undoped polysilicon layer, the oxidation rates of semiconductor layer 106 and semiconductor layer 110 may be different. In some embodiments, the oxidation rate of semiconductor layer 106 exposed through the sidewalls of channel hole 112 is higher than the oxidation rate of semiconductor layer 110 exposed through the sidewalls of channel hole 112.

In some embodiments, since NH ₃ treatment is performed on the top surfaces of the semiconductor layer 106 and the semiconductor layer 110 during formation of the semiconductor layer 106 and the semiconductor layer 110, the dielectric layer 114 and the dielectric layer 116 may be formed on the sidewalls of the channel hole 112 in the x-direction and the y-direction (which are planes perpendicular to the z-direction).

In a plan view of the 3D memory device 100, the channel hole 112 may be circular, and the exposed sidewall may be a circumference of the circular. In some embodiments, the formation of dielectric layer 114 and dielectric layer 116 begins at the circumference of the circle and then extends toward the center of the circle.

In some embodiments, the dielectric layer 114 formed on one side of the semiconductor layer 106 in the channel hole 112 may be in contact with the dielectric layer 114 formed on the other side of the polysilicon layer 106 based on the formation speed of the dielectric layer 114. In some embodiments, the dielectric layer 114 formed on one side of the polysilicon layer 106 in the channel hole 112 may be separated from the dielectric layer 114 formed on the other side of the polysilicon layer 106 by a gap. It should be appreciated that one side or the other of the channel holes 112 described herein is from a cross-sectional view perspective. In a practical structure, the channel hole 112 may be a hole from a plan view perspective, and the dielectric layer 114 formed on the semiconductor layer 106 may be formed from a circumferential direction to a center. In some embodiments, the dielectric layer 114 formed on the semiconductor layer 106 may cover the entire channel hole 112 in a plan view. In some embodiments, the dielectric layer 114 formed on the semiconductor layer 106 may have a gap (hole) located at the center of the channel hole 112 in a plan view. In some embodiments, the width of the gap may be controlled during the forming operation, and the size of the gap may further cause formation of various structures of the memory film in a later process. In some embodiments, the width of the gap may be controlled such that a portion of the memory film or the entire memory film fills in the gap. For example, a memory film including a tunneling layer, a memory layer, and a barrier layer filling the gap may be formed. For another example, a barrier layer may be formed that fills the gap. It should be appreciated that in fig. 8, the size of the gap in the two channel holes 112 is different; however, in other embodiments, the size of the gap in the two channel holes 112 may be the same.

In some embodiments, a dielectric layer 116 may be formed on the semiconductor layer 110 exposed through the sidewalls of the channel hole 112. Since semiconductor layer 106 includes doped polysilicon and semiconductor layer 110 includes undoped polysilicon, the formation rate of dielectric layer 114 may be higher than the formation rate of dielectric layer 116. Thus, the area of dielectric layer 114 may be greater than the area of dielectric layer 116. It should be understood that in the sectional view of fig. 8, the dielectric layer 116 is formed from both sides of the semiconductor layer 110, however, in a plan view of the structure, the dielectric layer 116 is formed from the circumference toward the center on the semiconductor layer 110.

During the oxidation operation, semiconductor layer 106 is divided into two parts by dielectric layer 135: one is a first portion located between the sidewalls of channel hole 112 and dielectric layer 135, and the other is a second portion located behind dielectric layer 135. The oxidation operation of the semiconductor layer 106 may be blocked by the dielectric layer 135 and the oxidation operation of the semiconductor layer 106 will be limited to the region of only the first portion.

As shown in fig. 9, and operation 1512 in fig. 15, a channel structure 118 and a channel structure 119 may be formed in the channel hole 112. Each of the channel structure 118 and the channel structure 119 may include a memory film 125 and a semiconductor channel 132. In some embodiments, each of channel structure 118 and channel structure 119 may further include a dielectric core 129 located at the center of the channel structure. In some implementations, the memory film 125 is a composite layer including a tunneling layer 130, a storage layer 128 (also referred to as a "charge trapping layer"), and a blocking layer 126. The channel structure 118 and the channel structure 119 may have a cylindrical shape (e.g., a pillar shape), and a bottom portion of the cylindrical shape may be shrunk at a portion having the dielectric layer 116 formed on the sidewall of the channel hole 112. In some embodiments, channel structures 118 and 119 may be cone-shaped with a bottom portion of the cone shape being smaller than an upper portion of the cone shape. In this case, the bottom portion of the conical shape may be shrunk at a portion having the dielectric layer 116 formed on the sidewall of the channel hole 112.

In some embodiments, when the dielectric layer 114 formed on the semiconductor layer 106 has a gap (hole) located at the center of the channel hole 112, a memory film 125 including a tunneling layer 130, a memory layer 128, and a blocking layer 126 filling the gap may be formed. In some embodiments, the memory film 125 may completely fill the gap, e.g., the channel structure 119. Thus, by controlling the size of the gap or hole formed by the dielectric layer 114 via the oxidation operation, the portion of the channel structure 118 located above the dielectric layer 114 is formed by the memory film 125 and the semiconductor channel 132. The portion of channel structure 119 that is located below dielectric layer 114 is formed only by memory film 125 including tunneling layer 130, memory layer 128, and blocking layer 126 (ONO layer). In some embodiments, the memory film 125 may not completely fill the gap, and the semiconductor channel 132 may also fill the gap, such as the channel structure 118.

According to some embodiments, the dielectric core 129, the semiconductor channel 132, the tunneling layer 130, the storage layer 128, and the barrier layer 126 are arranged radially from the center of the pillar to the outer surface of the pillar in this order. In some implementations, the tunneling layer 130 may include silicon oxide, silicon oxynitride, or any combination thereof. In some embodiments, the memory layer 128 may include silicon nitride, silicon oxynitride, silicon, or any combination thereof. In some implementations, the barrier layer 126 may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory film 125 may include a silicon oxide/silicon oxynitride (or silicon nitride)/silicon oxide (ONO) composite layer.

A gate line slit opening may be further formed in the z-direction through the dielectric stack 103 and the dielectric layer 135 to expose the substrate 102. The gate line slit opening may be formed by performing dry etching, wet etching, or other suitable processes. In some embodiments, the gate line slit opening may extend to the substrate 102.

Thereafter, a word line replacement operation may be performed, and the dielectric layer 109 may be removed and replaced with a word line (e.g., conductive layer 113). For example, dielectric layer 109 may be removed by dry etching, wet etching, or other suitable process to form a plurality of cavities. The conductive layer 113 may be formed in the cavity by sequentially providing a gate dielectric layer composed of a high-k dielectric material, an adhesive layer including titanium/titanium nitride (Ti/TiN) or tantalum/tantalum nitride (Ta/TaN), and a gate conductor composed of tungsten. After the word line replacement operation, a stacked structure 111 is formed, as shown in fig. 10.

In some embodiments, a removal process may be performed to clean the gate line slit opening. The removal process may remove residues of the previous process from the gate line slit opening. For example, the high-k dielectric material may be removed from the gate line slit opening. Thereafter, in some embodiments, a gate line slit 133 may be formed in the gate line slit opening. In some embodiments, the gate line slit 133 may include a dielectric layer 139, and a slit core, e.g., a conductive layer 141. In some embodiments, the conductive layer 141 may include one or more conductive layers, such as polysilicon, tungsten (W), or a combination of polysilicon and W.

In some embodiments, a dummy channel structure 124 extending in the z-direction may be formed in the stacked structure 111. In some embodiments, contact structures 134 extending in the z-direction may be formed in the stacked structure 111. In some embodiments, 134 may be in contact with semiconductor layer 110. In some embodiments, the gate line slit 133 may be formed before the word line replacement operation. In some embodiments, after forming the gate line slits 133, the dummy channel structures 124, and the contact structures 134 on the substrate 102, one or more interconnect layers may be further formed on the memory array. In addition, peripheral circuits may be formed on another substrate and bonded to the memory array in a later process.

As shown in fig. 11-12, and operation 1514 in fig. 15, a substrate removal operation is performed. In some embodiments, the substrate 102, the bottom portion of the dummy channel structure 124, the bottom portion of the gate line slit 133, the bottom portion of the dielectric layer 135, the bottom portion of the channel structure 118, and the bottom portion of the channel structure 119 may be removed by a CMP process, and the CMP process may stop at the dielectric layer 104. In some embodiments, bottom portions of channel structure 118 and channel structure 119 may be exposed after a CMP process. In some embodiments, the substrate 102 may be peeled off.

In some embodiments where the substrate 102 includes silicon, the substrate 102 may be removed using a silicon CMP, which may automatically stop when a stop layer having a material other than silicon (i.e., a bottom portion of the channel structure 118) is reached. In some embodiments, the substrate 102 may be further removed by wet etching, dry etching, or other suitable process until stopped by the dielectric layer 104. When wet etching is used to remove the substrate 102, the bottom portions of the channel structures 118, the bottom portions of the gate line slits 133, and the bottom portions of the dummy channel structures 124 may remain. In some embodiments, the substrate 102 is removed by tetramethylammonium hydroxide (TMAH) using a wet etch that is automatically stopped when a stop layer (i.e., dielectric layer 104) having a material other than silicon is reached. In some embodiments, the substrate 102 may be removed by a CMP process, and the bottom portion of the channel structure 118, the bottom portion of the gate line slit 133, and the bottom portion of the dummy channel structure 124 may be removed together.

As shown in fig. 12, portions of the dielectric layer 104, the dielectric layer 114, the channel structure 118, and a bottom portion of the channel structure 119, portions of a bottom portion of the gate line slit 133, and portions of a bottom portion of the dummy channel structure 124 may then be removed. In some embodiments, portions of the dielectric layer 104, the dielectric layer 114, the channel structure 118, and the bottom portion of the channel structure 119, portions of the bottom portion of the gate line slit 133, and portions of the bottom portion of the dummy channel structure 124 may be removed by wet etching, dry etching, CMP, or other suitable process.

Since the portion of the channel structure 119 located below the dielectric layer 114 is formed only by the memory film 125 including the tunneling layer 130, the memory layer 128, and the blocking layer 126 (ONO layer), the memory film 125 located below the dielectric layer 114 can also be completely removed when the dielectric layer 104 is removed. In addition, a portion of the channel structure 118 located below the dielectric layer 114 is formed of the memory film 125 and the semiconductor channel 132; upon removal of dielectric layer 104, memory film 125 located below dielectric layer 114 may be completely removed and semiconductor channel 132 may still remain. Thus, by using the polysilicon oxidation operation performed on the semiconductor layer 106, the depths of the channel structures 118 and 119 may be controlled within a predefined range, and the depths or bottom profile of the channel structures 118 and 119 will not be affected by residues formed in the channel holes 112. Thus improving control of the channel profile.

Since the dielectric layer 116 forms protrusions in the x-direction and/or the y-direction on the sidewalls of the channel hole 112 during the formation of the channel structure 118, the bottom portions of the cylindrical shapes of the channel structure 118 and the channel structure 119 are affected by the dielectric layer 116 and form a contracted structure or recess, as shown in fig. 12. After removing the bottom portion of the memory film, in some embodiments, the exposed portions of tunneling layer 130 and storage layer 128 may have smaller critical dimensions (or diameters from a plan view) than tunneling layer 130 and storage layer 128 at the upper portions of channel structure 118 and channel structure 119, as shown in fig. 12. Further, in some embodiments, the exposed portions of semiconductor channel 132 at the bottom portions of channel structure 118 and channel structure 119 also have a smaller critical dimension (or diameter from a plan view) than semiconductor channel 132 at the upper portions of channel structure 118 and channel structure 119.

In another embodiment, the dielectric layer 108 may be removed by a CMP process, and the bottom surfaces of the gate line slits 133 and the bottom surfaces of the dummy channel structures 124 may be coplanar or substantially coplanar with the bottom surface of the semiconductor layer 110.

As shown in fig. 13, and operation 1516 in fig. 15, a semiconductor layer 136 may be formed over the exposed channel structure 118 and channel structure 119. In some embodiments, the semiconductor layer 136 may be formed by CVD, PVD, ALD or other suitable processes.

As shown in fig. 14, a through silicon contact (through silicon contact, TSC) is formed to expose the contact structure, and a spacer layer 137, e.g., a silicon oxide layer, may be formed to cover the sidewalls of the TSC. A contact hole is formed on the spacer layer 137. Thereafter, contact pads 138 are formed in contact with the contact structures 134 or in contact with the semiconductor layer 136.

The channel hole 112 may be completely or partially filled with the dielectric layer 114 by forming the dielectric layer 114 on the semiconductor layer 106 exposed by the sidewalls of the channel hole 112. Thus, bottom portions of channel structure 118 and channel structure 119 may be defined by the locations of dielectric layer 114 and semiconductor layer 106. The bottom portions of channel structure 118 and channel structure 119 are not affected by the channel hole etch notching and therefore will greatly increase the process window for channel hole formation.

Fig. 16 illustrates a block diagram of an example system 1600 having a memory device, in accordance with some aspects of the disclosure. The system 1600 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, gaming machine, printer, positioning device, wearable electronic device, smart sensor, virtual Reality (VR) device, augmented Reality (AR) device, or any other electronic device having a memory bank therein. As shown in fig. 16, the system 1600 may include a host 1608 and a memory system 1602, the memory system 1602 having one or more memory devices 1604, and a memory controller 1606. The host 1608 may be a processor of an electronic device (e.g., a Central Processing Unit (CPU)), or may be a system on a chip (SoC), such as an Application Processor (AP). The host 1608 may be configured to send or receive data to or from the memory device 1604.

The memory device 1604 may be any memory device disclosed in this disclosure. As disclosed in detail above, the memory device 1604 (e.g., a NAND flash memory device) can have a controlled predefined discharge current in a discharge operation that discharges the bit line. According to some implementations, the memory controller 1606 is coupled to the memory device 1604 and the host 1608, and is configured to control the memory device 1604. The memory controller 1606 may manage data stored in the memory device 1604 and communicate with the host 1608. For example, memory controller 1606 may be coupled to memory device 1604 (e.g., 3D memory device 100 described above), and memory controller 1606 may be configured to control operation of channel structure 118 by a peripheral device. By forming a dielectric layer on the polysilicon layer exposed by the sidewalls of the channel holes, the bottom portion of the channel structure will not be affected by the channel hole etch notching and thus will greatly increase the process window for forming the 3D memory device 100.

In some implementations, the memory controller 1606 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, compact Flash (CF) card, universal Serial Bus (USB) flash drive, or other medium used in electronic devices such as personal computers, digital cameras, mobile phones, and the like. In some implementations, the memory controller 1606 is designed to operate in a high duty cycle environment SSD or embedded multimedia card (eMMC), which is used as a data storage for mobile devices such as smartphones, tablets, laptops, etc., as well as enterprise storage arrays. The memory controller 1606 may be configured to control operations of the memory device 1604, such as read, erase, and program operations. The memory controller 1606 may also be configured to manage various functions related to data stored in the memory device 1604 or to be stored in the memory device 1604, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, and the like. In some implementations, memory controller 1606 is further configured to process Error Correction Codes (ECC) related to data read from memory device 1604 or written to memory device 1604. Any other suitable function may also be performed by memory controller 1606, such as formatting memory device 1604. The memory controller 1606 may communicate with external devices (e.g., the host 1608) according to a particular communication protocol. For example, memory controller 1606 may communicate with external devices via at least one of various interface protocols, such as a USB protocol, an MMC protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI-express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a Small Computer Small Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a Firewire protocol, and the like.

The memory controller 1606 and the one or more memory devices 1604 may be integrated in various types of storage devices, e.g., included in the same package, such as a Universal Flash Storage (UFS) package or an eMMC package. That is, the memory system 1602 may be implemented and packaged into different types of terminal electronics. In one example, as shown in fig. 17A, a memory controller 1606 and a single memory device 1604 may be integrated into a memory card 1702. Memory card 1702 may include a PC card (PCMCIA, personal computer memory card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, or the like. The memory card 1702 may further include a memory card connector 1704 that couples the memory card 1702 to a host (e.g., the host 1608 of fig. 16). In another example, as shown in fig. 17B, a memory controller 1606 and a plurality of memory devices 1604 may be integrated into SSD 1706. The SSD1706 may further include an SSD connector 1708 that couples the SSD1706 with a host (e.g., host 1608 in fig. 16). In some implementations, the storage capacity and/or operating speed of the SSD1706 is greater than the storage capacity and/or operating speed of the memory card 1702.

The foregoing description of the specific embodiments may be readily modified and/or adapted for various applications. Therefore, based on the teachings and guidance provided herein, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments.

The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A three-dimensional (3D) memory device, comprising:

a stacked structure including staggered first conductive layers and first dielectric layers;

A channel structure extending through the stack structure in a first direction, the channel structure being in contact with a first semiconductor layer located at a bottom portion of the channel structure; and

A slit structure extending through the stacked structure in the first direction, the slit structure comprising:

A slit core; and

A second dielectric layer surrounding the slot core,

Wherein a first width of the second dielectric layer proximate the first semiconductor layer is greater than a second width of the second dielectric layer distal from the first semiconductor layer.

2. The 3D memory device of claim 1, wherein the channel structure comprises a semiconductor channel and a memory film over the semiconductor channel,

Wherein the semiconductor channel comprises an angled structure and a third width of the semiconductor channel at a bottom portion of the channel structure below the angled structure is less than a fourth width of the semiconductor channel at an upper portion of the channel structure above the angled structure.

3. The 3D memory device of claim 1, further comprising:

a second semiconductor layer located under the stacked structure,

Wherein the second semiconductor layer is located below a bottom surface of the second dielectric layer.

4. The 3D memory device of claim 3, wherein the second semiconductor layer is located below a bottom surface of the semiconductor channel and a top surface of the second semiconductor layer is treated with ammonia (NH ₃).

5. The 3D memory device of claim 3, wherein the second semiconductor layer comprises a p-type doped polysilicon layer.

6. The 3D memory device of claim 3, further comprising:

A third semiconductor layer located between the second semiconductor layer and the stacked structure,

Wherein a top surface of the third semiconductor layer is coplanar with a bottom surface of the second dielectric layer.

7. The 3D memory device of claim 6, wherein the third semiconductor layer comprises an undoped polysilicon layer and a top surface of the third semiconductor layer is treated with ammonia (NH ₃).

8. A three-dimensional (3D) memory device, comprising:

A first stacked structure including a first semiconductor layer, a second semiconductor layer located above the first semiconductor layer, and a third semiconductor layer surrounding the first semiconductor layer and the second semiconductor layer;

A second stack structure located above the first stack structure, the second stack structure including staggered first conductive layers and first dielectric layers; and

A channel structure extending through the second stack structure in a first direction, the channel structure being in contact with the third semiconductor layer at a bottom portion of the channel structure.

9. The 3D memory device of claim 8, further comprising:

a slit structure extending through the second stacked structure in the first direction, the slit structure comprising:

A slit core extending through the second stack structure in the first direction and contacting the third semiconductor layer; and

A second dielectric layer surrounding the slot core,

Wherein a first width of the second dielectric layer contacting the third semiconductor layer is greater than a second width of the second dielectric layer remote from the third semiconductor layer.

10. The 3D memory device of claim 8, wherein the channel structure comprises a semiconductor channel and a memory film over the semiconductor channel,

11. The 3D memory device of claim 8, wherein the first semiconductor layer comprises a p-type doped polysilicon layer and the second semiconductor layer comprises an undoped polysilicon layer.

12. A method for forming a three-dimensional (3D) memory device, comprising:

forming a first semiconductor layer, a first dielectric layer, and a second semiconductor layer on a substrate;

forming a second dielectric layer extending through the second semiconductor layer, the first dielectric layer, and the first semiconductor layer and in contact with the substrate;

forming a dielectric stack including staggered third and fourth dielectric layers on the second semiconductor layer and the second dielectric layer;

Forming a channel hole through the dielectric stack, the second semiconductor layer, the first dielectric layer, and the first semiconductor layer to expose the substrate;

Performing an oxidation operation to form a fifth dielectric layer on the first semiconductor layer exposed through the sidewall of the channel hole;

Forming a channel structure in the channel hole;

Removing the substrate, the fifth dielectric layer, and a bottom portion of the channel structure; and

A third semiconductor layer is formed over the channel structure.

13. The method of claim 12, wherein forming the second dielectric layer extending through the second semiconductor layer, the first dielectric layer, and the first semiconductor layer and in contact with the substrate comprises:

Forming a trench extending through the second semiconductor layer, the first dielectric layer and the first semiconductor layer to expose the substrate; and

The second dielectric layer is formed in the trench.

14. The method of claim 12, further comprising:

an ammonia (NH ₃) treatment is performed on top surfaces of the first semiconductor layer and the second semiconductor layer.

15. The method of claim 12, further comprising:

forming a gate line slit opening extending through the dielectric stack and the second dielectric layer,

Wherein the first semiconductor layer and the gate line slit opening are separated by the second dielectric layer.

16. The method of claim 15, further comprising:

Replacing the fourth dielectric layer with a first conductive layer through the gate line slit opening; and

And forming a gap structure in the gate line gap opening.

17. The method of claim 16, wherein removing the substrate, the fifth dielectric layer, and the bottom portion of the channel structure comprises:

Performing a planarization operation to remove the substrate, the bottom portion of the channel structure, and the bottom portion of the slit structure; and

And removing a part of the second dielectric layer and the fifth dielectric layer.

18. The method of claim 17, wherein removing the portion of the second dielectric layer and the fifth dielectric layer comprises:

An etching operation is performed using the second semiconductor layer as a stop layer.

19. The method of claim 17, wherein the channel structure comprises a semiconductor channel and a memory film over the semiconductor channel, and removing the portion of the second dielectric layer and the fifth dielectric layer comprises:

A bottom portion of the memory film is removed to expose the semiconductor channel.

20. The method of claim 19, wherein forming the channel structure in the channel hole comprises:

The semiconductor channel is formed in the channel hole over the first semiconductor layer.