CN118100981A - Echo cancellation method for full duplex high-speed wired communication, transceiver system and chip - Google Patents
Echo cancellation method for full duplex high-speed wired communication, transceiver system and chip Download PDFInfo
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Abstract
The invention relates to an echo cancellation method, a transceiver system and a chip for full duplex high-speed wired communication. The echo cancellation method for full duplex high-speed wired communication comprises the following steps: echo filtering, adding a high-pass filter at the receiving end of a high-speed receiver in a forward high-speed channel at the downstream of the forward direction of the bidirectional channel, wherein the high-pass filter is used for filtering low-frequency echoes from a low-speed transmitter of a reverse low-speed channel mixed in the bidirectional channel; and compensating the high-speed signal, wherein the high-speed signal is realized through a feedback loop, and after the high-speed data stream transmitted by the forward high-speed channel is judged through a judgment device in the forward high-speed channel, infinite impulse response filtering is carried out through the feedback loop and fed back to an adder in the forward high-speed channel so as to offset the influence of the high-pass filter on the high-speed data stream. The invention effectively suppresses and eliminates the low-speed echo of the channel, and performs feedback compensation on the high-speed signal, thereby improving the error-free margin of the channel and realizing high-fidelity data transmission.
Description
Technical Field
The invention relates to the technical field of full-duplex communication, in particular to an echo cancellation method, a transceiver system and a chip for full-duplex high-speed wired communication.
Background
Currently, some applications of the serial de-serializer require bidirectional data transmission, such as a wired video transmission serial de-serializer in an automobile, and require a forward channel to transmit high-speed data, and a reverse channel to transmit a low-speed control command.
Full bidirectional data transmission requires that low speed signals be sent to the transmitting end at the receiving end, which can produce reflected noise on the channel, thereby affecting the performance margin of the forward channel. No specific method for eliminating such non-uniform rate reflection noise has been known so far.
Meanwhile, in the process of bidirectional data transmission, information often needs to pass through a plurality of connection points, and each connection point has the condition of discontinuous impedance. Echoes (reflected noise) can occur as information passes between the various connection points, resulting in high speed signal distortion.
Disclosure of Invention
In view of the above, the present invention provides an echo cancellation method, transceiver system, and chip for full duplex high speed wired communications that solves or at least alleviates one or more of the above-identified problems and other problems of the prior art.
To achieve the foregoing object, a first aspect of the present invention provides an echo cancellation method for full duplex high-speed wired communication for a serializer-deserializer chip, wherein the full duplex communication transmission path includes a forward high-speed channel and a reverse low-speed channel, and a superposition portion of the forward high-speed channel and the reverse low-speed channel is a bidirectional channel, the echo cancellation method comprising:
echo filtering, adding a high-pass filter at a receiving end of a high-speed receiver in the forward high-speed channel downstream of the forward direction of the bidirectional channel, wherein the high-pass filter is used for filtering low-frequency echoes of a low-speed transmitter from the reverse low-speed channel mixed in the bidirectional channel;
And the high-speed compensation signal is realized through a feedback loop, the high-speed data stream transmitted by the forward high-speed channel is subjected to decision by a decision device in the forward high-speed channel, and then is fed back to an adder in the forward high-speed channel through infinite impulse response filtering by the feedback loop so as to offset the influence of the high-pass filter on the high-speed data stream, and finally is output to a high-speed receiver.
In the echo cancellation method of full duplex high-speed wired communication as described above, optionally, the serial deserializer chip includes a serial module and a deserializing module, and the serial module and the deserializing module send and receive a mixed data stream to and from each other through the bidirectional channel, where the mixed data stream includes a high-speed data stream and a low-speed data stream.
In the echo cancellation method of full duplex high-speed wired communication as described above, optionally, the forward high-speed channel is sequentially connected with a high-speed transmitter, the high-pass filter, the adder, the decision device and the high-speed receiver;
The high-speed transmitter transmits a high-speed data stream to the high-pass filter through the bidirectional channel for high-pass filtering, enters the adder for signal superposition, and outputs the high-speed data stream to the high-speed receiver after judgment by the judgment device;
A branch is split between the output of the decision device and the high-speed receiver and connected with the output end of the decision device and the input end of the adder to form the feedback loop, and the feedback loop comprises an IIR filter;
The input end of the adder is connected with the output end of the high-pass filter, the output end of the adder is connected with the input end of the decision device, the output end of the decision device is connected with the input end of the IIR filter, and the output end of the IIR filter is connected to the input end of the adder to form a closed loop.
To achieve the foregoing object, a second aspect of the present invention provides a transceiver system, wherein the transceiver system comprises:
A serial module including a high speed transmitter and a low speed receiver;
the device comprises a deserializing module, a first-speed transmitter, a second-speed filter, an adder, a decision device, a high-speed receiver and a feedback loop, wherein the input end of the adder is connected with the output end of the high-speed filter, the output end of the adder is connected with the input end of the decision device, and the output end of the decision device is connected with the input end of the high-speed receiver;
And the serial module is connected with the deserializing module through the bidirectional channel and is used for mutually transmitting and receiving data streams.
In the transceiver system as described above, optionally, the transceiver system includes a forward high speed channel and a reverse low speed channel;
the forward high-speed channel is sequentially connected with the high-speed transmitter, the high-pass filter, the adder, the decision device and the high-speed receiver and is used for transmitting a high-speed data stream from the high-speed transmitter in the serial module to the high-speed receiver in the deserializing module;
The reverse low speed channel is used to transmit a low speed data stream from the low speed transmitter in the deserializing module to the low speed receiver in the serial module;
And the superposition part of the forward high-speed channel and the reverse low-speed channel is the bidirectional channel.
In the transceiver system as described above, optionally, the high-pass filter is disposed at a receiving end of the high-speed receiver in a forward high-speed channel downstream of the bidirectional channel, for filtering out reflected noise generated from the low-speed transmitter port mixed in the bidirectional channel.
In the transceiver system as described above, optionally, a branch is split between the output of the decision device and the high-speed receiver to connect the output of the decision device and the input of the adder to form the feedback loop, so as to perform decision, filtering, compensation and weighting processing on the high-speed data stream.
In the transceiver system as described above, optionally, the feedback loop includes an IIR filter, an input end of the IIR filter is connected to an output end of the decision device, the high-speed data stream output after being decided by the decision device is subjected to infinite impulse response filtering by the IIR filter, and a low-frequency amplitude is reserved; the output end of the IIR filter is connected with the input end of the adder to form a closed loop, and the low-frequency amplitude is added on the high-speed data stream originally input to the adder through the adder to compensate the loss of the high-speed data stream when the high-pass filter carries out high-pass filtering.
In the transceiver system as described above, the adder may optionally be capable of weighting the low frequency amplitude input to the adder and the high speed data stream, the weighted coefficients being implemented by the algorithm of the smallest square root among the digital algorithms of the serial deserializer chip.
To achieve the foregoing object, a third aspect of the present invention provides a chip, wherein the chip comprises the transceiver system as described in any one of the foregoing second aspects or uses the full duplex high speed wired communication echo cancellation method as described in any one of the foregoing first aspects.
The invention provides an echo cancellation method, a transceiver system and a chip for full duplex high-speed wired communication aiming at echo cancellation existing in full bidirectional channel transmission in which high speed and low speed are mixed together, so that low-speed echo of a channel is effectively suppressed and cancelled, and the margin of no error code of the channel is improved.
In order to realize high-fidelity data stream transmission, the invention compensates and feeds back the loss of the high-speed data stream in the high-pass filtering process through a feedback loop.
Drawings
The present disclosure will become more apparent with reference to the accompanying drawings. It is to be understood that these drawings are solely for purposes of illustration and are not intended as a definition of the limits of the invention. In the figure:
Fig. 1 is a system block diagram of one embodiment of a transceiver system of the present disclosure;
FIG. 2 is a block diagram of a high-speed signal compensation scheme at the input of the high-speed receiver of the deserializing module of FIG. 1; and
Fig. 3 is a simulated waveform diagram of an embodiment of an echo cancellation method for full duplex high speed wired communications according to the present invention.
Reference numerals: 1-a high-pass filter; 2-low speed transmitter; 3-decision device; 4-an adder; a 5-IIR filter; a 6-serial module; 7-a deserializing module; 8-high speed transmitter; 9-a low speed receiver; 10-high speed receiver.
Detailed Description
The echo cancellation method, transceiver system and chip structure, composition, features and advantages of the present invention, full duplex high speed wired communication will now be described by way of example with reference to the accompanying drawings and specific embodiments, although all descriptions should not be taken to limit the invention in any way.
Furthermore, to the extent that any individual feature described or implied in the embodiments set forth herein, or any individual feature shown or implied in the figures, the invention still allows any combination or deletion of such features (or equivalents thereof) without any technical hurdle, and further embodiments according to the invention are considered to be within the scope of the disclosure herein.
Fig. 1 is a system block diagram of one embodiment of a transceiver system of the present disclosure.
A Serializer (Serializer) converts a parallel signal into a serial signal, and a Deserializer (Deserializer) converts a serial signal into a parallel signal. The serializer and deserializer chip integrates a serializer and a deserializer.
As shown in fig. 1, the transceiver system may specifically include a serial module 6 and a deserializing module 7, where the serial module 6 and the deserializing module 7 are connected through a bidirectional channel, and send and receive data streams to and from each other.
The serial module 6 is located at the transmitting end TX side of the system and may include a high-speed transmitter 8 and a low-speed receiver 9; the deserializing module 7 is located at the receiving end RX side of the system, and may include a low-speed transmitter 2, a high-speed receiver 10, and a high-pass filter 1. The full duplex means that the serial module 6 at the system transmitting end TX side and the deserializing module 7 at the system receiving end RX side can transmit and receive data to and from each other at the same time and in the same channel.
In the transceiver system, there are two transmitters (high-speed transmitter 8 and low-speed transmitter 2) and two receivers (low-speed receiver 9 and high-speed receiver 10) in common, and there are two transmission paths from the transmitter to the receiver, namely, a forward channel and a reverse channel.
The forward channel, i.e. the forward channel, is the channel of the data stream input, which is part of the system that is the front of the signal stream, and may include a plurality of content such as sensing, amplifying, adjusting, spectral transformation, etc. of the signal.
The data stream is a set of ordered, byte data sequences having a start and an end, and a digitally encoded signal sequence representing information used in the transmission.
The reverse channel, i.e. the feedback channel, is capable of transmitting control commands at low speeds. For example, in an in-vehicle video entertainment and ADAS (advanced driving assistance) system, an SOC (system on a chip) that processes video data is not disposed together with a display panel, nor is a sensor that acquires an image together with an ECU (electronic control unit) due to allocation and limitation of a vehicle space structure, which requires transmission of data output from the SOC or the image sensor to the display panel or the ECU via a wire harness. The video data are parallel high-speed data such as RGB/HDMI/OLDI/DSI/CSI, if the high-speed parallel data are directly transmitted without serial processing, the number of pins of the connector is required to be large, the size is large, meanwhile, the weight, the number and the cost of the wire harness are large, and the installation layout of the wire harness is difficult; meanwhile, obvious offset can occur in transmission phases among a plurality of pieces of parallel data and between the data and a clock, and transmission error codes are brought to a system; because of the large number of parallel data (up to 30 bits, if any) and single ended signals, only one way transmission is possible, requiring an additional back channel if two-way communication of the system is to be achieved.
Specifically, the parallel signal at the input end of the serial module 6 may include data streams such as video, control, voice, etc., the serial module 6 converts multiple parallel data (including video, control, voice, etc.) from the transmitting end into a single serial data stream and transmits the single serial data stream to the deserializing module 7 at high speed, and the deserializing module 7 converts the serial data to a parallel video format or a low-speed control signal that can be received by the display panel or the SOC again at the receiving end.
In this embodiment, the high-speed transmitter 8 in the serial module 6 transmits a serial high-speed data stream to the high-speed receiver 10 in the deserializing module 7 via a forward channel, which is referred to as a forward high-speed channel in this embodiment; the low-speed transmitter 2 in the deserializing module 7 transmits the parallel low-speed data stream to the low-speed receiver 9 in the serial module 6 via a reverse channel, which in this embodiment is referred to as a reverse low-speed channel. And a section of the channel shared by the forward high-speed channel and the reverse low-speed channel is a bidirectional channel. In the bi-directional channel there is a mixed data stream, i.e. a high speed data stream and a low speed data stream.
Because the low-speed data stream can generate reflection at the position of discontinuous impedance of the whole channel, a plurality of connection ports exist in the transmission channel, and the impedance of the position of the connection ports cannot be completely matched, so reflection noise, namely echo, always exists.
In this embodiment, the low-speed transmitter 2 generates reflected noise, i.e. echo, at the port, which is not related to the high-speed data stream, and the echo, once being transmitted to the high-speed receiver 10 along with the high-speed data stream in the bidirectional channel, has a great influence on the high-speed receiver 10, and adds more power consumption and interference factors to the process of processing the serial data by the deserializing module 7.
To solve this problem, the present invention adds a high-pass filter 1 to the input port of the high-speed receiver 10 to filter out low-frequency reflection noise, i.e., echo, generated at the port by the low-speed transmitter 2. In this embodiment, the high-speed data stream is sent by the high-speed transmitter 8 in the serial module 6, and is transmitted through a bidirectional channel, and during the transmission process, the echoes generated along with the port of the low-speed transmitter 2 enter the high-pass filter 1 to perform high-pass filtering, and are output to the high-speed receiver 10 after being subjected to superposition processing and decision by the adder 4 (shown in fig. 2) and the decision device 3 (shown in fig. 2) inherent in the forward high-speed channel.
It should be noted here that whether the signal of the data stream is high-speed or not has no direct relation with the frequency, but is regarded as a high-speed signal when the rising/falling edge of the signal is less than 50 ps. The signals in the high-speed data stream are not necessarily all high frequency signals, but some low frequency signals may be present. However, since the high-pass filter 1 filters the high-speed data stream entirely during the high-pass filtering, compensation for the high-speed data stream signal lost during the high-pass filtering is required. For this problem, the present invention proposes a design of a feedback loop, and introduces an IIR filter 5 to perform infinite impulse response filtering on the high-speed data stream subjected to high-pass filtering to compensate for the loss of the high-speed signal. See the embodiment of fig. 2 for details.
Fig. 2 is a block diagram of a high-speed signal compensation scheme at the input of the high-speed receiver of the deserializing module of fig. 1.
As shown in fig. 2, a feedback loop may also be included in the deserializing module. The feedback loop is connected with the output end of the high-pass filter 1 and is used for judging, filtering, compensating and weighting summation processing on the high-speed data stream after the high-pass filtering.
In this embodiment, the forward high speed channel is connected in sequence to a high speed transmitter 8, a high pass filter 1, an adder 4, a determiner 3 and a high speed receiver 10.
The high-speed transmitter 8 transmits a high-speed data stream to the high-pass filter 1 through the bidirectional channel for high-pass filtering, then enters the adder 4 for signal superposition, and outputs the high-speed data stream to the high-speed receiver 10 after being judged by the judgment device 3.
A branch is split between the output of the decision device 3 and the high-speed receiver 10 to connect the output end of the decision device 3 and the input end of the adder 4 to form the feedback loop, and the high-speed data stream originally output is compensated and then output to the high-speed receiver 10.
The feedback loop may comprise an IIR filter 5. The input end of the adder 4 is connected with the output end of the high-pass filter 1, the output end of the adder 4 is connected with the input end of the decision device 3, the output end of the decision device 3 is connected with the input end of the IIR filter 5, and the output end of the IIR filter 5 is connected to the input end of the adder 4 to form a closed loop. The high-speed data stream output after the judgment of the judgment device 3 is subjected to infinite impulse response filtering through the IIR filter 5, the low-frequency amplitude is reserved, the output end of the IIR filter 5 is connected to the adder 4 again, the low-frequency amplitude obtained by infinite impulse response filtering is added to the high-speed data stream signal which is originally input to the adder 4 and subjected to high-pass filtering, and the loss in the high-pass filtering process is compensated.
The decision device 3 is essentially a comparator, and after both the amplitude and the waveform meet the transmission requirements, the decision device 3 decides on each code. After the input signal amplitude reaches the rated amplitude required by the decision device 3, the decision device 3 needs to define a decision threshold value and clock circuits, and each clock indicates a 0 code or 1 code to be decided. At an instant indicated by the clock, if the input signal exceeds the decision threshold, the decision device 3 decides it as 1 and outputs a rectangular pulse of 1; if the input signal is below the decision threshold at the instant indicated by the clock, the decision 3 will decide it as 0.
The threshold value can be understood as a mean value, which is used to determine whether the data stream is a 0 or a 1, and a separate clock is required to indicate the instant of each code. It is also necessary to define the amplitude value of the signal, requiring that the input signal amplitude is a nominal amplitude, e.g. setting the decision threshold to 5V, then the input signal amplitude is required to be between 0-10V.
After the signal is transmitted through the channel, the received signal is restored into the transmitted baseband signal through filtering, sampling and judging, namely the signal source, namely the original signal which is sent by the transmitting end and is not modulated.
In an alternative embodiment the adder 4 performs a weighted summation of the low frequency amplitude retained by the infinite impulse response filtering at the input and the high speed data stream lost by the high pass filtering. The weight coefficients are implemented by a minimum square root algorithm built into the digital algorithm section in the serializer chip.
The invention provides an echo cancellation method of full duplex high-speed wired communication, which is realized by the transceiver system, and the echo cancellation method specifically comprises the following steps: echo filtering and compensation of the high-speed signal.
The specific implementation manner of the echo filtering is to add a high-pass filter 1 at the receiving end of a high-speed receiver 10 in the forward high-speed channel downstream of the forward direction of the bidirectional channel, wherein the high-pass filter 1 is used for filtering low-frequency echoes mixed in the bidirectional channel from a low-speed transmitter 2 of the reverse low-speed channel.
The specific implementation of the compensation high-speed signal is realized through a feedback loop. After the high-speed data stream transmitted by the forward high-speed channel is decided by the decision device 3 in the forward high-speed channel, infinite impulse response filtering feedback is performed through the feedback loop, the infinite impulse response filtering feedback is fed back to the adder 4 in the forward high-speed channel so as to counteract the influence of the high-pass filter 1 on the high-speed data stream, and finally the high-speed data stream is output to the high-speed receiver 10.
Fig. 3 is a simulated waveform diagram of an embodiment of an echo cancellation method for full duplex high speed wired communications according to the present invention.
As shown in fig. 3, three waveforms from top to bottom, the top first waveform is a waveform after the high-speed data stream passes through the high-pass filter 1, the middle second waveform is a waveform after the decided data stream passes through the IIR filter 5, and the bottom third waveform is a data stream waveform after the first two are added together by the adder 4.
It can be seen that the feedback of the infinite impulse response compensates for the effect of high pass filtering on the high speed signal stream. The scheme suppresses echo and improves the error-free margin of the high channel.
In alternative other embodiments, the present scheme may be used for low-frequency echo suppression as long as the use cases of low-speed and high-speed signal bidirectional transmission are used.
The technical scope of the present invention is not limited to the above description, and those skilled in the art may make various changes and modifications to the above-described embodiments without departing from the technical spirit of the present invention, and these changes and modifications should be included in the scope of the present invention.
Claims (10)
1. An echo cancellation method for full duplex high-speed wired communication, the echo cancellation method for full duplex high-speed wired communication being used in a serial deserializer, wherein the full duplex communication transmission path includes a forward high-speed channel and a reverse low-speed channel, a superposition portion of the forward high-speed channel and the reverse low-speed channel is a bidirectional channel, the echo cancellation method comprising:
Echo filtering, adding a high-pass filter (1) at a receiving end of a high-speed receiver (10) in the forward high-speed channel downstream of the forward direction of the bidirectional channel, wherein the high-pass filter (1) is used for filtering low-frequency echo from a low-speed transmitter (2) of the reverse low-speed channel mixed in the bidirectional channel;
And the high-speed signal compensation is realized through a feedback loop, the high-speed data stream transmitted by the forward high-speed channel is subjected to decision by a decision device (3) in the forward high-speed channel, and then is fed back to an adder (4) in the forward high-speed channel through infinite impulse response filtering by the feedback loop so as to counteract the influence of the high-pass filter (1) on the high-speed data stream, and finally is output to a high-speed receiver (10).
2. The echo cancellation method for full duplex high speed wired communication according to claim 1, wherein the serial de-serializer comprises a serial module (6) and a de-serializer module (7), the serial module (6) and the de-serializer module (7) transmitting and receiving a mixed data stream with each other through the bi-directional channel, the mixed data stream comprising a high speed data stream and a low speed data stream.
3. Echo cancellation method for full duplex high speed wired communication according to claim 1 or 2, wherein the forward high speed channel is connected in sequence to a high speed transmitter (8), the high pass filter (1), the adder (4), the decision maker (3) and the high speed receiver (10);
the high-speed transmitter (8) transmits a high-speed data stream to the high-pass filter (1) through the bidirectional channel to carry out high-pass filtering, then enters the adder (4) to carry out signal superposition, and is judged by the judgment device (3) and then is output to the high-speed receiver (10);
A branch is split between the output of the decision device (3) and the high-speed receiver (10) to be connected with the output end of the decision device (3) and the input end of the adder (4) to form the feedback loop, and the feedback loop comprises an IIR filter (5);
The input end of the adder (4) is connected with the output end of the high-pass filter (1), the output end of the adder (4) is connected with the input end of the decision device (3), the output end of the decision device (3) is connected with the input end of the IIR filter (5), and the output end of the IIR filter (5) is connected to the input end of the adder (4) to form a closed loop.
4. A transceiver system, the transceiver system comprising:
-a serial module (6), the serial module (6) comprising a high-speed transmitter (8) and a low-speed receiver (9);
the device comprises a deserializing module (7), wherein the deserializing module (7) comprises a low-speed transmitter (2), a high-pass filter (1), an adder (4), a judging device (3), a high-speed receiver (10) and a feedback loop, the input end of the adder (4) is connected with the output end of the high-pass filter (1), the output end of the adder (4) is connected with the input end of the judging device (3), and the output end of the judging device (3) is connected with the input end of the high-speed receiver (10);
And the serial module (6) is connected with the deserializing module (7) through the bidirectional channel and is used for mutually transmitting and receiving data streams.
5. The transceiver system of claim 4 wherein the transceiver system includes a forward high speed channel and a reverse low speed channel;
The forward high-speed channel is sequentially connected with the high-speed transmitter (8), the high-pass filter (1), the adder (4), the decision device (3) and the high-speed receiver (10) and is used for transmitting a high-speed data stream from the high-speed transmitter (8) in the serial module (6) to the high-speed receiver (10) in the deserializing module (7);
-the reverse low-speed channel is used for transmitting a low-speed data stream from the low-speed transmitter (2) in the deserializing module (7) to the low-speed receiver (9) in the serial module (6);
And the superposition part of the forward high-speed channel and the reverse low-speed channel is the bidirectional channel.
6. Transceiver system according to claim 4, characterized in that the high pass filter (1) is arranged at the receiving end of the high speed receiver (10) in the forward high speed channel downstream of the bi-directional channel for filtering out reflected noise from the port of the low speed transmitter (2) mixed in the bi-directional channel.
7. Transceiver system according to claim 4, characterized in that a branch is taken between the output of the decision device (3) to the high-speed receiver (10) to the output of the decision device (3) and the input of the adder (4) to form the feedback loop for decision, filtering, compensation and weighting of the high-speed data stream.
8. The transceiver system of claim 7, characterized in that the feedback loop comprises an IIR filter (5), an input of the IIR filter (5) being connected to an output of the decision device (3), the high-speed data stream output after decision by the decision device (3) being subjected to infinite impulse response filtering by the IIR filter (5), retaining low frequency amplitude; the output end of the IIR filter (5) is connected with the input end of the adder (4) to form a closed loop, and the low-frequency amplitude is added on the high-speed data stream originally input to the adder (4) through the adder (4) to compensate the loss of the high-speed data stream when the high-pass filter (1) carries out high-pass filtering.
9. Transceiver system according to claim 8, characterized in that the adder (4) is capable of weighting the low frequency amplitude and the high speed data stream input to the adder (4), the weighted coefficients being implemented by the algorithm of the least square root of the digital algorithms of the serializer-deserializer chip.
10. A chip comprising a transceiver system as claimed in any one of claims 4 to 9 or an echo cancellation method using full duplex high speed wired communication as claimed in any one of claims 1 to 3.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1262818A (en) * | 1998-01-30 | 2000-08-09 | 皇家菲利浦电子有限公司 | Method for cancelling echoes in communication system, communication device, and radio base station of cordless telephone device |
| US20050084003A1 (en) * | 2003-10-21 | 2005-04-21 | Mark Duron | Full-duplex radio frequency echo cancellation |
| US20180006795A1 (en) * | 2016-06-29 | 2018-01-04 | Intel IP Corporation | Digital-centric full-duplex architecture |
| CN110310653A (en) * | 2019-07-09 | 2019-10-08 | 杭州国芯科技股份有限公司 | A kind of echo cancel method |
| CN112929055A (en) * | 2021-01-19 | 2021-06-08 | 北京集睿致远科技有限公司 | Echo cancellation circuit |
| CN115133941A (en) * | 2022-05-27 | 2022-09-30 | 南京金阵微电子技术有限公司 | Signal receiving end, serializer and communication system |
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Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1262818A (en) * | 1998-01-30 | 2000-08-09 | 皇家菲利浦电子有限公司 | Method for cancelling echoes in communication system, communication device, and radio base station of cordless telephone device |
| US20050084003A1 (en) * | 2003-10-21 | 2005-04-21 | Mark Duron | Full-duplex radio frequency echo cancellation |
| US20180006795A1 (en) * | 2016-06-29 | 2018-01-04 | Intel IP Corporation | Digital-centric full-duplex architecture |
| CN110310653A (en) * | 2019-07-09 | 2019-10-08 | 杭州国芯科技股份有限公司 | A kind of echo cancel method |
| CN112929055A (en) * | 2021-01-19 | 2021-06-08 | 北京集睿致远科技有限公司 | Echo cancellation circuit |
| CN115133941A (en) * | 2022-05-27 | 2022-09-30 | 南京金阵微电子技术有限公司 | Signal receiving end, serializer and communication system |
Non-Patent Citations (1)
| Title |
|---|
| 赵玉洁: "同时同频全双工系统自干扰消除技术的研究", 《CNKI优秀硕士学位论文全文库》, 15 January 2021 (2021-01-15) * |
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