CN118100927A - Pipeline-noise shaping successive approximation type analog-to-digital converter and control method thereof - Google Patents
Pipeline-noise shaping successive approximation type analog-to-digital converter and control method thereof Download PDFInfo
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Abstract
The invention discloses a pipeline-noise shaping successive approximation type analog-to-digital converter and a control method thereof, wherein the analog-to-digital converter comprises: the first-order noise shaping successive approximation type analog-to-digital conversion circuit is used for sampling and quantizing an input signal to obtain residual voltage, sending the residual voltage to the interstage integration circuit for amplification integration, and obtaining a first-order processing result according to the residual voltage and an amplification integration result; the second-order noise shaping successive approximation type analog-digital conversion circuit is used for sampling, quantizing, amplifying and integrating the second-order processing result and processing the first-order processing result and the second-order processing result to obtain a target digital signal. The analog-to-digital converter can effectively reduce quantization noise in the signal bandwidth, and can maintain higher energy efficiency while improving the in-band signal-to-noise ratio of the analog-to-digital converter.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a pipeline-noise shaping successive approximation type analog-to-digital converter and a control method thereof.
Background
The successive approximation register analog-to-digital converter (Successive Approximation Register) has the characteristics of high energy efficiency and low power consumption due to high digitization and passivity, so that the successive approximation register analog-to-digital converter is widely used in application fields of medium and low speed and medium and low precision, but also cannot maintain high energy efficiency while exceeding the range of the good indicators due to nonideal factors caused by the passivity, and the nonideal factors include: mismatch of capacitor array weights, sampling thermal noise, quantization noise, etc. Therefore, an emerging oversampling noise shaping-successive approximation type architecture is proposed and becomes a research hot spot in the field of analog-to-digital converters in recent decades, which is a hybrid architecture combining a Sigma-Delta analog-to-digital converter and a successive approximation type analog-to-digital converter, a passive integration loop is realized based on a residual voltage generation mechanism carried by the successive approximation type analog-to-digital converter, the noise shaping successive approximation type analog-to-digital converter can reach medium and high precision at a medium speed by virtue of reasonable power consumption and smaller area cost, but is limited by a completely passive architecture, the architecture cannot realize high-order noise shaping at a low hardware cost, the development bottleneck of the current noise shaping successive approximation type analog-to-digital converter is limited to be in a precision range of less than or equal to 14 bits, a new hybrid architecture appears in recent two years, and the architecture mixes a pipeline and the noise shaping successive approximation type analog-to-digital converter together, so that a noise shaping effect similar to MASH (Multi Stage Noise Shaping, cascading noise shaping) can be obtained with a lower noise shaping cost.
In order to achieve good suppression of in-band noise, one highly efficient idea is to increase the noise shaping loop order, which can bring about two benefits: the same bandwidth is used for obtaining higher precision; or equal accuracy, resulting in a greater bandwidth. However, the higher-order (3 or more) noise shaping order is not easy to implement based on the passive noise shaping concept.
The invention aims to realize an energy-efficient high-precision noise shaping successive approximation type analog-to-digital converter and simultaneously combines some optimized schemes. The scheme integrates the noise shaping-successive approximation type analog-to-digital converter and the pipelined analog-to-digital converter, realizes a mechanism for enabling a plurality of noise shaping-successive approximation type analog-to-digital converters to perform pipelining, and realizes a cascading noise shaping technology by means of the mechanism, so that the noise shaping loop order of the analog-to-digital converter is improved with lower hardware cost. Higher signal-to-noise ratios and higher bandwidths are achieved with lower system complexity and higher energy efficiency.
Disclosure of Invention
The present invention aims to solve at least one of the technical problems in the related art to some extent. Therefore, the invention aims to provide a pipeline-noise shaping successive approximation type analog-to-digital converter and a control method thereof, which are used for effectively reducing quantization noise in a signal bandwidth, improving the in-band signal-to-noise ratio of the analog-to-digital converter and simultaneously keeping high energy efficiency.
To achieve the above object, an embodiment of a first aspect of the present invention provides a pipeline-noise shaping successive approximation type analog-to-digital converter, including: the first-order noise shaping successive approximation type analog-to-digital conversion circuit, the interstage integrating circuit and the second-order noise shaping successive approximation type analog-to-digital conversion circuit are respectively connected with the interstage integrating circuit and the second-order noise shaping successive approximation type analog-to-digital conversion circuit and are used for sampling and quantizing an input signal to obtain residual voltage, sending the residual voltage to the interstage integrating circuit for amplification integration, obtaining a first-order processing result according to the residual voltage and the amplification integration result, and sending the first-order processing result to the second-order noise shaping successive approximation type analog-to-digital conversion circuit; the second-order noise shaping successive approximation type analog-digital conversion circuit is connected with the inter-stage integration circuit and is used for sampling, quantizing, processing a secondary processing result obtained by amplifying the integration result and processing the primary processing result and the secondary processing result to obtain a target digital signal.
In addition, the pipeline-noise shaping successive approximation type analog-to-digital converter of the above embodiment of the present invention may further have the following additional technical features:
According to one embodiment of the present invention, the first-order noise shaping successive approximation type analog-to-digital conversion circuit includes: the first capacitor circuit is respectively connected with the input end of the first comparator and the inter-stage integrating circuit and is used for performing successive approximation conversion on the input signal obtained by sampling to obtain the residual voltage; the first comparator is connected with the first logic circuit and the inter-stage integrating circuit respectively, and is used for obtaining a first comparison result according to the residual voltage and the integration amplification result and sending the first comparison result to the first logic circuit; the first logic circuit is connected with the second-order noise shaping successive approximation type analog-to-digital conversion circuit, and is used for processing the first comparison result by using successive approximation register logic and dynamic element matching logic to obtain the first-stage processing result, and sending the first-stage processing result to the second-order noise shaping successive approximation type analog-to-digital conversion circuit.
According to an embodiment of the present invention, the inter-stage integrating circuit includes: the feedforward amplifier is connected with the first capacitor circuit, the first comparator and the second-order noise shaping successive approximation type analog-to-digital conversion circuit in parallel, and is used for amplifying the residual voltage to obtain an amplified signal, and the first capacitor is used for integrating the residual voltage to obtain an integrated signal, wherein the amplified and integrated result comprises the amplified signal and the integrated signal.
According to one embodiment of the invention, the feed forward amplifier comprises: first to fourteenth MOS transistors; the control ends of the first MOS tube are connected with the control ends of the second MOS tube and the fourteenth MOS tube and are used for inputting a first control signal; the second end of the first MOS tube is connected with the first end of the fifth MOS tube, the second end of the second MOS tube is connected with the first end of the sixth MOS tube, and the control end of the fifth MOS tube is connected with the control end of the sixth MOS tube for inputting a second control signal; the second end of the fifth MOS tube is respectively connected with the first end of the seventh MOS tube and the control end of the third MOS tube, the second end of the sixth MOS tube is respectively connected with the first end of the eighth MOS tube and the control end of the fourth MOS tube, and the control end of the seventh MOS tube is connected with the control end of the eighth MOS tube for inputting a third control signal; the second end of the seventh MOS tube is connected with the first end of the ninth MOS tube, the second end of the eighth MOS tube is connected with the first end of the tenth MOS tube, the control ends of the ninth MOS tube and the thirteenth MOS tube are connected with the positive end of the first capacitance circuit, and the control ends of the tenth MOS tube and the twelfth MOS tube are connected with the negative end of the first capacitance circuit; the second ends of the ninth MOS tube and the tenth MOS tube are connected with the first end of the eleventh MOS tube, the control end of the eleventh MOS tube is used for inputting a fourth control signal, and the second ends of the eleventh MOS tube and the fourteenth MOS tube are grounded; the second end of the third MOS tube is connected with the first end of the twelfth MOS tube and is used as the positive output end of the feedforward amplifier, and the second end of the fourth MOS tube is connected with the first end of the thirteenth MOS tube and is used as the negative output end of the feedforward amplifier; the twelfth MOS tube and the second end of the thirteenth MOS tube are connected with the first end of the fourteenth MOS tube.
According to one embodiment of the present invention, the second-order noise shaping successive approximation type analog-to-digital conversion circuit includes: a second capacitance circuit, a second order noise shaping loop, a second comparator, and a second logic circuit; wherein,
The second capacitor circuit is respectively connected with the inter-stage integrating circuit, the second comparator and the second-order noise shaping loop, and is used for performing successive approximation conversion on the amplified integration result obtained by sampling to obtain a conversion voltage, and transmitting the conversion voltage to the second comparator and the second-order noise shaping loop; the second comparator is connected with the second logic circuit and is used for obtaining a second comparison result according to the conversion voltage and sending the second comparison result to the second logic circuit; and the second logic circuit is used for processing the second comparison result by using successive approximation register logic to obtain the secondary processing result.
According to an embodiment of the present invention, the second-order noise shaping successive approximation type analog-to-digital conversion circuit further includes: and the digital alignment error correction circuit is respectively connected with the first logic circuit and the second logic circuit and is used for carrying out noise modulation function cancellation, digital alignment and correction processing on the received primary processing result and the received secondary processing result to obtain the target digital signal.
According to one embodiment of the invention, the second order noise shaping loop comprises: the amplifying module is connected with the second capacitance circuit and is used for amplifying the received conversion voltage; the feedback EF module is connected with the amplifying module and is used for sampling and delaying the amplified conversion voltage so as to feed back the sampled and amplified quantization error voltage to the second capacitor circuit in the next quantization period; the feedforward CIFF module is respectively connected with the amplifying module and the second comparator and is used for carrying out integral processing on the sampled and amplified quantization error voltage and then sending the sampled and amplified quantization error voltage after integral processing to the second comparator.
According to one embodiment of the invention, the amplification module employs a passive integration loop.
According to one embodiment of the invention, the first to sixth MOS transistors are PMOS transistors, and the seventh to fourteenth MOS transistors are NMOS transistors.
According to one embodiment of the present invention, the first-order noise shaping successive approximation analog-to-digital conversion circuit is a 5-bit analog-to-digital conversion circuit, the second-order noise shaping successive approximation analog-to-digital conversion circuit is a 7-bit analog-to-digital conversion circuit, and the target digital signal is an 11-bit digital signal.
To achieve the above object, a second aspect of the present invention provides a control method of a pipeline-noise shaping successive approximation type analog-to-digital converter, wherein a duty cycle of the pipeline-noise shaping successive approximation type analog-to-digital converter includes a sampling period, a quantization period, and an integration period, which are sequentially set, the method including: in the sampling period, the first-order noise shaping successive approximation type analog-digital conversion circuit is controlled to sample an input signal, the second-order noise shaping successive approximation type analog-digital conversion circuit is controlled to quantize an amplified integration result sampled in the last integration period, the obtained secondary processing result is processed, and the secondary processing result and a primary processing result obtained in the last integration period are processed to obtain a target digital signal; in the quantization period, the first-order noise shaping successive approximation type analog-to-digital conversion circuit is controlled to quantize the sampled input signal to obtain residual voltage; and in the integration period, controlling the inter-stage integration circuit to amplify and integrate the residual voltage, controlling the second-order noise shaping successive approximation type analog-to-digital conversion circuit to sample an amplified integration result, controlling the first-order noise shaping successive approximation type analog-to-digital conversion circuit to obtain a first-order processing result according to the residual voltage and the amplified integration result, and transmitting the first-order processing result to the second-order noise shaping successive approximation type analog-to-digital conversion circuit.
In addition, the control method of the pipeline-noise shaping successive approximation type analog-to-digital converter according to the above embodiment of the present invention may further have the following additional technical features:
according to one embodiment of the invention, the sampling period is smaller than the quantization period, which is smaller than the integration period.
To achieve the above object, an embodiment of a third aspect of the present invention provides a chip, including: the pipeline-noise shaping successive approximation type analog-to-digital converter described above.
To achieve the above object, a fourth aspect of the present invention provides a sensor, including: the chip described above.
The assembly line-noise shaping successive approximation type analog-to-digital converter and the control method thereof can effectively reduce quantization noise in the signal bandwidth, improve the in-band signal-to-noise ratio of the analog-to-digital converter and simultaneously maintain high energy efficiency.
Drawings
FIG. 1 is a block diagram of a pipeline-to-noise shaping successive approximation type analog-to-digital converter according to one embodiment of the invention;
FIG. 2 is a circuit topology of a pipeline-to-noise shaping successive approximation type analog-to-digital converter of one embodiment of the present invention;
FIG. 3 is a circuit topology of a feed forward amplifier according to one embodiment of the invention;
FIG. 4 is a block diagram of the structure of a second order noise shaping loop of one embodiment of the present invention;
FIG. 5 is a circuit topology of a passive integration loop of one embodiment of the invention;
FIG. 6 is a flowchart of the operation of a pipeline-to-noise shaping successive approximation type analog-to-digital converter of one embodiment of the present invention;
FIG. 7 is a flow chart of a method of controlling a pipeline-noise shaping successive approximation type analog-to-digital converter according to an embodiment of the present invention;
FIG. 8 is a block diagram of the structure of a chip according to one embodiment of the invention;
FIG. 9 is a block diagram of a sensor according to one embodiment of the invention.
Detailed Description
Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative and intended to explain the present invention and should not be construed as limiting the invention.
A pipeline-noise shaping successive approximation type analog-to-digital converter and a control method thereof according to an embodiment of the present invention are described below with reference to the accompanying drawings.
Fig. 1 is a block diagram of a pipeline-noise shaping successive approximation type analog-to-digital converter according to an embodiment of the present invention.
As shown in fig. 1, the pipeline-noise shaping successive approximation type analog-to-digital converter 100 includes: the first-order noise shaping successive approximation analog-to-digital conversion circuit 101, the inter-stage integrating circuit 102 and the second-order noise shaping successive approximation analog-to-digital conversion circuit 103, wherein the first-order noise shaping successive approximation analog-to-digital conversion circuit 101 is respectively connected with the inter-stage integrating circuit 102 and the second-order noise shaping successive approximation analog-to-digital conversion circuit 103, and is used for sampling and quantizing an input signal to obtain a residual voltage, sending the residual voltage to the inter-stage integrating circuit 1012 for amplification integration, obtaining a first-order processing result according to the residual voltage and the amplification integration result, and sending the first-order processing result to the second-order noise shaping successive approximation analog-to-digital conversion circuit 103; the second-order noise shaping successive approximation type analog-to-digital conversion circuit 103 is connected to the inter-stage integrating circuit 102, and is used for sampling, quantizing, amplifying, and integrating the result to obtain a second-stage processing result, and processing the first-stage processing result and the second-stage processing result to obtain a target digital signal.
Specifically, as shown in fig. 2, the first-order noise-shaping successive approximation type analog-to-digital conversion circuit 101 may be a 5-bit analog-to-digital conversion circuit, the second-order noise-shaping successive approximation type analog-to-digital conversion circuit 103 may be a 7-bit analog-to-digital conversion circuit, and the target digital signal may be an 11-bit digital signal. For the first-order noise-shaping successive approximation type analog-to-digital conversion circuit 101 and the second-order noise-shaping successive approximation type analog-to-digital conversion circuit 103 shown in fig. 2, the positive electrode side and the negative electrode side are identical in structure. Wherein Vcm is a common mode voltage, vrefp is one reference voltage, and Vrefp is another reference voltage.
The pipeline-noise shaping successive approximation type analog-to-digital converter can effectively reduce quantization noise in a signal bandwidth, and can maintain higher energy efficiency while improving the in-band signal-to-noise ratio of the analog-to-digital converter.
In some embodiments, as shown in fig. 2, the first order noise shaping successive approximation type analog-to-digital conversion circuit 101 includes: a first capacitance circuit 201, a first comparator 202, and a first logic circuit 203, wherein,
The first capacitance circuit 201 is connected with the input end of the first comparator 202 and the inter-stage integrating circuit 102 respectively, and is used for performing successive approximation conversion on the sampled input signal to obtain residual voltage; a first comparator 202 connected to the first logic circuit 203 and the inter-stage integrating circuit 102, respectively, for obtaining a first comparison result according to the residual voltage and the integration amplification result, and transmitting the first comparison result to the first logic circuit 203; the first logic circuit 203 is connected to the second-order noise shaping successive approximation type analog-to-digital conversion circuit 103, and is configured to process the first comparison result by using the successive approximation register logic and the dynamic element matching logic to obtain a first-order processing result, and send the first-order processing result to the second-order noise shaping successive approximation type analog-to-digital conversion circuit 103.
Specifically, the capacitance values in the first capacitance circuit 201 may be C1, 2C1, 4C1, 8C1, and 16C1, respectively, the first capacitance circuit 201 on the positive side may obtain two residual voltages, the inter-stage integrating circuit 102 amplifies the two residual voltages, and the amplified two residual voltages are input to the positive input end of the first comparator 202; the negative-side first capacitor circuit 201 may obtain two residual voltages, the inter-stage integrating circuit 102 amplifies the two residual voltages, and the amplified two residual voltages are input to the negative input terminal of the first comparator 202, and the first comparator 202 compares the two residual voltages input to the positive input terminal with the two residual voltages input to the negative input terminal.
In some embodiments, as shown in fig. 2, the inter-stage integrating circuit 102 includes: the feedforward amplifier 301 is connected with the first capacitor circuit 201, the first comparator 202 and the second-order noise shaping successive approximation type analog-digital conversion circuit 103 in parallel, and is used for amplifying residual voltage to obtain an amplified signal, and the first capacitor 302 is used for integrating the residual voltage to obtain an integrated signal, wherein the amplified integrated result comprises the amplified signal and the integrated signal. The inter-stage integrating circuit 102 may amplify the residual voltage 16 times. The capacitance of the first capacitor 302 may be 2C1.
In some embodiments, as shown in fig. 3, the feed forward amplifier 301 includes: the first MOS tube S1 to the fourteenth MOS tube S14; the first ends of the first MOS tube S1, the second MOS tube S2, the third MOS tube S3 and the fourth MOS tube S4 are connected with a preset power supply P1, and the control end of the first MOS tube S1 is connected with the control ends of the second MOS tube S2 and the fourteenth MOS tube S14 for inputting a first control signal Vcmfb; the second end of the first MOS tube S1 is connected with the first end of the fifth MOS tube S5, the second end of the second MOS tube S2 is connected with the first end of the sixth MOS tube S6, and the control end of the fifth MOS tube S5 is connected with the control end of the sixth MOS tube S6 for inputting a second control signal Vb3; the second end of the fifth MOS tube S5 is respectively connected with the first end of the seventh MOS tube S7 and the control end of the third MOS tube S3, the second end of the sixth MOS tube S6 is respectively connected with the first end of the eighth MOS tube S8 and the control end of the fourth MOS tube S4, and the control end of the seventh MOS tube S7 is connected with the control end of the eighth MOS tube S8 for inputting a third control signal Vb2; the second end of the seventh MOS tube S7 is connected with the first end of the ninth MOS tube S9, the second end of the eighth MOS tube S8 is connected with the first end of the tenth MOS tube S10, the control ends of the ninth MOS tube S9 and the thirteenth MOS tube S13 are connected with the positive end vin+ of the first capacitor circuit 201, and the control ends of the tenth MOS tube S10 and the twelfth MOS tube S12 are connected with the negative end of the first capacitor circuit 201; the second ends of the ninth MOS tube S9 and the tenth MOS tube S10 are connected with the first end of the eleventh MOS tube S11, the control end of the eleventh MOS tube S11 is used for inputting a fourth control signal Vb1, and the second ends of the eleventh MOS tube S11 and the fourteenth MOS tube S14 are grounded; the second end of the third MOS tube S3 is connected with the first end of the twelfth MOS tube S12, and is used as a positive output end Vout+ of the feedforward amplifier 301, and the second end of the fourth MOS tube S4 is connected with the first end of the thirteenth MOS tube S13, and is used as a negative output end Vout-of the feedforward amplifier 301; the second ends of the twelfth MOS transistor S12 and the thirteenth MOS transistor S13 are connected with the first end of the fourteenth MOS transistor S14. Wherein, the first MOS tube S1 to the sixth MOS tube S6 can be PMOS tubes, and the seventh MOS tube to the fourteenth MOS tube can be NMOS tubes. The feedforward amplifier 301 operates in a discrete manner, and the two phase amplifying phases and the reset phases of the feedforward amplifier 301 correspond to the amplifying integral phase and other phases except the amplifying integral phase of the time sequence of the pipeline-noise shaping successive approximation type analog-digital converter 100 respectively, the feedforward amplifier 301 does not generate a time sequence control signal, but uses the time sequence of the pipeline-noise shaping successive approximation type analog-digital converter 100 to control, and the first control signal Vcmfb, the second control signal Vb3, the third control signal Vb2 and the fourth control signal Vb1 correspond to the reset phase of the feedforward amplifier 301 for controlling the stabilization of the bias potential of the MOS transistor.
Specifically, the feed forward amplifier 301 includes a three-stage amplifying stage circuit, as shown in fig. 3, g m1、gm2 is a transconductance stage of two-stage amplifying, g m3 is a transconductance of a feed forward path, and a specific working principle is as follows:
Wherein H(s) is a transfer function, LHP Zero is a left half plane Zero, s is a complex variable in a frequency domain, A 1、A2、A3 is gains of g m1、gm2 and g m3 respectively, p1 is a first-stage output pole, and p2 is a second-stage output pole. The feed forward amplifier 301 may create a left half-plane zero in its center-of-gravity band to cancel the secondary pole, thus achieving stability of any capacitive load, but due to the current multiplexing structure, there are:
Where z 1 is the first zero of the transfer function, it can be seen that first pole p 1 cannot be equal to first zero z 1, and therefore the present invention chooses to use first zero z 1 to cancel second pole p 2.
In some embodiments, as shown in fig. 2, the second order noise shaping successive approximation type analog-to-digital conversion circuit 103 includes: a second capacitance circuit 501, a second order noise shaping loop 502, a second comparator 503, and a second logic circuit 504; the second capacitance circuit 501 is connected to the inter-stage integrating circuit 102, the second comparator 503 and the second-order noise shaping loop 502, and is configured to perform successive approximation conversion on the sampled amplified integration result to obtain a converted voltage, and send the converted voltage to the second comparator 503 and the second-order noise shaping loop 502; a second comparator 503 connected to the second logic circuit 504, for obtaining a second comparison result according to the converted voltage, and sending the second comparison result to the second logic circuit 504; a second logic circuit 504 for processing the second comparison result using successive approximation register logic to obtain a secondary processing result.
Specifically, the capacitance values in the second capacitance circuit 501 may be C, C, 2C, 4C, 8C, 16C, 32C, and 64C, respectively.
In some embodiments, as shown in fig. 2, the second-order noise-shaping successive approximation type analog-to-digital conversion circuit 103 further includes: the digital alignment error correction circuit 505 is connected to the first logic circuit 203 and the second logic circuit 504, and is configured to perform noise modulation function cancellation, digital alignment and correction processing on the received primary processing result and secondary processing result, so as to obtain a target digital signal.
In some embodiments, as shown in fig. 4, the second order noise shaping loop 502 includes: the amplifying module 601, the feedback EF module 602 and the feedforward CIFF module 603, wherein the amplifying module 601 is connected with the second capacitance circuit 501 and is used for amplifying the received converted voltage; the feedback EF module 602 is connected to the amplifying module 601, and is configured to sample and delay the amplified converted voltage, so as to feed back the sampled and amplified quantization error voltage to the second capacitance circuit 501 in the next quantization period; the feedforward CIFF module 603 is connected to the amplifying module 601 and the second comparator 503, and is configured to integrate the sampled and amplified quantization error voltage, and then send the integrated sampled and amplified quantization error voltage to the second comparator 503. Wherein the amplification module 601 employs a passive integration loop, wherein the passive integration loop may be as shown in fig. 5.
Specifically, as shown in fig. 6, the pipeline-noise shaping successive approximation type analog-to-digital converter 100 may employ asynchronous timing, and generate each relevant control signal with one master clock for control, and the working procedure is as follows:
The first two master clocks are used for the first capacitor circuit 201 sampling phase (clks _1) in the first stage, followed by three master clocks for the first capacitor circuit 201 quantization phase (conv_1) to get the residual voltage, and then five master clocks for the quantization completion phase (EOC 1); five master clocks are then used for the inter-stage integrating circuit 102 to amplify the residual voltage by an integrated phase (RA), which is also the sampling phase of the second-order noise-shaping successive approximation type analog-to-digital converting circuit 103 in the second stage (clks 2); the second capacitor circuit 501 performs a quantization phase (conv_2), followed by a second stage error feedback phase (EF), a feed forward phase (CIFF), a quantization completion phase (EOC 2), while the first capacitor circuit 201 in the first stage performs a sampling phase (clks 1) and a quantization phase (conv 1) on the second sample, and so on, to implement pipelining of the two-stage analog-to-digital converter.
In the above-described workflow, the residual voltage V res1 of the first stage is generated at the end of the quantization phase of the first stage, and is amplified and integrated 16 times through the inter-stage integrating circuit 102, the integrated result is divided into two paths, one path goes to the second stage, the other path goes back to the first stage and completes the construction of the first-stage noise shaping successive approximation type analog-digital converting circuit 101 through gain attenuation, so that the quantization noise in the first-stage noise shaping successive approximation type analog-digital converting circuit 101 becomes NTF 1(z)×Vres1, where z is a z domain signal, NTF 1 is a noise transfer function of the first-stage noise shaping successive approximation type analog-digital converting circuit 101, the noise transfer function may be 1-z -1, and the quantization noise input enters the second stage to be further quantized and modulated; in the second stage working process, the signal passes through a second-order noise shaping successive approximation type analog-digital conversion circuit 103 comprising error feedback and cascade feedforward, and finally, the first-stage noise modulation function cancellation and pipeline output alignment and correction processing are carried out on the first-stage processing result and the second-stage processing result in the second-stage pair Ji Jiucuo phase, so that an 11-bit target digital signal is obtained, and the third-order noise shaping effect is achieved.
In the second-order noise shaping successive approximation type analog-digital conversion circuit 103, a differential capacitor stacking technology is adopted to generate 4 multiplication benefit compensation required by noise shaping integral loss, on the basis, 20 multiplication benefit compensation required by the feedforward CIFF module 603 benefits from the marginless gain, only 5 times of relative gain of the second comparator 503 is required to realize a modulation function of 1-0.8z -1, and in general, the second-order conversion process is shown in the following formula, so that the second-order noise shaping effect is realized.
D out(z)＝Vin (z) Ten 4V EF(z)*z-1+20VCIFF(z)*z-1 +Q (z)
＝Vin(z)+Q(z)(1-0.8z-1)2
Wherein D out (z) is a second-order noise-shaped output voltage, V in (z) is a voltage input to the second-order noise-shaped successive approximation type analog-to-digital conversion circuit 103, V EF (z) is a voltage obtained by sampling and delaying the amplified converted voltage by the feedback EF module 602, V CIFF (z) is a voltage obtained by integrating the sampled and amplified quantization error voltage by the feedforward CIFF module 603, and Q (z) is a quantization error voltage of the second-order noise-shaped successive approximation type analog-to-digital conversion circuit 103.
In summary, the pipeline-noise shaping successive approximation type analog-to-digital converter according to the embodiment of the present invention adopts a two-stage noise shaping successive approximation type analog-to-digital converter architecture, wherein the first stage realizes first-order active noise shaping, the second stage realizes second-order passive noise shaping, and a cascading noise shaping technology, that is, a third-order noise shaping effect, is implemented for the whole system; the first stage multiplexes the interstage gain of the pipeline structure, provides the active gain needed by the noise shaping loop for the first stage, the second stage adopts the noise shaping loop with the feedback-feedforward (EF-CIFF) structure, and realizes the second-order noise transfer function with lower cost on the basis of passive integration. The invention can be applied to a medium-speed high-precision sensor system, can effectively inhibit noise and improve the in-band signal-to-noise ratio of the analog-to-digital converter.
Fig. 7 is a flow chart of a method of controlling a pipeline-noise shaping successive approximation type analog-to-digital converter according to an embodiment of the present invention.
As shown in fig. 7, the duty cycle of the pipeline-noise shaping successive approximation type analog-to-digital converter includes a sampling period, a quantization period, and an integration period, which are sequentially set, and the method includes:
And S71, in a sampling period, controlling the first-order noise shaping successive approximation type analog-digital conversion circuit to sample an input signal, controlling the second-order noise shaping successive approximation type analog-digital conversion circuit to quantize an amplified integration result sampled in a last integration period, obtaining a secondary processing result, and processing the secondary processing result and a primary processing result obtained in the last integration period to obtain a target digital signal.
S72, in a quantization period, the first-order noise shaping successive approximation type analog-to-digital conversion circuit is controlled to quantize the sampled input signal, and residual voltage is obtained.
S73, in the integral period, controlling an interstage integral circuit to amplify and integrate residual voltage, controlling a second-order noise shaping successive approximation type analog-digital conversion circuit to sample an amplified integral result, enabling and controlling a first-order noise shaping successive approximation type analog-digital conversion circuit to obtain a first-order processing result according to the residual voltage and the amplified integral result, and sending the first-order processing result to the second-order noise shaping successive approximation type analog-digital conversion circuit.
In some embodiments, the sampling period is less than the quantization period, which is less than the integration period.
Fig. 8 is a block diagram of the structure of a chip according to an embodiment of the invention.
As shown in fig. 8, the chip 800 includes: the pipeline-noise shaping successive approximation type analog-to-digital converter 100 described above.
FIG. 9 is a block diagram of a sensor according to one embodiment of the invention.
As shown in fig. 9, the sensor 900 includes: chip 800 described above.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the device or element being referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present invention.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present invention, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise.
In the present invention, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; either directly or indirectly, through intermediaries, or both, may be in communication with each other or in interaction with each other, unless expressly defined otherwise. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
In the present invention, unless expressly stated or limited otherwise, a first feature "up" or "down" a second feature may be the first and second features in direct contact, or the first and second features in indirect contact via an intervening medium. Moreover, a first feature being "above," "over" and "on" a second feature may be a first feature being directly above or obliquely above the second feature, or simply indicating that the first feature is level higher than the second feature. The first feature being "under", "below" and "beneath" the second feature may be the first feature being directly under or obliquely below the second feature, or simply indicating that the first feature is less level than the second feature.
While embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the invention, and that variations, modifications, alternatives and variations may be made to the above embodiments by one of ordinary skill in the art within the scope of the invention.
Claims (14)
1. A pipeline-to-noise shaping successive approximation type analog-to-digital converter comprising: a first-order noise-shaping successive approximation type analog-to-digital conversion circuit, an inter-stage integrating circuit, and a second-order noise-shaping successive approximation type analog-to-digital conversion circuit, wherein,
The first-order noise shaping successive approximation type analog-to-digital conversion circuit is respectively connected with the inter-stage integrating circuit and the second-order noise shaping successive approximation type analog-to-digital conversion circuit and is used for sampling and quantizing an input signal to obtain residual voltage, sending the residual voltage to the inter-stage integrating circuit for amplification integration, obtaining a first-order processing result according to the residual voltage and the amplification integration result, and sending the first-order processing result to the second-order noise shaping successive approximation type analog-to-digital conversion circuit;
the second-order noise shaping successive approximation type analog-digital conversion circuit is connected with the inter-stage integration circuit and is used for sampling, quantizing, processing a secondary processing result obtained by amplifying the integration result and processing the primary processing result and the secondary processing result to obtain a target digital signal.
2. The pipeline-to-noise shaping successive approximation type analog-to-digital converter of claim 1, wherein the first order noise shaping successive approximation type analog-to-digital converter circuit comprises: a first capacitance circuit, a first comparator, and a first logic circuit, wherein,
The first capacitor circuit is respectively connected with the input end of the first comparator and the inter-stage integrating circuit and is used for performing successive approximation conversion on the input signal obtained by sampling to obtain the residual voltage;
The first comparator is connected with the first logic circuit and the inter-stage integrating circuit respectively, and is used for obtaining a first comparison result according to the residual voltage and the integration amplification result and sending the first comparison result to the first logic circuit;
The first logic circuit is connected with the second-order noise shaping successive approximation type analog-to-digital conversion circuit, and is used for processing the first comparison result by using successive approximation register logic and dynamic element matching logic to obtain the first-stage processing result, and sending the first-stage processing result to the second-order noise shaping successive approximation type analog-to-digital conversion circuit.
3. The pipeline-to-noise shaping successive approximation type analog-to-digital converter of claim 2, wherein the inter-stage integrating circuit comprises:
The feedforward amplifier is connected with the first capacitor circuit, the first comparator and the second-order noise shaping successive approximation type analog-to-digital conversion circuit in parallel, and is used for amplifying the residual voltage to obtain an amplified signal, and the first capacitor is used for integrating the residual voltage to obtain an integrated signal, wherein the amplified and integrated result comprises the amplified signal and the integrated signal.
4. A pipeline-noise shaping successive approximation analog-to-digital converter as claimed in claim 3, wherein the feed forward amplifier comprises: first to fourteenth MOS transistors; wherein,
The first ends of the first MOS tube, the second MOS tube, the third MOS tube and the fourth MOS tube are connected with a preset power supply, and the control end of the first MOS tube is connected with the control ends of the second MOS tube and the fourteenth MOS tube and used for inputting a first control signal; the second end of the first MOS tube is connected with the first end of the fifth MOS tube, the second end of the second MOS tube is connected with the first end of the sixth MOS tube, and the control end of the fifth MOS tube is connected with the control end of the sixth MOS tube for inputting a second control signal; the second end of the fifth MOS tube is respectively connected with the first end of the seventh MOS tube and the control end of the third MOS tube, the second end of the sixth MOS tube is respectively connected with the first end of the eighth MOS tube and the control end of the fourth MOS tube, and the control end of the seventh MOS tube is connected with the control end of the eighth MOS tube for inputting a third control signal; the second end of the seventh MOS tube is connected with the first end of the ninth MOS tube, the second end of the eighth MOS tube is connected with the first end of the tenth MOS tube, the control ends of the ninth MOS tube and the thirteenth MOS tube are connected with the positive end of the first capacitance circuit, and the control ends of the tenth MOS tube and the twelfth MOS tube are connected with the negative end of the first capacitance circuit; the second ends of the ninth MOS tube and the tenth MOS tube are connected with the first end of the eleventh MOS tube, the control end of the eleventh MOS tube is used for inputting a fourth control signal, and the second ends of the eleventh MOS tube and the fourteenth MOS tube are grounded; the second end of the third MOS tube is connected with the first end of the twelfth MOS tube and is used as the positive output end of the feedforward amplifier, and the second end of the fourth MOS tube is connected with the first end of the thirteenth MOS tube and is used as the negative output end of the feedforward amplifier; the twelfth MOS tube and the second end of the thirteenth MOS tube are connected with the first end of the fourteenth MOS tube.
5. A pipeline-noise-shaping successive approximation type analog-to-digital converter as claimed in claim 3, wherein the second-order noise-shaping successive approximation type analog-to-digital converter circuit comprises: a second capacitance circuit, a second order noise shaping loop, a second comparator, and a second logic circuit; wherein,
The second capacitor circuit is respectively connected with the inter-stage integrating circuit, the second comparator and the second-order noise shaping loop, and is used for performing successive approximation conversion on the amplified integration result obtained by sampling to obtain a conversion voltage, and transmitting the conversion voltage to the second comparator and the second-order noise shaping loop;
the second comparator is connected with the second logic circuit and is used for obtaining a second comparison result according to the conversion voltage and sending the second comparison result to the second logic circuit;
and the second logic circuit is used for processing the second comparison result by using successive approximation register logic to obtain the secondary processing result.
6. The pipeline-to-noise shaping successive approximation type analog-to-digital converter of claim 5, wherein the second order noise shaping successive approximation type analog-to-digital converter circuit further comprises:
and the digital alignment error correction circuit is respectively connected with the first logic circuit and the second logic circuit and is used for carrying out noise modulation function cancellation, digital alignment and correction processing on the received primary processing result and the received secondary processing result to obtain the target digital signal.
7. The pipeline-to-noise shaping successive approximation type analog-to-digital converter of claim 5, wherein the second order noise shaping loop comprises: an amplifying module, a feedback EF module and a feedforward CIFF module, wherein,
The amplifying module is connected with the second capacitor circuit and is used for amplifying the received conversion voltage;
The feedback EF module is connected with the amplifying module and is used for sampling and delaying the amplified conversion voltage so as to feed back the sampled and amplified quantization error voltage to the second capacitor circuit in the next quantization period;
The feedforward CIFF module is respectively connected with the amplifying module and the second comparator and is used for carrying out integral processing on the sampled and amplified quantization error voltage and then sending the sampled and amplified quantization error voltage after integral processing to the second comparator.
8. The pipeline-to-noise shaping successive approximation type analog-to-digital converter of claim 7, wherein the amplification module employs a passive integration loop.
9. The pipeline-noise shaping successive approximation type analog-to-digital converter of claim 4, wherein the first to sixth MOS transistors are PMOS transistors, and the seventh to fourteenth MOS transistors are NMOS transistors.
10. The pipeline-to-noise shaping successive approximation analog-to-digital converter of claim 1, wherein the first order noise shaping successive approximation analog-to-digital conversion circuit is a 5bit analog-to-digital conversion circuit, the second order noise shaping successive approximation analog-to-digital conversion circuit is a 7bit analog-to-digital conversion circuit, and the target digital signal is an 11bit digital signal.
11. A method of controlling a pipeline-noise-shaping successive approximation type analog-to-digital converter according to any one of claims 1 to 10, wherein a duty cycle of the pipeline-noise-shaping successive approximation type analog-to-digital converter comprises a sampling period, a quantization period, an integration period, which are set in sequence, the method comprising:
In the sampling period, the first-order noise shaping successive approximation type analog-digital conversion circuit is controlled to sample an input signal, the second-order noise shaping successive approximation type analog-digital conversion circuit is controlled to quantize an amplified integration result sampled in the last integration period, the obtained secondary processing result is processed, and the secondary processing result and a primary processing result obtained in the last integration period are processed to obtain a target digital signal;
in the quantization period, the first-order noise shaping successive approximation type analog-to-digital conversion circuit is controlled to quantize the sampled input signal to obtain residual voltage;
And in the integration period, controlling the inter-stage integration circuit to amplify and integrate the residual voltage, controlling the second-order noise shaping successive approximation type analog-to-digital conversion circuit to sample an amplified integration result, controlling the first-order noise shaping successive approximation type analog-to-digital conversion circuit to obtain a first-order processing result according to the residual voltage and the amplified integration result, and transmitting the first-order processing result to the second-order noise shaping successive approximation type analog-to-digital conversion circuit.
12. The control method of the pipeline-noise shaping successive approximation type analog-to-digital converter according to claim 11, wherein the sampling period is smaller than the quantization period, and wherein the quantization period is smaller than the integration period.
13. A chip, comprising: the pipeline-noise shaping successive approximation type analog-to-digital converter according to any one of claims 1-10.
14. A sensor, comprising: the chip of claim 13.
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