CN118099193A - Adjustable SGT power device and preparation method thereof - Google Patents
Adjustable SGT power device and preparation method thereof Download PDFInfo
- Publication number
- CN118099193A CN118099193A CN202410459307.1A CN202410459307A CN118099193A CN 118099193 A CN118099193 A CN 118099193A CN 202410459307 A CN202410459307 A CN 202410459307A CN 118099193 A CN118099193 A CN 118099193A
- Authority
- CN
- China
- Prior art keywords
- trench
- source
- gate
- semiconductor substrate
- switching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000002360 preparation method Methods 0.000 title abstract description 5
- 239000000758 substrate Substances 0.000 claims abstract description 82
- 239000004065 semiconductor Substances 0.000 claims abstract description 80
- 210000004027 cell Anatomy 0.000 claims abstract description 40
- 210000005056 cell body Anatomy 0.000 claims abstract description 36
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 claims abstract description 17
- 239000010410 layer Substances 0.000 claims description 210
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 91
- 229910052751 metal Inorganic materials 0.000 claims description 73
- 239000002184 metal Substances 0.000 claims description 73
- 229920005591 polysilicon Polymers 0.000 claims description 69
- 238000000034 method Methods 0.000 claims description 31
- 238000005530 etching Methods 0.000 claims description 25
- 239000011229 interlayer Substances 0.000 claims description 23
- 238000000151 deposition Methods 0.000 claims description 16
- 229910045601 alloy Inorganic materials 0.000 claims description 11
- 239000000956 alloy Substances 0.000 claims description 11
- 238000004519 manufacturing process Methods 0.000 claims description 11
- 238000000605 extraction Methods 0.000 claims description 10
- 238000005468 ion implantation Methods 0.000 claims description 9
- 238000000137 annealing Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 7
- 239000000463 material Substances 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 230000000903 blocking effect Effects 0.000 description 3
- 239000005380 borophosphosilicate glass Substances 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000001413 cellular effect Effects 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000007613 environmental effect Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 210000000746 body region Anatomy 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000007500 overflow downdraw method Methods 0.000 description 1
- 125000004437 phosphorous atom Chemical group 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000010248 power generation Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The application relates to the technical field of semiconductors, and discloses an adjustable SGT power device and a preparation method thereof, wherein the adjustable SGT power device comprises: an epitaxial layer is formed on the semiconductor substrate; the groove structure comprises a source groove group, a grid groove group and a switching groove group, wherein the source groove group is arranged in a cell area of the epitaxial layer, the grid groove group is symmetrically arranged at the side edge of the source groove group, the switching groove group is arranged on the source groove group and is positioned between the grid groove groups, and a thick oxygen oxide layer is filled between the source groove group and the grid groove group and between the grid groove group and the switching groove group; the cell body region is arranged on the semiconductor substrate and is positioned between the adjacent groove structures; the cell source region is arranged on the semiconductor substrate and correspondingly arranged on the upper surface of the cell body region; the contact hole is located at the center between adjacent trench structures. The application can switch the morphology of the SGT structure according to the actual scene, and improve the application range of the SGT power device.
Description
Technical Field
The application relates to the technical field of semiconductors, in particular to an adjustable SGT power device and a preparation method thereof.
Background
In the semiconductor manufacturing process, SGT (Shield Gate Trench) MOSFET is a novel power semiconductor device, has the advantage of low conduction loss of the traditional deep trench MOSFET in the middle-low voltage field, has lower switching loss, and is used as a switching device for a motor driving system, an inverter system and a power management system in the fields of new energy electric vehicles, novel photovoltaic power generation, energy-saving household appliances and the like, and the SGT MOSFET is a core power control component. In the related art, most of SGT MOSFET devices are designed in a single structure, so that design parameters such as gate capacitance and the like are relatively fixed, and application scenes are relatively single, and the situation needs to be changed.
Disclosure of Invention
In view of the above, the present application provides an adjustable SGT power device and a method for manufacturing the same, so as to solve the above-mentioned problems.
To achieve the above object, according to a first aspect, the following technical solution is adopted:
a tunable SGT power device comprising:
a semiconductor substrate on which an epitaxial layer is formed;
The gate trench group is symmetrically arranged at the side edge of the source trench group, the switching trench group is arranged on the source trench group and is positioned between the gate trench groups, and a thick oxygen oxide layer is filled between the source trench group and the gate trench group and between the switching trench group;
The cell body region is arranged on the semiconductor substrate and is positioned between the adjacent groove structures;
the cell source region is arranged on the semiconductor substrate and is correspondingly arranged on the upper surface of the cell body region;
The contact hole is positioned in the center between the adjacent groove structures and penetrates through the cell source region and then penetrates into the cell body region.
The application is further provided with: the source electrode groove group comprises a first groove, source electrode polycrystalline silicon and a field oxide layer, the first groove is formed in a cell area of the epitaxial layer, the field oxide layer is formed in the first groove, the source electrode polycrystalline silicon is deposited on the field oxide layer, and the thick oxide layer is located in the first groove and covers the source electrode polycrystalline silicon.
The application is further provided with: the gate groove group comprises a second groove, gate polysilicon and a gate oxide layer, wherein the second groove is symmetrically arranged on the semiconductor substrate and is close to the side edge of the first groove, the gate oxide layer is formed in the second groove, and the gate polysilicon is deposited in the second groove.
The application is further provided with: the switching groove group comprises a third groove and switching polysilicon, the third groove is arranged on the thick oxygen oxide layer, the third groove is positioned above the source polysilicon and is arranged between the second grooves, and the switching polysilicon is deposited in the third groove.
The application is further provided with: the grid polycrystalline silicon and the switching polycrystalline silicon are flush with the top surface of the semiconductor substrate, and the source polycrystalline silicon and the top surface of the semiconductor substrate are provided with set etching back heights.
The application is further provided with: an interlayer dielectric layer is arranged on the semiconductor substrate, the interlayer dielectric layer covers the source electrode groove group, the gate electrode groove group and the switching groove group, an alloy leading-out layer is deposited inside the contact hole, and the contact hole penetrates through the interlayer dielectric layer and the cell source region and then penetrates into the cell body region.
The application is further provided with: the semiconductor substrate comprises a semiconductor substrate, a dielectric layer, a front metal layer, a back metal layer and an interlayer dielectric layer, wherein the front metal layer is arranged on the top surface of the semiconductor substrate and covers the interlayer dielectric layer, and the back metal layer is arranged on one side, away from the front metal layer, of the semiconductor substrate.
The application is further provided with: the source electrode groove group is connected with a source electrode metal cushion layer, the grid electrode groove group is connected with a grid electrode metal cushion layer, the switching groove group is connected with an adjustable metal cushion layer, and the adjustable metal cushion layer is connected with the source electrode metal cushion layer or the grid electrode metal cushion layer.
According to a second aspect, the technical scheme adopted is as follows:
An adjustable SGT power device manufacturing method comprises the following steps:
providing a semiconductor substrate, and forming an epitaxial layer on the semiconductor substrate;
etching to obtain a plurality of first grooves in a cell area of the epitaxial layer, forming a field oxide layer in the first grooves, depositing source polycrystalline silicon in the first grooves and carrying out back etching for one time;
Depositing a thick oxygen oxide layer on the source polycrystalline silicon after one-time back etching, respectively etching synchronously on the semiconductor substrate and the thick oxygen oxide layer to obtain a second groove and a third groove, forming a gate oxygen oxide layer in the second groove, synchronously depositing gate polycrystalline silicon in the second groove, and depositing switching polycrystalline silicon in the third groove to form a groove structure;
forming a cell body region and a cell source region on the semiconductor substrate by ion implantation and annealing processes in sequence from aligning the groove structure;
and forming a contact hole on the semiconductor substrate, wherein the contact hole is positioned in the center between the adjacent groove structures and penetrates through the cell source region and then stretches into the cell body region.
The application is further provided with: the first groove with the source polycrystalline silicon and the field oxide layer forms a source groove group, the second groove with the gate polycrystalline silicon and the gate oxide layer forms a gate groove group, the third groove with the switching polycrystalline silicon forms a switching groove group, the source groove group is connected with a source metal cushion layer, the gate groove group is connected with a gate metal cushion layer, the switching groove group is connected with an adjustable metal cushion layer, and the adjustable metal cushion layer is connected with the source metal cushion layer or the gate metal cushion layer.
In summary, compared with the prior art, the application discloses an adjustable SGT power device and a preparation method thereof, an epitaxial layer is formed on a semiconductor substrate, a groove structure comprising a source groove group, a gate groove group and a switching groove group is arranged in a cell region of the epitaxial layer, the gate groove group is symmetrically arranged at the side edge of the source groove group, the switching groove group is arranged on the source groove group and is positioned between the gate groove groups, a thick oxide layer is filled between the source groove group and the gate groove group and between the switching groove groups, a cell body region is arranged on the semiconductor substrate and is positioned between adjacent groove structures, the cell source region is arranged on the semiconductor substrate and is correspondingly arranged on the upper surface of the cell body region, a contact hole is positioned at the center between the adjacent groove structures and penetrates through the cell source region and then is detected into the cell body region, namely through the arrangement, the switching groove group can be selectively connected with the source groove group or the gate groove group through a metal layer, so that the SGT structure appearance can be switched according to an actual scene, and the application range of the SGT power device is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following description will briefly explain the drawings needed in the description of the embodiments, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a first cross-sectional block diagram of a tunable SGT power device of the present embodiment;
FIG. 2 is a second cross-sectional block diagram of the tunable SGT power device of this embodiment;
FIG. 3 is a third cross-sectional block diagram of the tunable SGT power device of this embodiment;
FIG. 4 is a fourth cross-sectional block diagram of the tunable SGT power device of this embodiment;
FIG. 5 is a fifth cross-sectional block diagram of the tunable SGT power device of the present embodiment;
FIG. 6 is a sixth cross-sectional block diagram of the tunable SGT power device of this embodiment;
FIG. 7 is a schematic diagram of a first planar connection of the tunable SGT power device of the present embodiment;
FIG. 8 is a schematic diagram of a second planar connection of the tunable SGT power device of the present embodiment;
FIG. 9 is a flow chart of a method of fabricating an adjustable SGT power device of this embodiment.
Reference numerals: 1. a semiconductor substrate; 11. a cellular body region; 12. a cell source region; 13. a front side metal layer; 14. a back metal layer; 2. an epitaxial layer; 3. a trench structure; 4. a source trench set; 41. a first trench; 42. source polycrystalline silicon; 43. a field oxide layer; 5. a gate trench set; 51. a second trench; 52. gate polysilicon; 53. a gate oxide layer; 6. switching the group of slots; 61. a third trench; 62. switching polysilicon; 7. a thick oxide layer; 8. a contact hole; 81. an alloy extraction layer; 9. an interlayer dielectric layer; 401. a source metal pad layer; 501. a gate metal pad layer; 601. an adjustable metal cushion layer.
Detailed Description
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the application. Rather, they are merely examples of apparatus and methods consistent with aspects of the application as detailed in the accompanying claims.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, the element defined by the phrase "comprising one … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element, and furthermore, elements having the same name in different embodiments of the application may have the same meaning or may have different meanings, the particular meaning of which is to be determined by its interpretation in this particular embodiment or by further combining the context of this particular embodiment.
It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.
In the following description, suffixes such as "module", "part" or "unit" for representing elements are used only for facilitating the description of the present application, and have no specific meaning per se. Thus, "module," "component," or "unit" may be used in combination.
In the description of the present application, it should be noted that the positional or positional relationship indicated by the terms such as "upper", "lower", "left", "right", "inner", "outer", etc. are based on the positional or positional relationship shown in the drawings, are merely for convenience of describing the present application and simplifying the description, and do not indicate or imply that the apparatus or element in question must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
The technical scheme shown in the application will be described in detail through specific examples. The following description of the embodiments is not intended to limit the priority of the embodiments.
As described in the background art, most SGT MOSFET devices in the prior art are designed in a single structure, so that design parameters such as gate capacitance and the like are relatively fixed, and application scenarios are relatively single.
Referring to fig. 6, the tunable SGT power device of the present application may include a semiconductor substrate 1, a trench structure 3, a cell body region 11, a cell source region 12, and a contact hole 8.
Specifically, the semiconductor substrate 1 is formed with an epitaxial layer 2, and the trench structure 3 is designed on the epitaxial layer 2, and the trench structure 3 may include a source trench group 4, a gate trench group 5, and a switching trench group 6.
In the implementation process, the source trench set 4 is disposed in the cell region of the epitaxial layer 2, the gate trench set 5 is symmetrically arranged at the side edges of the source trench set 4, the switching trench set 6 is disposed on the source trench set 4 and is located between the gate trench sets 5, and a thick oxide layer 7 for isolating the trench sets is filled between the source trench set 4 and the gate trench set 5 and between the source trench set 6.
Further, the cell body region 11 is disposed on the semiconductor substrate 1 and between the adjacent trench structures 3, and the cell source region 12 is disposed on the semiconductor substrate 1 and correspondingly arranged on the upper surface of the cell body region 11.
The contact hole 8 is located at the center between the adjacent trench structures 3 and penetrates through the cell source region 12 and then penetrates into the cell body region 11.
In one embodiment, the epitaxial layer 2 may not be formed on the semiconductor substrate 1, i.e., the source trench set 4 is disposed in the semiconductor substrate 1, the gate trench set 5 is symmetrically arranged at the side of the source trench set 4, and the switching trench set 6 is disposed on the source trench set 4 and between the gate trench sets 5.
According to the embodiment, through the design of the groove structure 3, the switching groove group 6 can be selected to be connected with the source groove group 4 according to actual environment requirements, or the switching groove group 6 is selected to be connected with the grid groove group 5, so that different environment requirements are correspondingly met, when the switching groove group 6 is connected with the grid groove group 5 in parallel, the SGT power device of the embodiment is constructed into an SGT shape with an upper structure and a lower structure, the Miller capacitance is smaller, the switching loss is low, the sgT power device is suitable for high-frequency scene application, and when the switching groove group 6 is connected with the source groove group 4 in parallel, the SGT power device of the embodiment is constructed into an SGT shape with a left structure and a right structure, the SGT power device can resist avalanche breakdown and surge current impact, and is suitable for scene application such as power management, and the like, and therefore, the defects of single structure, single application scene and fixed parameters of the SGT MOSFET device in the related technology are overcome.
In an implementation process, the source trench set 4 may include a first trench 41, a source polysilicon 42, and a field oxide layer 43, where the first trench 41 is opened in a cell region of the epitaxial layer 2, the field oxide layer 43 is formed in the first trench 41, the source polysilicon 42 is deposited on the field oxide layer 43, and the thick oxide layer 7 is located in the first trench 41 and covers the source polysilicon 42.
The field oxide layer 43 may cover the bottom and the sidewall of the first trench 41, and the source polysilicon 42 is deposited in the first trench 41 and located on the field oxide layer 43, and further the thick oxide layer 7 is further covered on the source polysilicon 42, so that the source polysilicon 42 may be considered as being wrapped by the field oxide layer 43 and the thick oxide layer 7 in the first trench 41, and the field oxide layer 43 may exert the field oxide and isolation effects, and the thick oxide layer 7 may provide a structural basis for the formation of the switching trench group 6 and the gate trench group 5.
Further, the gate trench group 5 may include a second trench 51, a gate polysilicon 52, and a gate oxide layer 53, where the second trench 51 is symmetrically disposed on the semiconductor substrate 1 and near a side of the first trench 41, the gate oxide layer 53 is formed in the second trench 51, the gate polysilicon 52 is deposited in the second trench 51, that is, the gate oxide layer 53 may cover a sidewall of the second trench 51, and the gate polysilicon 52 is deposited in the second trench 51 and covers the gate oxide layer 53.
Further, the switching groove set 6 may include a third groove 61 and a switching polysilicon 62, wherein the third groove 61 is disposed on the thick oxide layer 7, which may be performed synchronously with the opening of the second groove 51 during the grooving process, the third groove 61 is disposed above the source polysilicon 42 and arranged between the second grooves 51, and the switching polysilicon 62 is deposited in the third groove 61.
Wherein the third trenches 61 are located between the symmetrically arranged second trenches 51 and are isolated by the thick oxygen oxide layer 7, while the third trenches 61 and the second trenches 51 are kept at a distance from the first trenches 41 and are isolated by the thick oxygen oxide layer 7.
The adjustable SGT power device of this embodiment, based on the designs of the source trench set 4, the gate trench set 5 and the switching trench set 6, can select the switching polysilicon 62 of the switching trench set 6 to be connected with the source trench set 4 or select the switching polysilicon 62 of the switching trench set 6 to be connected with the gate trench set 5 according to the actual environmental requirements, so as to be suitable for different environmental requirements.
Specifically, referring to fig. 7 and 8, the source trench group 4 is connected with the source metal pad layer 401, the gate trench group 5 is connected with the gate metal pad layer 501, the switching trench group 6 is connected with the adjustable metal pad layer 601, then the adjustable metal pad layer 601 may be connected with the source metal pad layer 401 or connected with the gate metal pad layer 501, when the adjustable metal pad layer 601 is connected with the gate metal pad layer 501 for wire bonding, i.e. the switching trench group 6 is connected with the gate trench group 5 in parallel, the SGT power device is constructed as an SGT morphology with an up-down structure, the miller capacitance is smaller, the switching loss is low, and is suitable for high frequency scene application, when the adjustable metal pad layer 601 is connected with the source metal pad layer 401 for wire bonding, i.e. the switching trench group 6 is connected with the source trench group 4 in parallel, and the SGT power device is constructed as an SGT morphology with a left-right structure, which is more resistant to avalanche breakdown and surge current impact, and is suitable for scene application such as power management.
It should be noted that, the trench structures of the switching trench group 6 and the gate trench group 5 and the polysilicon structure of the present embodiment may be formed simultaneously in the same manufacturing process, that is, the SGT process in the related art is compatible without increasing the cost, so as to improve the cost performance of the adjustable SGT power device.
In a specific implementation process, an interlayer dielectric layer 9 is disposed on the semiconductor substrate 1, the interlayer dielectric layer 9 covers the source trench group 4, the gate trench group 5 and the switching trench group 6, and the gate polysilicon 52 and the switching polysilicon 62 are flush with the top surface of the semiconductor substrate 1, so that the polysilicon structure of this embodiment is ensured to be completely buried in the trench, wherein the interlayer dielectric layer 9 can be planarized with respect to the semiconductor substrate 1, so as to eliminate the space occupied by the surface gate source dielectric isolation between the SGT device source/body contact and the polysilicon gate, improve the cell density, and also reduce the crosstalk effect between the gate sources, and finally reduce the Rsp of the device.
Further, the interlayer dielectric layer 9 may be formed of TEOS and BPSG, where TEOS (TETRAETHYL ORTHOSILICATE ) has good thermal stability and chemical inertness, and in the process of preparing the interlayer dielectric layer 9, TEOS may be deposited by Chemical Vapor Deposition (CVD) or Physical Vapor Deposition (PVD) to form a dense silicon dioxide (SiO 2) layer, and BPSG is a SiO2 material doped with boron and phosphorus, and may be deposited on the SGT device by a fusion method, so as to provide better planarization effect, and have a lower dielectric constant, which is beneficial to reduce capacitance and crosstalk effects.
In order to provide sufficient space for the thick oxide layer 7 in the first trench 41 so that the switching trench set 6 is formed on the thick oxide layer 7, the source polysilicon 42 and the top surface of the semiconductor substrate 1 have a set etching back height, i.e. after the source polysilicon 42 is deposited in the first trench 41 and is located on the field oxide layer 43, the source polysilicon 42 is etched back by the set etching back height.
It will be appreciated that in order to provide sufficient layout space for the thick oxide layer 7, the source polysilicon 42 and the field oxide layer 43 located on the sidewalls of the first trench 41 may be etched back simultaneously by a selective etching process.
The set etch back height of this embodiment includes 0.5-3um.
In some embodiments, the set back etching height is 1.8um, that is, at the set back etching height of 1.8um, the thick oxide layer 7 has enough configuration space in the first trench 41 to form the third trench 61 of the switching trench group 6, thereby ensuring the effect of isolating each trench group by the thick oxide layer 7 and improving the stability of the device.
It should be noted that, in this embodiment, the alloy extraction layer 81 is deposited inside the contact hole 8, the contact hole 8 penetrates through the interlayer dielectric layer 9 and the cell source region 12 and then is inserted into the cell body region 11, that is, the contact hole 8 is extracted and externally connected through the alloy extraction layer 81, for example, the source metal pad layer 401, the gate metal pad layer 501, the adjustable metal pad layer 601 and the like are connected through the alloy extraction layer 81, wherein the forming material of the alloy extraction layer 81 may include Ti or TiN, W and the like.
In some embodiments, the contact holes 8 may be of a cubic or a cubic taper design.
In a specific implementation process, the adjustable SGT power device further includes a front metal layer 13 and a back metal layer 14, the front metal layer 13 is disposed on the top surface of the semiconductor substrate 1, and covers the inter-layer dielectric layer 9 for surface protection and passivation of the adjustable SGT power device, and provides PAD for the alloy extraction layer 81, thereby providing electrical connection and signal transmission, and the back metal layer 14 is disposed on a side of the semiconductor substrate 1 facing away from the front metal layer 13 for playing a drain function.
In the process of forming the back metal layer 14, the semiconductor substrate 1 may be thinned to a certain thickness, and then the back metal layer 14 is formed by depositing metal.
The semiconductor substrate 1, the epitaxial layer 2, and the cell source region 12 of the present embodiment have a first conductivity type, the cell body region 11 has a second conductivity type, and the ion implantation type for forming the contact hole 8 is the same as that of the cell body region 11, wherein the first conductivity type may include a P-type or an N-type, and the second conductivity type may include an N-type or a P-type.
Referring to fig. 9, this embodiment also discloses a method for manufacturing an adjustable SGT power device, where the method for manufacturing an adjustable SGT power device according to any one of the above embodiments may include:
s101, a semiconductor substrate 1 is provided, and an epitaxial layer 2 is formed on the semiconductor substrate 1.
In a specific implementation, referring to fig. 1, an epitaxial layer 2 may be deposited on a semiconductor substrate 1 by an epitaxial growth process.
The semiconductor substrate 1 of this embodiment may be formed of monocrystalline silicon, polycrystalline silicon, amorphous silicon, doped silicon, or the like, and the semiconductor substrate 1 may be formed of SiGe substrate, iii-v compound substrate, silicon carbide substrate, or a stacked structure thereof, or a silicon-on-insulator structure, or may be formed of diamond substrate or other semiconductor material substrate known to those skilled in the art, for example, P atoms may be implanted into monocrystalline silicon to form an N-type conductive semiconductor substrate, or B atoms may be implanted into monocrystalline silicon to form a P-type conductive semiconductor substrate, so as to improve the selectivity of the material and the adaptability to the actual production environment.
The semiconductor substrate 1 and the epitaxial layer 2 are the same type of ion implantation.
S102, etching a plurality of first trenches 41 in a cell region of the epitaxial layer 2, forming a field oxide layer 43 in the first trenches 41, depositing source polysilicon 42 in the first trenches 41 and etching back once.
In this step, with continued reference to fig. 1, etching the plurality of first trenches 41 may specifically include: and depositing a blocking layer on the epitaxial layer 2, photoetching and exposing a groove pattern by taking the blocking layer as a hard mask, carrying out dry etching on a cell area of the epitaxial layer 2 through the groove pattern to obtain a plurality of first grooves 41, and removing the blocking layer after the first grooves 41 are obtained.
The formation of the field oxide layer 43 may be achieved by a diffusion growth process or a chemical vapor deposition method, and the obtained field oxide layer 43 may cover the bottom and the sidewall of the first trench 41, thereby providing a structural foundation for the deposition of the source polysilicon 42 in the first trench 41.
In some embodiments, the deposited thickness of field oxide layer 43 comprises 0.1-1um.
It should be noted that, after the source polysilicon 42 is deposited, a back etching needs to be performed on the source polysilicon 42 to ensure that the top surface of the source polysilicon 42 is located below the notch of the first trench 41, so as to provide sufficient layout space for the subsequent thick oxide layer 7, so that the switching trench group 6 meets the set requirement and is formed on the thick oxide layer 7.
In the process of etching back the source polysilicon 42, the field oxide layer 43 on the sidewall of the first trench 41 can be removed simultaneously by a selective etching process, so as to ensure that the space of the etched back first trench 41 is neat.
That is, the source polysilicon 42 in this embodiment has a set etch back height H, which may include 0.5-3um.
The etch back height H is set to 1.8um in some embodiments.
S103, depositing a thick oxygen oxide layer 7 on the source polycrystalline silicon 42 after one time of back etching, synchronously etching to obtain a second groove 51 and a third groove 61 on the semiconductor substrate 1 and the thick oxygen oxide layer 7 respectively, forming a gate oxygen oxide layer 53 in the second groove 51, synchronously depositing a gate polycrystalline silicon 52 in the second groove 51, and depositing a switching polycrystalline silicon 62 in the third groove 61 to form the groove structure 3.
In this step, referring to fig. 2 and 3, the second trench 51 and the third trench 61 are simultaneously formed on the semiconductor substrate 1 and the thick oxygen oxide layer 7, i.e., the gate oxide layer 53 may cover the sidewall of the second trench 51, the gate polysilicon 52 is deposited in the second trench 51 and covers the gate oxide layer 53, and the switching polysilicon 62 is deposited in the third trench 61.
Further, the third trench 61 is located above the source polysilicon 42 and is arranged between the second trenches 51.
The formation of the thick oxide layer 7 in this embodiment may be obtained by an HDP (High-DENSITY PLASMA) or CVD (Chemical Vapor Deposition) process, where the deposition thickness of the thick oxide layer 7 may include 0.3-1.2um, and after the thick oxide layer 7 is formed, a second etching back process may be performed on the thick oxide layer 7, so that the thick oxide layer 7 is flush with the top surface of the semiconductor substrate 1, so as to facilitate the formation of the third trench 61.
In some embodiments, the deposited thickness of gate oxide layer 53 may comprise 0.04-0.1um.
In some embodiments, the deposited thickness of gate polysilicon 52 may comprise 0.6-1.2um.
The gate polysilicon 52 and the switching polysilicon 62 may be formed by a furnace tube thermal growth process, and three etchbacks may be performed after the gate polysilicon 52 and the switching polysilicon 62 are formed, so that the gate polysilicon 52 and the switching polysilicon 62 are flush with the top surface of the semiconductor substrate 1.
The source polysilicon 42 after one etching back is matched with the first trench 41 and the field oxide layer 43 to form a source trench group 4, the gate polysilicon 52 is matched with the second trench 51 and the gate oxide layer 53 to form a gate trench group 5, and the switching polysilicon 62 is matched with the third trench 61 to form a switching trench group 6.
Namely, the source trench set 4, the gate trench set 5 and the switching trench set 6 can form a trench structure 3, the trench structure 3 is designed on the epitaxial layer 2, the source trench set 4 is arranged in a cellular region of the epitaxial layer 2, the gate trench set 5 is symmetrically arranged at the side edge of the source trench set 4, the switching trench set 6 is arranged on the source trench set 4 and is positioned between the gate trench sets 5, and a thick oxygen oxide layer 7 for isolating the trench sets is filled between the source trench set 4 and the gate trench set 5 and between the switching trench set 6.
S104, forming a cell body region 11 and a cell source region 12 on the semiconductor substrate 1 by the self-aligned groove structure 3 through ion implantation and annealing processes.
In this step, referring to fig. 4, the formation of the cell body region 11 and the cell source region 12 is based on the self-aligned process of the trench structures 3, the cell body region 11 is on the semiconductor substrate 1 and is located between the adjacent trench structures 3, and the cell source region 12 is correspondingly arranged on the upper surface of the cell body region 11 on the semiconductor substrate 1, that is, on the basis that the cell source region 12 is formed on the cell body region 11, it may be considered that the cell body region 11 overlaps on the cell source region 12.
In some embodiments, P-type impurities may be used for the formation of the cell body region 11, for example, with boron ion implantation into the substrate, while N-type impurities may be used for the formation of the cell source region 12, for example, with phosphorus or arsenic ion implantation into the substrate, thereby altering its conductive properties.
S105, forming a contact hole 8 on the semiconductor substrate 1, wherein the contact hole 8 is located at the center between the adjacent trench structures 3, penetrates through the cell source region 12 and then penetrates into the cell body region 11.
In this step, referring to fig. 5 and 6, the ion implantation type for forming the contact hole 8 may be the same as the ion implantation type for forming the cell body region 11.
The contact hole 8 may be in a cubic structure design and an alloy extraction layer 81 is deposited inside, i.e. the contact hole 8 is extracted and externally connected through the alloy extraction layer 81.
The adjustable SGT power device of this embodiment may further include, before forming the contact hole 8: an interlayer dielectric layer 9 is deposited on the semiconductor substrate 1 and subjected to high-temperature reflow planarization, and then the interlayer dielectric layer 9 covers the source trench set 4, the gate trench set 5 and the switching trench set 6.
The interlayer dielectric layer 9 is formed of TEOS and BPSG materials, and is planarized by high temperature reflow, and the interlayer dielectric layer 9 is processed by etching or CMP (chemical polishing) so that the interlayer dielectric layer 9 is flush with the top surface of the semiconductor substrate 1.
The adjustable SGT power device of this embodiment may further include, after forming the contact hole 8: a front side metal layer 13 covering the inter-layer dielectric layer 9 is formed on the top side of the semiconductor substrate 1, and a back side metal layer 14 is formed on the side of the semiconductor substrate 1 facing away from the front side metal layer 13.
Front side metal layer 13 is used for surface protection and passivation of the tunable SGT power device and provides PAD for alloy extraction layer 81 to provide electrical connection and signal transmission, and back side metal layer 14 is used for drain function.
Further, referring to fig. 7 and 8, the first trench 41 having the source polysilicon 42 and the field oxide layer 43 forms the source trench group 4, the second trench 51 having the gate polysilicon 52 and the gate oxide layer 53 forms the gate trench group 5, the third trench 61 having the switching polysilicon 62 forms the switching trench group 6, the source trench group 4 is connected with the source metal pad layer 401, the gate trench group 5 is connected with the gate metal pad layer 501, the switching trench group 6 is connected with the adjustable metal pad layer 601, the adjustable metal pad layer 601 is connected with the source metal pad layer 401 or the gate metal pad layer 501, it is understood that the source metal pad layer 401 is connected with the source polysilicon 42 through the contact hole 8 and the gate metal pad layer 501 is connected with the gate polysilicon 52 through the contact hole 8 to form the gate region, the adjustable metal pad layer 601 is connected with the switching polysilicon 62 through the contact hole 8 to form the adjustable switching region, and the adjustable switching region can be selectively connected with the source region or the gate region.
The field oxide layer 43, the thick oxide layer 7, and the gate oxide layer 53 of this embodiment may be formed of the same material.
In summary, the application discloses an adjustable SGT power device and a manufacturing method thereof, an epitaxial layer 2 is formed on a semiconductor substrate 1, a trench structure 3 comprising a source trench group 4, a gate trench group 5 and a switching trench group 6 is arranged in a cell region of the epitaxial layer 2, the gate trench group 5 is symmetrically arranged at the side edge of the source trench group 4, the switching trench group 6 is arranged on the source trench group 4 and is positioned between the gate trench groups 5, a thick oxide layer 7 is filled between the source trench group 4 and the gate trench group 5 and between the switching trench group 6, a cell body region 11 is arranged on the semiconductor substrate 1 and is positioned between adjacent trench structures 3, a cell source region 12 is arranged on the semiconductor substrate 1 and is correspondingly arranged on the upper surface of the cell body region 11, the contact hole 8 is located at the center between the adjacent trench structures 3 and penetrates through the cell source region 12 and then penetrates into the cell body region 11, so that the switching trench group 6 can be connected with the source trench group 4 or the gate trench group 5 through cushion layer selection, namely when the switching trench group 6 is connected with the gate trench group 5 in parallel, the SGT power device of the embodiment is constructed into an SGT morphology of an upper structure and a lower structure, the miller capacitance is smaller, the switching loss is low, the sgT power device is suitable for high-frequency scene application, and when the switching trench group 6 is connected with the source trench group 4 in parallel, the SGT power device of the embodiment is constructed into an SGT morphology of a left-right structure, the SGT power device is more resistant to avalanche breakdown and surge current impact, and is suitable for scene application such as power management, so that the SGT structure morphology can be switched according to actual scenes, and the application range of the SGT power device is improved.
The foregoing has outlined rather broadly the more detailed description of the application in order that the detailed description of the principles and embodiments of the application may be implemented in conjunction with the detailed description of the embodiments that follow; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in light of the ideas of the present application, the present description should not be construed as limiting the present application.
Claims (10)
1. A tunable SGT power device, comprising:
a semiconductor substrate on which an epitaxial layer is formed;
The gate trench group is symmetrically arranged at the side edge of the source trench group, the switching trench group is arranged on the source trench group and is positioned between the gate trench groups, and a thick oxygen oxide layer is filled between the source trench group and the gate trench group and between the switching trench group;
The cell body region is arranged on the semiconductor substrate and is positioned between the adjacent groove structures;
the cell source region is arranged on the semiconductor substrate and is correspondingly arranged on the upper surface of the cell body region;
The contact hole is positioned in the center between the adjacent groove structures and penetrates through the cell source region and then penetrates into the cell body region.
2. The tunable SGT power device of claim 1, wherein the source trench set includes a first trench open to a cell region of the epitaxial layer, source polysilicon deposited on the field oxide layer, and a field oxide layer in the first trench and covering the source polysilicon.
3. The tunable SGT power device of claim 2, wherein the set of gate trenches includes a second trench symmetrically disposed on the semiconductor substrate and adjacent to a side of the first trench, gate polysilicon and a gate oxide layer formed within the second trench, the gate polysilicon deposited in the second trench.
4. The tunable SGT power device of claim 3, wherein the set of switching trenches includes a third trench open on the thick oxide layer and a switching polysilicon disposed above the source polysilicon and between the second trenches, the switching polysilicon deposited in the third trench.
5. The tunable SGT power device of claim 4, wherein the gate polysilicon and the switching polysilicon are level with a top surface of the semiconductor substrate, and the source polysilicon has a set etch back height with the top surface of the semiconductor substrate.
6. The tunable SGT power device of claim 1, wherein an interlayer dielectric layer is disposed on the semiconductor substrate, wherein the interlayer dielectric layer covers the source trench set, the gate trench set, and the switching trench set, wherein an alloy extraction layer is deposited inside the contact hole, and wherein the contact hole penetrates through the interlayer dielectric layer and the cell source region and then extends into the cell body region.
7. The tunable SGT power device of claim 6, further comprising a front side metal layer disposed on a top surface of the semiconductor substrate and covering the interlayer dielectric layer, and a back side metal layer disposed on a side of the semiconductor substrate facing away from the front side metal layer.
8. The tunable SGT power device of claim 1, wherein the source trench group is connected with a source metal pad, the gate trench group is connected with a gate metal pad, the switching trench group is connected with a tunable metal pad, and the tunable metal pad is connected with either the source metal pad or the gate metal pad.
9. An adjustable SGT power device manufacturing method, comprising:
providing a semiconductor substrate, and forming an epitaxial layer on the semiconductor substrate;
etching to obtain a plurality of first grooves in a cell area of the epitaxial layer, forming a field oxide layer in the first grooves, depositing source polycrystalline silicon in the first grooves and carrying out back etching for one time;
Depositing a thick oxygen oxide layer on the source polycrystalline silicon after one-time back etching, respectively etching synchronously on the semiconductor substrate and the thick oxygen oxide layer to obtain a second groove and a third groove, forming a gate oxygen oxide layer in the second groove, synchronously depositing gate polycrystalline silicon in the second groove, and depositing switching polycrystalline silicon in the third groove to form a groove structure;
forming a cell body region and a cell source region on the semiconductor substrate by ion implantation and annealing processes in sequence from aligning the groove structure;
and forming a contact hole on the semiconductor substrate, wherein the contact hole is positioned in the center between the adjacent groove structures and penetrates through the cell source region and then stretches into the cell body region.
10. The method of manufacturing a tunable SGT power device of claim 9, wherein the first trench with the source polysilicon and the field oxide layer forms a source trench group, the second trench with the gate polysilicon and the gate oxide layer forms a gate trench group, the third trench with the switching polysilicon forms a switching trench group, the source trench group is connected with a source metal pad, the gate trench group is connected with a gate metal pad, the switching trench group is connected with a tunable metal pad, the tunable metal pad is connected with the source metal pad or the gate metal pad.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410459307.1A CN118099193A (en) | 2024-04-17 | 2024-04-17 | Adjustable SGT power device and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410459307.1A CN118099193A (en) | 2024-04-17 | 2024-04-17 | Adjustable SGT power device and preparation method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN118099193A true CN118099193A (en) | 2024-05-28 |
Family
ID=91149266
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202410459307.1A Pending CN118099193A (en) | 2024-04-17 | 2024-04-17 | Adjustable SGT power device and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN118099193A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103137699A (en) * | 2011-11-29 | 2013-06-05 | 株式会社东芝 | Semiconductor device for power and method of manufacture thereof |
| US20160315053A1 (en) * | 2011-04-28 | 2016-10-27 | Ji Pan | Flexible crss adjustment in a sgt mosfet to smooth waveforms and to avoid emi in dc-dc application |
| CN114242786A (en) * | 2021-11-10 | 2022-03-25 | 南瑞联研半导体有限责任公司 | Shielded gate type IGBT device and manufacturing method thereof |
| CN117712156A (en) * | 2023-12-21 | 2024-03-15 | 江苏易矽科技有限公司 | SGT IGBT structure with adjustable capacitance and preparation method |
-
2024
- 2024-04-17 CN CN202410459307.1A patent/CN118099193A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20160315053A1 (en) * | 2011-04-28 | 2016-10-27 | Ji Pan | Flexible crss adjustment in a sgt mosfet to smooth waveforms and to avoid emi in dc-dc application |
| CN103137699A (en) * | 2011-11-29 | 2013-06-05 | 株式会社东芝 | Semiconductor device for power and method of manufacture thereof |
| CN114242786A (en) * | 2021-11-10 | 2022-03-25 | 南瑞联研半导体有限责任公司 | Shielded gate type IGBT device and manufacturing method thereof |
| CN117712156A (en) * | 2023-12-21 | 2024-03-15 | 江苏易矽科技有限公司 | SGT IGBT structure with adjustable capacitance and preparation method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI542018B (en) | Mosfet with integrated schottky diode | |
| CN101635277B (en) | Spacer shape engineering for void-free gap-filling process | |
| KR100232319B1 (en) | Large value capacitor for soi | |
| US7858457B2 (en) | Methods of forming integrated circuit devices including a depletion barrier layer at source/drain regions | |
| CN103887342B (en) | Groove MOSFET and preparation method thereof | |
| JPH0851208A (en) | Soi transistor with self-matching base body contact and its preparation | |
| GB2383190A (en) | Bipolar junction transistor compatible with vertical replacment gate transistors | |
| GB2381124A (en) | Integrated circuits comprising vertical tranistors and capaci rs | |
| US9601382B2 (en) | Method for the formation of a FinFET device with epitaxially grown source-drain regions having a reduced leakage path | |
| CN103208424B (en) | For manufacturing method and the field-effect semiconductor element of semiconductor element | |
| US20120132986A1 (en) | Semiconductor devices and methods of manufacturing the same | |
| US8048760B2 (en) | Semiconductor structure and method of manufacture | |
| KR20140132662A (en) | Silicon-on-insulator itergrated circuits with local oxidation of silicon and methods for fabricating the same | |
| US20140147985A1 (en) | Methods for the fabrication of semiconductor devices including sub-isolation buried layers | |
| CN116884972A (en) | SGT power device and manufacturing method thereof | |
| CN101924103A (en) | Groove type power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) and manufacturing method thereof | |
| CN118099193A (en) | Adjustable SGT power device and preparation method thereof | |
| TW201731100A (en) | VDMOS and method for making the same | |
| CN114496762A (en) | Method for manufacturing trench MOSFET | |
| EP1067599B1 (en) | A method of forming structures with buried oxide regions in a semiconductor substrate | |
| CN117747672A (en) | SGT device and method of making same | |
| KR100729016B1 (en) | Trench type mosfet and method of making the same | |
| CN116190227B (en) | IGBT chip preparation method and IGBT chip | |
| US20100289074A1 (en) | Semiconductor device and method of fabricating the same | |
| CN117747671A (en) | SGT MOSFET device and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination |