CN118096767A - Wafer cutting defect detection method, system, equipment and storage medium - Google Patents

Wafer cutting defect detection method, system, equipment and storage medium Download PDF

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CN118096767A
CN118096767A CN202410521657.6A CN202410521657A CN118096767A CN 118096767 A CN118096767 A CN 118096767A CN 202410521657 A CN202410521657 A CN 202410521657A CN 118096767 A CN118096767 A CN 118096767A
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Abstract

The invention provides a wafer cutting defect detection method, a system, equipment and a storage medium, which relate to the technical field of defect detection and comprise the following steps: firstly, carrying out defect classification detection on a grain image based on a multi-classification model to obtain a defect classification detection result; if the defect classification detection result is that the wafer is poorly cut, extracting the image contour of the grain image to obtain the luminous area information and the open ring information of the grain image; then constructing a first minimum circumscribed rectangle and a second minimum circumscribed rectangle based on the luminous area information and the open ring information of the grain image; and finally, judging the severity level of the defect based on the distance between the first minimum circumscribed rectangle and the second minimum circumscribed rectangle so as to obtain a judgment result of the defective level of the wafer cutting. The invention adopts a mode of combining deep learning and machine vision to detect the defects, and solves the problems that the existing wafer appearance defect detection cannot measure the defect influence degree and is easy to cause over-detection and omission.

Description

Wafer cutting defect detection method, system, equipment and storage medium
Technical Field
The present invention relates to the field of defect detection technologies, and in particular, to a method, a system, an apparatus, and a storage medium for detecting defective wafer dicing.
Background
In the chip production process, appearance defect detection is required to be performed on the crystal grains on the wafer so as to evaluate whether the quality of each crystal grain is qualified. Appearance defect detection is a process of detecting whether appearance defects such as dirt, scratch, breakage, metal residue, needle mark abnormality, cutting failure and the like exist on the surface of a crystal grain.
The existing wafer appearance defect detection method comprises the following steps: 1. machine vision methods (CV methods); 2. deep learning method. The machine vision method can realize defect detection, but has the defects of high time consumption and incapability of realizing defect classification. The deep learning method can realize detection and classification of defects, but has the defects of over-detection and omission easily caused by incapability of measuring the influence degree of the defects for the defect types with insignificant defect characteristics, such as wafer cutting failure.
Disclosure of Invention
The invention provides a wafer cutting defect detection method, a system, equipment and a storage medium, which solve the problems that the existing wafer appearance defect detection cannot measure the defect influence degree and is easy to cause over-detection and omission.
In a first aspect, an embodiment of the present invention provides a method for detecting a defective wafer dicing, including the following steps:
Performing defect classification detection on the grain image based on the multi-classification model to obtain a defect classification detection result;
if the defect classification detection result is that the wafer is poorly cut, extracting the image contour of the grain image to obtain the luminous area information and the open ring information of the grain image;
Constructing a first minimum circumscribed rectangle and a second minimum circumscribed rectangle based on the luminous area information and the open ring information of the grain image, and calculating the distance between the first minimum circumscribed rectangle and the second minimum circumscribed rectangle;
And judging the severity level of the defect based on the distance between the first minimum circumscribed rectangle and the second minimum circumscribed rectangle so as to obtain a judgment result of the defective level of the wafer cutting.
In the embodiment, the invention adopts a mode of combining deep learning and machine vision to detect the defects, firstly adopts a deep learning technology to detect and classify the defects, and then adopts a machine vision technology to judge the severity level of the defects of poor wafer cutting, so that the influence degree of the defects can be measured, and the problem that the existing defect detection technology is easy to over-detect and miss-detect is solved.
As some optional embodiments of the present application, before performing defect classification detection on a grain image based on a multi-classification model, model training is required, where the flow of model training is as follows:
acquiring a wafer image, and performing image binarization and image segmentation on the wafer image to obtain grain images of different defect types;
Performing defect classification and feature marking on the grain images with different defect types to construct training sample sets with different defect types;
model training is carried out on the deep learning model based on training sample sets of different defect types so as to obtain a multi-classification model.
In the above embodiment, the present invention enables the multi-classification model to detect and classify defects of the die image by performing model training on the deep learning model.
As some optional embodiments of the present application, the process of performing image binarization and image segmentation on a wafer image to obtain die images of different defect types is as follows:
performing image binarization on the wafer image to obtain a wafer binarization image;
and performing image positioning on the wafer binarized image to obtain grain position information, and performing image segmentation on the wafer image based on the grain position information to obtain grain images of different defect types.
In the above embodiment, the present invention can locate the die position by performing image binarization on the wafer image to obtain die position information; and through analysis of the crystal grain position information, the crystal grain images with different defect types can be segmented from the original wafer image.
As some optional embodiments of the present application, the process of extracting the image contour of the grain image to obtain the light emitting area information and the open ring information of the grain image is as follows:
Extracting image contours of the grain images to be detected to obtain coordinate information of edge contours;
And selecting the relative position and roundness of the edge contour based on the coordinate information of the edge contour to obtain the luminous area information and the open ring information of the grain image.
In the above embodiment, the present invention can obtain texture information of the image surface by performing edge contour image on the grain image; and by carrying out position selection and roundness selection on the texture information of the image surface, the luminous area information and the open ring information of the grain image surface can be positioned.
As some optional embodiments of the present application, the process of selecting the relative position and roundness of the edge profile based on the coordinate information of the edge profile to obtain the light emitting region information and the open ring information of the grain image is as follows:
Selecting coordinate information corresponding to the edge contour of the outermost layer from the coordinate information of the edge contour as luminous area information;
Calculating the distance from each contour point of the edge contour to the circle center of the circumscribing circle and the average distance from all contour points to the circle center of the circumscribing circle based on the coordinate information of the edge contour;
And calculating the roundness of the edge contour based on the distance from each contour point to the circle center of the circumscribing circle and the average distance from all the contour points to the circle center of the circumscribing circle, and selecting the coordinate information corresponding to the edge contour with the maximum roundness as the open ring information.
In the above embodiment, the present invention combines the actual structural features of the die to locate the light emitting region and the split ring, thereby obtaining the light emitting region information and the split ring information.
As some optional embodiments of the present application, the calculation formula of the roundness of the edge profile is as follows:
Wherein R represents the average distance from all the contour points to the circle center of the circumscribing circle, and S represents the average deviation between the distance from each contour point to the circle center of the circumscribing circle and the average distance from all the contour points to the circle center of the circumscribing circle.
As some optional embodiments of the present application, the calculation formula of the average distance from all contour points to the center of the circumscribing circle is as follows:
Wherein, Represents the/>The number of all contour points of the edge contour, P represents the/>J-th contour point of edge contour,/>Represents the/>The circle centers of the circumscribing circles of the edge profiles.
As some optional embodiments of the present application, the calculation formula of the average deviation between the distance from each contour point to the center of the circumscribing circle and the average distance from all contour points to the center of the circumscribing circle is as follows:
Wherein, Represents the/>The number of all contour points of the edge contour, P represents the/>J-th contour point of edge contour,/>Represents the/>And R represents the average distance from all contour points to the circle center of the circumscribing circle.
As some optional embodiments of the present application, a procedure of constructing a first minimum bounding rectangle and a second minimum bounding rectangle based on light emitting region information and open ring information of a die image, and calculating distances of the first minimum bounding rectangle and the second minimum bounding rectangle is as follows:
Extracting a first minimum circumscribed rectangle based on the luminous area information of the grain image to obtain coordinate information of the first minimum circumscribed rectangle;
constructing a minimum circumscribing circle of the split ring based on the split ring information of the grain image, and extracting a second minimum circumscribing rectangle based on the minimum circumscribing circle to obtain coordinate information of the second minimum circumscribing rectangle;
And calculating the outer edge line distance of the first minimum bounding rectangle and the second minimum bounding rectangle based on the coordinate information of the first minimum bounding rectangle and the coordinate information of the first minimum bounding rectangle.
In the above embodiment, the present invention can obtain the first minimum bounding rectangle and the second minimum bounding rectangle representing the positions thereof by extracting the coordinate information of the light emitting region information and the split ring information.
As some optional embodiments of the present application, the process of determining the severity level of the defect based on the distance between the first minimum bounding rectangle and the second minimum bounding rectangle to obtain the determination result of the wafer dicing defect level is as follows:
Carrying out positive and negative judgment and threshold judgment on the outer line distances of the first minimum circumscribed rectangle and the second minimum circumscribed rectangle to obtain a positive and negative judgment result and a threshold judgment result;
and carrying out defect severity level judgment based on the positive and negative judgment results and the threshold judgment result to obtain a wafer cutting failure level judgment result.
In the above embodiment, the present invention performs threshold determination on the outer edge distance between the first minimum circumscribed rectangle and the second minimum circumscribed rectangle, so that the intersection condition of the light emitting region and the open ring can be determined, and further, defect severity level determination can be performed according to the intersection condition of the light emitting region and the open ring, so as to obtain a wafer cutting defect level determination result.
In a second aspect, the present invention provides a wafer under-cut defect detection system, the system comprising:
the model classification detection unit is used for carrying out defect classification detection on the grain image based on the multi-classification model so as to obtain a defect classification detection result;
The image contour extraction unit is used for extracting the image contour of the grain image so as to obtain the luminous area information and the open ring information of the grain image;
The rectangular distance detection unit is used for constructing a first minimum circumscribed rectangle and a second minimum circumscribed rectangle based on the luminous area information and the open ring information of the grain image, and calculating the distance between the first minimum circumscribed rectangle and the second minimum circumscribed rectangle;
and the defect grade judging unit is used for judging the severity grade of the defect based on the distance between the first minimum circumscribed rectangle and the second minimum circumscribed rectangle so as to obtain a wafer cutting defect grade judging result.
In a third aspect, the present invention provides a computer device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, the processor implementing the wafer dicing defect detection method when executing the computer program.
In a fourth aspect, the present invention provides a computer readable storage medium having a computer program stored thereon, which when executed by a processor, implements the method for detecting wafer dicing defects.
The beneficial effects of the invention are as follows: the invention adopts a mode of combining deep learning and machine vision to detect the defects, firstly carries out detection and classification of the defects through a deep learning technology, then carries out defect severity level judgment on the defects of poor wafer cutting through a machine vision technology, can measure the influence degree of the defects, and solves the problem that the existing defect detection technology is easy to overstock and miss.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a computer device in a hardware operating environment according to an embodiment of the present invention;
FIG. 2 is a flow chart of a method for detecting defective dicing of a wafer according to an embodiment of the invention;
FIG. 3 is a diagram illustrating an example of a local position structure of a wafer image according to an embodiment of the present invention;
FIG. 4 is a diagram of a wafer binarized image according to an embodiment of the present invention;
FIG. 5 is an exemplary diagram of training samples of different defect types according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a wafer under-cut according to an embodiment of the present invention;
FIG. 7 is a schematic view illustrating the positioning of the light emitting region and the outline of the split ring according to an embodiment of the present invention;
FIG. 8 is a diagram showing an example of judgment of intersection of a light emitting region and a split ring according to an embodiment of the present invention;
Fig. 9 is a block diagram of a system for detecting defective dicing of a wafer according to an embodiment of the invention.
Detailed Description
It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.
In order to solve the problems that the existing wafer appearance defect detection cannot measure the defect influence degree and overstock and omission are easy to occur. The application provides a wafer cutting defect detection method, a system, equipment and a storage medium.
Referring to fig. 1, fig. 1 is a schematic diagram of a computer device structure of a hardware running environment according to an embodiment of the present application.
As shown in fig. 1, the computer device may include: a processor, such as a central processing unit (Central Processing Unit, CPU), a communication bus, a user interface, a network interface, a memory. Wherein the communication bus is used to enable connection communication between these components. The user interface may comprise a Display, an input unit such as a Keyboard (Keyboard) and optionally a standard wired interface, a wireless interface. The network interface may optionally include a standard wired interface, a wireless interface (e.g., a wireless fidelity interface). The Memory may be a high-speed random access Memory (Random Access Memory, RAM) Memory, a stable Non-Volatile Memory (NVM), such as a disk Memory, or alternatively may be a storage device independent of the aforementioned processor.
Those skilled in the art will appreciate that the architecture shown in fig. 1 is not limiting of a computer device and may include more or fewer components than shown, or may combine certain components, or a different arrangement of components.
As shown in fig. 1, an operating system, a data storage module, a network communication module, a user interface module, and an electronic program module may be included in a memory as one type of storage medium.
In the computer device shown in fig. 1, the network interface is mainly used for data communication with the network server; the user interface is mainly used for carrying out data interaction with a user; the processor and the memory in the computer equipment can be arranged in the computer equipment, and the computer equipment calls the wafer defective cutting defect detection system stored by the electronic program module through the processor and executes the wafer defective cutting defect detection method provided by the embodiment of the application.
Based on the hardware environment of the foregoing embodiments, an embodiment of the present application provides a method for detecting a defective wafer dicing defect, referring to fig. 2, fig. 2 is a flowchart of the method for detecting a defective wafer dicing defect, and the method flow is as follows:
(1) And carrying out defect classification detection on the grain image based on the multi-classification model to obtain a defect classification detection result, wherein the defect classification detection result comprises, but is not limited to, appearance defects such as dirt, scratch, breakage, metal residue, needle mark abnormality, cutting defect and the like.
In the embodiment of the invention, before defect classification detection is performed on a grain image based on a multi-classification model, model training is required, and the model training process is as follows:
(1.1) obtaining a wafer image, and performing image binarization and image segmentation on the wafer image to obtain die images with different defect types, wherein one wafer image may have hundreds of thousands of dies, please refer to fig. 3, and fig. 3 is a diagram illustrating a local position structure of the wafer image.
(1.2) Performing defect classification and feature labeling on the grain images with different defect types to construct training sample sets with different defect types, wherein the defect classification includes but is not limited to appearance defects such as dirt, scratch, breakage, metal residue, needle mark abnormality, poor cutting and the like, please refer to fig. 5, and fig. 5 is a diagram of training sample examples with different defect types.
(1.3) Model training the deep learning model based on training sample sets of different defect types to obtain a multi-classification model, wherein the deep learning model includes but is not limited toAnd (5) a model.
Specifically, the process of performing image binarization and image segmentation on the wafer image to obtain the die images with different defect types is as follows:
(1.11) performing image binarization on the wafer image to obtain a wafer binarized image, referring to fig. 4, wherein the white area is the die position.
(1.12) Performing image positioning on the wafer binarized image to obtain grain position information, and performing image segmentation on the wafer image based on the grain position information to obtain grain images of different defect types; firstly, acquiring the position information of the crystal grains from the binarized image of the wafer, and then, carrying out image segmentation on the corresponding position of the original wafer image to obtain the crystal grain images with different defect types.
(2) If the defect classification detection result is that the wafer is poorly cut, image contour extraction is carried out on the grain image so as to obtain luminous area information and open ring information of the grain image.
In the embodiment of the invention, the process of extracting the image contour of the grain image to obtain the luminous area information and the open ring information of the grain image is as follows:
(2.1) extracting image contours of the to-be-detected grain images to obtain coordinate information of a plurality of edge contours, referring to fig. 6, fig. 6 is a schematic diagram of poor wafer dicing, wherein a white area is an electrode area, a black loop line outside the white area is an open loop, and a rectangular area at the outermost layer is a light-emitting area; the poor dicing of the wafer refers to the situation that the dicing line cuts into the split ring when dicing the die on one wafer; in addition, higher demand products may require that the cut line not cut to the split ring, and that the cut must be scrapped within a certain distance of the split ring, thus requiring accurate positioning measures.
And (2.2) selecting the relative position and roundness of the edge contour based on the coordinate information of the edge contour to obtain the luminous area information and the open ring information of the grain image.
Specifically, the process of selecting the relative position and roundness of the edge contour based on the coordinate information of the edge contour to obtain the light emitting area information and the open ring information of the grain image is as follows:
(2.21) selecting coordinate information corresponding to the edge profile of the outermost layer from the coordinate information of the edge profile as the light emitting region information.
And (2.22) calculating the distance from each contour point of the edge contour to the circle center of the circumscribing circle and the average distance from all contour points to the circle center of the circumscribing circle based on the coordinate information of the edge contour.
(2.23) Calculating the roundness of the edge contour based on the distance from each contour point to the center of the circumscribing circle and the average distance from all the contour points to the center of the circumscribing circle, and selecting the coordinate information corresponding to the edge contour with the maximum roundness as the open ring information, please refer to fig. 7, fig. 7 is a schematic diagram of the positioning example of the luminous area and the open ring contour.
Specifically, the calculation formula of the roundness of the edge profile is as follows:
Wherein, Representing the roundness of the edge contour, R representing the average distance between all contour points and the circle center of the circumscribing circle, S representing the average deviation between the distance between each contour point and the circle center of the circumscribing circle and the average distance between all contour points and the circle center of the circumscribing circle, in particular,/>The closer to 1, the closer to the standard circle, so the position of the split ring can be located by a certain roundness threshold.
Specifically, the calculation formula of the average distance from all the contour points to the circle center of the circumscribing circle is as follows:
Wherein, Represents the/>The number of all contour points of the edge contour, P represents the/>J-th contour point of edge contour,/>Represents the/>The circle centers of the circumscribing circles of the edge profiles can be preset by the average coordinate values of the profile points.
Specifically, the calculation formula of the average deviation between the distance from each contour point to the center of the circumscribing circle and the average distance from all contour points to the center of the circumscribing circle is as follows:
Wherein, Represents the/>The number of all contour points of the edge contour, P represents the/>J-th contour point of edge contour,/>Represents the/>And R represents the average distance from all contour points to the circle center of the circumscribing circle.
(3) And constructing a first minimum circumscribed rectangle and a second minimum circumscribed rectangle based on the luminous area information and the open ring information of the grain image, and calculating the distance between the first minimum circumscribed rectangle and the second minimum circumscribed rectangle.
In the embodiment of the invention, a first minimum bounding rectangle and a second minimum bounding rectangle are constructed based on the luminous area information and the open ring information of the grain image, and the process of calculating the distance between the first minimum bounding rectangle and the second minimum bounding rectangle is as follows:
And (3.1) extracting the first minimum bounding rectangle based on the luminous area information of the grain image to obtain the coordinate information of the first minimum bounding rectangle.
And (3.2) constructing a minimum circumscribing circle of the split ring based on the split ring information of the grain image, and extracting a second minimum circumscribing rectangle based on the minimum circumscribing circle to obtain coordinate information of the second minimum circumscribing rectangle.
And (3.3) calculating the outer edge distance between the first minimum bounding rectangle and the second minimum bounding rectangle based on the coordinate information of the first minimum bounding rectangle and the coordinate information of the first minimum bounding rectangle.
(4) And judging the severity level of the defect based on the outer line distance between the first minimum circumscribed rectangle and the second minimum circumscribed rectangle so as to obtain a wafer cutting failure level judgment result.
In the embodiment of the invention, the process of judging the severity level of the defect based on the distance between the first minimum circumscribed rectangle and the second minimum circumscribed rectangle to obtain the judging result of the defective level of the wafer cutting is as follows:
And (4.1) carrying out positive and negative judgment and threshold judgment on the outer line distances of the first minimum circumscribed rectangle and the second minimum circumscribed rectangle to obtain a positive and negative judgment result and a threshold judgment result.
And (4.2) performing defect severity level judgment based on the positive and negative judgment results and the threshold judgment result to obtain a wafer cutting defect level judgment result.
In the embodiment of the present invention, referring to fig. 8, fig. 8 is a diagram showing an example of intersection judgment between a light emitting area and a split ring, and fig. 8 is a case where the split ring may be cut off during dicing, in order to accurately reflect the distance between a dicing line and the split ring, a minimum circumcircle is calculated for the split ring outline, then a minimum circummoment is extracted for the circumcircle, and at the same time, a minimum circummoment is also extracted for the light emitting area, and the distance between the outer edges of two rectangles can measure the severity of wafer dicing failure. The normal good product split ring is inside the luminous area, and the distance from the split ring to the edge of the luminous area is positive at this moment, if the split ring is cut inside, the outer edge of the split ring extends to the outside of the luminous area at this moment, and the distance from the split ring to the edge of the luminous area is negative, and according to the factory judging requirement, the crystal grain discarding is judged by setting the distance to be smaller than a certain threshold value. By the method, the severity of the defective cutting can be accurately evaluated, whether the crystal grain is scrapped or not can be judged, and the over-inspection rate of the classification model is greatly reduced.
In summary, the invention adopts a mode of combining deep learning and machine vision to detect defects, firstly detects and classifies the defects through a deep learning technology, then judges the severity level of the defects of poor wafer cutting through a machine vision technology, can measure the influence degree of the defects, and solves the problem that the existing defect detection technology is easy to overstock and miss.
In addition, in an embodiment, based on the same inventive concept as the foregoing embodiment, an embodiment of the present invention provides a system for detecting a defective wafer dicing defect, which corresponds to the method of embodiment 1 one by one, please refer to fig. 9, fig. 9 is a block diagram of a system for detecting a defective wafer dicing defect, the system includes:
the model classification detection unit is used for carrying out defect classification detection on the grain image based on the multi-classification model so as to obtain a defect classification detection result;
The image contour extraction unit is used for extracting the image contour of the grain image so as to obtain the luminous area information and the open ring information of the grain image;
the rectangular distance detection unit is used for constructing a first minimum circumscribed rectangle and a second minimum circumscribed rectangle based on the luminous area information and the open ring information of the grain image, and calculating the distance between the first minimum circumscribed rectangle and the second minimum circumscribed rectangle;
and the defect grade judging unit is used for judging the severity grade of the defect based on the distance between the first minimum circumscribed rectangle and the second minimum circumscribed rectangle so as to obtain a wafer cutting defect grade judging result.
It should be noted that, each unit in the wafer defect detection system in this embodiment corresponds to each step in the wafer defect detection method in the foregoing embodiment one by one, so the specific implementation manner and the achieved technical effect of this embodiment may refer to the implementation manner of the foregoing wafer defect detection method, and will not be described herein again.
Furthermore, in an embodiment, the present application also provides a computer device, which includes a processor, a memory, and a computer program stored in the memory, which when executed by the processor, implements the method in the foregoing embodiment.
Furthermore, in an embodiment, the present application also provides a computer storage medium, on which a computer program is stored, which computer program, when being executed by a processor, implements the method in the previous embodiment.
In some embodiments, the computer readable storage medium may be FRAM, ROM, PROM, EPROM, EEPROM, flash memory, magnetic surface memory, optical disk, or CD-ROM; but may be a variety of devices including one or any combination of the above memories. The computer may be a variety of computing devices including smart terminals and servers.
In some embodiments, the executable instructions may be in the form of programs, software modules, scripts, or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and they may be deployed in any form, including as stand-alone programs or as modules, components, subroutines, or other units suitable for use in a computing environment.
As an example, executable instructions may, but need not, correspond to files in a file system, may be stored as part of a file that holds other programs or data, such as in one or more scripts in a hypertext markup language (HTML, hyper Text Markup Language) document, in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files that store one or more modules, sub-programs, or portions of code).
As an example, executable instructions may be deployed to be executed on one computing device or on multiple computing devices located at one site or distributed across multiple sites and interconnected by a communication network.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or system. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or system that comprises the element.
The foregoing embodiment numbers of the present application are merely for the purpose of description, and do not represent the advantages or disadvantages of the embodiments.
From the above description of the embodiments, it will be clear to those skilled in the art that the above-described embodiment method may be implemented by means of software plus a necessary general hardware platform, but of course may also be implemented by means of hardware, but in many cases the former is a preferred embodiment. Based on such understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art in the form of a software product stored in a storage medium (e.g. read-only memory/random-access memory, magnetic disk, optical disk), comprising instructions for causing a multimedia terminal device (which may be a mobile phone, a computer, a television receiver, or a network device, etc.) to perform the method according to the embodiments of the present application.
The foregoing description is only of the preferred embodiments of the present application, and is not intended to limit the scope of the application, but rather is intended to cover any equivalents of the structures or equivalent processes disclosed herein or in the alternative, which may be employed directly or indirectly in other related arts.

Claims (13)

1. The wafer defective cutting defect detection method is characterized by comprising the following steps of:
Performing defect classification detection on the grain image based on the multi-classification model to obtain a defect classification detection result;
if the defect classification detection result is that the wafer is poorly cut, extracting the image contour of the grain image to obtain the luminous area information and the open ring information of the grain image;
Constructing a first minimum circumscribed rectangle and a second minimum circumscribed rectangle based on the luminous area information and the open ring information of the grain image, and calculating the distance between the first minimum circumscribed rectangle and the second minimum circumscribed rectangle;
And judging the severity level of the defect based on the distance between the first minimum circumscribed rectangle and the second minimum circumscribed rectangle so as to obtain a judgment result of the defective level of the wafer cutting.
2. The method for detecting defective wafer dicing according to claim 1, wherein before performing defect classification detection on a die image based on a multi-classification model, model training is required, and the flow of the model training is as follows:
acquiring a wafer image, and performing image binarization and image segmentation on the wafer image to obtain grain images of different defect types;
performing defect classification and feature labeling on the grain images with different defect types to construct training sample sets with different defect types;
model training is carried out on the deep learning model based on training sample sets of different defect types so as to obtain a multi-classification model.
3. The method for detecting defective dicing defects according to claim 2, wherein the process of performing image binarization and image segmentation on the wafer image to obtain the die images of different defect types comprises:
performing image binarization on the wafer image to obtain a wafer binarization image;
and performing image positioning on the wafer binarized image to obtain grain position information, and performing image segmentation on the wafer image based on the grain position information to obtain grain images of different defect types.
4. The method for detecting defective wafer dicing according to claim 1, wherein the process of extracting the image profile of the die image to obtain the light emitting area information and the open ring information of the die image is as follows:
Extracting image contours of the grain images to be detected to obtain coordinate information of edge contours;
And selecting the relative position and roundness of the edge contour based on the coordinate information of the edge contour to obtain the luminous area information and the open ring information of the grain image.
5. The method for detecting defective wafer dicing according to claim 4, wherein the process of selecting the relative position and roundness of the edge profile based on the coordinate information of the edge profile to obtain the light emitting area information and the open ring information of the die image is as follows:
Selecting coordinate information corresponding to the edge contour of the outermost layer from the coordinate information of the edge contour as luminous area information;
Calculating the distance from each contour point of the edge contour to the circle center of the circumscribing circle and the average distance from all contour points to the circle center of the circumscribing circle based on the coordinate information of the edge contour;
And calculating the roundness of the edge contour based on the distance from each contour point to the circle center of the circumscribing circle and the average distance from all the contour points to the circle center of the circumscribing circle, and selecting the coordinate information corresponding to the edge contour with the maximum roundness as the open ring information.
6. The method for detecting defective cutting of wafer according to claim 5, wherein the roundness of the edge profile is calculated as follows:
wherein/> The roundness of the edge contour is represented, R represents the average distance from all contour points to the circle center of the circumscribing circle, and S represents the average deviation between the distance from each contour point to the circle center of the circumscribing circle and the average distance from all contour points to the circle center of the circumscribing circle.
7. The method for detecting defective cutting of wafer as set forth in claim 6, wherein the average distance from all contour points to the center of the circumscribing circle is calculated as follows:
wherein/> Represents the/>The number of all contour points of the edge contour, P represents the/>J-th contour point of edge contour,/>Represents the/>The circle centers of the circumscribing circles of the edge profiles.
8. The method for detecting defective cutting of wafer as set forth in claim 7, wherein the calculation formula of the average deviation of the distance from each contour point to the center of the circumscribing circle and the average distance from all contour points to the center of the circumscribing circle is as follows:
wherein/> Represents the/>The number of all contour points of the edge contour, P represents the/>J-th contour point of edge contour,/>Represents the/>And R represents the average distance from all contour points to the circle center of the circumscribing circle.
9. The method for detecting defective dicing of wafer according to claim 1, wherein the first minimum bounding rectangle and the second minimum bounding rectangle are constructed based on the light emitting region information and the split ring information of the die image, and the process of calculating the distance between the first minimum bounding rectangle and the second minimum bounding rectangle is as follows:
Extracting a first minimum circumscribed rectangle based on the luminous area information of the grain image to obtain coordinate information of the first minimum circumscribed rectangle;
constructing a minimum circumscribing circle of the split ring based on the split ring information of the grain image, and extracting a second minimum circumscribing rectangle based on the minimum circumscribing circle to obtain coordinate information of the second minimum circumscribing rectangle;
And calculating the outer line distance between the first minimum bounding rectangle and the second minimum bounding rectangle based on the coordinate information of the first minimum bounding rectangle and the coordinate information of the second minimum bounding rectangle.
10. The method for detecting defective wafer dicing according to claim 9, wherein the process of determining the severity level of the defect based on the distance between the first minimum bounding rectangle and the second minimum bounding rectangle to obtain the result of determining the defective wafer dicing is as follows:
Carrying out positive and negative judgment and threshold judgment on the outer line distances of the first minimum circumscribed rectangle and the second minimum circumscribed rectangle to obtain a positive and negative judgment result and a threshold judgment result;
and carrying out defect severity level judgment based on the positive and negative judgment results and the threshold judgment result to obtain a wafer cutting failure level judgment result.
11. A wafer dicing defect detection system, the system comprising:
the model classification detection unit is used for carrying out defect classification detection on the grain image based on the multi-classification model so as to obtain a defect classification detection result;
The image contour extraction unit is used for extracting the image contour of the grain image so as to obtain the luminous area information and the open ring information of the grain image;
the rectangular distance detection unit is used for constructing a first minimum circumscribed rectangle and a second minimum circumscribed rectangle based on the luminous area information and the open ring information of the grain image, and calculating the distance between the first minimum circumscribed rectangle and the second minimum circumscribed rectangle;
and the defect grade judging unit is used for judging the severity grade of the defect based on the distance between the first minimum circumscribed rectangle and the second minimum circumscribed rectangle so as to obtain a wafer cutting defect grade judging result.
12. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized by: the processor, when executing a computer program, implements a method for detecting wafer under-cut defects as claimed in any one of claims 1-10.
13. A computer readable storage medium, characterized in that the computer readable storage medium has stored thereon a computer program which, when executed by a processor, implements a wafer under-cut defect detection method according to any one of claims 1-10.
CN202410521657.6A 2024-04-28 2024-04-28 Wafer cutting defect detection method, system, equipment and storage medium Active CN118096767B (en)

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CN117670876A (en) * 2024-01-31 2024-03-08 成都数之联科技股份有限公司 Panel defect severity level judging method, system, equipment and storage medium

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CN101079387A (en) * 2003-09-15 2007-11-28 罗姆和哈斯电子材料有限责任公司 Device package and methods for the fabrication and testing thereof
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