CN118092929A - Register description file conversion method, device, computer equipment and storage medium - Google Patents
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Abstract
The application relates to a register description file conversion method, a device, a computer device and a storage medium. The method comprises the following steps: acquiring a first register description file to be converted and a second register description file with a dependency relationship with the first register description file; according to the analysis result of the first register description file, a first tree model corresponding to the first register description file and a second tree model corresponding to the second register description file are obtained; splicing the first tree model and the second tree model according to the description information of the second register description file to generate a target tree structure; and compiling the target tree structure to obtain the register description file after the conversion of the first register description file. The method can improve the generation efficiency of the tree structure, thereby improving the file conversion efficiency.
Description
Technical Field
The present application relates to the field of computer chip technology, and in particular, to a method, an apparatus, a computer device, a storage medium, and a computer program product for converting a register description file.
Background
With the development of computer chip technology, a file for describing register information in the entire chip, i.e., rdl file, has emerged, which can be used to authenticate the individual chip subsystems. And the rdl files for describing the register information generally need to be converted, for example, the files need to be converted into files conforming to the grammar of the c language, so that a developer can write and verify test cases conveniently.
At present, the conversion of the register description file can be generally realized through an parsing library, and when a certain rdl file is parsed, another rdl file on which the rdl file depends is queried, and then a corresponding complete tree structure can be generated according to the description of the rdl file, so that the converted file is generated by utilizing the tree structure.
However, in the current register description file conversion process, when a complete tree structure is generated, node replication is generally required, and a large number of repeated nodes are generated in the process, and the process of generating the tree structure is very slow due to the generation of the repeated nodes, so that in the current register description file conversion method, the file conversion efficiency is low.
Disclosure of Invention
In view of the foregoing, it is desirable to provide a register description file conversion method, apparatus, computer device, computer readable storage medium, and computer program product that can improve file conversion efficiency.
In a first aspect, the present application provides a method for converting a register description file, including:
acquiring a first register description file to be converted and a second register description file with a dependency relationship with the first register description file;
acquiring a first tree model corresponding to the first register description file according to the analysis result of the first register description file, and acquiring a second tree model corresponding to the second register description file according to the analysis result of the second register description file;
Splicing the first tree model and the second tree model according to the description information of the second register description file to generate a target tree structure;
and compiling the target tree structure to obtain the register description file after the first register description file is converted.
In one embodiment, the first tree model and the second tree model each comprise a plurality of nodes; the splicing the first tree model and the second tree model according to the description information of the second register description file to generate a target tree structure, including: acquiring nodes to be spliced from a plurality of nodes contained in the second tree model according to the description information of the second register description file; and splicing each node contained in the first tree model with the node to be spliced to generate the target tree structure.
In one embodiment, the obtaining, according to the description information of the second register description file, the node to be spliced from the plurality of nodes included in the second tree model includes: acquiring target description information for describing a register address from the description information of the second register description file; and taking the node matched with the target description information from the plurality of nodes contained in the second tree model as the node to be spliced.
In one embodiment, the obtaining, according to the analysis result of the first register description file, a first tree model corresponding to the first register description file, and obtaining, according to the analysis result of the second register description file, a second tree model corresponding to the second register description file includes: according to the analysis result of the first register description file, acquiring each piece of physical address information contained in the first register description file and the field width corresponding to each piece of physical address information; constructing nodes matched with the physical address information according to the physical address information and the field widths corresponding to the physical address information respectively, and generating the first tree model by using the nodes matched with the physical address information; acquiring an initial register address contained in the second register description file and a register word field range contained in the second register description file according to an analysis result of the second register description file; constructing a node matched with the initial register address, and a node matched with the register word field range, and generating the second tree model by using the node matched with the initial register address and the node matched with the register word field range.
In one embodiment, the compiling the target tree structure to obtain the converted register description file of the first register description file includes: inputting the target tree structure into a compiling module, and compiling the target tree structure through the compiling module to obtain a plurality of target registers of description information to be generated contained in the target tree structure; acquiring exclusive register information corresponding to each target register in the target tree structure through a father pointer arranged in the compiling module; and acquiring general register information of the plurality of target registers from the target tree structure, and constructing the converted register description file by utilizing the exclusive register information and the general register information.
In one embodiment, the dedicated register information includes: physical address information corresponding to each target register and field width information corresponding to each target register respectively; the general register information comprises register word domain range information of the plurality of target registers; the constructing the converted register description file by using the dedicated register information and the general register information includes: acquiring physical address information corresponding to a current target register and field width information corresponding to the current target register respectively; the current target register is any one of the target registers; taking the physical address information corresponding to the current target register as register address information corresponding to the current target register, and obtaining a word domain range corresponding to the current target register by utilizing field width information respectively corresponding to the current target register and the register word domain range information; and constructing register description information corresponding to the current target register according to the register address information corresponding to the current target register and the word field range corresponding to the current target register, and constructing the converted register description file by utilizing the register description information corresponding to each current target register.
In one embodiment, the obtaining a first register description file to be converted and a second register description file having a dependency relationship with the first register description file includes: acquiring a plurality of candidate register description files; obtaining candidate register description files which are not depended from the candidate register description files as the first register description file; and acquiring keywords representing the dependency relationship from the first register description file, and taking candidate register description files associated with the keywords as the second register description file.
In a second aspect, the present application further provides a register description file conversion apparatus, including:
The device comprises a to-be-converted file acquisition module, a first register description file generation module and a second register description file generation module, wherein the to-be-converted file acquisition module is used for acquiring a to-be-converted first register description file and a second register description file which has a dependency relationship with the first register description file;
the tree model acquisition module is used for acquiring a first tree model corresponding to the first register description file according to the analysis result of the first register description file and acquiring a second tree model corresponding to the second register description file according to the analysis result of the second register description file;
the tree model splicing module is used for splicing the first tree model and the second tree model according to the description information of the second register description file to generate a target tree structure;
and the post-conversion file acquisition module is used for compiling the target tree structure to obtain the post-conversion register description file of the first register description file.
In a third aspect, the present application also provides a computer device comprising a memory and a processor, the memory storing a computer program, the processor implementing the following steps when executing the computer program:
acquiring a first register description file to be converted and a second register description file with a dependency relationship with the first register description file;
According to the analysis result of the first register description file, a first tree model corresponding to the first register description file and a second tree model corresponding to the second register description file are obtained;
Splicing the first tree model and the second tree model according to the description information of the second register description file to generate a target tree structure;
and compiling the target tree structure to obtain the register description file after the first register description file is converted.
In a fourth aspect, the present application also provides a computer readable storage medium having stored thereon a computer program which when executed by a processor performs the steps of:
acquiring a first register description file to be converted and a second register description file with a dependency relationship with the first register description file;
According to the analysis result of the first register description file, a first tree model corresponding to the first register description file and a second tree model corresponding to the second register description file are obtained;
Splicing the first tree model and the second tree model according to the description information of the second register description file to generate a target tree structure;
and compiling the target tree structure to obtain the register description file after the first register description file is converted.
In a fifth aspect, the application also provides a computer program product comprising a computer program which, when executed by a processor, performs the steps of:
acquiring a first register description file to be converted and a second register description file with a dependency relationship with the first register description file;
According to the analysis result of the first register description file, a first tree model corresponding to the first register description file and a second tree model corresponding to the second register description file are obtained;
Splicing the first tree model and the second tree model according to the description information of the second register description file to generate a target tree structure;
and compiling the target tree structure to obtain the register description file after the first register description file is converted.
The register description file conversion method, the device, the computer equipment, the storage medium and the computer program product are used for obtaining a first register description file to be converted and a second register description file with a dependency relationship with the first register description file; according to the analysis result of the first register description file, a first tree model corresponding to the first register description file and a second tree model corresponding to the second register description file are obtained; splicing the first tree model and the second tree model according to the description information of the second register description file to generate a target tree structure; and compiling the target tree structure to obtain the register description file after the conversion of the first register description file. According to the method, the first register description file to be converted and the second register description file which depends on the first register description file are obtained, the first tree model and the second tree model which are obtained after the first register description file and the second register description file are analyzed are spliced to generate the target tree structure, and then the target tree structure is compiled to obtain the converted register description file.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the related art, the drawings that are required to be used in the embodiments or the related technical descriptions will be briefly described, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to the drawings without inventive effort for those skilled in the art.
FIG. 1 is a flow chart of a method for converting a register description file in one embodiment;
FIG. 2 is a flow diagram of generating a target tree structure in one embodiment;
FIG. 3 is a flow diagram of generating a first tree model and a second tree model in one embodiment;
FIG. 4 is a schematic diagram of a first tree model in one embodiment;
FIG. 5 is a schematic diagram of a structure of a second tree model in one embodiment;
FIG. 6 is a schematic diagram of a structure of a target tree structure in one embodiment;
FIG. 7 is a flow diagram of constructing a converted register description file in one embodiment;
FIG. 8 is a flow diagram of a method for converting rdl files into register descriptions in one embodiment;
FIG. 9 is a schematic diagram of a tree structure of register descriptions generated in one embodiment;
FIG. 10 is a flowchart of a method for converting rdl files into register descriptions in another embodiment;
FIG. 11 is a schematic diagram of a tree structure of register descriptions generated in another embodiment;
FIG. 12 is a block diagram of a register file conversion device in one embodiment;
Fig. 13 is an internal structural view of a computer device in one embodiment.
Detailed Description
The present application will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present application more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.
In one embodiment, as shown in fig. 1, a method for converting a register description file is provided, and this embodiment is applied to a terminal for illustration by using the method, it is understood that the method may also be applied to a server, and may also be applied to a system including the terminal and the server, and implemented through interaction between the terminal and the server. In this embodiment, the method includes the steps of:
step S101, a first register description file to be converted and a second register description file having a dependency relationship with the first register description file are obtained.
The first register description file to be converted refers to a register description file to be converted, for example, rdl files to be converted, and the second register description file has a dependency relationship with the first register description file, for example, may be a register file to be called or referenced in the first register file. Specifically, when the register description file is converted, the rdl file that needs to be converted can be determined as the first register description file, and then another rdl file on which the rdl file depends can be determined as the second register description file.
Step S102, according to the analysis result of the first register description file, a first tree model corresponding to the first register description file is obtained, and according to the analysis result of the second register description file, a second tree model corresponding to the second register description file is obtained.
The first tree model refers to a model corresponding to the first register description file, the model can be realized through a model rule, the analysis result is an analysis result of the first register description file, the result can be obtained through a parser, and similarly, the second tree model is a model corresponding to the second register description file, and the model is similar to the first tree model and can also be realized through the model rule. Specifically, the terminal may input the acquired first register file and second register file into the parser, where the parser obtains the parsing result of the first register description file and the parsing result of the second register description file respectively. And then, the terminal can also input the analysis results into the model combi, and the model combi can obtain a first tree model according to the analysis results of the first register description file and obtain a second tree model according to the analysis results of the second register description file.
And step S103, splicing the first tree model and the second tree model according to the description information of the second register description file to generate a target tree structure.
The target tree structure is a tree structure for finally generating the converted register description file, in this embodiment, the generation of the target tree structure is directly obtained by splicing the first tree model and the second tree model, and the independent nodes are not required to be generated according to the tree model for splicing, so that the process and the generation of the target tree structure do not contain a large number of repeated nodes, and the efficiency of generating the target tree structure can be improved.
Specifically, after the terminal obtains the first tree-shaped model and the second tree-shaped model, the terminal can directly splice the first tree-shaped model and the second tree-shaped model according to the description information of the parsed second register description file to obtain the target tree-shaped structure.
Step S104, compiling the target tree structure to obtain a register description file after the conversion of the first register description file.
After the target tree structure is obtained, a compiling module, for example Dynamic Compile module, may be used to implement compiling processing on the target tree structure, so as to obtain a register description file after the first register description file is converted.
In the above method for converting a register description file, a first register description file to be converted and a second register description file having a dependency relationship with the first register description file are obtained; according to the analysis result of the first register description file, a first tree model corresponding to the first register description file and a second tree model corresponding to the second register description file are obtained; splicing the first tree model and the second tree model according to the description information of the second register description file to generate a target tree structure; and compiling the target tree structure to obtain the register description file after the conversion of the first register description file. According to the method, the first register description file to be converted and the second register description file which depends on the first register description file are obtained, the first tree model and the second tree model which are obtained after the first register description file and the second register description file are analyzed are spliced to generate the target tree structure, and then the target tree structure is compiled to obtain the converted register description file.
In one embodiment, the first tree model and the second tree model each comprise a plurality of nodes; as shown in fig. 2, step S103 may further include:
Step S201, according to the description information of the second register description file, the node to be spliced is obtained from a plurality of nodes contained in the second tree model.
In this embodiment, the first tree model and the second tree model may both include a plurality of nodes, and since the second register description file is a file that is relied on by the first register description file, each node in the second tree model and each node in the first tree model need to be spliced to ensure accuracy of a target tree structure after being spliced, and the node to be spliced is a node in the second tree model and each node in the first tree model, and the terminal may determine the node to be spliced from the plurality of nodes included in the second tree model according to description information of the second register description file.
Step S202, each node contained in the first tree model is spliced with the node to be spliced, and a target tree structure is generated.
After determining the node to be spliced, the terminal may splice each node included in the first tree model with the node to be spliced to generate a final target tree structure, for example, the first tree model includes nodes A1 and B1, the second tree model includes nodes A2, B2 and C2, and if the node to be spliced is node B2, the terminal may splice nodes A1 and B2, and nodes B1 and B2 to generate the target tree structure.
In this embodiment, the terminal may determine, from the second tree model including nodes, the node to be spliced according to the description information of the second register description file, and then splice the node to be spliced with each node included in the first tree model, so as to implement generation of the target tree structure.
Further, step S201 may further include: acquiring target description information for describing the register address from the description information of the second register description file; and taking the node matched with the target description information from the plurality of nodes contained in the second tree model as the node to be spliced.
In this embodiment, the first register description file may be a file for describing physical addresses of registers, for example, hostview _64b.rdl file, so that it includes at least one physical address information for recording IP inside a chip, and the plurality of nodes for generating the first tree model may also respectively correspond to different physical address information of registers. For example, the first register description file may record that the register address information of a0 is 0x0, and the address of the register in a1 is 0x1000, and then the first tree model may include two nodes corresponding to the register address information of a 0x0 and the address of the register of a 1x 1000.
And then the terminal can find the target description information for describing the register address from the description information of the second register description file, so that the node matched with the target description information in the plurality of nodes contained in the second tree model is used as the node to be spliced.
In this embodiment, the first register description file includes at least one physical address information for recording IP inside the chip, and the plurality of nodes of the first tree model respectively correspond to different physical address information, and the terminal may determine, from the description information of the second register description file, target description information for describing the register address, and use a node matched with the information as a node to be spliced.
In addition, as shown in fig. 3, step S102 may further include:
Step S301, according to the analysis result of the first register description file, each piece of physical address information included in the first register description file and the field width corresponding to each piece of physical address information are obtained.
In this embodiment, in addition to the physical address information of each register being recorded in the first register description file, the width of the field corresponding to each physical address information, that is, the width of the field may be recorded, for example, the first register description file may be recorded with A a0 (width=4) @ 0x0, that is, the physical address information of the register indicating a0 is 0x0, and the corresponding width of the field is width=4.
Specifically, when the terminal obtains the analysis result of the first register description file, each piece of physical address information contained in the first register description file and the field width corresponding to each piece of physical address information can be obtained according to the analysis result.
Step S302, constructing nodes matched with the physical address information according to the physical address information and the field widths corresponding to the physical address information, and generating a first tree model by using the nodes matched with the physical address information.
The terminal may then construct a matched node using each physical address information and a field width corresponding to each physical address information, thereby generating a first tree model based on the matched node.
For example, the first register description file may be the following:
addrmap hostview_64b {
`include` “A.rdl”
A a0 (width=4) @ 0x0;
A a1 @ 0x1000;
};
The register physical address information containing a0 is 0x0, the corresponding field width is width=4, and the register physical address information containing a1 is 0x1000, the field width is not set, so the first tree model can be generated as shown in fig. 4.
Step S303, according to the analysis result of the second register description file, obtaining the initial register address contained in the second register description file and the register word field range contained in the second register description file;
Step S304, constructing a node matched with the initial register address and a node matched with the register word field range, and generating a second tree model by using the node matched with the initial register address and the node matched with the register word field range.
The initial register address refers to a default register address recorded in the second register description file, and the register word field range refers to a bit range recorded in the second register description file, and in this embodiment, the second tree model may be generated by constructing a node matching the initial register address and constructing a node matching the register word field range, so that the second tree model is formed by using the two nodes.
For example, the second register description file relied upon by the first register description file may be a.rdl, which file may contain the following:
addrmap A (width=1) {
reg {
field {
desc = “f1”;
} f1[width-1:0];
} CFG @ 0x0;
};
It contains an initial register address, i.e., CFG register address of 0x0, and register field range is f1 [ width-1:0], so the second tree model is generated as shown in FIG. 5.
Then, the first tree model shown in fig. 4 and the second tree model shown in fig. 5 may be spliced, for example, the node associated with the target description information describing the register address, that is, the initial register address information, that is, CFG 0x0 in fig. 5, is taken as the node to be spliced, and is spliced with each node included in the first tree model, so that the formed target tree structure may be as shown in fig. 6.
In this embodiment, each physical address information included in the first register description file and a field width corresponding to each physical address information construct a node with which the physical address information is matched to generate a first tree model, and meanwhile, a corresponding matching node may also be constructed according to an initial register address and a register word field range included in the second register description file to generate a second tree model.
In one embodiment, as shown in fig. 7, step S104 may further include:
Step S701, inputting the target tree structure into a compiling module, and compiling the target tree structure by the compiling module to obtain a plurality of target registers of description information to be generated contained in the target tree structure.
The target register refers to a register needed to generate the description information, and the confirmation of the target register can be determined by the compiling module according to the target tree structure, for example, for the target tree structure shown in fig. 6, the target register included in the target tree structure can include a0 register and a1 register.
Step S702, obtaining the exclusive register information corresponding to each target register in the target tree structure through the father pointer set in the compiling module.
The exclusive register information refers to the exclusive register information used by different target registers, that is, the exclusive register information of different target registers is also different, and the exclusive register information can be obtained by reading from the target tree structure through a father pointer set in the compiling module. For example, for the target tree structure shown in fig. 6, the dedicated register information of the register corresponding to a0 may be that the physical address information thereof is 0x0, the field width is width=4, and the dedicated register information corresponding to a1 may be that the physical address information of the register is 0x1000, which may be obtained by compiling the parent pointer in the module. For example, when the exclusive register information of the register a0 needs to be obtained, the parent pointer may be pointed to a0 to obtain a value of width of 4, and the address of a0 is 0x0, and similarly when the exclusive register information of the register a1 needs to be obtained, the parent pointer may be pointed to a1 to obtain an address of a1 is 0x1000.
In step S703, general register information of a plurality of target registers is obtained from the target tree structure, and a converted register description file is constructed using each dedicated register information and the general register information.
The general register information is common register information of a plurality of target registers, for example, for the target tree structure shown in fig. 6, the general register information may be a register field range, that is, f1 [ width-1:0], and when the terminal obtains the dedicated register information and the general register information of the plurality of target registers, the terminal may use each dedicated register information and the general register information to construct a converted register description file.
In this embodiment, when compiling the target tree structure, dedicated register information corresponding to each target register may be obtained by using the parent pointer, so as to implement dynamic compiling.
In one embodiment, the proprietary register information includes: physical address information corresponding to each target register and field width information corresponding to each target register; general register information including register word field range information of a plurality of target registers; step S703 may further include: acquiring physical address information corresponding to a current target register and field width information corresponding to the current target register respectively; the current target register is any one of the target registers; taking physical address information corresponding to a current target register as register address information corresponding to the current target register, and obtaining a word domain range corresponding to the current target register by utilizing field width information and register word domain range information respectively corresponding to the current target register; according to the register address information corresponding to the current target register and the word domain range corresponding to the current target register, constructing the register description information corresponding to the current target register, and constructing a converted register description file by utilizing the register description information corresponding to each current target register.
In this embodiment, the dedicated register information may be physical address information and field width information corresponding to each target register, for example, a0 address shown in fig. 6 is 0x0, a width value is 4, the general register information may be register field range information of a plurality of target registers, for example, f1[ width-1:0] shown in fig. 6, and the current target register may be any one of the target registers.
Specifically, the terminal may use any one of the target registers as the current target register, so as to obtain physical address information and field width information corresponding to the current target register. And then, the physical address information corresponding to the current target register can be used as register address information corresponding to the current target register, and the field width information and the register word domain range information respectively corresponding to the current target register are utilized to obtain the word domain range corresponding to the current target register. Taking the register of a0 in the target tree structure shown in fig. 6 as an example, if the register of a0 is the current target register, the corresponding physical address information of the register is 0x0, then the corresponding register address information of the current target register is 0x0, meanwhile the corresponding field width information of the register is width=4, and the register word field range information is f1 [ width-1:0], so that the obtained word field range corresponding to the current target register, namely, the bit range of f1 is 0 to 3.
After obtaining the register address information and the word field range corresponding to each current target register, the register description information corresponding to each current target register can be obtained according to the register address information and the word field range, so that the converted register description file is further constructed by using the register description information corresponding to each current target register.
In this embodiment, the terminal may obtain the register description information corresponding to each target register by using the physical address information, the field width information and the general register word field range information corresponding to each target register, so as to construct a register description file, and by this way, the efficiency of constructing the register description file may be improved.
In one embodiment, step S101 may further include: acquiring a plurality of candidate register description files; obtaining a candidate register description file which is not depended from a plurality of candidate register description files as a first register description file; and acquiring keywords representing the dependency relationship from the first register description file, and taking candidate register description files associated with the keywords as second register description files.
The candidate register description file refers to a register file that may be selected as the first register description file or the second register description file, and in this embodiment, when the terminal obtains the first register description file and the second register description file, the terminal needs to first screen out the suitable first register description file and second register description file from the candidate register description files. The first register description file may be a candidate register description file that is not to be relied upon as the first register description file. For example hostview _64b.rdl, is not referenced by other files, i.e. the file is not relied upon by other register description files, and thus the register description file may then be used as the first register description file.
After determining the first register description file, determining a second register description file on which the first register description file depends from the candidate register description files, wherein the process may be to determine a keyword representing the dependency relationship, so that the candidate register description file associated with the keyword is used as the second register description file. For example, the register description file hostview _64b.rdl includes "include" a.rdl ", where include is a key for characterizing a dependency, and then the associated candidate register description file, i.e., a.rdl, may be used as the second register description file.
In this embodiment, the terminal may screen out the first register description file that is not depended from the plurality of candidate register description files, and determine the second register description file that is depended from the key words that characterize the dependency relationship, so that the screening efficiency of the first register description file and the second register description file may be improved.
In one embodiment, there is also provided a method for quickly converting rdl files into register descriptions, by which speed increases are evident when there are a large number of repeated and complex node descriptions in rdl, where the existing method for converting rdl files into register descriptions may include the following steps as shown in fig. 8:
The hostview _64b.rdl file is used as a first register description file to be input, and another rdl file which is dependent is found according to an include key in the file, namely a second register description file A.rdl, wherein the content of the hostview _64b.rdl file is as follows:
addrmap hostview_64b {
`include` “A.rdl”
A a0 (width=4) @ 0x0;
A a1 @ 0x1000;
};
The contents of the rdl file are:
addrmap A (width=1) {
reg {
field {
desc = “f1”;
} f1[width-1:0];
} CFG @ 0x0;
};
Then, hostview _64b.rdl and A.rdl are respectively parsed, then a corresponding model is generated, a tree structure is generated in the memory according to the description of addrmap in elaborate stage, each node on the tree is an independent object, and finally validity check is performed on the content of the generated tree structure, for example, the value of stride of an array register must be equal to the width of the register, and the like. The user generates a final register description file from this complete tree structure. Wherein the process of generating a tree structure is the most time-consuming stage in the overall flow. Fig. 9 shows the tree structure of the generated in-memory register descriptions, the CFG register address in a0 is 0x0, the bit range of f1 is 0 to 3, the CFG register address in a1 is 0x1000, and the bit range of f1 is 0 to 0.
The original method generates a complete tree structure of register descriptions with many repeated nodes, such as addrmap A in addrmap hostview _64b, but the required parameters with are different, and when the repeated nodes are many, the tree structure is generated very slowly.
The method provided by this embodiment does not create corresponding nodes on the register description tree for these duplicate portions. Thereby shortening the generation time of the register description tree. While for the differences of a0 and a1 dynamic processing is performed at the time of generating the final register description file.
FIG. 10 shows the workflow of the method provided by this embodiment, which also takes the hostview _64b.rdl file as input, parses hostview _64b.rdl and A.rdl, respectively, based on the include key in the file, then generates the corresponding model, and then generates a tree structure in memory based on the addrmap description, which does not generate independent nodes for the model from the same rdl file. Thereby shortening the time for generating the tree structure. And finally generating a final register description file by means of a dynamic compiling module. FIG. 11 shows a tree structure of the register description of the present method, when it is required to generate the CFG register description of a0, the Dynamic Compile module points the parent pointer (dotted line) to a0, then obtains the value of width, and the address of a0, and finally obtains that the address of the register CFG under a0 is 0x0, and the bit range of f1 is 0 to 3.
Therefore, by the method provided by the embodiment, repeated and complex node description can be reduced, so that the generation time of the register description tree is shortened, and the conversion efficiency of the register description file is improved.
It should be understood that, although the steps in the flowcharts related to the embodiments described above are sequentially shown as indicated by arrows, these steps are not necessarily sequentially performed in the order indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least some of the steps in the flowcharts described in the above embodiments may include a plurality of steps or a plurality of stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of the steps or stages is not necessarily performed sequentially, but may be performed alternately or alternately with at least some of the other steps or stages.
Based on the same inventive concept, the embodiment of the application also provides a register description file conversion device for realizing the above mentioned register description file conversion method. The implementation of the solution provided by the device is similar to the implementation described in the above method, so the specific limitation in the embodiments of the register description file conversion device provided below may refer to the limitation of the register description file conversion method hereinabove, and will not be repeated herein.
In one embodiment, as shown in fig. 12, there is provided a register description file conversion apparatus including: a file to be converted acquiring module 1201, a tree model acquiring module 1202, a tree model splicing module 1203 and a file after conversion acquiring module 1204, wherein:
The to-be-converted file obtaining module 1201 is configured to obtain a first register description file to be converted and a second register description file having a dependency relationship with the first register description file;
The tree model obtaining module 1202 is configured to obtain a first tree model corresponding to the first register description file according to an analysis result of the first register description file, and obtain a second tree model corresponding to the second register description file according to an analysis result of the second register description file;
The tree model splicing module 1203 is configured to splice the first tree model and the second tree model according to the description information of the second register description file, so as to generate a target tree structure;
the post-conversion file obtaining module 1204 is configured to compile the target tree structure to obtain a post-conversion register description file of the first register description file.
In one embodiment, the first tree model and the second tree model each comprise a plurality of nodes; the tree model splicing module 1203 is further configured to obtain, according to the description information of the second register description file, a node to be spliced from a plurality of nodes included in the second tree model; and splicing each node contained in the first tree model with the node to be spliced to generate a target tree structure.
In one embodiment, the tree model stitching module 1203 is further configured to obtain, from the description information of the second register description file, target description information for describing the register address; and taking the node matched with the target description information from the plurality of nodes contained in the second tree model as the node to be spliced.
In one embodiment, the tree model obtaining module 1202 is further configured to obtain, according to an analysis result of the first register description file, each piece of physical address information included in the first register description file, and a field width corresponding to each piece of physical address information respectively; constructing nodes matched with the physical address information according to the physical address information and the field widths corresponding to the physical address information respectively, and generating a first tree model by using the nodes matched with the physical address information; according to the analysis result of the second register description file, acquiring an initial register address contained in the second register description file and a register word field range contained in the second register description file; constructing a node matching the initial register address and a node matching the register word field range, and generating a second tree model by using the node matching the initial register address and the node matching the register word field range.
In one embodiment, the post-conversion file obtaining module 1204 is further configured to input the target tree structure into a compiling module, and compile the target tree structure through the compiling module to obtain a plurality of target registers of description information to be generated included in the target tree structure; acquiring exclusive register information corresponding to each target register in the target tree structure through a father pointer arranged in the compiling module; and acquiring general register information of a plurality of target registers from the target tree structure, and constructing a converted register description file by utilizing the special register information and the general register information.
In one embodiment, the proprietary register information includes: physical address information corresponding to each target register and field width information corresponding to each target register; general register information including register word field range information of a plurality of target registers; the post-conversion file obtaining module 1204 is further configured to obtain physical address information corresponding to the current target register and field width information corresponding to the current target register respectively; the current target register is any one of the target registers; taking physical address information corresponding to a current target register as register address information corresponding to the current target register, and obtaining a word domain range corresponding to the current target register by utilizing field width information and register word domain range information respectively corresponding to the current target register; according to the register address information corresponding to the current target register and the word domain range corresponding to the current target register, constructing the register description information corresponding to the current target register, and constructing a converted register description file by utilizing the register description information corresponding to each current target register.
In one embodiment, the file to be converted obtaining module 1201 is further configured to obtain a plurality of candidate register description files; obtaining a candidate register description file which is not depended from a plurality of candidate register description files as a first register description file; and acquiring keywords representing the dependency relationship from the first register description file, and taking candidate register description files associated with the keywords as second register description files.
The respective modules in the above-described register description file conversion apparatus may be implemented in whole or in part by software, hardware, and combinations thereof. The above modules may be embedded in hardware or may be independent of a processor in the computer device, or may be stored in software in a memory in the computer device, so that the processor may call and execute operations corresponding to the above modules.
In one embodiment, a computer device is provided, which may be a terminal, and the internal structure thereof may be as shown in fig. 13. The computer device includes a processor, a memory, an input/output interface, a communication interface, a display unit, and an input means. The processor, the memory and the input/output interface are connected through a system bus, and the communication interface, the display unit and the input device are connected to the system bus through the input/output interface. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The input/output interface of the computer device is used to exchange information between the processor and the external device. The communication interface of the computer device is used for carrying out wired or wireless communication with an external terminal, and the wireless mode can be realized through WIFI, a mobile cellular network, NFC (near field communication) or other technologies. The computer program, when executed by a processor, implements a register description file conversion method. The display unit of the computer device is used for forming a visual picture, and can be a display screen, a projection device or a virtual reality imaging device. The display screen can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer equipment can be a touch layer covered on the display screen, can also be a key, a track ball or a touch pad arranged on the shell of the computer equipment, and can also be an external keyboard, a touch pad or a mouse and the like.
It will be appreciated by those skilled in the art that the structure shown in FIG. 13 is merely a block diagram of some of the structures associated with the present inventive arrangements and is not limiting of the computer device to which the present inventive arrangements may be applied, and that a particular computer device may include more or fewer components than shown, or may combine some of the components, or have a different arrangement of components.
In an embodiment, there is also provided a computer device comprising a memory and a processor, the memory having stored therein a computer program, the processor implementing the steps of the method embodiments described above when the computer program is executed.
In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored which, when executed by a processor, carries out the steps of the method embodiments described above.
In an embodiment, a computer program product is provided, comprising a computer program which, when executed by a processor, implements the steps of the method embodiments described above.
It should be noted that, the user information (including but not limited to user equipment information, user personal information, etc.) and the data (including but not limited to data for analysis, stored data, presented data, etc.) related to the present application are both information and data authorized by the user or sufficiently authorized by each party, and the collection, use and processing of the related data are required to meet the related regulations.
Those skilled in the art will appreciate that implementing all or part of the above described methods may be accomplished by way of a computer program stored on a non-transitory computer readable storage medium, which when executed, may comprise the steps of the embodiments of the methods described above. Any reference to memory, database, or other medium used in embodiments provided herein may include at least one of non-volatile and volatile memory. The nonvolatile Memory may include Read-Only Memory (ROM), magnetic tape, floppy disk, flash Memory, optical Memory, high density embedded nonvolatile Memory, resistive random access Memory (ReRAM), magneto-resistive random access Memory (Magnetoresistive Random Access Memory, MRAM), ferroelectric Memory (Ferroelectric Random Access Memory, FRAM), phase change Memory (PHASE CHANGE Memory, PCM), graphene Memory, and the like. Volatile memory can include random access memory (Random Access Memory, RAM) or external cache memory, and the like. By way of illustration, and not limitation, RAM can be in various forms such as static random access memory (Static Random Access Memory, SRAM) or dynamic random access memory (Dynamic Random Access Memory, DRAM), etc. The databases referred to in the embodiments provided herein may include at least one of a relational database and a non-relational database. The non-relational database may include, but is not limited to, a blockchain-based distributed database, and the like. The processor referred to in the embodiments provided in the present application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic unit, a data processing logic unit based on quantum computing, or the like, but is not limited thereto.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The foregoing examples illustrate only a few embodiments of the application and are described in detail herein without thereby limiting the scope of the application. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of the application should be assessed as that of the appended claims.
Claims (11)
1. A method of converting a register description file, the method comprising:
acquiring a first register description file to be converted and a second register description file with a dependency relationship with the first register description file;
acquiring a first tree model corresponding to the first register description file according to the analysis result of the first register description file, and acquiring a second tree model corresponding to the second register description file according to the analysis result of the second register description file;
Splicing the first tree model and the second tree model according to the description information of the second register description file to generate a target tree structure;
and compiling the target tree structure to obtain the register description file after the first register description file is converted.
2. The method of claim 1, wherein the first tree model and the second tree model each comprise a plurality of nodes;
The splicing the first tree model and the second tree model according to the description information of the second register description file to generate a target tree structure, including:
Acquiring nodes to be spliced from a plurality of nodes contained in the second tree model according to the description information of the second register description file;
And splicing each node contained in the first tree model with the node to be spliced to generate the target tree structure.
3. The method according to claim 2, wherein the obtaining the node to be spliced from the plurality of nodes included in the second tree model according to the description information of the second register description file includes:
acquiring target description information for describing a register address from the description information of the second register description file;
and taking the node matched with the target description information from the plurality of nodes contained in the second tree model as the node to be spliced.
4. The method of claim 3, wherein the obtaining a first tree model corresponding to the first register description file according to the parsing result of the first register description file, and obtaining a second tree model corresponding to the second register description file according to the parsing result of the second register description file, comprises:
According to the analysis result of the first register description file, acquiring each piece of physical address information contained in the first register description file and the field width corresponding to each piece of physical address information;
Constructing nodes matched with the physical address information according to the physical address information and the field widths corresponding to the physical address information respectively, and generating the first tree model by using the nodes matched with the physical address information;
Acquiring an initial register address contained in the second register description file and a register word field range contained in the second register description file according to an analysis result of the second register description file;
Constructing a node matched with the initial register address, and a node matched with the register word field range, and generating the second tree model by using the node matched with the initial register address and the node matched with the register word field range.
5. The method according to claim 1, wherein compiling the target tree structure to obtain the converted register description file of the first register description file includes:
Inputting the target tree structure into a compiling module, and compiling the target tree structure through the compiling module to obtain a plurality of target registers of description information to be generated contained in the target tree structure;
Acquiring exclusive register information corresponding to each target register in the target tree structure through a father pointer arranged in the compiling module;
And acquiring general register information of the plurality of target registers from the target tree structure, and constructing the converted register description file by utilizing the exclusive register information and the general register information.
6. The method of claim 5, wherein the dedicated register information comprises: physical address information corresponding to each target register and field width information corresponding to each target register respectively; the general register information comprises register word domain range information of the plurality of target registers;
The constructing the converted register description file by using the dedicated register information and the general register information includes:
Acquiring physical address information corresponding to a current target register and field width information corresponding to the current target register respectively; the current target register is any one of the target registers;
Taking the physical address information corresponding to the current target register as register address information corresponding to the current target register, and obtaining a word domain range corresponding to the current target register by utilizing field width information respectively corresponding to the current target register and the register word domain range information;
And constructing register description information corresponding to the current target register according to the register address information corresponding to the current target register and the word field range corresponding to the current target register, and constructing the converted register description file by utilizing the register description information corresponding to each current target register.
7. The method according to any one of claims 1 to 6, wherein the obtaining a first register description file to be converted and a second register description file having a dependency relationship with the first register description file comprises:
acquiring a plurality of candidate register description files;
Obtaining candidate register description files which are not depended from the candidate register description files as the first register description file;
And acquiring keywords representing the dependency relationship from the first register description file, and taking candidate register description files associated with the keywords as the second register description file.
8. A register description file conversion apparatus, the apparatus comprising:
The device comprises a to-be-converted file acquisition module, a first register description file generation module and a second register description file generation module, wherein the to-be-converted file acquisition module is used for acquiring a to-be-converted first register description file and a second register description file which has a dependency relationship with the first register description file;
the tree model acquisition module is used for acquiring a first tree model corresponding to the first register description file according to the analysis result of the first register description file and acquiring a second tree model corresponding to the second register description file according to the analysis result of the second register description file;
the tree model splicing module is used for splicing the first tree model and the second tree model according to the description information of the second register description file to generate a target tree structure;
and the post-conversion file acquisition module is used for compiling the target tree structure to obtain the post-conversion register description file of the first register description file.
9. A computer device comprising a memory and a processor, the memory storing a computer program, characterized in that the processor implements the steps of the method of any of claims 1 to 7 when the computer program is executed.
10. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the steps of the method of any of claims 1 to 7.
11. A computer program product comprising a computer program, characterized in that the computer program, when being executed by a processor, implements the steps of the method of any of claims 1 to 7.
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