CN118080034A - Base structure of digital micro-fluidic chip and chip with same - Google Patents

Abstract

The application relates to the technical field of digital microfluidic chip device design, in particular to a substrate structure of a digital microfluidic chip and the chip with the substrate structure, comprising: a first layer, wherein the area where each electrode is positioned is provided with a first wiring hole; a second layer, the first perforated region having a plurality of second wiring holes linearly arranged along the first direction; the third layer is provided with a plurality of third wiring holes which are linearly arranged along the first direction, the third layer is connected in series with a plurality of third wiring holes which are positioned on the same straight line along the second direction so as to form a plurality of series circuits which are arranged in an extending way along the second direction, the end heads of the series circuits in each line group are arranged at intervals along the second direction, and the area where each end head is positioned is provided with a steering hole; and the fourth layer is connected with the corresponding steering holes in series, and the fourth layer is positioned on a plurality of fourth wiring holes on the same straight line along the first direction. The application solves the problem that the array size can not be increased due to the limitation of the number of the outgoing lines when the electrode array is driven by the passive matrix.

Description

Base structure of digital micro-fluidic chip and chip with same

Technical Field

The invention relates to the technical field of digital microfluidic chip device design, in particular to a substrate structure of a digital microfluidic chip and the chip with the substrate structure.

Background

Individual droplets can be independently processed and manipulated by electrodes on a substrate using a Digital Microfluidic (DMF) technique based on dielectric wetting (EWOD). The structure mainly comprises two structures: one is an open structure (single plate); the other is a closed structure (double plate). In the open structure, the drive electrode and the ground electrode are on the same substrate; in the closed structure, the upper plate is usually used as a ground electrode, and the lower plate is usually used as a driving electrode, and comprises a series of electrode arrays. By applying a specific timed voltage to the dielectric wetting chip, multiple droplets on the chip can be manipulated in parallel. At present, a digital microfluidic platform based on dielectric wetting can realize various biochemical applications, including PCR amplification, high-throughput sequencing library preparation and the like. In the design of a small array digital microfluidic chip, each electrode can be easily connected to a corresponding substrate by a wire. Assuming an array size of mxn, a Passive Matrix (PM) chip is constructed by mxn+1 pinouts. However, when the array size is increased, the number of leads of the digital microfluidic chip is increased in geometric multiple, which not only increases the difficulty of array preparation, but also causes complex peripheral control circuits and huge volume. High-throughput digital microfluidic chips therefore typically employ Active Matrix (AM) technology. The active matrix can provide limited driving voltage by adopting the existing device, and the large voltage which is usually required to be larger than 50V when driving reagents such as viscous liquid and the like can not meet the requirements of the active array control technology.

The digital microfluidic is particularly suitable for complex operation flow or repeated operation due to flexible droplet operation, small reaction volume and very little consumption of additional consumable materials. In addition, the operation process has high reliability and good consistency, and is particularly suitable for batch processing of multi-sample reaction. Bulk sample processing requires large scale electrode array control.

Existing digital microfluidic array controllers face the following challenges: the large-scale control electrode array has a huge number of electrodes, and in order to realize multi-drop or active area control, a huge number of interconnection leads need to be configured, so that the preparation difficulty of the array substrate is increased, and the peripheral control circuit is complicated and huge in size. Although the active matrix can reduce the number of lead wires, the driving voltage provided is limited and the driving capability of liquid is limited. There is an urgent need for a realization scheme of a drivable large-scale electrode array with strong driving capability, few lead wires, simple controller design, and suitability for multiple samples.

In view of the above problems in the prior art, no effective solution has been proposed at present.

Disclosure of Invention

The invention mainly aims to provide a substrate structure of a digital micro-fluidic chip and the chip with the substrate structure, so as to solve the problem that the array size cannot be increased due to the limitation of the number of outgoing lines when a passive matrix is utilized to realize large-scale electrode array driving in the prior art.

In order to achieve the above object, according to one aspect of the present invention, there is provided a substrate structure of a digital microfluidic chip, comprising: the first layer is provided with a plurality of identical reaction areas, the reaction areas are arranged in a rectangular array, a plurality of electrodes arranged in the rectangular array are arranged in each reaction area, and a first wiring hole is formed in the area where each electrode is located; the second layer is positioned at the bottom of the first layer, a plurality of first perforated areas in a rectangular array are arranged on the second layer, the first perforated areas are arranged in one-to-one correspondence with the reaction areas, the first perforated areas are provided with a plurality of second wiring holes which are linearly arranged along the first direction, and the second wiring holes are arranged in one-to-one correspondence with the first wiring holes and are communicated with the first wiring holes; the third layer is positioned at the bottom of the second layer, a plurality of second punching areas in a rectangular array are arranged on the third layer, the second punching areas are arranged in one-to-one correspondence with the first punching areas, the second punching areas are provided with a plurality of third wiring holes which are linearly arranged along the first direction, the third wiring holes are in one-to-one correspondence with the second wiring holes and are communicated with the second wiring holes, the third layer is connected in series with the third wiring holes which are positioned on the same straight line along the second direction so as to form a plurality of series circuits which extend along the second direction, the plurality of series circuits form a plurality of line groups, the end heads of the series circuits in each line group are arranged at intervals along the second direction, and the area where each end head is positioned is provided with a steering hole; the fourth layer is positioned at the bottom of the third layer, a plurality of fourth wiring holes are formed in the fourth layer, the distribution of the fourth wiring holes in the fourth layer is identical to that of the steering holes in the third layer, the fourth wiring holes are communicated with the corresponding steering holes, and the fourth layer is connected in series with the plurality of fourth wiring holes positioned on the same straight line along the first direction so as to form a plurality of outgoing lines.

Further, the first layer, the second layer, the third layer, and the fourth layer are all conductive layers.

Further, the first direction is perpendicular to the second direction.

Further, the first direction is a length direction of the base structure, the second direction is a width direction of the base structure, and/or the first direction is a width direction of the base structure, and the second direction is a length direction of the base structure.

Further, the second wiring holes in each first perforated area are in one-to-one correspondence with and are in conduction with the first wiring holes in the corresponding reaction area.

Further, the third wiring holes in each second punching area are in one-to-one correspondence with and are in conduction with the second wiring holes in the corresponding first punching area.

Further, the number of the line groups is the same as the number of columns of the second perforation areas in the rectangular array.

Further, the first wiring hole, the second wiring hole, the third wiring hole, and the fourth wiring hole are each used for filling a conductive material.

Further, the number of the lead wires is the same as the number of the ends of the series lines arranged at intervals in the second direction.

According to an aspect of the present invention, there is provided a chip comprising a base structure of a digital microfluidic chip, the base structure of the digital microfluidic chip being the base structure of the digital microfluidic chip described above.

By applying the technical scheme of the application, a special design is carried out on a four-layer structure of a substrate structure, a scheme of driving the electrode array by utilizing a passive matrix mode to carry out multi-sample reaction is realized, the defect of low driving voltage of an active matrix driving electrode array is avoided, and the number of outgoing lines is greatly reduced through a special structural design, so that the limitation of a process on the electrode array scale of a single chip is relieved, and large-scale electrode array driving is realized. By adopting the technical scheme of the application, the problem that the array size cannot be increased due to the fact that the number of the outgoing lines is limited when the passive matrix is used for realizing large-scale electrode array driving is solved.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the application. In the drawings:

Fig. 1 shows a schematic structural diagram of an embodiment of a first layer of a base structure of a digital microfluidic chip according to the present invention;

fig. 2 shows a schematic structural diagram of an embodiment of a second layer of a base structure of a digital microfluidic chip according to the present invention;

fig. 3 shows a schematic structural view of an embodiment of a third layer of a base structure of a digital microfluidic chip according to the present invention;

Fig. 4 shows a schematic structural diagram of an embodiment of a fourth layer of a base structure of a digital microfluidic chip according to the present invention.

Wherein the above figures include the following reference numerals:

1. a first layer; 11. a reaction zone; 111. an electrode; 112. a first wiring hole;

2. A second layer; 21. a first perforated section; 211. a second wiring hole;

3. A third layer; 31. a second perforated region; 311. a third wiring hole; 32. a series line; 33. a steering hole;

4. A fourth layer; 41. a fourth wiring hole;

5. And (5) leading out wires.

Detailed Description

It should be noted that, without conflict, the embodiments of the present application and features of the embodiments may be combined with each other. The application will be described in detail below with reference to the drawings in connection with embodiments.

It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of exemplary embodiments according to the present application. As used herein, the singular is also intended to include the plural unless the context clearly indicates otherwise, and furthermore, it is to be understood that the terms "comprises" and/or "comprising" when used in this specification are taken to specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof.

It should be noted that the terms "first," "second," and the like in the description and the claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the application described herein are, for example, capable of operation in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

Exemplary embodiments according to the present application will now be described in more detail with reference to the accompanying drawings. These exemplary embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. It should be understood that these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of these exemplary embodiments to those skilled in the art, that in the drawings, it is possible to enlarge the thicknesses of layers and regions for clarity, and that identical reference numerals are used to designate identical devices, and thus descriptions thereof will be omitted.

The digital microfluidic chip is a miniaturized fluid control system, and accurate control of micro liquid drops and microfluidics is realized through a micro structure and a microfluidic technology. The structure mainly comprises a digital micro-fluidic chip, a control system and a sensor.

The digital microfluidic chip is a miniaturized fluid control system composed of micro structures such as a micro flow channel, a micro valve, a micro pump, a micro mixer and the like. Through miniaturized structure and micro-fluid technology, accurate control of micro-droplets and micro-fluid can be realized, including functions of segmentation, mixing, analysis, detection and the like. The microstructure of the digital microfluidic chip can realize the division and mixing of tiny liquid drops, and the precise control and control of microfluid can be realized through a micro valve and a micro pump.

The control system is a core part of the digital micro-fluidic chip, and can realize accurate control and operation of the digital micro-fluidic chip. Through the control system, the micro valve and the micro pump of the digital micro-fluidic chip can be accurately controlled, so that the accurate control of micro liquid drops and micro fluid is realized. The sensor is an important component of the digital microfluidic chip, and can realize accurate detection and monitoring of micro liquid drops and microfluidics. The flow state and the characteristics of the micro liquid drops and the microfluid can be monitored in real time through the sensor, so that the accurate control and the control of the digital microfluidic chip are realized.

The digital microfluidic chip realizes accurate control of micro liquid drops and microfluid through a micro structure and a microfluid technology, and the functions of segmentation, mixing, analysis, detection and the like are included. The structure of the micro-fluidic device mainly comprises a digital micro-fluidic chip, a control system and a sensor, and through the synergistic effect of the three parts, accurate control and monitoring of micro liquid drops and micro fluid can be realized.

In the prior art, for small-scale digital microfluidic chip designs, each electrode can be easily connected to a corresponding substrate by a wire. For large-scale digital microfluidic chip design, a high-flux digital microfluidic chip is generally designed in an active matrix mode, but the active matrix adopts the existing device to provide limited driving voltage, and the application range of the active matrix is smaller.

If the passive matrix scheme is adopted to drive the electrode array, when the size of the array is increased, the number of leads of the digital microfluidic chip is increased in geometric multiple, so that the preparation difficulty of the array is increased, and the peripheral control circuit is complicated. How to solve the limitation of the number of leads to the large-scale array arrangement becomes a technical problem to be solved in the industry.

As shown in connection with fig. 1 to 4. According to a specific embodiment of the application. A substrate structure of a digital microfluidic chip is provided. The substrate structure of the digital microfluidic chip comprises: a first layer 1, a second layer 2, a third layer 3, a fourth layer 4. The first layer 1 is provided with a plurality of identical reaction zones 11. The plurality of reaction zones 11 are arranged in a rectangular array. Each reaction zone 11 has a plurality of electrodes 111 arranged in a rectangular array. The region where each electrode 111 is located is provided with a first wiring hole 112. The second layer 2 is located at the bottom of the first layer 1. The second layer 2 is provided with a plurality of first perforated sections 21 in a rectangular array. The plurality of first perforated sections 21 are disposed in one-to-one correspondence with the plurality of reaction sections 11. The first perforated section 21 has a plurality of second wiring holes 211 linearly arranged in the first direction. The second wiring holes 211 are in one-to-one correspondence with the first wiring holes 112 and are arranged in a conductive manner. The third layer 3 is located at the bottom of the second layer 2. The third layer 3 is provided with a plurality of second perforated areas 31 in a rectangular array. The plurality of second perforated sections 31 are disposed in one-to-one correspondence with the plurality of first perforated sections 21. The second perforated region 31 has a plurality of third wiring holes 311 linearly arranged in the first direction. The third wiring holes 311 are in one-to-one correspondence with the second wiring holes 211 and are in conductive arrangement. The plurality of third wiring holes 311 of the third layer 3 on the same straight line in the second direction are connected in series to form a plurality of series lines 32 extending in the second direction. The plurality of series lines 32 form a plurality of line groups. The ends of the series lines 32 in each line group are arranged at intervals along the second direction. The area of each end is provided with a turning hole 33. The fourth layer 4 is located at the bottom of the third layer 3. The fourth layer 4 is provided with a plurality of fourth wiring holes 41. The distribution of the fourth wiring holes 41 in the fourth layer 4 is the same as the distribution of the turning holes 33 in the third layer 3. The fourth wiring hole 41 is in communication with the corresponding steering hole 33. The fourth layer 4 is connected in series with a plurality of fourth wiring holes 41 located on the same straight line in the first direction. To form a plurality of lead wires 5.

Wherein the distribution of the fourth wiring holes 41 in the fourth layer 4 is the same as the distribution of the turning holes 33 in the third layer 3, which means that the number of the fourth wiring holes 41 is the same as the number of the turning holes 33, and the projection of each turning hole 33 along the height direction of the base structure coincides with the projection of the corresponding fourth wiring hole 41 along the height direction of the base structure. The single reaction zone 11 forms a reaction space containing one sample.

As shown in fig. 3, the line group is 3, i.e. the plurality of series lines 32 is divided into three parts. The ends of the series line 32 refer to the linear ends of the series line 32.

By applying the technical scheme of the application, a special design is carried out on a four-layer structure of a substrate structure, a scheme of driving the electrode array by utilizing a passive matrix mode to carry out multi-sample reaction is realized, the defect of low driving voltage of an active matrix driving electrode array is avoided, and the number of outgoing lines is greatly reduced through a special structural design, so that the limitation of a process on the electrode array scale of a single chip is relieved, and large-scale electrode array driving is realized. By adopting the technical scheme of the application, the problem that the array size cannot be increased due to the fact that the number of the outgoing lines is limited when the passive matrix is used for realizing large-scale electrode array driving is solved.

It should be noted that "first" of the "first layer" and "second" of the "second layer" in the above embodiments are only used to describe the levels of the corresponding structures, respectively. Common digital microfluidic chips include open structures (single plates) and closed structures (double plates). In the open structure, the driving electrode and the ground electrode are on the same substrate, and the sample is on the substrate; in the closed structure, the sample is located between an upper plate and a lower plate, the upper plate is usually used as a ground electrode, and is usually composed of Indium Tin Oxide (ITO), and the lower plate is used as a driving electrode and comprises a series of electrode arrays. For a closed structure, the ground electrode is located in the first layer, whereas the first layer 1 of the base structure is located in the lower part of the ground electrode. The technical scheme of the application can be applied to both open structures (single flat plate) and closed structures (double flat plate).

Alternatively, the first wiring hole 112 is a wiring hole between the first layer 1 and the second layer 2 for electrically connecting the first layer 1 and the second layer 2. The second wiring hole 211 is a wiring hole between the second layer 2 and the third layer 3 for electrically connecting the second layer 2 and the third layer 3. The third wiring hole 311 is a wiring hole between the third layer 3 and the fourth layer 4 for electrically connecting the third layer 3 and the fourth layer 4. The fourth wiring hole 41 is a wiring hole between the fourth layer 4 and the substrate for electrically connecting the fourth layer 4 and the substrate. The lead wires 5 are used to receive electrical signals to control the electrode signals within each reaction zone 11.

By adopting the technical scheme of the application, the number of the conductive layers of the substrate structure can be more, such as six layers or eight layers. Each electrode on the conductive layer is connected with the substrate through a signal line.

Further, the first layer 1, the second layer 2, the third layer 3 and the fourth layer 4 are all conductive layers. Optionally, the conductive layer further includes an insulating material (or referred to as an insulating layer) located under the conductive layer, and the main structures of adjacent conductive layers are electrically isolated by the insulating material, where the insulating material is only perforated at the perforated positions (i.e. at each wiring hole), and then used to fill the conductive material (or adopt other wiring processes), so that the adjacent conductive layers are electrically connected at specific points.

The wiring holes in the above embodiments are conducted with the wiring holes, which may mean that conduction is performed by the conductive material disposed in the holes.

Preferably, the substrate structure is made of a PCB, and other materials that can be perforated or used to form interlayer conductive connections can also implement the design.

Referring now to fig. 1 to 4, the construction of the base structure and the wiring method are described as follows:

as shown in fig. 1, the first layer is the top layer of the substrate structure, 9 reaction areas are shown in fig. 1 and are arranged in a 3*3 rectangular array, each reaction area has the same structure, and each reaction area comprises 6 electrodes (arranged in a 2-row 3-column rectangular array); each electrode is perforated to form a plurality of first wiring holes. 9 reaction zones are shown in FIG. 2, arranged in a 3*3 rectangular array; the arrangement of the electrodes within a single reaction zone changed from the 2*3 array shown in fig. 1 to 1*6 linear repeating units, which was arranged to reduce the number of lead-out wires in the row dimension within a single reaction zone; the second layer in fig. 2 is perforated to the third layer, forming a plurality of second wiring holes. In fig. 3, a third layer is shown, where the third layer has a plurality of third wiring holes, and the third layer has a plurality of third wiring holes on the same line along the second direction, and the third layer is connected in series to form a plurality of serial lines extending along the second direction, and in fig. 3, 3 line groups and 18 serial lines are shown, which can be regarded as a matrix distribution form of 1×18; the purpose of the series connection along the second direction is to reduce the number of outgoing lines of the electrode array in the column dimension; the plurality of series lines in one line group are arranged at intervals along the second direction by rotating the connecting point wiring by 90 degrees, and the purpose of the arrangement is to align the plurality of series lines of different line groups in the row dimension so as to be convenient for connection with the fourth layer. In fig. 4, 6 lead-out wires are shown, the purpose of which is to connect the transfer holes of a plurality of series lines of different line groups located in the same row dimension, whereby only 6 lead-out wires control 54 electrodes in the first layer. As the electrodes adopt a rectangular array mode, the matrix arrangement of the reaction area is not limited by design, and only 6 outgoing lines are provided no matter how large the matrix arrangement area of the reaction area is, depending on the processing and manufacturing capacity of the substrate.

Further, the first direction is perpendicular to the second direction.

In an alternative embodiment, the first direction is the length direction of the base structure, the second direction is the width direction of the base structure, and/or the first direction is the width direction of the base structure, and the second direction is the length direction of the base structure. Preferably, F2 is a first direction as shown in FIG. 4, and F1 is a second direction as shown in FIG. 4.

In another alternative embodiment, the present application achieves large-scale electrode array driving of multiple sample reactions in a passive matrix fashion with no less than 4 conductive layers. The application adopts a passive matrix scheme, reduces outgoing lines while maintaining high voltage and strong liquid drop driving capability, and simplifies the design difficulty of a controller. The reaction area of each sample is assumed to be M multiplied by N electrodes, the reaction areas can be repeatedly arranged to form a large-scale electrode array, and the corresponding electrodes in the corresponding areas are connected in series to form parallel synchronous control of liquid, so that the number of outgoing lines can be reduced. From the wiring point of view, it is easy to think that the reaction area is arranged in 2 rows or 2 columns separately, the electrodes are arranged in mirror image, and the wiring is convenient, but the design array is limited in scale. The matrix arrangement of the reaction areas is not limited by design and depends on the processing and manufacturing capacity of the substrate. The reaction area matrix arrangement can connect the leads of the corresponding electrodes together in series through the wiring of the multilayer board rule (namely, the wiring of the substrate structure provided by the application), and no matter how large the reaction area matrix arrangement area is, only M multiplied by N lead wires can be formed.

Assuming that each sample occupies a reaction zone, each reaction zone is provided with M rows and N columns of electrodes (assuming M is larger than or equal to N), and the electrodes in each reaction zone are uniformly distributed; the reaction areas are arranged in a matrix manner, and X rows and Y columns are arranged; at least 4 conductive layers, the top layer is an electrode layer;

The wiring method is as follows: punching the top electrode to the second layer; m rows and N columns of electrodes in each reaction area of the second layer are arranged in a row in the reaction area to form repeated units of M multiplied by N electrodes, and X rows and Y columns are perforated to the third layer; the third layer connects the electrodes corresponding to each column of the Y-column reaction area in series, rotates the last connecting point wiring by 90 degrees, converts the last connecting point wiring into M multiplied by N electrodes to be arranged in a column, and forms a repeating unit of M multiplied by N electrodes, wherein 1 row of Y columns exist, and the repeating unit is perforated to the fourth layer; and the fourth layer connects the electrodes corresponding to the Y columns in series to form M multiplied by N control points, and finally controls the corresponding electrodes in each reaction zone.

Specifically, the plurality of second wiring holes 211 in each first perforated region 21 are arranged in one-to-one correspondence with and in conduction with the plurality of first wiring holes 112 in the corresponding reaction region 11.

Further, the third wiring holes 311 in each second perforated region 31 are in one-to-one correspondence with and are in conduction with the corresponding second wiring holes 211 in the first perforated region 21.

Alternatively, the number of line groups is the same as the number of columns of the second perforated sections 31 in a rectangular array. This arrangement allows for switching of multiple series lines within a single second perforated section 31, thereby allowing for switching of the series lines within different second perforated sections 31 in series in the same row dimension.

Further, the first wiring hole 112, the second wiring hole 211, the third wiring hole 311, and the fourth wiring hole 41 are each used for filling with a conductive material. The different electrode layers can be connected by filling with a conductive material.

Further, the number of the lead wires 5 is the same as the number of the ends of the series lines 32 arranged at intervals in the second direction.

In an alternative embodiment, a 48 sample reaction zone is implemented using a4 layer PCB with 4 rows and 7 columns of electrodes per reaction zone, for a total of 1344 electrode actuation steps as follows:

Step 1 (PCB design): electrode sizes were set at 2 x 2mm with electrode spacing of 4mil, and a Gerber file was generated for delivery to PCB fab proofing using solder mask ink as the insulating layer.

Step 2 (chip assembly): and after the PCB shields the sealing area, spraying a hydrophobic layer and solidifying. The sealing rubber ring is 0.5mm high, the double-sided back adhesive is adhered to the conductive surface of the conductive glass, and the area glued with the PCB is shielded, sprayed with a hydrophobic layer and cured. And (3) aligning the PCB and the conductive glass, and then adhering the PCB and the conductive glass by using UV adhesive.

Step 3 (drive verification): the device is connected with a driving circuit, silicone oil is injected, and aqueous solution, saline solution and the like can be flexibly and synchronously driven in each reaction area in the range of 50-300V.

According to another embodiment of the present invention, a chip is provided, including a substrate structure of a digital microfluidic chip, where the substrate structure of the digital microfluidic chip is the substrate structure of the digital microfluidic chip.

From the above description, it can be seen that the above embodiments of the present invention achieve the following technical effects: the novel wiring method is provided for the reaction area with multiple samples in matrix arrangement, the control of the large-scale micro-fluid array can be realized, and meanwhile, the scheme has the unique advantages of strong driving capability, fewer outgoing lines, simple controller design and suitability for the multi-sample drivable large-scale electrode array.

The invention relates to the design of digital microfluidic devices, and provides a wiring method for matrix arrangement of multiple sample reaction areas. Digital microfluidic is a droplet operation technology based on electrowetting, and in the reaction of multiple samples, practical application often divides M×N electrodes into a reaction area, each sample occupies one reaction area, and isolation can be performed between the reaction areas to prevent pollution among samples. The common reaction area arrangement is a matrix type, and the corresponding electrode of each reaction area can be synchronously controlled. The ultra-large electrode array is realized by adopting a 4-layer PCB (printed Circuit Board) in a passive matrix mode, the synchronous reaction of large samples is realized, the control mode is simple and direct, the control difficulty of a large-scale micro-fluid array can be greatly reduced, and the number of leads is reduced.

Spatially relative terms, such as "above … …," "above … …," "upper surface on … …," "above," and the like, may be used herein for ease of description to describe one device or feature's spatial location relative to another device or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "above" or "over" other devices or structures would then be oriented "below" or "beneath" the other devices or structures. Thus, the exemplary term "above … …" may include both orientations "above … …" and "below … …". The device may also be positioned in other different ways (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

In addition to the foregoing, references in the specification to "one embodiment," "another embodiment," "an embodiment," etc., indicate that the particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the application, as generally described. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with any embodiment, it is intended that such feature, structure, or characteristic be implemented within the scope of the application.

In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to related descriptions of other embodiments.

The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (10)

1. A substrate structure for a digital microfluidic chip, comprising:

The device comprises a first layer (1), wherein a plurality of identical reaction areas (11) are arranged on the first layer (1), the reaction areas (11) are arranged in a rectangular array, a plurality of electrodes (111) arranged in the rectangular array are arranged in each reaction area (11), and a first wiring hole (112) is formed in the area where each electrode (111) is located;

The second layer (2) is positioned at the bottom of the first layer (1), a plurality of first perforated areas (21) in a rectangular array are arranged on the second layer (2), the first perforated areas (21) are arranged in a one-to-one correspondence with the reaction areas (11), the first perforated areas (21) are provided with a plurality of second wiring holes (211) which are linearly arranged along a first direction, and the second wiring holes (211) are in one-to-one correspondence with the first wiring holes (112) and are in conduction arrangement;

The third layer (3) is positioned at the bottom of the second layer (2), a plurality of second punching areas (31) which are in a rectangular array are arranged on the third layer (3), the plurality of second punching areas (31) are arranged in a one-to-one correspondence with the plurality of first punching areas (21), the second punching areas (31) are provided with a plurality of third wiring holes (311) which are linearly arranged along the first direction, the plurality of third wiring holes (311) are in one-to-one correspondence with the plurality of second wiring holes (211) and are in conduction arrangement, the plurality of third wiring holes (311) which are positioned on the same straight line along the second direction of the third layer (3) are connected in series to form a plurality of series circuits (32) which are arranged along the second direction, the plurality of series circuits (32) form a plurality of wire groups, the ends of the series circuits (32) in each wire group are arranged at intervals along the second direction, and the end areas are provided with turning holes (33);

The fourth layer (4), fourth layer (4) are located the bottom of third layer (3), be provided with a plurality of fourth wiring hole (41) on fourth layer (4), the distribution of fourth wiring hole (41) in fourth layer (4) is the same with turn to hole (33) in the distribution of third layer (3), fourth wiring hole (41) with corresponding turn to hole (33) switch on, fourth layer (4) are followed a plurality of fourth wiring hole (41) on the same straight line are established ties to form a plurality of lead-out wires (5).

2. The substrate structure of a digital microfluidic chip according to claim 1 wherein the first layer (1), the second layer (2), the third layer (3) and the fourth layer (4) are all electrically conductive layers.

3. The substrate structure of a digital microfluidic chip according to claim 1 wherein said first direction is perpendicular to said second direction.

4. The substrate structure of the digital microfluidic chip according to claim 1 wherein the first direction is a length direction of the substrate structure, the second direction is a width direction of the substrate structure, and/or the first direction is a width direction of the substrate structure, and the second direction is a length direction of the substrate structure.

5. The base structure of the digital microfluidic chip according to claim 1, wherein a plurality of the second wiring holes (211) in each of the first perforated regions (21) are provided in one-to-one correspondence and conduction with a plurality of the first wiring holes (112) in the corresponding reaction region (11).

6. The base structure of the digital microfluidic chip according to claim 1, wherein a plurality of the third wiring holes (311) in each of the second perforated regions (31) are provided in one-to-one correspondence and conduction with a plurality of the second wiring holes (211) in the corresponding first perforated region (21).

7. The base structure of a digital microfluidic chip according to claim 1 wherein the number of line groups is the same as the number of columns of the second perforated areas (31) in a rectangular array.

8. The base structure of a digital microfluidic chip according to claim 1 wherein the first wiring hole (112), the second wiring hole (211), the third wiring hole (311) and the fourth wiring hole (41) are each for filling with a conductive material.

9. The base structure of a digital microfluidic chip according to claim 1 wherein the number of lead-out wires (5) is the same as the number of ends of the series lines (32) arranged at intervals along the second direction.

10. A chip comprising a base structure of a digital microfluidic chip, characterized in that the base structure of the digital microfluidic chip is the base structure of the digital microfluidic chip according to any one of claims 1 to 9.