CN118077981A - Signal processing method, signal processing circuit, piezoelectric sensing system and electronic cigarette - Google Patents

Abstract

The application relates to a signal processing method, a signal processing circuit, a piezoelectric sensing system and an electronic cigarette, wherein the method comprises the following steps: in response to the first pulse signal, initiating a timer; if the first pulse signal is input under the condition that the timing does not exceed the threshold time, shielding the first pulse signal; if the first pulse signal continues to be input under the condition that the timing exceeds the threshold time, outputting a second pulse signal when the timing reaches the threshold time, and turning over the level of the second pulse signal in response to the level turning over of the first pulse signal; the first pulse signal is obtained by detecting the output voltage of the piezoelectric sensor; the threshold time is not less than the maintenance time of the burr signal generated by the piezoelectric sensor due to the impact; the level inversion of the second pulse signal is used to indicate resetting of the piezoelectric sensor. The application solves the problem that the filter capacitor is not suitable for eliminating the impact burr of the piezoelectric sensor in the related technology, and does not influence the elimination of rebound voltage.

Description

Signal processing method, signal processing circuit, piezoelectric sensing system and electronic cigarette

Technical Field

The application relates to the field of piezoelectric sensor signal processing, in particular to a signal processing method, a signal processing circuit, a piezoelectric sensing system and an electronic cigarette.

Background

A piezoelectric sensor, which is a sensor that converts mechanical pressure into an electrical signal, uses the characteristics of a piezoelectric material, and when an external force is applied to the surface thereof, the internal charge distribution changes, thereby generating a voltage. The piezoelectric sensor converts a physical quantity into an electrical signal, and the processing of the electrical signal requires a chip. Therefore, in practical applications, the piezoelectric sensor and the signal processing circuit are usually combined with each other, so as to enhance the function and measurement accuracy of the sensor, and better meet the requirements of different industries.

Fig. 1 is a schematic diagram of a state change process of a piezoelectric sensor. Wherein, fig. 1a represents the state change process of the piezoelectric sensor when the piezoelectric sensor is normally stressed, and fig. 1b represents the state change process of the piezoelectric sensor when the piezoelectric sensor is impacted. Referring to fig. 1a, the piezoelectric sensor is typically a parallel plate-like capacitor structure with uniform positive and negative charges in the medium. Under the condition of no external force, the whole body presents electric neutrality, and when the sensor is stressed, the geometric centers of positive and negative charges are dislocated, so that induced charges are presented on the two polar plates. The greater the force, the greater the degree of misalignment of the geometric centers of the positive and negative charges, and the greater the amount of charge on the plate. If the sensor is subjected to pressure in the opposite direction, charges are generated as well, but the charge sign corresponding to each polar plate is changed according to the direction of the force. The piezoelectric sensor outputs voltage when the internal charge of the piezoelectric sensor changes, and the signal processing circuit judges whether a pressure event occurs according to the output voltage.

Referring to fig. 1b, in addition to the normal applied pressure, if a piezoelectric sensor encounters an impact, the impact is divided into two processes of applying the impact and ending the impact. During the impact, the piezoelectric transducer will rapidly generate an induced charge. During the end of the impact, the piezoelectric transducer will quickly generate an induced charge of opposite polarity to neutralize the induced charge generated by the impact before, thereby quickly returning to neutrality. The impact may generate a glitch signal having a large amplitude that, if left untreated, may falsely trigger a pressure event. The related art adopts a filter capacitor to eliminate interference signals, and the method is not suitable for filtering the impact burrs of the piezoelectric sensor because the piezoelectric sensor generates the burr signals due to impact and has long maintenance time.

Aiming at the problem that the piezoelectric sensor generates a burr signal due to collision in the related art, no effective solution is proposed at present.

Disclosure of Invention

In view of the foregoing, it is desirable to provide a signal processing method, a signal processing circuit, a piezoelectric sensing system, and an electronic cigarette capable of eliminating a burr signal of a piezoelectric sensor.

In a first aspect, the present application provides a signal processing method, including:

In response to the first pulse signal, initiating a timer;

If the first pulse signal is input under the condition that the timing does not exceed the threshold time, shielding the first pulse signal;

If the first pulse signal continues to be input under the condition that the timing exceeds the threshold time, outputting a second pulse signal when the timing reaches the threshold time, and turning over the level of the second pulse signal in response to the level turning over of the first pulse signal;

The first pulse signal is obtained by detecting the output voltage of the piezoelectric sensor; the threshold time is not less than the maintenance time of a burr signal generated by the piezoelectric sensor due to impact; the level inversion of the second pulse signal is used for indicating the reset of the piezoelectric sensor.

In some of these embodiments, the first pulse signal is not less than a threshold voltage; wherein the threshold voltage is used to characterize a voltage at which the piezoelectric sensor is able to detect a pressure event.

In some of these embodiments, the method further comprises: the piezoelectric sensor is reset in response to a level reversal of the second pulse signal.

In a second aspect, the present application provides a signal processing circuit comprising: the device comprises a comparison unit and a logic module, wherein the comparison unit is connected with the logic module; wherein,

The comparing unit is used for comparing the output voltage of the piezoelectric sensor with a threshold voltage and generating a first pulse signal under the condition that the output voltage of the piezoelectric sensor is not smaller than the threshold voltage; wherein the threshold voltage is used to characterize a voltage at which the piezoelectric sensor is able to detect a pressure event;

The logic module is configured to perform the signal processing method described in the first aspect.

In some of these embodiments, the logic module comprises: the frequency dividing unit, the OR gate, the inverter and the first trigger; the clock input end of the frequency dividing unit is connected with a clock source, the reset end of the frequency dividing unit is connected with the comparing unit, and the output end of the frequency dividing unit is connected with the clock input end of the first trigger; the output end of the inverter is connected with the first input end of the OR gate; the second input end of the OR gate is connected with the comparison unit, and the output end of the OR gate is connected with the reset end of the first trigger; wherein,

The frequency dividing unit is used for responding to the first pulse signal, outputting a frequency dividing signal and carrying out level inversion on the output frequency dividing signal when the cancel reset time reaches the threshold time;

the first trigger is used for responding to the level inversion of the frequency division signal and outputting the second pulse signal.

In some of these embodiments, the logic module further comprises: a delay unit; the input end of the delay unit is connected with the comparison unit, and the output end of the delay unit is connected with the input end of the inverter.

In some of these embodiments, the frequency dividing unit includes: a plurality of second flip-flops; the clock input end of the first-stage second trigger is connected with the clock source, the complement output end of the last-stage second trigger is connected with the first trigger, the reset end of each stage second trigger is connected with the comparison unit, the data input end of each stage second trigger is connected with the complement output end, and the complement output end of the previous-stage second trigger is connected with the clock input end of the next-stage second trigger.

In some of these embodiments, the signal processing current further comprises: and the reset switch is connected with the logic module and can respond to a reset signal of the logic module to reset/release the piezoelectric sensor through switching the state of the switch.

In a third aspect, the present application provides a piezoelectric sensing system comprising: a piezoelectric sensor and the signal processing circuit according to the second aspect, wherein the piezoelectric sensor is connected with the signal processing circuit.

In a fourth aspect, the present application provides an electronic cigarette, comprising: the main body is provided with a piezoelectric sensor and the signal processing circuit of the second aspect, and the piezoelectric sensor is connected with the signal processing circuit.

The signal processing method, the signal processing circuit, the piezoelectric sensing system and the electronic cigarette determine whether the first pulse signal is a burr signal or a pressure signal through the threshold value when the first pulse signal is introduced; if the first pulse signal is the burr signal, shielding the first pulse signal; if the pressure signal is the pressure signal, outputting a second pulse signal; the level inversion of the second pulse signal is used for indicating the reset of the piezoelectric sensor; the problem that a filter capacitor is not suitable for eliminating the impact burrs of the piezoelectric sensor in the related art is solved, and the elimination of rebound voltage is not influenced.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments or the conventional techniques of the present application, the drawings required for the descriptions of the embodiments or the conventional techniques will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to the drawings without inventive effort for those skilled in the art.

FIG. 1a is a schematic diagram showing the state change process of a piezoelectric sensor when the piezoelectric sensor is normally stressed;

FIG. 1b is a schematic diagram showing a state change process of a piezoelectric sensor when the piezoelectric sensor encounters an impact;

FIG. 2 is a schematic diagram of an equivalent circuit of a piezoelectric sensor;

FIG. 3 is a schematic diagram of a response curve of a piezoelectric sensor;

FIG. 4 is a flow diagram of a signal processing method in one embodiment;

FIG. 5 is a schematic diagram of a circuit for eliminating the bounce voltage in one embodiment;

FIG. 6 is an effect diagram of a signal processing method in one embodiment;

FIG. 7 is a schematic diagram of the architecture of a signal processing circuit in one embodiment;

FIG. 8 is a schematic diagram of the internal architecture of a logic module in one embodiment;

FIG. 9 is a schematic diagram of an internal structure of a frequency dividing unit in one embodiment;

FIG. 10 is a schematic diagram of an alternative configuration of a trigger in one embodiment;

FIG. 11 is a schematic diagram of the operation of the signal processing circuit in one embodiment;

Fig. 12 is a second schematic diagram of the operation of the signal processing circuit in one embodiment.

Reference numerals illustrate: 1. a signal processing circuit; 11. a comparison unit; 12. a logic module; 121. a frequency dividing unit; 122. or gate; 123. a first inverter; 124. a first trigger; 125. a delay unit; 126. a second inverter; 127. a second trigger; 13. a first pin; 14. a second pin; 15. a third pin; 16. an amplifying unit; 17. a voltage generation module; K. a reset switch; C. a filter capacitor; CK. A clock input; rst, reset end; D. a data input of the flip-flop; the data output end of the Q and trigger; q', complement output of the trigger; MEMS, piezoelectric sensor; q, a charge source; cp, capacitance; rp, resistance; voltage output pins of the Vout and piezoelectric sensors; vref, reference voltage input pin of the piezoelectric sensor.

Detailed Description

In order that the application may be readily understood, a more complete description of the application will be rendered by reference to the appended drawings. Embodiments of the application are illustrated in the accompanying drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

It will be understood that the terms first, second, etc. as used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another element. For example, a first resistance may be referred to as a second resistance, and similarly, a second resistance may be referred to as a first resistance, without departing from the scope of the application. Both the first resistor and the second resistor are resistors, but they are not the same resistor.

It is to be understood that in the following embodiments, "connected" is understood to mean "electrically connected", "communicatively connected", etc., if the connected circuits, modules, units, etc., have electrical or data transfer between them.

It is understood that "at least one" means one or more and "a plurality" means two or more. "at least part of an element" means part or all of the element.

As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," and/or the like, specify the presence of stated features, integers, steps, operations, elements, components, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof. Also, the term "and/or" as used in this specification includes any and all combinations of the associated listed items.

Fig. 2 is a schematic diagram of an equivalent circuit of a piezoelectric sensor. As shown in fig. 2, where MEMS represents a piezoelectric sensor, which can be equivalently referred to as a charge source q, a capacitor Cp, and a resistor Rp are connected in parallel with each other, vout represents the output voltage of the MEMS, and Vref represents the reference voltage of the piezoelectric sensor. When the plate is pressed, the charge source q generates a charge and stores the charge in the capacitor Cp, forming a voltage difference of Vout-vref=q/Cp, however, due to the resistor Rp, the charge on the capacitor Cp slowly leaks through Rp, resulting in a decrease in the charge amount on the capacitor Cp, and thus the value of Vout-Vref decreases until vout=vref, where the charge is 0.

Fig. 3 is a schematic diagram of a response curve of a piezoelectric sensor. As shown in fig. 3, in the latter half of the curve, a glitch signal is generated when the piezoelectric sensor encounters an impact. The glitch hold time is typically between a few ms and a few tens of ms and its magnitude is large, which if left untreated, will falsely trigger a pressure event.

Based on the above analysis, fig. 4 shows a signal processing method of the present embodiment, and as shown in fig. 4, the flow includes the following steps:

Step S401, responding to the first pulse signal, starting timing;

step S402, if the first pulse signal is input under the condition that the timing does not exceed the threshold time, shielding the first pulse signal;

step S403, if the first pulse signal continues to be input when the timing exceeds the threshold time, outputting a second pulse signal when the timing reaches the threshold time, and turning over the level of the second pulse signal in response to the level turning over of the first pulse signal;

The first pulse signal is obtained by detecting the output voltage of the piezoelectric sensor. The output voltage of the piezoelectric sensor may be compared with a threshold voltage; regenerating into a first pulse signal under the condition that the output voltage of the piezoelectric sensor is not less than a threshold voltage; wherein the threshold voltage is used to characterize the voltage at which the piezoelectric sensor is able to detect a pressure event.

The threshold time is not less than the maintenance time of the burr signal generated by the piezoelectric sensor due to the impact. In response to the first pulse signal, a timer is started in the sense that a magnitude comparison is made between the sustain time and the threshold time of the first pulse signal. If the maintaining time of the first pulse signal is longer than the threshold time, judging that the first pulse signal is a pressure signal; otherwise, the first pulse signal is judged to be the burr signal.

The second pulse signal is a signal which starts to be output from the time when the first pulse signal is the pressure signal. The first pulse signal and the second pulse signal have the same amplitude, and the second pulse signal corresponds to a signal obtained by cutting the first pulse signal into a first half waveform corresponding to the threshold time. The level inversion of the second pulse signal is used to indicate resetting of the piezoelectric sensor.

The embodiment discards the filter capacitor and introduces a time threshold to determine whether the first pulse signal is a glitch signal or a pressure signal. If the first pulse signal is the burr signal, shielding the first pulse signal; and if the pressure signal is the pressure signal, outputting a second pulse signal. The problem that a filter capacitor is not suitable for eliminating the collision burrs of the piezoelectric sensor in the related art is solved.

Further, the embodiment not only can effectively eliminate the collision burrs, but also can not influence the elimination effect of the rebound voltage. To illustrate this effect, another characteristic of the pinch point sensor, namely, the bounce voltage and the bounce voltage cancellation method, are described below, respectively.

With continued reference to fig. 3, in the first half of the curve, when a back pressure is applied to the piezoelectric sensor (e.g., to the lower plate of fig. 1 a), an electrical charge is generated on the plate, creating a voltage; as the force increases, the amount of charge increases and the output voltage Vout increases. The output voltage Vout peaks when the force just changes from increasing to remaining unchanged. Subsequently, the output voltage Vout slowly decreases due to the aforementioned charge leakage. If the "force-withdrawing process" occurs before the charge is completely leaked, the charges with opposite signs are generated inside the piezoelectric sensor, so that the charges generated in the "force-withdrawing process" are counteracted, and the steep force-withdrawing edge and the rebound voltage are shown on the output voltage. The rebound voltage is a voltage formed by the residual charge on the capacitor Cp after the residual charge generated by the "force removing process" and the residual charge generated by the "force removing process start time" have been cancelled. With the slow leakage of the residual charge, the rebound voltage is gradually restored to the baseline potential (the schematic is shown as 0 potential for convenience).

Similarly, when a positive pressure is applied to the sensor (e.g., the top plate of fig. 1 is forced), the above-mentioned four processes of voltage peak with increasing force, charge leakage with stable force maintenance, voltage drop, rebound voltage when the force is removed, and slow recovery of the rebound voltage are still experienced. The bounce voltage will likely trigger a false positive, resulting in a "misunderstanding" of the signal processing circuitry that pressure has occurred. For example, industrial equipment false-start, medical equipment false-alarm, and electronic cigarette false-ignition, which can cause inconvenience and even safety hazards.

In one embodiment, a rebound voltage cancellation method is presented, i.e., resetting the piezoelectric sensor upon the occurrence of a force-withdrawal event. Fig. 5 shows a schematic circuit diagram for eliminating the rebound voltage, and as shown in fig. 5, a reset switch K is arranged between a voltage output pin Vout and a reference voltage input pin Vref of the piezoelectric sensor, and the reset is completed by closing the reset switch K when a force-removing event occurs, and discharging the induced charge of the piezoelectric sensor.

It should be noted that the timing of the reset operation must follow the force-withdrawal event, since the reset is to be completed before the rebound voltage has not caused a false trigger. Therefore, the glitch elimination method cannot affect the timing of the force-withdrawal reset.

Returning to the signal processing method shown in fig. 4, in this embodiment, whether the first pulse signal is a glitch signal or a pressure signal is determined by the threshold time, and since the determination process itself consumes the threshold time, there is a time delay between the output of the second pulse signal and the input of the first pulse signal, and this time delay affects another action: the force is removed to reset to eliminate the rebound voltage. Therefore, after the second pulse signal is output, when the first pulse signal is subjected to level inversion, the second pulse signal is immediately caused to be subjected to level inversion, and the force-withdrawal reset is not affected. Finally, the effect of eliminating burr signals under the condition of not influencing the force-removing reset is realized.

To further disclose the effect of the present embodiment, fig. 6 shows a schematic diagram of the effect of the signal processing method. Please refer to fig. 6. First, a threshold time is set, preferably greater than the retention time of the strike. When the collision burr occurs, a short pulse (first pulse signal) will be output. Next, the sustain time of the first pulse signal is compared with the threshold time, and if the threshold time is not exceeded, it is considered that the glitch signal due to the impact occurs, that is, the first pulse signal should be eliminated. When the piezoelectric sensor is under pressure to work normally, the waveform width of the first pulse signal is relatively large. Likewise, the sustain time of the first pulse signal needs to be compared with the threshold time, and if it is greater than the threshold time, it is considered not to be the strike burr. Since the above-mentioned time comparison process has consumed time of the "threshold time" size, the rising edge of the processed waveform is delayed by a "threshold time" size compared with the original waveform, so that the timing of the force-withdrawal reset is not affected, and when the falling edge of the original waveform indicates the moment of force-withdrawal, the processed waveform must also immediately generate the falling edge, so that the timing of the force-withdrawal reset is not delayed.

The signal processing method provided by the embodiment can be operated in a signal processing circuit, and the signal processing circuit is connected with the piezoelectric sensor. On the one hand, the signal processing circuit eliminates the burr signal without affecting the force-withdrawal reset by executing the above steps S401 to S403.

In one embodiment, the method further comprises: the piezoelectric sensor is reset in response to a level reversal of the second pulse signal. Since the second pulse signal is flipped following the level flip of the first pulse signal, the level flip of the first pulse signal is indicative of the occurrence of a force withdrawal event. It has been mentioned above that the cancellation of the bounce voltage is immediately followed by a force-withdrawal event, and therefore, in order not to delay the moment of force withdrawal, the piezoelectric sensor is reset immediately after the second pulse signal has been level-inverted, so as to cancel the bounce voltage.

In one embodiment, a signal processing circuit is provided. Fig. 7 is a schematic diagram of the structure of the signal processing circuit of the present embodiment, and as shown in fig. 7, the signal processing circuit 1 includes: the device comprises a comparison unit 11 and a logic module 12, wherein the comparison unit 11 is connected with the logic module 12. The comparing unit 11 is configured to detect an output voltage of the piezoelectric sensor and generate a first pulse signal. Specifically, the comparing unit 11 is configured to compare the output voltage of the piezoelectric sensor with a threshold voltage, and generate a first pulse signal if the output voltage of the piezoelectric sensor is not less than the threshold voltage; wherein the threshold voltage is used to characterize the voltage at which the piezoelectric sensor is able to detect a pressure event. The logic module 12 is configured to perform the signal processing method of any of the above embodiments.

In this embodiment, the logic module 12 is capable of performing short pulse cancellation logic. Optionally, the logic module 12 is also capable of executing force-withdrawal reset logic.

The signal processing circuit provided in this embodiment, corresponding to the signal processing method provided above, detects the output voltage of the piezoelectric sensor in real time, generates the first pulse signal when the output voltage of the piezoelectric sensor is greater than the threshold voltage, and introduces the threshold time to determine whether the first pulse signal is a glitch signal or a pressure signal. If the signal is a glitch, the signal is masked. If the pressure signal is, the output is made. Since this discrimination process itself consumes a threshold time, there is a delay between the output of the second pulse signal and the input of the first pulse signal, which affects another action: the force is removed to reset to eliminate the rebound voltage. Therefore, after the second pulse signal is output, when the first pulse signal is subjected to level inversion, the second pulse signal is immediately caused to be subjected to level inversion, and the force-withdrawal reset is not affected. Finally, the effect of eliminating burr signals under the condition of not influencing the force-removing reset is realized. Reference is made to the above for specific principles and effects of the signal processing method, and details thereof are not repeated herein.

Optionally, the signal processing circuit 1 further comprises a first pin 13, a second pin 14, and a third pin 15. The first pin 13 is used for being connected with a voltage output pin Vout of the piezoelectric sensor, the second pin 14 is used for being connected with a reference voltage input pin Vref of the piezoelectric sensor, the third pin 15 is used as a signal output end of the whole signal processing circuit, and the meaning represented by the output signal is determined by application requirements.

Alternatively, the signal processing circuit 1 may also be provided with an amplifying unit 16 and a voltage generating module 17. An amplifying unit 16 is connected between the first pin 14 and the comparing unit 11 for amplifying the output voltage of the piezoelectric sensor and improving the driving capability. The amplifying unit 16 may be implemented with a buffer amplifier, a single-ended amplifier, a differential amplifier, or a programmable gain amplifier. The voltage generating module 17 is connected to the second pin 14 and is responsible for providing a dc bias to the piezoelectric sensor. The voltage generating module 17 can be selected and removed according to the application requirement, and at this time, the reference voltage input pin Vref of the piezoelectric sensor can be grounded according to the application requirement.

Optionally, the signal processing circuit 1 further includes a reset switch K connected to the logic module 12, and capable of resetting/releasing the piezoelectric sensor by switching the switch state in response to a reset signal of the logic module 12. In this embodiment, the piezoelectric sensor may be reset in response to the level inversion of the second pulse signal. When the force removing event occurs, the reset switch K is closed, the induced charges of the piezoelectric sensor are discharged, and reset is completed, so that rebound voltage is eliminated.

In one embodiment, FIG. 8 presents a schematic view of the internal structure of a logic module. As shown in fig. 8, the logic module 12 includes: a frequency dividing unit 121, an or gate 122, a first inverter 123, and a first flip-flop 124. The clock input end CK of the frequency dividing unit 121 is connected with a clock source, the reset end of the frequency dividing unit 121 is connected with a comparison unit, and the output end of the frequency dividing unit 121 is connected with the clock input end CK of the first trigger 124; the output of the first inverter 123 is connected to a first input of the or gate 122; a second input terminal of the or gate 122 is connected to the comparing unit, and an output terminal of the or gate 122 is connected to the reset terminal Rst of the first flip-flop 124. The frequency dividing unit 121 is configured to output a frequency-divided signal in response to the first pulse signal, and perform level inversion on the output frequency-divided signal when the cancel reset time reaches the threshold time. The first flip-flop 124 is configured to output the second pulse signal in response to a level inversion of the frequency-divided signal.

Optionally, the logic module further comprises: a delay unit 125; an input terminal of the delay unit 125 is connected to the comparison unit 11, and an output terminal of the delay unit 125 is connected to an input terminal of the first inverter 123.

Optionally, the logic module further comprises: a second inverter 126; an input terminal of the second inverter 126 is connected to an output terminal of the frequency dividing unit 121, and an output terminal of the second inverter 126 is connected to the clock input terminal CK of the first flip-flop 124.

Optionally, the logic module further comprises: the filter capacitor C is disposed between the second inverter 126 and the clock input CK of the first flip-flop 124. The filter capacitor is used for filtering the interference signal and preventing the first trigger 124 from being triggered by mistake.

In one embodiment, fig. 9 shows a schematic diagram of the internal structure of the frequency dividing unit 121. As shown in fig. 9, the frequency dividing unit 121 includes: a plurality of second flip-flops 127; the clock input terminal CK of the first stage second flip-flop 127 is connected to a clock source, the complement output terminal Q ' of the last stage second flip-flop 127 is connected to the first flip-flop 124, the reset terminal Rst of each stage second flip-flop 127 is connected to the comparing unit, the data input terminal D of each stage second flip-flop 127 is connected to the complement output terminal Q ', and the complement output terminal Q ' of the previous stage second flip-flop 127 is connected to the clock input terminal CK of the next stage second flip-flop 127.

The first flip-flop 124 or the second flip-flop 127 shown above may employ a D flip-flop. The D flip-flop illustrated in the figures is an alternative, and in some of these embodiments may be derived from other types of flip-flop and logic gate combinations. For example, referring to fig. 10, the RS flip-flop or JK flip-flop can be changed to a "D flip-flop" in combination with an inverter.

The operation principle of the above-described signal processing circuit will be described below based on two types of pulse signal cases.

Case one: the sustain time of the first pulse signal does not exceed the threshold time. Fig. 11 shows an operation schematic diagram of the above-described signal processing circuit. As shown in fig. 11, the square wave of the first pulse signal is narrower, less than the set threshold time, to represent the situation where the piezoelectric sensor encounters an impact. The reset end Rst of the frequency dividing unit 121 is connected with the output of the comparing unit 11, and when the piezoelectric sensor is not impacted in the initial state, the reset end rst=0 of the frequency dividing unit 121, and the frequency dividing unit 121 is in a continuous reset state. Under the design of fig. 9, the frequency dividing unit 121 in the reset state continuously outputs a high level; when the rising edge occurs in the input, the reset terminal rst=1 of the frequency dividing unit 121, the frequency dividing unit 121 is reset, and the frequency dividing unit 121 starts to operate. The frequency dividing unit 121 should output the falling edge after the threshold time, but since the falling edge of the first pulse signal occurs earlier, the frequency dividing unit 121 has not yet output the falling edge, the reset terminal Rst of the frequency dividing unit 121 is set to 0 again, and the frequency dividing unit 121 enters the continuous reset state, so the output of the frequency dividing unit 121 always maintains the high level. Thus, after passing through the second inverter 126, the clock input CK of the first flip-flop 124 is always low, i.e. the first flip-flop 124 is always not triggered. In addition, the reset terminal Rst of the first flip-flop 124 will be reset by a short negative pulse generated by the delay unit 125, the first inverter 123 and the or gate 122 at the time of the falling edge of the input square wave, and since the first flip-flop 124 is not always triggered, its output is always low regardless of whether the first flip-flop 124 is reset or not.

In summary, when the sustain time of the first pulse signal does not exceed the threshold time, the output of the first flip-flop 124, i.e., the output of the signal processing circuit, is always at a low level, i.e., the impact of the glitch is eliminated.

And a second case: the sustain time of the first pulse signal is greater than the threshold time. Fig. 12 shows an operation schematic diagram of the above-described signal processing circuit. As shown in fig. 12, the square wave of the first pulse signal is wider and longer than the set threshold time to represent the situation that the piezoelectric sensor is normally under pressure. The reset end Rst of the frequency dividing unit 121 is connected with the output of the comparing unit 11, and when the piezoelectric sensor is not impacted in the initial state, the reset end rst=0 of the frequency dividing unit 121, and the frequency dividing unit 121 is in a continuous reset state. Under the design of fig. 9, the frequency dividing unit 121 in the reset state continuously outputs a high level; when the rising edge occurs in the input, the reset terminal rst=1 of the frequency dividing unit 121, the frequency dividing unit 121 is reset, and the frequency dividing unit 121 starts to operate. Since the sustain time of the first pulse signal is longer than the threshold time, the frequency dividing unit 121 outputs the falling edge after the threshold time. After the falling edge output by the frequency dividing unit 121 passes through the second inverter 126, the falling edge is input to the clock input end CK of the first flip-flop 124, which triggers the first flip-flop 124 to pull high the output until the moment when the falling edge occurs in the input square wave, the reset end rst=0 of the frequency dividing unit 121, and the frequency dividing unit 121 is continuously reset again, and the output is pulled high. Meanwhile, the reset terminal Rst of the first flip-flop 124 will be reset by a short negative pulse generated by the delay unit 125, the first inverter 123 and the or gate 122 at the falling edge time of the input square wave, and the output of the first flip-flop 124 is pulled down.

In summary, when the hold time of the input square wave is greater than the threshold time, the output of the first flip-flop 124, i.e., the output of the signal processing circuit, is pulled up after the rising edge of the input square wave by a threshold time, and the high level is pulled down again until the falling edge of the input square wave. Therefore, the falling edge of the output of the signal processing circuit immediately follows the falling edge of the input, namely immediately follows the force removing process, so the impact burr eliminating circuit does not influence the moment of force removing reset.

It should be noted that the rising edge, the falling edge, the logic 0, the logic 1, etc. of the design are not fixed, and may be freely determined according to the design habit of the designer. In some embodiments, the CK terminal of the D flip-flop may be defined as a falling edge trigger, and if so defined, the second inverter 126 is not required, and the falling edge of the comparing unit 11 is directly connected to the clock input CK of the D flip-flop. For another example, in some embodiments, it may be defined that the reset terminal Rst of the D flip-flop is reset by logic 0, and then the frequency dividing unit 121 must output a logic 0 after the count reaches the preset value, or the output of the frequency dividing unit 121 is connected to an inverter to convert the count positive logic output into the count negative logic output.

The signal processing circuit provided by the embodiment combines the design methods of the synchronous circuit and the asynchronous circuit, and can eliminate the collision burrs with the time level width of tens of ms with only little hardware area cost and power consumption cost.

In one embodiment, a piezoelectric sensing system is provided, and may include a piezoelectric sensor and a signal processing circuit of any of the above embodiments, with reference to fig. 7, the piezoelectric sensor being coupled to the signal processing circuit. The piezoelectric sensor converts the physical quantity into an electrical signal, and the processing of the electrical signal can be accomplished by a signal processing circuit. The signal processing circuit can eliminate burr signals under the condition of not influencing force-withdrawal reset, so that the reliability of the piezoelectric induction system is improved. The piezoelectric sensing system can be widely applied to various fields, including but not limited to: industrial automation, piezoelectric sensors can be used to measure the execution dynamics of the robot terminal actuators to ensure that they operate accurately; the medical equipment, the piezoelectric sensor can be used for measuring physiological parameters such as blood pressure, respiratory rate, heartbeat rate and the like; the piezoelectric sensor can be used for measuring the weight and pressure distribution of the vehicle in the automobile industry, providing data support for the design of the vehicle and monitoring the systems such as an air bag, a brake and the like; air quality detection, piezoelectric sensors can be used to measure pressure and humidity in the air, thereby helping to detect harmful gases in the air; the piezoelectric sensor can be used for monitoring the structural safety and stability of a building and measuring the vibration conditions of structures such as bridges, tunnels and the like; consumer electronics, such as electronic cigarettes, piezoelectric sensors may be used to detect a smoking or blowing action, triggering a function switch of the electronic cigarette.

In one embodiment, an electronic cigarette is provided that includes a body configured with a piezoelectric sensor, the body further configured with the signal processing circuit described above, or integrated with a chip including the signal processing circuit described above, or configured with the piezoelectric sensing system described above. Optionally, the main body further comprises a PCB motherboard, and the piezoelectric sensor is disposed on the PCB motherboard.

In the description of the present specification, reference to the term "some embodiments," "other embodiments," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.

The above examples merely represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the present application. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of the application should be assessed as that of the appended claims.

Claims (10)

1. A signal processing method, comprising:

In response to the first pulse signal, initiating a timer;

If the first pulse signal is input under the condition that the timing does not exceed the threshold time, shielding the first pulse signal;

If the first pulse signal continues to be input under the condition that the timing exceeds the threshold time, outputting a second pulse signal when the timing reaches the threshold time, and turning over the level of the second pulse signal in response to the level turning over of the first pulse signal;

The first pulse signal is obtained by detecting the output voltage of the piezoelectric sensor; the threshold time is not less than the maintenance time of a burr signal generated by the piezoelectric sensor due to impact; the level inversion of the second pulse signal is used for indicating the reset of the piezoelectric sensor.

2. The signal processing method according to claim 1, wherein the first pulse signal is not less than a threshold voltage; wherein the threshold voltage is used to characterize a voltage at which the piezoelectric sensor is able to detect a pressure event.

3. The signal processing method according to claim 1, characterized in that the method further comprises: the piezoelectric sensor is reset in response to a level reversal of the second pulse signal.

4. A signal processing circuit, comprising: the device comprises a comparison unit and a logic module, wherein the comparison unit is connected with the logic module; wherein,

The comparing unit is used for comparing the output voltage of the piezoelectric sensor with a threshold voltage and generating a first pulse signal under the condition that the output voltage of the piezoelectric sensor is not smaller than the threshold voltage; wherein the threshold voltage is used to characterize a voltage at which the piezoelectric sensor is able to detect a pressure event;

The logic module is configured to perform the signal processing method of any one of claims 1 to 3.

5. The signal processing circuit of claim 4, wherein the logic module comprises: the frequency dividing unit, the OR gate, the inverter and the first trigger; the clock input end of the frequency dividing unit is connected with a clock source, the reset end of the frequency dividing unit is connected with the comparing unit, and the output end of the frequency dividing unit is connected with the clock input end of the first trigger; the output end of the inverter is connected with the first input end of the OR gate; the second input end of the OR gate is connected with the comparison unit, and the output end of the OR gate is connected with the reset end of the first trigger; wherein,

The frequency dividing unit is used for responding to the first pulse signal, outputting a frequency dividing signal and carrying out level inversion on the output frequency dividing signal when the cancel reset time reaches the threshold time;

the first trigger is used for responding to the level inversion of the frequency division signal and outputting the second pulse signal.

6. The signal processing circuit of claim 5, wherein the logic module further comprises: a delay unit; the input end of the delay unit is connected with the comparison unit, and the output end of the delay unit is connected with the input end of the inverter.

7. The signal processing circuit of claim 5, wherein the frequency dividing unit comprises: a plurality of second flip-flops; the clock input end of the first-stage second trigger is connected with the clock source, the complement output end of the last-stage second trigger is connected with the first trigger, the reset end of each stage second trigger is connected with the comparison unit, the data input end of each stage second trigger is connected with the complement output end, and the complement output end of the previous-stage second trigger is connected with the clock input end of the next-stage second trigger.

8. The signal processing circuit of claim 4, further comprising: and the reset switch is connected with the logic module and can respond to a reset signal of the logic module to reset/release the piezoelectric sensor through switching the state of the switch.

9. A piezoelectric sensing system, comprising: a piezoelectric sensor and the signal processing circuit of any one of claims 4 to 8, the piezoelectric sensor being connected to the signal processing circuit.

10. An electronic cigarette, comprising: a main body on which a piezoelectric sensor and the signal processing circuit of any one of claims 4 to 8 are provided, the piezoelectric sensor being connected to the signal processing circuit.