CN118074724A

CN118074724A - Shifting digital-to-analog conversion device

Info

Publication number: CN118074724A
Application number: CN202410465843.2A
Authority: CN
Inventors: 魏源; 王斌; 赵振宇; 王晶峰
Original assignee: Shenzhen Zhongke Tianying Technology Co ltd
Current assignee: Shenzhen Zhongke Tianying Technology Co ltd
Priority date: 2024-04-18
Filing date: 2024-04-18
Publication date: 2024-05-24
Anticipated expiration: 2044-04-18
Also published as: CN118074724B

Abstract

The invention discloses a shift digital-to-analog conversion device, belongs to the technical field of digital-to-analog conversion, and can solve the problems of large data writing quantity and high synchronization difficulty when the existing digital-to-analog converter array writes data. The device comprises: the digital-to-analog conversion units are used for converting digital quantity into analog quantity; the shift output unit is provided with a plurality of output bits, and each output bit is stored with a digital quantity; the shift output unit is used for performing cyclic shift operation on the digital quantity on all output bits of the shift output unit once per clock period, and providing the digital quantity before initial cycle and the digital quantity after each cyclic shift to each digital-to-analog conversion unit. The invention is used for digital-to-analog conversion.

Description

Shifting digital-to-analog conversion device

Technical Field

The invention relates to a shift digital-to-analog conversion device, and belongs to the technical field of digital-to-analog conversion.

Background

Digital-to-analog converters (also called D/a converters, DACs for short) can convert digital quantities in a computer into analog quantities, and their inputs are digital signals and their outputs are analog signals. The different DAC input bits differ, with each input bit corresponding to an input register. When the DAC works independently, the upper controller writes data into each input register. However, when the plurality of DACs form an array and the output of the plurality of DACs has a certain rule, for example, when the output of the plurality of DACs is simply shifted, in the prior art, data needs to be independently written into each DAC by the upper controller in each clock period, and at this time, a large amount of repeated writing data exists, so that the problem of large writing data amount and high synchronization difficulty of the plurality of DACs is caused.

Disclosure of Invention

The invention provides a shift digital-to-analog conversion device which can solve the problems of large data writing quantity and high synchronization difficulty when the existing digital-to-analog converter array writes data.

The invention provides a shift digital-to-analog conversion device, comprising:

The digital-to-analog conversion units are used for converting digital quantity into analog quantity;

the shift output unit is provided with a plurality of output bits, and each output bit is stored with a digital quantity;

The shift output unit is used for performing cyclic shift operation on the digital quantity on all output bits of the shift output unit once per clock period, and providing the digital quantity before initial cycle and the digital quantity after each cyclic shift to each digital-to-analog conversion unit.

Optionally, the number of the digital-to-analog conversion units is M, and each digital-to-analog conversion unit has N input bits; and M and N are both greater than or equal to 2.

Optionally, the number of the shift output units is N, and each shift output unit has M output bits; each shift output unit is used for providing digital quantity for one input bit in each digital-to-analog conversion unit;

Each shift output unit is used for performing a cyclic right shift operation of one bit on each clock cycle on the digital quantity on all output bits of the shift output unit.

Optionally, the shift output unit has m×n output bits;

the shift output unit is used for performing a cyclic right shift operation of N bits on each clock cycle on the digital quantity on all output bits.

Optionally, the plurality of digital-to-analog conversion units are arranged in an array.

Optionally, the digital-to-analog conversion unit is a digital-to-analog converter.

Optionally, the shift output unit is a shift register.

The invention has the beneficial effects that:

According to the shift digital-to-analog conversion device provided by the invention, different input amounts are provided for a plurality of digital-to-analog conversion units on each clock period by utilizing the cyclic shift function of the shift output unit, so that a large amount of repeated writing data is avoided, and the problems of large writing data amount and high synchronization difficulty in the writing of the data of the existing digital-to-analog conversion array are solved.

Drawings

FIG. 1 is a schematic diagram of a DAC array cycle output provided by an embodiment of the present invention;

Fig. 2 is a schematic structural diagram of a shift digital-to-analog conversion device according to an embodiment of the present invention.

Detailed Description

The present invention is described in detail below with reference to examples, but the present invention is not limited to these examples.

An embodiment of the present invention provides a shift digital-to-analog conversion apparatus, as shown in fig. 1 and fig. 2, including:

And the digital-to-analog conversion units are used for converting digital quantity into analog quantity.

Specifically, the number of the digital-to-analog conversion units is M, and each digital-to-analog conversion unit is provided with N input bits; m and N are each greater than or equal to 2. In practical applications, the digital-to-analog conversion unit may be a digital-to-analog converter (DAC).

In the embodiment of the invention, a plurality of digital-to-analog conversion units are arranged in an array.

DAC arrays with shift function are commonly used in cases where output data is frequently multiplexed. For example, a three-bit DAC array is used, and the shift function refers to that the output of one DAC in the period is the output of the adjacent DAC in the previous period, and the DACs at the edge are cyclically shifted. Referring specifically to fig. 1, the DAC array includes DAC1, DAC2, and DAC3, and the output of the DAC array in the first period is A1, A2, and A3, respectively; in the second period, the output cycle of the DAC array is shifted right, and the outputs of the DAC array in the second period are A3, A1 and A2 respectively; on the third period, the output of the DAC array is again cycled right on the basis of the output of the second period, and the outputs of the DAC array on the third period are A2, A3, and A1, respectively.

The DACs have the same output, meaning that their inputs are also the same, i.e. all input bits of a certain DAC in the current period are the same as the corresponding input bits of the adjacent DACs in the previous period. In other words, the adjacent DACs correspond to the input bits as the output, shifted once per cycle.

In order to realize shift input, the invention designs a shift output unit.

Specifically, the shift output unit is provided with a plurality of output bits, and each output bit is stored with a digital quantity;

In the embodiment of the invention, the number of the shift output units is N, and each shift output unit is provided with M output bits; each shift output unit is used for providing digital quantity for one input bit in each digital-to-analog conversion unit; each shift output unit is used for performing a cyclic right shift operation of one bit on each clock cycle on the digital quantity on all output bits of the shift output unit.

In practical applications, the shift output unit may be a shift register.

The shift register may concatenate the same input bits of each DAC, with the output of the shift register being the serial input of data and driven using the same clock.

The structure of the shift digital-to-analog conversion device of the present invention is shown in fig. 2. Assume that three DACs are provided, each DAC has 2-bit input, and the three DACs are named DAC1, DAC2 and DAC3 respectively, and the input bits of all DACs are I11-I32.I represents the Input (Input), the first digit being the DAC number and the second digit being the Input bit of the DAC. Other cases, such as DAC strings of different lengths, different number of input bits, can be analogized with reference to the example above. In fig. 2, there are two shift registers, each having a 3-bit output, the box in which Q, D, CK is located representing one "bit" of the shift register, where Q represents the output, D represents the input, CK represents the clock signal; the 3 output bits of the shift register on the right side respectively deliver digital quantities to the first input bits of the 3 DACs; the 3 output bits of the shift register on the left side respectively deliver digital quantities to the second input bits of the 3 DACs; the control signal a may control the cyclic shift of the digital quantity on the output bits of the shift register once per clock cycle, thus achieving a cyclic shift of the input of the DAC array once per clock cycle.

The main function of the device is that adjacent digital-to-analog converters can sequentially output the same analog signals, which are similar to analog shift registers.

In another embodiment of the present invention, the shift output unit has m×n output bits;

Because the number of the digital-to-analog conversion units is M, each digital-to-analog conversion unit is provided with N input bits, the operation of circularly shifting the digital-to-the-right by N bits once is carried out on each clock period, so that the input of the left digital-to-analog conversion unit in the digital-to-analog conversion array in the current period can be changed into the input of the adjacent right digital-to-analog conversion unit in the next period. This achieves a cyclic shift input of the digital-to-analog conversion array.

While the application has been described in terms of preferred embodiments, it will be understood by those skilled in the art that various changes and modifications can be made without departing from the scope of the application, and it is intended that the application is not limited to the specific embodiments disclosed.

Claims

1. A shift digital-to-analog conversion apparatus, said apparatus comprising:

2. The apparatus of claim 1, wherein the digital to analog conversion units are M, each digital to analog conversion unit having N input bits; and M and N are both greater than or equal to 2.

3. The apparatus of claim 2, wherein the shift output units are N, each shift output unit having M output bits; each shift output unit is used for providing digital quantity for one input bit in each digital-to-analog conversion unit;

4. The apparatus of claim 2, wherein the shift output unit has M x N output bits;

5. The apparatus of claim 1, wherein the plurality of digital to analog conversion units are arranged in an array.

6. The apparatus of claim 1, wherein the digital-to-analog conversion unit is a digital-to-analog converter.

7. The apparatus of claim 1, wherein the shift output unit is a shift register.