CN118074714A - Nonlinear compensation of sampling capacitance of successive approximation analog-to-digital converter - Google Patents

Abstract

The application relates to the technical field of integrated circuits and discloses a circuit and a method for nonlinear compensation of a sampling capacitor of a successive approximation analog-to-digital converter. The circuit comprises: the resistor voltage division signal generator is used for generating a voltage test signal; a first gate for gating the voltage test signal; the second gating device is used for gating an external input signal or a voltage test signal of the chip; one end of each capacitor is connected with an external input signal or voltage test signal of the chip and the first or second reference voltage respectively; a comparator having an input connected to the other end of each capacitor in the array of capacitors; successive approximation logic outputs a digital signal to the capacitor array according to the comparison result; the compensation logic is used for determining a normalization interval and a compensation value where the digital signal is located; and the correction digital-to-analog converter is used for converting the compensation value into an analog signal and outputting the analog signal to the comparator. The nonlinear compensation of the application only needs simple digital operation and a small amount of analog circuits, and can reduce the power consumption and the cost.

Description

Nonlinear compensation of sampling capacitance of successive approximation analog-to-digital converter

Technical Field

The application relates to the technical field of integrated circuits, in particular to a circuit and a method for nonlinear compensation of a sampling capacitor of a successive approximation analog-to-digital converter.

Background

Most Successive Approximation (SAR) analog-to-digital converters (Analog to Digital Converter, ADC for short) use switched capacitor circuit sampling. The capacitors provided by low cost integrated circuit manufacturing processes have voltage coefficients and the integrated nonlinearity (Integral Nonlinearity, INL) of the analog-to-digital converter implemented with such capacitors becomes large, especially when the input signal amplitude becomes high. In order to reduce INL errors of analog-to-digital conversion, correction is required.

The nonlinearity of the sampling capacitor is usually contained in the nonlinearity error caused by the capacitor mismatch, the problem of the capacitor mismatch is focused on by the traditional SAR ADC circuit, the nonlinearity correction of the sampling capacitor during the large swing input is less focused, and the nonlinearity of the sampling capacitor is less corrected independently. However, when the input signal amplitude is high enough, it is necessary to correct the non-linearity of the capacitor before correcting the non-linearity error caused by the mismatch of the capacitor. The method for correcting the nonlinearity of the capacitor is low in cost, low in power consumption and high in efficiency.

Disclosure of Invention

The application aims to provide a circuit and a method for compensating nonlinearity of a sampling capacitor of a successive approximation analog-to-digital converter, which are used for independently correcting nonlinearity of the capacitor, so that INL index which can be realized only by using a high-linearity capacitor under the same condition can be reached or approached, and the production cost of a chip is reduced.

The application discloses a nonlinear compensation circuit for sampling capacitance of a successive approximation analog-to-digital converter, which comprises:

a resistor voltage division signal generator for generating a multi-bit voltage test signal;

a first gate connected to the resistor divider signal generator and gating one of the multi-bit voltage test signals;

the second gating device is used for gating one of an external input signal of the chip and a voltage test signal output by the first gating device;

one end of each capacitor in the capacitor array is respectively connected with one of the external input signal of the chip or the voltage test signal output by the first gating device and one of the first reference voltage or the second reference voltage, and the other end of each capacitor in the capacitor array is connected to a fixed potential through a switch;

A comparator, a first input of which is connected to the other end of each capacitor in the capacitor array, and a second input of which is connected to the fixed potential;

successive approximation logic connected to the output of the comparator and outputting a digital signal to the capacitor array according to the comparison result of the comparator;

The compensation logic is connected to the successive approximation logic and is used for determining a normalization interval in which the digital signal is located according to the digital signal and inquiring a compensation value corresponding to the normalization interval from a compensation lookup table; and

And the correction digital-to-analog converter is used for converting the compensation value into an analog signal and outputting the analog signal to the first input end of the comparator.

In a preferred embodiment, the method further comprises:

A pseudorandom number generator coupled to the compensation logic and operable to generate a pseudorandom sequence; the compensation logic determines an interval correction value according to the pseudo-random sequence and a preset variable, determines a normalization interval in which the digital signal is located according to the interval correction value and the digital signal, and queries a compensation value corresponding to the normalization interval from a compensation lookup table.

In a preferred embodiment, when the current value in the pseudo-random sequence is 1, the interval correction value is +Δ or- Δ, and when the current value in the pseudo-random sequence is 0, the interval correction value is- Δ or +Δ, where Δ is the preset variable, and the compensation logic adds the normalized interval in which the digital signal determined according to the digital signal is located to the interval correction value to obtain a corrected normalized interval.

In a preferred embodiment, the resistor divider signal generator includes m resistors connected in series to a third reference voltage and a ground terminal, and outputs m voltage test signals to the first gate.

In a preferred embodiment, the first gate is a m-th gate.

In a preferred embodiment, m is 4, 8, 16 or 32.

In a preferred embodiment, the second gate is a half gate.

In a preferred embodiment, the capacitor array determines, from the digital signal, that one end of each capacitor is connected to the first reference voltage or the second reference voltage.

The application discloses a nonlinear compensation method for sampling capacitance of a successive approximation analog-to-digital converter, which is applied to the circuit for nonlinear compensation of the sampling capacitance of the successive approximation analog-to-digital converter, and comprises the following steps:

The second gate gates one of the voltage test signals output by the first gate;

Under a fourth reference voltage, sequentially outputting a multi-bit voltage test signal to one end of each capacitor of the capacitor array, and acquiring a normalized first digital signal measured value under the fourth reference voltage according to the digital signal output by the successive approximation logic;

Under a fifth reference voltage, sequentially outputting a multi-bit voltage test signal to one end of each capacitor of the capacitor array, and acquiring a normalized second digital signal measured value under the fifth reference voltage according to the digital signal output by the successive approximation logic, wherein the fifth reference voltage is far smaller than the fourth reference voltage; and

The difference between the first digital signal measurement and the second digital signal measurement is stored as the compensation value in a compensation look-up table of the compensation logic.

In a preferred embodiment, the fifth reference voltage is one fourth of the fourth reference voltage.

In the embodiment of the application, the nonlinearity of the capacitor is corrected independently, the INL index which can be realized by using the high-linearity capacitor under the same condition can be reached or approached, and the correction method only needs simple digital operation and a small amount of analog circuits, thereby reducing the power consumption and the cost.

The numerous technical features described in the description of the present application are distributed among the various technical solutions, which can make the description too lengthy if all possible combinations of technical features of the present application (i.e., technical solutions) are to be listed. In order to avoid this problem, the technical features disclosed in the above summary of the application, the technical features disclosed in the following embodiments and examples, and the technical features disclosed in the drawings may be freely combined with each other to constitute various new technical solutions (which should be regarded as having been described in the present specification) unless such a combination of technical features is technically impossible. For example, in one example, feature a+b+c is disclosed, in another example, feature a+b+d+e is disclosed, and features C and D are equivalent technical means that perform the same function, technically only by alternative use, and may not be adopted simultaneously, feature E may be technically combined with feature C, and then the solution of a+b+c+d should not be considered as already described because of technical impossibility, and the solution of a+b+c+e should be considered as already described.

Drawings

FIG. 1 is a schematic diagram of a resistor divider signal generator and a gate in accordance with one embodiment of the application.

Fig. 2 is a schematic diagram of a circuit for nonlinear compensation of sampling capacitance of a successive approximation analog-to-digital converter in accordance with one embodiment of the application.

Fig. 3 is a schematic diagram of total sampling capacitance in one embodiment in accordance with the application.

FIG. 4 is a graph illustrating normalized INL error curves for different reference voltages according to one embodiment of the application.

Fig. 5 is a schematic diagram of INL errors before and after compensating for non-linearities of a sampling capacitance in accordance with one embodiment of the present application.

Fig. 6 is a schematic diagram of a circuit for nonlinear compensation of sampling capacitance of a successive approximation analog-to-digital converter in accordance with another embodiment of the present application.

FIG. 7 is a schematic diagram of INL interval variation after adding random disturbance according to one embodiment of the present application.

Fig. 8 is a flow chart of a method of non-linearity compensation of sampling capacitance of a successive approximation analog to digital converter in accordance with an embodiment of the present application.

Detailed Description

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. It will be understood by those skilled in the art that the claimed application may be practiced without these specific details and with various changes and modifications from the embodiments that follow.

For the purpose of making the objects, technical solutions and advantages of the present application more apparent, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

Partial term interpretation:

The integral nonlinearity (Integral Nonlinearity, INL) is an error value representing the point at which the analog-to-digital converter has the greatest error between the corresponding analog and real values at all points in the digital signal, i.e., the distance at which the output value deviates from linearity by the greatest. The unit is LSB, i.e. least significant bit. INL is the mathematical integral of DNL (DIFFERENTIAL NONLINEARITY, differential non-linearity) error, i.e. an ADC with good INL guarantees good DNL.

A first embodiment of the present application relates to a circuit for nonlinear compensation of sampling capacitance of a successive approximation analog-to-digital converter (SAR ADC), and the compensation circuit described with reference to fig. 1 and 2 includes a resistive divider signal generator (RDAC) 101, a first gate 102, a second gate 103, a capacitor array 104, a comparator 105, successive Approximation (SAR) logic 106, compensation logic 107, and a modified digital-to-analog converter 108. Wherein the resistor divider signal generator 101, the first gate 102 and the second gate 103 are sequentially connected. The second gate 103 is connected to the capacitor array 104. The capacitor array 104 and the modified digital-to-analog converter 108 are connected to the input of a comparator 105, respectively, and the output of the comparator 105 is in turn connected to a successive approximation logic 106 and a compensation logic 107. Successive approximation logic 106 outputs a digital signal to capacitive array 104.

Referring to fig. 1, a resistor divider signal generator 101 is used to generate a multi-bit voltage test signal. The first gate 102 is connected to the resistor divider signal generator 101 and gates one of the multi-bit voltage test signals. In one embodiment, the resistor-divided signal generator 101 includes m resistors R connected in series between the third reference voltage VREF and the ground gnd, and outputs m voltage test signals to the first gate 102. In one embodiment, the first gate 102 is a m-th gate. In one embodiment, m is 4, 8, 16 or 32. It should be understood that in the embodiment of the present application, m may be any positive integer, and the present application is not limited thereto.

The resistor voltage division signal generator 101 divides and outputs m voltage test signals of V1 to VREF, for example, V1, V2, V3, … …, vm-3, vm-2, vm-1, and VREF, to the first gate 102, and voltages between adjacent two resistors R are each different by VREF/m, and voltages of the m voltage test signals are sequentially gated by the first gate 102. For example, taking m=8 as an example, 8 resistors R are connected in series between VREF and ground gnd, and the resistor divider signal generator 101 generates and outputs VREF/8, 2×vref/8, 3×vref/8, … …,7×vref/8, VREF to the first gate 102, respectively. The first gate 102 is a 1/8 gate and outputs VREF/8, 2×vref/8, 3×vref/8, … …,7×vref/8, VREF to the second gate 103 in sequence.

The second gate 103 is for gating one of the chip external input signal Vin and the voltage test signal from the output of the first gate 101, and outputting a signal Ain. In one embodiment, the second gate 102 is a one-half gate. It should be appreciated that the second gate 103 is a selection for implementing the operational mode and the test mode. When the second gate 103 gates the voltage test signal output by the first gate 101 to the successive approximation logic 106, a test mode is entered at this time. In the test mode, measurement of the sample capacitance nonlinearity is implemented and the measured compensation value is stored in a look-up table (LUT) of the compensation logic 107. When the second gate 103 gates the chip external input signal Vin, the operation mode is entered at this time, the SAR ADC performs analog-to-digital conversion on the chip external input signal Vin, and the compensation logic 107 may implement nonlinear compensation of the sampling capacitance on the result of the analog-to-digital conversion.

Referring to fig. 2, the successive approximation analog-to-digital converter is an n-bit ADC and the capacitor array 104 includes n sampling capacitors. The capacitance values of the n sampling capacitors from low to high are C, 2C and 2 ²C、……、2^n-1 C in sequence. In one embodiment, n is 4, 8, 16 or 32. It should be understood that in the embodiment of the present application, n may be any positive integer, and the present application is not limited thereto.

Specifically, one end of each capacitor in the capacitor array 104 is respectively connected to the output Ain signal of the second gate 103 (i.e. the chip external input signal Vin or the voltage test signal output by the first gate 101). One end of each capacitor in the capacitor array 104 is further connected to one of the first reference voltage Refp or the second reference voltage Refn, for example, to confirm whether one end of each capacitor is connected to the first reference voltage Refp or the second reference voltage Refn according to a digital signal obtained by SAR logic. The other end of each capacitor in the capacitor array 104 is connected to a fixed potential (e.g., ground gnd) through a switch sp. A first input of the comparator 105 is connected to the other end of each capacitor in the capacitor array 104, and a second input of the comparator 105 is connected to a fixed potential (e.g., ground gnd). Successive approximation logic 106 is coupled to the output of comparator 105 and outputs digital signals D (n-1), D (n-2), … …, D (0) to capacitive array 104 based on the comparison by comparator 105. The capacitor array 104 determines whether one end of each capacitor is connected to the first reference voltage Refp or the second reference voltage Refn based on the digital signals D (n-1), D (n-2), … …, D (0).

The sampling capacitance is typically a 2-ary based capacitive array. The capacitance of the lowest bit (LSB) weight is 2≡0×C, the capacitance of the highest bit (MSB) weight is 2≡n-1, n capacitors in total, and the process of realizing n-bit ADC conversion coding is as follows:

1. The input signal Ain is connected to one port of all the sampling capacitors through a switch sin, and the other port of all the capacitors is connected to a switch sp. The switch sp is connected to a fixed potential. With reasonable timing control, the input signal Ain can be sampled onto a 2-ary based capacitive array.

2. In addition to the input signal Ain, there is a fixed reference voltage Refp/Refn connected to the sampling capacitor. The choice of whether Refp or Refn to connect to the capacitor after the sampling is completed is determined by the values of the codes D (n-1), D (n-2), … …, D (0) output by the successive approximation logic 106. After sampling is completed, the successive approximation logic 106 connects Refp the most significant bit of the sampling capacitance to the remaining connections Refn. Namely, D (n-1) =1, D (n-2), … …, and D (0) =0.

3. Through the operation of step 2, the signal at the input end of the comparator 105 is changed from Ain to Ain-1/2 (Refp-Refn), and then the comparator 105 compares the signal with the fixed potential, namely, judges whether Ain-1/2 (Refp-Refn) >0 is true or not. D (n-1) =1 if true, otherwise D (n-1) =0. Successive approximation logic 106, upon determining the value of D (n-1), sets D (n-2) to 1, with the remaining D (i) continuing to remain at 0, i.e., D (n-3), … …, D (0) =0.

4. The comparator 105 proceeds to determine whether the new input signal Ain-1/2 x (Refp-Refn) D (n-1) -1/4 x (Refp-Refn) is greater than or less than 0, and sets the final value of D (n-2) according to the determination result.

5. The process of operations 3 and 4 is repeated until all values of D (n-1), D (n-2), … …, D (0) are determined, i.e., n-bit ADC encoding is achieved.

With continued reference to fig. 2, the compensation logic 107 is further connected to the successive approximation logic 106, and is configured to determine, according to a digital signal obtained by the successive approximation logic 106, a normalized interval (i.e. a value between 0 and 1) in which the digital signal is located, and query a compensation lookup table thereof for a compensation value (or referred to as a correction value) corresponding to the normalized interval, and output the compensation value to a modified digital-to-analog converter (DAC) 108. The correction DAC 108 converts the compensation value into an analog signal and outputs the analog signal to the first input terminal of the comparator 105, thereby realizing nonlinear error compensation of the sampling capacitance.

In the application, a correction DAC and compensation logic are added in the traditional SAR ADC circuit structure. In addition, to generate the input stimulus signal, a set of resistive divider signal generators RDAC and strobe MUX (shown in FIG. 1) are added in test mode. The RDAC and the strobe MUX are used to test for errors caused by capacitive nonlinearities in the test mode. The compensation logic is used for storing data for non-linear correction of the capacitance. The correction DAC is used to convert the correction data into an analog charge for compensation.

The input Ain of the sampling capacitor is disconnected from the chip external connection in test mode, connected to the output of the RDAC and the gating MUX (output of the second gate). The error value of the capacitance nonlinearity is obtained by using RDAC output level test under different VREF conditions. The error value is stored in a compensation look-up table LUT of the compensation logic. The RDAC may be turned off when the test mode is over to save power consumption. During operation of the SAR ADC, the compensation logic determines the approximate range of the signal according to the output code of the SAR logic, and then compensates the nonlinearity of the sampling capacitor according to the predetermined correction value.

In the conventional SAR ADC process, it is assumed that the reference Refp =vref, refn =0, vin is a signal in the range of 0 to Vref, so vin=k×vref,0< k <1. Referring to fig. 3, it can be known from the operating principle of the SAR ADC that, when the conversion is completed, a capacitor with a ratio of about k×cs in the total sampling capacitor Cs is connected Refp, and a capacitor with a ratio of (1-k) ×cs is connected Refn. The capacitance of the capacitor and the voltage V across the capacitor are correlated, which can be expressed as c= (1+v 3) C0, and from this equation, the larger the voltage across the capacitor, the larger the capacitance. Deriving the final ADC coding error e according to the SAR ADC operating principle can be expressed as e=Vref≡3 (k-k≡3) -Vref≡3[ 1-k- (1-k) ≡3], which expression reaches a maximum value at k=0.78. The error e is proportional to the power of Vref and increases sharply as Vref increases.

According to the error principle generated by the nonlinearity of the capacitor, the error caused by the nonlinearity of the capacitor when different input signals are obtained through testing. FIG. 4 shows the INL error curve for different Vref. The INL error due to capacitance nonlinearity is proportional to Vref to the power of 3. Fig. 4 is an example of generating an input stimulus signal. Firstly, different VREF values are set, different test values are generated through resistor voltage division, and different excitation signals are selected to SAR ADC through 1:m MUX so as to test capacitance nonlinear errors under different signal amplitudes.

And 2 times of measurement are carried out when the ADC is used for testing the nonlinearity of the capacitor, a higher Vref is used by the resistor voltage division signal generator during the 1 st time of measurement to obtain a normalized digital signal measured value emax1, and a lower Vref is used during the 2 nd time of measurement to obtain a normalized digital signal measured value emax2. For example, the Vref value used for the 2 nd time is 1/4 of the first time. The 2 calculations of emax1 and emax2 will differ by a factor of 64. The emax2 obtained at time 2 is almost negligible. Therefore, the ADC code of the 2 nd test is close to an ideal value, contains little capacitance nonlinear error and can be used as a reference value. The INL error caused by the non-linearity of the capacitance at the higher Vref can be calculated by subtracting the 2 measurements.

Principle of RDAC partitioning different amplitudes: the non-linear error caused by the capacitance is not a fixed value over the entire signal range, but varies with the amplitude of the signal. The error e is a value that varies with the amplitude of the signal, and is small when the signal is full or 0. Error e reaches a maximum at a signal amplitude close to 0.78 vref. It is therefore necessary to compensate for capacitive non-linearity errors for different signal amplitudes.

Principle of nonlinear compensation: the whole signal amplitude range is divided into a plurality of ranges, different compensation values are set in different ranges, and the compensation value of the current input signal is determined by a table look-up (LUT) mode. The compensation value is converted to an analog signal to be compensated by the DAC and subtracted from the comparator input. Fig. 5 is a schematic diagram of INL errors before and after compensating for non-linearities of the sampling capacitance. The INL error before correction is shown in the solid line part in fig. 5, and the INL curve after divided area correction is shown in the broken line part in fig. 5. It is apparent that the INL maximum in the dashed line is much lower than before correction.

As can be seen from fig. 5, the modified INL curve has some abrupt points. The principle of creating these abrupt points is that different amplitude regions are provided with different correction values, resulting in discontinuous abrupt changes at the boundaries of the amplitude regions. These mutated INLs correspond to the introduction of DNL errors.

To this end, the application introduces random disturbances in the correction, the circuit configuration of which is shown in fig. 6, the compensation circuit comprising a resistive divider signal generator (not shown), a first gate (not shown), a second gate (not shown), a capacitor array 104', a comparator 105', successive approximation logic 106', compensation logic 107', a correction digital-to-analog converter 108 'and a pseudo-random number generator (PRN) 109'. The resistor divider signal generator (not shown), the first gate (not shown), the second gate (not shown), the capacitor array 104', the comparator 105', the successive approximation logic 106' operate in a similar manner to the compensation circuits of fig. 1 and 2, unless otherwise indicated. The pseudo-random number generator 109 'is coupled to the compensation logic 107' and is operable to generate a pseudo-random sequence. The compensation logic 107 'determines an interval correction value according to the pseudo-random sequence and a preset variable, and the compensation logic 107' determines a normalization interval in which the digital signal is located (i.e. updates the normalization interval in which the digital signal is located) according to the interval correction value and the digital signal, and queries a compensation value corresponding to the normalization interval from the compensation lookup table.

In one embodiment, the interval correction value may be +Δ when the current value in the pseudorandom sequence is 1, and- Δ when the current value in the pseudorandom sequence is 0. Wherein delta is a preset variable. The compensation logic 107' adds the normalized section in which the digital signal determined from the digital signal is located to the section correction value to obtain a corrected normalized section. In another embodiment, the interval correction value may be- Δ when the current value in the pseudorandom sequence is 1, and +Δ when the current value in the pseudorandom sequence is 0.

The boundaries of the amplitude regions of the different correction values are thus in random disturbances, and discontinuous abrupt changes occurring at the boundaries are suppressed. The deterioration of DNL due to improvement of INL is reduced. The boundary variation is shown with reference to fig. 7. Fig. 7 (a) shows the boundary of the normalized section to which no random disturbance is added (indicated by a broken line in the figure), fig. 7 (b) shows the change in the boundary of the normalized section when the section correction value is +Δ, and fig. 7 (c) shows the change in the boundary of the normalized section when the section correction value is- Δ.

In one example, for example, the random sequence is 1011000101, which occurs with a1 and 0 rule that is not fixed. The aforementioned non-linear correction of the ADC requires first determining which interval range (e.g., one of 8 ranges) the currently sampled signal is in. Then the table look-up generates the corresponding compensation value according to which interval range the current signal falls within. When the pseudo-random sequence is 1, the boundary of the range is added by a delta, and if 0, the boundary of the range is reduced by a delta. Delta is a value representing the signal range given in advance. The purpose of the above operation is to randomly change the boundary of the corrected section range. For example, the current sample results in a signal having a value of 0.76 in the normalized ADC that falls within the interval of 0.75 to 0.875, and theoretically, a correction value corresponding to the interval of 0.75 to 0.875 should be used. But the current random sequence value is exactly 1 (if the 0 boundary changes to the other direction), resulting in the original interval range becoming 0.75+0.1-0.875+0.1, where 0.1 is a preset variable. It is clear that 0.75 no longer falls within this range and that the corresponding correction values within this range cannot be used. The range of the original 0.625 to 0.75 is 0.625+0.1 to 0.75+0.1 by adding Δ, and therefore the actual correction value should be selected as the correction value corresponding to this range.

The second embodiment of the present application further relates to a method for nonlinear compensation of a sampling capacitor of a successive approximation analog-to-digital converter, which is applied to the circuit for nonlinear compensation of a sampling capacitor of a successive approximation analog-to-digital converter, and the flow of the method is shown in fig. 8, and includes the following steps:

In step 801, the second gate gates one of the voltage test signals output by the first gate.

Step 802, under the fourth reference voltage, sequentially outputting a multi-bit voltage test signal to one end of each capacitor of the capacitor array, and obtaining a normalized first digital signal measurement value emax1 under the fourth reference voltage according to the digital signal output by the successive approximation logic.

Step 803, under a fifth reference voltage, sequentially outputting a multi-bit voltage test signal to one end of each capacitor of the capacitor array, and obtaining a normalized second digital signal measurement value emax2 under the fifth reference voltage according to the digital signal output by the successive approximation logic, wherein the fifth reference voltage is far smaller than the fourth reference voltage. In one embodiment, the fifth reference voltage is one-fourth of the fourth reference voltage.

Step 804, the difference between the first digital signal measurement and the second digital signal measurement is used as a compensation value and stored in a compensation look-up table of the compensation logic.

The RDAC may be turned off when the test mode is over to save power consumption. In the working process of the SAR ADC, the input Ain of the sampling capacitor is connected with the external input signal Vin of the chip, the compensation logic determines the interval range of the signal according to the output code of the SAR logic, and then the nonlinearity of the sampling capacitor is corrected according to the compensation value determined in the test mode.

The first embodiment is a circuit implementation corresponding to the present embodiment, and the technical details in the first embodiment may be applied to the present embodiment, and the technical details in the present embodiment may also be applied to the first embodiment.

It should be noted that in the present patent application, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. In the present patent application, if it is mentioned that an action is performed according to an element, it means that the action is performed at least according to the element, and two cases are included: the act is performed solely on the basis of the element and is performed on the basis of the element and other elements. Multiple, etc. expressions include 2, 2 times, 2, and 2 or more, 2 or more times, 2 or more.

This specification includes combinations of the various embodiments described herein. Separate references to embodiments (e.g., "one embodiment" or "some embodiments" or "preferred embodiments") do not necessarily refer to the same embodiment; however, unless indicated as mutually exclusive or as would be apparent to one of skill in the art, the embodiments are not mutually exclusive. It should be noted that the term "or" is used in this specification in a non-exclusive sense unless the context clearly indicates otherwise or requires otherwise.

All references mentioned in this specification are to be considered as being included in the disclosure of the application in its entirety so as to be applicable as a basis for modification when necessary. Furthermore, it should be understood that the foregoing description is only of the preferred embodiments of the present application and is not intended to limit the scope of the present application. Any modification, equivalent replacement, improvement, or the like, which is within the spirit and principles of one or more embodiments of the present disclosure, is intended to be included within the scope of one or more embodiments of the present disclosure.

In some cases, the actions or steps recited in the claims can be performed in a different order than in the embodiments and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

Claims (10)

1. A circuit for nonlinear compensation of sampling capacitance of a successive approximation analog-to-digital converter, comprising:

a resistor voltage division signal generator for generating a multi-bit voltage test signal;

a first gate connected to the resistor divider signal generator and gating one of the multi-bit voltage test signals;

the second gating device is used for gating one of an external input signal of the chip and a voltage test signal output by the first gating device;

one end of each capacitor in the capacitor array is respectively connected with one of the external input signal of the chip or the voltage test signal output by the first gating device and one of the first reference voltage or the second reference voltage, and the other end of each capacitor in the capacitor array is connected to a fixed potential through a switch;

A comparator, a first input of which is connected to the other end of each capacitor in the capacitor array, and a second input of which is connected to the fixed potential;

successive approximation logic connected to the output of the comparator and outputting a digital signal to the capacitor array according to the comparison result of the comparator;

The compensation logic is connected to the successive approximation logic and is used for determining a normalization interval in which the digital signal is located according to the digital signal and inquiring a compensation value corresponding to the normalization interval from a compensation lookup table; and

And the correction digital-to-analog converter is used for converting the compensation value into an analog signal and outputting the analog signal to the first input end of the comparator.

2. The circuit of claim 1, further comprising:

A pseudorandom number generator coupled to the compensation logic and operable to generate a pseudorandom sequence; the compensation logic determines an interval correction value according to the pseudo-random sequence and a preset variable, determines a normalization interval in which the digital signal is located according to the interval correction value and the digital signal, and queries a compensation value corresponding to the normalization interval from a compensation lookup table.

3. The circuit of claim 2, wherein the interval correction value is +Δ or- Δ when the current value in the pseudo-random sequence is 1, and the interval correction value is- Δ or +Δ when the current value in the pseudo-random sequence is 0, wherein Δ is the preset variable, and wherein the compensation logic adds the normalized interval in which the digital signal determined from the digital signal is located to the interval correction value to obtain a corrected normalized interval.

4. The circuit of claim 1, wherein the resistor divider signal generator includes m resistors connected in series to a third reference voltage and ground, and outputs m voltage test signals to the first gate.

5. The circuit of claim 4, wherein the first gate is a m-th gate.

6. The circuit of claim 4, wherein m is 4, 8, 16 or 32.

7. The circuit of claim 1, wherein the second gate is a one-half gate.

8. The circuit of claim 1, wherein the array of capacitors determines from the digital signal that one end of each capacitor is connected to the first reference voltage or the second reference voltage.

9. A method of non-linearity compensation of a sampling capacitance of a successive approximation analog to digital converter, the method being applied to a circuit of non-linearity compensation of a sampling capacitance of a successive approximation analog to digital converter as claimed in any of claims 1 to 8, the method comprising:

The second gate gates one of the voltage test signals output by the first gate;

Under a fourth reference voltage, sequentially outputting a multi-bit voltage test signal to one end of each capacitor of the capacitor array, and acquiring a normalized first digital signal measured value under the fourth reference voltage according to the digital signal output by the successive approximation logic;

Under a fifth reference voltage, sequentially outputting a multi-bit voltage test signal to one end of each capacitor of the capacitor array, and acquiring a normalized second digital signal measured value under the fifth reference voltage according to the digital signal output by the successive approximation logic, wherein the fifth reference voltage is far smaller than the fourth reference voltage; and

The difference between the first digital signal measurement and the second digital signal measurement is stored as the compensation value in a compensation look-up table of the compensation logic.

10. The method of claim 9, wherein the fifth reference voltage is one-fourth of the fourth reference voltage.