CN118074708A

CN118074708A - Gain calibration of digitally controlled delay line

Info

Publication number: CN118074708A
Application number: CN202311560121.7A
Authority: CN
Inventors: 阿迈德·萨瓦特·穆罕默德·阿博兰尼·艾玛哈; 阿姆勒·塔瑞克·哈米德·阿比德莱兹克·卡许巴; 蒙哈迈德·穆赫辛·阿布杜萨拉姆·阿卜杜拉帝夫; 塔梅尔·穆罕默德·阿里
Original assignee: MediaTek Inc
Current assignee: MediaTek Inc
Priority date: 2022-11-22
Filing date: 2023-11-21
Publication date: 2024-05-24

Abstract

Gain calibration of digitally controlled delay lines is disclosed. A system operating as a Phase Locked Loop (PLL) includes a frequency synthesizer in a feedback path of the PLL and a delay line arranged to receive an output of the frequency synthesizer. The re-timer subsystem is arranged to receive the output of the frequency synthesizer. A Digitally Controlled Delay Line (DCDL) is arranged to receive the output of the retimer. The phase detector is arranged to receive the output of the delay line and the output of the DCDL and to provide an error signal indicative of the difference in phase of the output of the delay line relative to the output of the DCDL. The controller causes closed loop operation of the PLL during a normal mode of operation and open loop operation of the PLL during a calibration mode of operation during which a gain of the DCDL defining a relationship between the control code and the resulting delay is calibrated.

Description

Gain calibration of digitally controlled delay line

Cross Reference to Related Applications

The present application claims priority from U.S. provisional application No.63/384,614 entitled "DIGITAL PHASE-LOCKED LOOP AND RELATED TECHNIQUE FOR DIGITAL-CONTROLLED DELAY LINE GAIN CALIBRATION" filed on day 22 11 of 2022 and U.S. patent application Ser. No. 18/493,378 filed on day 24 of 10 of 2023, the entire contents of which are incorporated herein by reference.

Technical Field

The present invention relates to digitally controlled delay lines (DIGITALLY CONTROLLED DELAY LINE, DCDL), and more particularly to gain calibration of DCDL.

Background

Generally, in electronic devices, and more particularly in digital electronic devices, a clock signal is a voltage or current based electronic logic signal that oscillates between a low state and a high state at a constant frequency. The clock signal is used to synchronize actions in various digital circuits. Sometimes, delays are introduced in the clock signal to correct and compensate for variations in signal propagation time between different signal paths. The delayed clock signal may facilitate improving synchronization of the various signals in the circuit by allowing each signal to stabilize (setle) before being used. In various applications, the delay of DCDL is found to be controllable. For example, DCDL may be used in a retimer that acts as a repeater for a high speed serial link. DCDL may also be used as part of a frequency synthesizer in a Radio Frequency (RF) transmitter or receiver, or more specifically, as part of a phase-locked loop (PLL) based frequency synthesizer.

Disclosure of Invention

In accordance with one or more embodiments, a system operating as a Phase Locked Loop (PLL) includes: a frequency synthesizer in the feedback path of the PLL and a delay line arranged to receive the output of the frequency synthesizer. The re-timer subsystem is arranged to receive the output of the frequency synthesizer. A Digitally Controlled Delay Line (DCDL) is arranged to receive the output of the retimer. The phase detector is arranged to receive the output of the delay line and the output of the DCDL and to provide an error signal indicative of the difference in phase of the output of the delay line relative to the output of the DCDL. The controller is configured to cause closed loop operation of the PLL during a normal mode of operation and open loop operation of the PLL during a calibration mode of operation during which the gain of the DCDL is calibrated. The gain of the DCDL defines the relationship between the control code provided to the DCDL and the resulting delay implemented by the DCDL on the input clock.

According to another embodiment, a method of calibrating a Digitally Controlled Delay Line (DCDL) within a Phase Locked Loop (PLL) includes: closed loop operation is utilized to control the operation of the PLL in a normal operating mode. During the normal operation mode, the DCDL delays the output of the retimer based on the control code provided to the DCDL, and the output of the DCDL is used to obtain the output of the voltage controlled oscillator (voltage controlled oscillator, VCO), the output of the VCO being provided as the output of the PLL and also provided to the feedback path. The method further comprises the steps of: the operation of the PLL is controlled in a calibration mode during which the gain of the DCDL is calibrated, wherein the closed loop operation is suspended. The gain of the DCDL defines the relationship between the control code provided to the DCDL and the resulting delay implemented by the DCDL on the output of the retimer. The output of the VCO during the previous normal operation mode is maintained during the calibration mode.

The foregoing has outlined some of the pertinent features of the disclosed subject matter. These features are merely illustrative.

Drawings

In the drawings, each identical or nearly identical component that is illustrated in various figures is represented by a like numeral. For purposes of clarity, not every component may be labeled in every drawing. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating various aspects of the technology and devices described herein.

FIG. 1A is a block diagram illustrating aspects of a Phase Locked Loop (PLL) of a first step in a calibration process according to one embodiment;

FIG. 1B shows the block diagram of FIG. 1A to illustrate a second step in the calibration process;

fig. 2A is a block diagram of an exemplary PLL in a first mode of operation according to one embodiment;

fig. 2B is a block diagram of the exemplary PLL of fig. 2A in a second mode of operation according to one embodiment; and

Fig. 2C is a block diagram of the exemplary PLL of fig. 2A in a third mode of operation according to one embodiment.

Detailed Description

The present disclosure will now be described in detail with reference to the accompanying drawings. It should be understood that the drawings and the exemplary embodiments are not limited to the details thereof. Modifications may be made without departing from the spirit and scope of the disclosed subject matter.

The use of DCDL may have benefits such as lower power usage, smaller area, improved linearity and resolution compared to other devices such as phase rotators that have been used in applications such as digital Phase Locked Loop (PLL) based frequency synthesizers. However, DCDL can be a source of fractional spurs, known as fractional spurs, which can be challenging to filter out without affecting the desired output. One cause of fractional spurs is the gain error of the DCDL. The gain of the DCDL refers to a relationship between a control code input to the DCDL and a delay output by the DCDL. The control code may be a digital codeword ranging from 0 to full scale values (e.g., 512, 2023). Gain error refers to the change in a known mapping of control codes to delays such that a given control code results in a delay that is different from the expected delay for that code.

The inventors have realized that performing gain calibration of feedback DCDL (FBDCDL) by taking the PLL offline eliminates FBDCDL dependence on PLL state and allows for faster settling times. That is, the PLL state may be frozen for one period and the closed loop operation may be suspended to facilitate the open loop operation and calibration of FBDCDL. This may be repeated every few cycles (e.g., periodically, every 1000 cycles) or on another basis (e.g., based on events). For example, a period may refer to a fixed period of time or a fixed number of clock cycles. According to an embodiment, the calibration of FBDCDL involves setting the delay of the delay line to a reference and then using this reference delay to adjust FBDCDL as needed.

Calibration FBDCDL by itself (rather than an offline copy) avoids mismatch errors. At the same time, suspending PLL operation and not modifying the feedback path avoids offset compared to the normal mode of operation. When the PLL is offline, its time-to-digital converter (TDC) can be reused as a phase detector and its frequency synthesizer (e.g., multi-mode divider (multi-modulus divider, MMD)) can be used as an infinite range digital-to-time converter (digital to time converter, DTC). The MMD in the feedback loop may be used to obtain the output of the high frequency Voltage Controlled Oscillator (VCO) at FBDCDL instead of the reference clock of the PLL.

As detailed, a two-step process may be used. As a first step, a reference with a delay of one VCO period (1T _VCO delay) may be created using a retimer Multiplexer (MUX). This may be the maximum delay expected by FBDCDL. Then, when the code is at full scale (i.e., maximum code value), the reference may be matched to calibrate the full scale code to the maximum delay. In practice, full scale code values may be implemented using the full range of codewords and the appended least significant bits (LEAST SIGNIFICANT bits, LSBs).

Advantageously, any one or combination of the methods detailed herein facilitates calibration of DCDL gain. This in turn may reduce fractional spurs caused by DCDL. As a result, for example, the final output in a PLL-based frequency synthesizer using DCDL can be improved.

Fig. 1A and 1B illustrate simplified block diagrams of aspects of a PLL 100 according to one embodiment to illustrate a calibration procedure for FBDCDL used in the PLL 100. The controller 105 shown in fig. 1A and 1B may provide control codes and other control signals discussed with respect to the PLL 100 to FBDCDL 110. The example simplifications FBDCDL 110 are not the differences FBDCDL 210 (as discussed with reference to fig. 2A-2C). The components of PLL 200 (fig. 2A-2C) are used for calibration because PLL operation is suspended. Specifically, MMD 130, a re-timer subsystem (labeled as re-timer and Multiplexer (MUX) 140), and a time-to-digital converter, TDC (serving as a Phase Detector (PD) 160) are re-used. Delay line 150 is added to a conventional PLL configuration for calibration. Delay line 150 may include, for example, capacitors and inverters, and its components and arrangement are not limited to known configurations.

Fig. 1A illustrates a block diagram of aspects of a PLL 100 to illustrate a first step in a calibration process, according to one embodiment. The retimer and MUX 140 are controlled to be on such that the output of VCO 120 (denoted VCO _CLK) (which is passed through MMD 130) is delayed by one cycle based on the retimer delay. That is, the output of the retimer and MUX 140 is 1T _VCO. FBDCDL 110 has a code of 0. Ideally, a code value of 0 would mean that there is no delay through FBDCDL 110. However, there may be a nominal delay D _nom. Thus, in the case of input clock 1T _VCO and code value 0, the output of FBDCDL 110 may be 1T _VCO+D_nom.

The desired output of PD 160 is 0, indicating that the inputs from FBDCDL and delay line 150 are the same. The delay line 150 is set accordingly. That is, the delay line 150 is adjusted to delay the input VCO _CLK (the output of VCO 120 delivered through MMD 130) to match the delay through the retimer and MUX 140 and FBDCDL with code 0 (i.e., delay of 1T _VCO+D_nom). This results in an output of 0 for PD 160.

Fig. 1B illustrates a block diagram of aspects of the exemplary PLL 100 of fig. 1A to show a second step in the calibration process, according to one embodiment. The delay of delay line 150 is set by the first step in the calibration process (output 1T _VCO+D_nom when VCO _CLK is input), as discussed with reference to fig. 1A. The output of VCO 120 (again denoted VCO _CLK) is delivered by MMD 130. Based on the delay of the delay line 150 (set in the first step of the calibration process), the output of the delay line 150 is 1T _VCO+D_nom.

As shown in fig. 1B, during the second step of the calibration process, the retimer and MUX 140 are controlled to be off. As a result, VCO _CLK is passed to FBDCDL 110 through both MMD 130 and retimer and MUX 140 without any additional delay. During the second step of the calibration process, the code for control FBDCDL 110 is set to its full scale (i.e., maximum) value. The full scale value is based on the number of bits of the codeword and may correspond to the number of delay elements that are part of FBDCDL 110. As one non-limiting example, the full scale value of the code may be 512 based on FBDCDL's 110 including 512 delay elements. When the code-delay relationship is as expected (i.e., when FBDCDL a 110 is calibrated), the full scale value of the code should result in a maximum delay (e.g., based on the input clock of VCO _CLK, which is a delay of 1T _VCO, or in view of the nominal delay at code value 0, which is a delay of 1T _VCO+D_nom).

Calibration FBDCDL110 is very simple because the delay of the delay line 150 is set. That is, during the first step of the calibration process, the delay line 150 is set such that the delay line 150 outputs 1T _VCO+D_nom for the input clock of the VCO _CLK. Specifically, the control voltage of FBDCDL110 is adjusted to control an inverter within FBDCDL110 that changes the delay associated with the least significant bit of the code. This is the desired delay of FBDCDL110 for the full scale code value. Calibration FBDCDL110 requires that FBDCDL110 be adjusted to obtain an output of 1T _VCO+D_nom (where the code is set to a full scale value) by ensuring that the output of PD 160 is 0.

Fig. 2A, 2B, and 2C illustrate block diagrams of an exemplary PLL 200 in three different modes of operation according to one embodiment. The controller 205 shown in fig. 2A, 2B, and 2C may provide codes and other control signals for components of the PLL 200 to FBDCDL 210. The controller 205 may also pause the closed loop operation of the PLL 200 for a fixed period (e.g., every 1100 periods) or on another predetermined basis and initiate FBDCDL the calibration process of 210. During the calibration process, the output of PLL 200 (VCO _CLK) may be held from the last control period.

The example FBDCDL210,210 in the example PLL 200 is a differential DCDL having a reference input and a reference output and a feedback input and a feedback output. The two outputs of the differential FBDCDL210 are provided to the TDC 250, and the TDC 250 is used as PD during calibration of FBDCDL 210. Thus, during calibration, the output from the TDC 250 is observed as an output error 255. Delay line 240 is also added to a typical PLL arrangement for the calibration process. In the first mode of operation, as shown in fig. 2A, normal PLL functionality may be implemented. In the second mode of operation, as shown in fig. 2B, the delay of delay line 240 may be set as in the first step in calibration, as discussed with reference to fig. 1A. In a third mode of operation, as shown in fig. 2C, the delay line 240 may be used to calibrate FBDCDL a 210 in a second step in the calibration, as discussed with reference to fig. 1B. Each mode is discussed further.

As shown in fig. 2A, in the first mode of operation (i.e., the normal mode of operation), the error 255 output by the TDC 250 is not used as an output, as shown by the dashed line and the box. The operation of PLL 200 as a phase locked loop may involve control of MMD 280, which is denoted as driver control, including fractional divider control based on pulse position modulation (pulse position modulation, PPM) control. In the normal PPL mode of operation, the multiplexer 242 of the delay line 240 may be controlled such that the delay line 240 is disabled. In contrast, the output of multiplexer 230 associated with reference clock (REFERENCE CLOCK, REFCLK) 220 is passed by multiplexer 242 as a reference input (input a) into FBDCDL to produce a reference output (output a'). The reference clock 220 may be multiplied by a multiplier (doubler, DUB) 225 to generate a reference input (input a), for example, based on the control of the multiplexer 230. Based on the time outputs a 'and B' from FBDCDL 210,210, the TDC 250 produces a digital output that is filtered by a Low Pass Filter (LPF) 260 and provided to an inductor capacitor (inductor capacitor, LC) or a resonance-based VCO 270.

The output of LC VCO 270 (VCO _CLK) is the output of PLL200 and is the output of interest during normal operation of PLL 200. That is, in normal operation, the purpose of PLL200 is to monitor and control the output of LC VCO 270 (VCO _CLK). In the feedback portion of PLL200, this output (VCO _CLK) is also input to MMD 280 and retimer subsystem 290. During normal operation, the output of the retimer subsystem 290 is provided as a feedback input (input B) to FBDCDL 210,210 and used to generate a feedback output (output B').

As noted, the first mode of operation may be performed for a number of cycles (e.g., one thousand cycles) before the state of the PLL 200 is frozen, and the calibration procedure is performed on FBDCDL in the second and third modes of operation. During the second mode and the third mode, the output of interest is the error 255 from the TDC 250, which TDC 250 is used as the PD during calibration. The LC VCO 270 is not further controlled during the second and third modes of operation and the output VCO _CLK generated by the latest control of the LC VCO 270 is used in calibration instead of the reference clock 220.

Fig. 2B shows a second mode of operation, which is the first step in the calibration of FBDCDL 210,210. Similar to the discussion with reference to fig. 1A, this first step in calibration sets the delay line (DCDL 241). As described above, the closed loop operation of PLL 200 may be suspended during calibration, and LC VCO 270 output VCO _CLK may be held from the previous control period. This LC VCO 270 outputs VCO _CLK for obtaining both inputs a and B of FBDCDL 210 during calibration. Specifically, the MMD 280 passes the clock VCO _CLK through the flip-flop 293, and supplies the clock VCO _CLK to the DCDL 241 of the delay line 240 through the multiplexer 243 based on the operation of the flip-flop 293. This clock VCO _CLK with the delay imposed by DCDL 241 will be output as input a by multiplexer 242 to FBDCDL 210.

In addition, during the second mode of operation (i.e., the first step of calibration), the clock VCO _CLK passed through MD 280 is delayed based on the multiplexer 292 and the flip-flop 291 of the re-timer subsystem 290 to provide a delayed output of 0.5T _VCO at input B of FBDCDL 210. In the case of control code 0 applied to FBDCDL 210,210, no additional delay is added through FBDCDL 210,210, except for the possible nominal delay D _nom. Thus FBDCDL output B' is 0.5T _VCO+D_nom, as shown in fig. 2B. In the case of the differential FBDCDL a 210, 0.5T _VCO+D_nom may be the maximum delay provided by one of the paths through FBDCDL a 210 when the maximum code value is provided to FBDCDL a because there are delay elements in both paths through FBDCDL a 210. Thus, 0.5T _VCO+D_nom is the reference delay set during the second mode of operation.

As discussed with reference to fig. 1A, once the reference delay is determined, the PD 160 is used to set the delay line 150. In the embodiment of fig. 2B, the TDC 250 acts as a PD during calibration, and the expected value of the error 255 output by the TDC 250 is 0. That is, given an output B 'of 0.5T _VCO+D_nom, the desired output a' of FBDCDL 210 is also 0.5T _VCO+D_nom to obtain an error 255 of 0. This means that the DCDL 241 of the delay line 240 must delay its input (VCO _CLK) to output 0.5T _VCO+D_nom in order to provide the desired input a (which will also be output a' with code 0) to FBDCDL 210. The second mode of operation of PLL 200 involves setting the DCDL 241 delay using error 255 as a guide. When the value of the code is full scale, the delay set for DCDL 241 is the maximum expected delay of FBDCDL 210,210. Thus, the delay set for DCDL 241 may be used as a reference during the second step of calibration.

Fig. 2C shows a third mode of operation, which is the second step in the calibration of FBDCDL 210,210. This second step depends on the reference delay set during the first step in the calibration, i.e., the delay of DCDL 241 (e.g., output 0.5T _VCO+D_nom based on the input of VCO _CLK). When full scale code control FBDCDL 210,210 is used, the reference delay reflects the desired maximum delay provided by FBDCDL 210,210. As discussed in fig. 1B and shown in fig. 2C, the retimer subsystem 290 is controlled such that the clock VCO _CLK is provided as both the input to the delay line 240 and the input B to FBDCDL 210. With the delay of DCDL 241 set as part of the second mode of operation (i.e., the first phase of calibration), the output of delay line 240 (which is input a of FBDCDL 210) is 0.5T _VCO+D_nom.

With input B of VCO _CLK and the code set to the maximum (full scale) value, FBDCDL 210 is adjusted to provide output B' of 0.5T _VCO+D_nom. In this case, the outputs a 'and B' will be equal and thus provide the desired error 255 at the output of the TDC 250 as 0. That is, FBDCDL may be adjusted 210 (e.g., the control voltage may be adjusted) until the error 255 is 0. Once the calibration process is complete, the first mode of operation may be resumed until the next cycle when calibration is performed by implementing the second mode of operation and the third mode of operation.

The techniques operating in accordance with the principles described herein may be implemented in any suitable manner. The processes and decision blocks of the flowcharts described above represent steps and actions that may be included in algorithms that perform these various processes. The algorithms resulting from these processes may be implemented as software integrated with and directing the operation of one or more single-purpose or multi-purpose processors, may be implemented as functionally equivalent circuits, such as DSP circuits or ASICs, or may be implemented in any other suitable manner. It will be appreciated that the flow charts included herein do not depict any particular circuitry or syntax or operation of any particular programming language or programming language type. Rather, the flow diagrams illustrate functional information one of ordinary skill in the art can use to fabricate circuits or to implement computer software algorithms to perform the processing of the particular apparatus of the type of techniques described herein. For example, the flowcharts, or portions thereof, may be implemented by separate hardware (e.g., one or more analog or digital circuits, one or more hardware implemented state machines, etc., and/or any combination thereof) configured or constructed to perform the various processes of the flowcharts. In some examples, the flowcharts, or portions thereof, may be implemented by machine-executable instructions (e.g., machine-readable instructions, computer-executable instructions, etc.) that, when executed by one or more single-purpose or multi-purpose processors, perform the various processes of the flowcharts. It is also to be understood that the specific sequences of steps and/or actions described in each flowchart are merely illustrative of algorithms that can be implemented and can vary in implementation and implementation of the principles described herein, unless otherwise indicated herein.

Thus, in some embodiments, the techniques described herein may be implemented as machine-executable instructions embodied in software, including as application software, system software, firmware, middleware, embedded code, or any other suitable type of computer code. Such machine-executable instructions may be generated, written, etc. using any of a number of suitable programming languages and/or programming or scripting tools, and also may be compiled as executable machine language code or intermediate code that is executed on a framework, virtual machine, or container.

When the techniques described herein are implemented as machine-executable instructions, the machine-executable instructions may be implemented in any suitable manner, including as a plurality of functional devices, each functional device providing one or more operations to perform execution of algorithms operating in accordance with the techniques. However, a "functional device" is a structural component of a computer system that, when integrated with and executed by one or more computers, causes the one or more computers to perform a particular operational role. The functional device may be a part of a software element or the whole software element. For example, the functional device may be implemented as a function of a process or as a discrete process or as any other suitable processing unit. If the techniques described herein are implemented as multiple functional devices, each functional device may be implemented in its own manner; it is not required that all functional devices be implemented in the same way. In addition, these functional devices may be suitably executed in parallel and/or in series and may communicate information with each other using a messaging protocol or in any other suitable manner using a shared memory on the computer on which they are executing.

Generally, functional devices include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types. Typically, the functions of the functional devices may be combined or distributed as desired in the system in which they operate. In some implementations, one or more functional devices performing the techniques herein may together form a complete software package. In alternative implementations, these functional devices may be adapted to interact with other, unrelated functional devices and/or processes to implement software program applications.

Some example functional devices for performing one or more tasks have been described herein. However, it should be understood that the described functional devices and task partitions are merely illustrative of the types of functional devices that may be implemented using the exemplary techniques described herein, and that embodiments are not limited to implementation in any particular number, partition, or type of functional devices. In some implementations, all of the functions may be implemented in a single functional device. It should also be appreciated that in some implementations, some of the functional devices described herein may be implemented together with other functional devices or separately (e.g., as a single unit or separate units), or some of the functional devices may not be implemented.

In some implementations, machine-executable instructions that implement the techniques described herein (when implemented as one or more functional devices or in any other manner) may be encoded on one or more computer-readable media, machine-readable media to provide functionality to the media. Computer-readable media include magnetic media such as hard disk drives, optical media such as CDs or DVDs, persistent or non-persistent solid state memory (e.g., flash memory, magnetic RAM, etc.), or any other suitable storage media. Such computer-readable media may be implemented in any suitable manner. The terms "computer-readable medium" (also referred to as "computer-readable storage medium") and "machine-readable medium" (also referred to as "machine-readable storage medium") as used herein refer to tangible storage media. The tangible storage medium is non-transitory and has at least one physical structural component. In "computer-readable medium" and "machine-readable medium" as used herein, at least one physical structural component has at least one physical attribute that may be changed in some way during the process of creating a medium with embedded information, the process of recording information thereon, or any other process of encoding a medium with information. For example, the magnetization state of a portion of the physical structure of a computer readable medium, machine readable medium, or the like may change during the recording process.

Moreover, some of the techniques described above include acts of storing information (e.g., data and/or instructions) in some manner for use by such techniques. In some implementations of the techniques, such as implementations in which the techniques are implemented as machine-executable instructions, the information may be encoded on a computer-readable storage medium. Where specific structures are described herein as advantageous formats for storing such information, these structures may be used to impart a physical organization to the information when encoded on a storage medium. These advantageous structures may then provide functionality to the storage medium by affecting the operation of the one or more processors interacting with the information; for example, by increasing the efficiency of computer operations performed by the processor.

In some, but not all, implementations of techniques that may be embodied as machine-executable instructions, the instructions may be executed on one or more suitable computing devices and/or electronic devices operating in any suitable computer and/or electronic system, or one or more computing devices (or one or more processors of one or more computing devices) and/or one or more electronic devices (or one or more processors of one or more electronic devices) may be programmed to execute the machine-executable instructions. The computing device, electronic device, or processor (e.g., processor circuitry) may be programmed to execute instructions when the instructions are stored in a manner accessible to the computing device, electronic device, or processor, such as in a data store (e.g., an on-chip cache or instruction register, a computer-readable storage medium and/or a machine-readable storage medium accessible via a bus, a computer-readable storage medium and/or a machine-readable storage medium accessible via one or more networks and accessible by the device/processor, etc.). Functional devices comprising these machine-executable instructions may be integrated with and direct the operation of a single multipurpose programmable digital computing device, a coordinated system of two or more multipurpose computing devices that share processing capabilities and collectively perform the techniques described herein, a coordinated system of single computing devices or computing devices dedicated to performing the techniques described herein (co-located or geographically distributed), one or more FPGAs for performing the techniques described herein, or any other suitable system.

Embodiments have been described in which these techniques are implemented in circuitry and/or machine-executable instructions. It should be appreciated that some embodiments may be in the form of methods, at least one example of which has been provided. Acts performed as part of the method may be ordered in any suitable manner. Thus, embodiments may be constructed in which acts are performed in a different order than shown, which may include performing some acts simultaneously, even though shown as sequential acts in the illustrative embodiments.

The various aspects of the above-described embodiments may be used alone, in combination, or in a variety of arrangements not specifically discussed in the embodiments described in the foregoing and is therefore not limited in its application to the details and arrangement of components set forth in the foregoing description or illustrated in the drawings. For example, aspects described in one embodiment may be combined in any manner with aspects described in other embodiments.

The phrase "and/or" as used herein in the specification and claims should be understood to mean "either or both" of the elements so coupled, e.g., elements that are in some cases present in combination and in other cases not in combination. A plurality of elements listed as "and/or" should be interpreted in the same manner, e.g., "one or more" of the elements so coupled. Other elements than those specifically identified by the "and/or" clause may optionally be present, whether related or unrelated to those elements specifically identified. Thus, as a non-limiting example, when used in conjunction with an open language (such as "comprising"), references to "a and/or B" may refer in one embodiment to a only (optionally including elements other than B); in another embodiment, refer to B only (optionally including elements other than a); in yet another embodiment, both a and B (optionally including other elements) and the like are referred to.

The indefinite articles "a" and "an" as used herein in the specification and claims should be understood to mean "at least one" unless explicitly indicated to the contrary.

As used herein the specification and claims, the phrase "at least one" with reference to a list of one or more elements should be understood to mean at least one element selected from any one or more of the elements in the list of elements, but does not necessarily include each element specifically listed within the list of elements and at least one element in each element, and does not exclude any combination of elements in the list of elements. The definition also allows that elements may optionally exist outside of the specifically identified elements within the list of elements referenced by the phrase "at least one," whether related or unrelated to those elements specifically identified. Thus, as a non-limiting example, in one embodiment, "at least one of a and B" (or equivalently, "at least one of a or B," or equivalently, "at least one of a and/or B") may refer to at least one (optionally including more than one) a but no B present (and optionally including elements other than B) in one embodiment; in another embodiment at least one (optionally including more than one) B is referred to but no a is present (and optionally including elements other than a); in yet another embodiment, reference is made to at least one (optionally including more than one) a and at least one (optionally including more than one) B (and optionally including other elements); etc.

Use of ordinal terms such as "first," "second," "third," etc., in the claims to modify a claim element does not by itself connote any priority, precedence, or order of one claim element over another or the temporal order in which acts of a method are performed, but are used merely as labels to distinguish one claim element having a certain name from another element having a same name (but for use of the ordinal term) to distinguish the claim elements.

Also, the phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting. The use of "including," "comprising," "having," "containing," "involving," and variations thereof herein, is meant to encompass the items listed thereafter and equivalents thereof as well as additional items.

All definitions as defined and used herein should be understood to control dictionary definitions, definitions incorporated by reference into documents, and/or ordinary meanings of defined terms.

The word "exemplary" is used herein to mean serving as an example, instance, or illustration. Thus, any embodiments, implementations, processes, features, etc. described herein as exemplary should be construed as exemplary and should not be construed as preferred or advantageous examples unless otherwise specified.

Having thus described several aspects of at least one embodiment, it is to be appreciated various alterations, modifications, and improvements will readily occur to those skilled in the art. Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and scope of the principles described herein. Accordingly, the foregoing description and drawings are by way of example only.

Claims

1. A system that operates as a phase locked loop, PLL, the system comprising:

a frequency synthesizer in a feedback path of the PLL;

A delay line arranged to receive an output of the frequency synthesizer;

A retimer arranged to receive the output of the frequency synthesizer;

a digitally controlled delay line DCDL arranged to receive an output of the retimer;

a phase detector arranged to receive an output of the delay line and an output of the DCDL and to provide an error signal indicative of a difference in phase of the output of the delay line relative to the output of the DCDL; and

A controller configured to cause closed loop operation of the PLL during a normal mode of operation and open loop operation of the PLL during a calibration mode of operation during which a gain of the DCDL is calibrated, wherein the gain of the DCDL defines a relationship between a control code provided to the DCDL and a resulting delay implemented by the DCDL on an input clock.

2. The system of claim 1, wherein during the normal mode of operation, the controller is configured to disable the delay line such that an output of the delay line is not used.

3. The system of claim 1, wherein during the normal mode of operation, a reference clock is configured as the input clock of the DCDL and an output of the DCDL is configured to control an output of a voltage controlled oscillator VCO.

4. A system according to claim 3, wherein during the normal operation mode the output of the VCO is arranged to be provided as an output of the PLL and as an input to a feedback path in the closed loop operation of the PLL.

5. The system of claim 3, wherein during the calibration mode of operation, the output of the VCO is configured to be used in place of the reference clock and maintained without additional control.

6. The system of claim 5, wherein during the calibration mode of operation, the output of the VCO is controlled to be provided to the delay line and the retimer via the frequency synthesizer.

7. The system of claim 6 wherein during a first portion of the calibration mode of operation, the retimer is controlled to delay the output of the VCO and provide a delayed VCO output to the DCDL.

8. The system of claim 7, wherein during the first portion of the calibration mode of operation, the control code provided to the DCDL is 0 such that the output of the DCDL is nominally the delayed VCO output, and the delay line is controlled based on adjusting the delay line to provide the same delay as the output of the DCDL until the error signal of the phase detector is 0.

9. The system of claim 8, wherein during a second portion of the calibration mode of operation, the retimer is controlled such that the output of the VCO is provided to both the delay line and the DCDL.

10. The system of claim 9, wherein the control code provided to the DCDL is a maximum value of the DCDL during the second portion of the calibration mode of operation, and the DCDL is controlled based on adjusting the DCDL to provide the same delay as the delay line until the error signal of the phase detector is 0.

11. The system of claim 1, wherein the DCDL is a differential DCDL.

12. A method of calibrating a digitally controlled delay line DCDL within a phase locked loop PLL, the method comprising:

Controlling operation of the PLL with closed loop operation in a normal operation mode, wherein during the normal operation mode the DCDL delays an output of a re-timer based on a control code provided to the DCDL and uses the output of the DCDL to obtain an output of a voltage controlled oscillator VCO, the output of the VCO being provided as an output of the PLL and also provided to a feedback path; and

Controlling the operation of the PLL in a calibration mode during which a gain of the DCDL is calibrated, wherein the closed loop operation is suspended, the gain of the DCDL defining a relationship between the control code provided to the DCDL and a resulting delay implemented by the DCDL on the output of the retimer, wherein the output of the VCO during a previous normal operation mode is maintained during the calibration mode.

13. The method of claim 12, wherein the controlling the operation of the PLL is effected periodically in the calibration mode.

14. The method of claim 12, wherein for each specified number of cycles in which the operation of the control of the PLL is in the normal operation mode, the operation of the control of the PLL is in the calibration mode is implemented for one cycle, wherein the specified number of cycles is two or more.

15. The method of claim 12, wherein the controlling the operation of the PLL in the calibration mode comprises: the control code provided to the DCDL is set to 0 in a first calibration phase and the control code provided to the DCDL is set to a maximum value of the control code in a second calibration phase.

16. The method of claim 15, wherein the controlling the operation of the PLL in the calibration mode comprises: the delay of the reference delay line is set to the maximum delay expected by the DCDL during the first calibration phase.

17. The method of claim 16, wherein the controlling the operation of the PLL in the normal mode of operation comprises disabling the reference delay line.

18. The method of claim 16, wherein the controlling the operation of the PLL in the calibration mode comprises adjusting the DCDL to provide the delay of the reference delay line during the second calibration phase.

19. The method of claim 18, wherein the setting the delay of the reference delay line and the adjusting the DCDL are determined based on an error between an output of the reference delay line and an output of the DCDL during the calibration mode using an output of a phase detector of the PLL.

20. The method of claim 19, wherein the setting the delay of the reference delay line and the adjusting the DCDL are based on minimizing the output of the phase detector.