CN118074558A - Half-bridge driver with conversion rate adjusting function and half-bridge driving method - Google Patents

Abstract

A half-bridge driver with conversion rate adjusting function and a half-bridge driving method. The half-bridge driver is used for driving a half-bridge circuit, wherein the half-bridge circuit comprises an upper bridge switch and a lower bridge switch which are connected in series. The half-bridge driver comprises a switch selection circuit and at least one conversion rate adjusting circuit, wherein the conversion rate adjusting circuit comprises a pulse width control unit, an adjustment pulling unit and a stop adjustment pulling unit. The switch selection circuit is used for generating power supply current or drawing current to correspondingly pull up or pull down the gate-source voltage of the upper bridge switch or the lower bridge switch, so as to turn on or off the upper bridge switch or the lower bridge switch, and convert the input voltage into output voltage. The pull-up adjusting unit is used for adjusting the pull-up or the pull-down of the gate-source voltage of the upper bridge switch or the lower bridge switch. The stop adjustment pull-in unit is used for stopping adjustment of the pull-up or adjustment of the gate-source voltage of the pull-down upper bridge switch or the lower bridge switch.

Description

Half-bridge driver with conversion rate adjusting function and half-bridge driving method

Technical Field

The present invention relates to a half-bridge driver, and more particularly, to a half-bridge driver with a slew rate adjusting function. The invention also relates to a half-bridge driving method with the conversion rate adjusting function.

Background

Half-bridge drivers (Half-bridge drivers) are widely used in a variety of circuits (e.g., half-bridge circuits), wherein the Half-bridge drivers are used to generate a control signal to drive the switches of the Half-bridge circuits, thereby controlling the Half-bridge circuits to convert an input voltage into an output voltage. However, when the switching rate (Slew rate) of the switch is controlled improperly, parasitic inductance in the half-bridge driver or the half-bridge circuit may cause problems of electromagnetic interference (Electromagnetic Interference, EMI), thereby negatively affecting the overall circuit.

The related art is U.S. Pat. No. 4,124,52,52,2,2,64,2. The half-bridge drivers disclosed in these patents are all high-voltage drivers, and need to operate in a high-voltage range to adjust and control the driving voltage of the half-bridge circuit, so that circuits and elements bearing high voltages are needed, and different numbers of high-voltage elements need to be selectively driven according to requirements, so that the manufacturing cost and the circuit area are relatively high. In addition, in order to adjust the conversion rate of the output voltage, the prior art half-bridge driver further needs a gate-source voltage sensing circuit and a drain-source voltage sensing circuit, which both make the half-bridge driver relatively large. Moreover, when the half-bridge driver in the prior art drives the half-bridge circuit, the charge accumulated in the gate-source capacitor of the half-bridge circuit cannot be recycled, so that the power loss is high.

In view of the above, the present invention provides a half-bridge driver with a slew rate adjusting function to effectively control a half-bridge circuit, thereby reducing the electromagnetic interference, reducing the number of high voltage devices, reducing the circuit area, reducing the manufacturing cost, recycling the charge accumulated in the gate-source capacitance of the half-bridge circuit, and reducing the power consumption.

Disclosure of Invention

The invention provides a half-bridge driver for driving a half-bridge circuit, wherein the half-bridge circuit comprises an upper bridge switch and a lower bridge switch connected in series, the half-bridge driver comprises: a switch selection circuit for determining to turn on or off the upper bridge switch or the lower bridge switch according to a control signal, and generating a Source current (Source current) or a Sink current (Sink current), and correspondingly pulling up (Pull up) or pulling down (Pull down) the gate-Source voltage of the upper bridge switch or the lower bridge switch, so as to turn on or off the upper bridge switch or the lower bridge switch, so as to convert an input voltage into an output voltage; and at least one Slew rate (Slew rate) adjusting circuit coupled to the half bridge circuit, the Slew rate adjusting circuit comprising: a pulse width control unit for generating an adjusting pull control signal with a preset pulse according to the control signal; the adjusting pull unit is used for adjusting the gate-source voltage of the upper bridge switch or the lower bridge switch to be pulled up or pulled down according to the adjusting pull control signal so as to adjust the conversion rate of the output voltage; the pull-up adjusting unit is coupled with the pull-up adjusting unit and used for stopping adjusting the pull-up or the pull-down of the upper bridge switch or the gate-source voltage of the lower bridge switch according to a preset threshold value; wherein, the voltage difference between a high power voltage and a low power voltage of the conversion rate adjusting circuit is lower than the voltage difference between a power voltage and a ground potential; wherein the power supply voltage is higher than the input voltage and the output voltage.

The present invention also provides a half-bridge driving method for driving a half-bridge circuit, wherein the half-bridge circuit includes an upper bridge switch and a lower bridge switch connected in series, the half-bridge driving method comprising: determining to turn on or off the upper bridge switch or the lower bridge switch according to a control signal, and generating a power current (Source current) or a Sink current (Sink current), and correspondingly pulling up (Pull up) or pulling down (Pull down) the gate-Source voltage of the upper bridge switch or the lower bridge switch, so as to turn on or off the upper bridge switch or the lower bridge switch, so as to convert an input voltage into an output voltage; and a conversion rate (Slew rate) adjustment step including: generating an adjusting pull control signal with a preset pulse according to the control signal; adjusting the pull-up or the pull-down of the gate-source voltage of the upper bridge switch or the lower bridge switch according to the adjusting pull-up control signal to adjust the conversion rate of the output voltage; stopping adjusting the pull-up or adjusting the gate-source voltage of the pull-down upper bridge switch or the pull-down lower bridge switch according to a preset threshold; the conversion rate adjusting step is operated between a high power supply voltage and a low power supply voltage, and the voltage difference between the high power supply voltage and the low power supply voltage is lower than the voltage difference between a power supply voltage and a ground potential; wherein the power supply voltage is higher than the input voltage and the output voltage.

In some embodiments, the at least one slew rate adjustment circuit includes a pull-up slew rate adjustment circuit, a pull-down slew rate adjustment circuit, a pull-up slew rate adjustment circuit, and/or a pull-down slew rate adjustment circuit.

In some embodiments, the pull-up adjusting unit adjusts the pull-up or pull-down of the gate-source voltage of the upper bridge switch or the lower bridge switch for an adjustment period, and the adjustment period is related to the pulse width of the preset pulse, the preset threshold value, and/or the level of the pull-up adjusting control signal.

In some embodiments, the adjusting pull unit includes at least one MOS device, and the period of the adjusting is related to the number of the at least one MOS device coupled in parallel.

In some embodiments, the stop adjustment pull unit includes at least one diode element, and the predetermined threshold is related to the number of the at least one diode elements coupled in series.

In some embodiments, the slew rate adjusting circuit includes the upper-bridge adjusting pull-down slew rate adjusting circuit and/or the lower-bridge adjusting pull-down slew rate adjusting circuit, and during the period of the adjusting, the upper-bridge adjusting pull-down slew rate adjusting circuit and/or the lower-bridge adjusting pull-down slew rate adjusting circuit adjusts the gate-source voltage of the upper-bridge switch and/or the lower-bridge switch to generate an adjusted pull-down current, and the adjusted pull-down current flows through the corresponding stop-adjusting pull-down unit and flows to an adjusting power supply to reuse the electric energy of the adjusted pull-down current.

In some embodiments, the stop adjustment pull unit is a unidirectional conductive device to prevent current from flowing backward.

In some embodiments, the switch selection circuit includes: an upper bridge switch selection circuit for determining to turn on or off the upper bridge switch according to the control signal, and generating an upper bridge power supply current or an upper bridge current to correspondingly pull up or pull down the gate-source voltage of the upper bridge switch, so as to turn on or off the upper bridge switch; and a lower bridge switch selection circuit for determining to turn on or off the lower bridge switch according to the control signal, and generating a lower bridge power supply current or a lower bridge drawing current, and correspondingly pulling up or down the gate-source voltage of the lower bridge switch, so as to turn on or off the lower bridge switch, wherein the power supply current comprises the upper bridge power supply current or the lower bridge power supply current; wherein the current draw includes the upper bridge current draw or the lower bridge current draw.

In some embodiments, the half-bridge driver further includes a level shift circuit for shifting the level of the control signal to be input to the upper bridge switch selection circuit.

In some embodiments, the at least one MOS device in the pull-up unit of the pull-up switching rate adjusting circuit has a withstand voltage higher than a voltage difference between the input voltage and the ground potential.

In some embodiments, the at least one diode element of the pull-up unit for stopping the pull-up switching rate adjusting circuit has a withstand voltage higher than a voltage difference between the input voltage and the ground potential.

In some embodiments, the voltage difference between the high power voltage and the low power voltage is not higher than 5 volts, and the power voltage is not lower than 20 volts.

The objects, technical contents, features and effects achieved by the present invention will be more readily understood by the following detailed description of specific embodiments.

Drawings

FIG. 1 is a block diagram of a half-bridge driver according to an embodiment of the present invention.

Fig. 2 is a circuit diagram of a switch selection circuit according to an embodiment of the invention.

FIG. 3 is a block diagram of a slew rate adjustment circuit according to an embodiment of the invention.

Fig. 4A is a circuit schematic of the pwm control unit according to an embodiment of the present invention.

Fig. 4B is a waveform diagram of a pulse width control unit according to an embodiment of the invention.

Fig. 5A is a schematic circuit diagram (one) of a slew rate adjusting circuit according to an embodiment of the invention.

Fig. 5B is a circuit diagram of a slew rate adjusting circuit according to an embodiment of the invention (ii).

Fig. 5C is a circuit diagram of a slew rate adjusting circuit according to an embodiment of the invention.

FIG. 5D is a block diagram of a slew rate adjustment circuit according to an embodiment of the invention.

Fig. 6A is an enlarged schematic diagram of waveforms of the slew rate adjusting circuit according to an embodiment of the present invention.

Fig. 6B is an enlarged schematic diagram of waveforms of the slew rate adjusting circuit according to an embodiment of the present invention (ii).

Fig. 7A is a schematic waveform diagram of a gate of an upper bridge switch according to an embodiment of the invention.

Fig. 7B is a waveform diagram of an output voltage of the half-bridge circuit according to an embodiment of the invention.

Description of the symbols in the drawings

10: Half-bridge driver

100: Switch selection circuit

101: Switch selection circuit for upper bridge

102: Lower bridge switch selection circuit

110: Conversion rate adjusting circuit

110A: upper bridge adjusting pull-up conversion rate adjusting circuit

110B: circuit for adjusting pull-down conversion rate by upper bridge

110C: lower bridge adjusting pull-up conversion rate adjusting circuit

110D: circuit for adjusting pull-down conversion rate by adjusting lower bridge

111: Pulse width control unit

112: Adjusting the pulling unit

112A: adjusting the pulling unit

112B: adjusting the pulling unit

112C: adjusting the pulling unit

112D: adjusting the pulling unit

113: Stop adjusting pull unit

113A: stop adjusting pull unit

113B: stop adjusting pull unit

113C: stop adjusting pull unit

113D: stop adjusting pull unit

120: Level shift circuit

200: Half-bridge circuit

AND (2) AND: AND gate

DTC: delay time circuit

GND: ground potential

Ipd: adjusting pull-down current

Isink1: upper bridge draws current

Isink2: lower bridge draws current

Isrc1: upper bridge power supply current

Isrc2: lower bridge supply current

INV: inverter with a high-speed circuit

LG: gate of lower bridge switch

LX: node

N1, N2: switch

P1, P2: switch

Ppre: preset threshold value

Ppre1, ppre2: preset threshold value

QL: lower bridge switch

QU: switch for upper bridge

Sc: control signal

Sc': control signal

Scd: control signal

Sc1, sc2: control signal

Scs: adjusting the pull control signal

Scs1-Scs4: adjusting the pull control signal

T1-t6: time point

T1-T4: during the period of time

UG: gate of upper bridge switch

Vboot: supply voltage

Vemi: threshold of electromagnetic interference

Vin: input voltage

Vout: output voltage

Vreg1: regulating voltage

Vreg2: regulating voltage

Vthp: preset threshold value

VH: high supply voltage

VL: low supply voltage

Detailed Description

The drawings in the present invention are schematic and are mainly intended to represent coupling relationships between circuits and relationships between signal waveforms, which are not drawn to scale.

Referring to fig. 1, fig. 1 is a block diagram of a half-bridge driver 10 according to an embodiment of the invention, wherein the half-bridge driver 10 is used for driving a half-bridge circuit 200, and the half-bridge circuit 200 includes an upper bridge switch QU and a lower bridge switch QL connected in series with each other. As shown in fig. 1, the half-bridge driver 10 includes a switch selection circuit 100, at least one slew rate adjustment circuit 110, a level shift circuit 120 and an inverter INV. In the present embodiment, the switch selection circuit 100 includes an upper bridge switch selection circuit 101 and a lower bridge switch selection circuit 102. The upper bridge switch selection circuit 101 is coupled between the level shift circuit 120 and the upper bridge switch QU; the lower bridge switch selection circuit 102 is coupled between the inverter INV and the lower bridge switch QL. In the present embodiment, at least one conversion rate adjustment circuit 110 is shown with a dashed line, so as to illustrate that the conversion rate adjustment circuit 110 may include at least one of the conversion rate adjustment circuits 110A, 110B, 110C, and 110D or a combination thereof according to the present invention. The slew rate adjusting circuit 110 is coupled to the switch selection circuit 100 and to the gate UG of the upper bridge switch QU and/or the gate LG of the lower bridge switch QL.

In some embodiments, the switch selection circuit 100 is configured to turn on or off the upper bridge switch QU or the lower bridge switch QL according to a control signal Sc. And the switch selection circuit 100 generates an upper bridge power supply current Isrc1, an upper bridge drawing current Isink1, a lower bridge power supply current Isrc2, or a lower bridge drawing current Isink2 according to the control signal Sc to charge the gate-source capacitance of the upper bridge switch QU to pull up the gate-source voltage of the upper bridge switch QU and turn on the upper bridge switch QU, discharge the gate-source capacitance of the upper bridge switch QU to pull down the gate-source voltage of the upper bridge switch QU and turn off the upper bridge switch QU, charge the gate-source capacitance of the lower bridge switch QL to pull up the gate-source voltage of the lower bridge switch QL and turn on the lower bridge switch QL, or discharge the gate-source capacitance of the lower bridge switch QL to pull down the gate-source voltage of the lower bridge switch QL, respectively, thereby converting an input voltage Vin received by the upper bridge switch QU into an output voltage Vout generated at the node LX. The node LX may further be coupled to an inductor to apply the half-bridge circuit 200 to a switching power converter (SWITCHING REGULATOR) or a class D amplifier (class-DAMPLIFIER CIRCUIT) or the like.

It should be noted that, in the operation of the half-bridge circuit 200, the upper bridge switch QU and the lower bridge switch QL are not turned on simultaneously, and therefore, the upper bridge power supply current Isrc1 and the lower bridge power supply current Isrc2 are not generated simultaneously, and therefore, one of the upper bridge power supply current Isrc1 and the lower bridge power supply current Isrc2 may be referred to as a power supply current. On the other hand, the upper bridge drawing current Isink1 and the lower bridge drawing current Isink2 are not generated simultaneously, so that one of the upper bridge drawing current Isink1 and the lower bridge drawing current Isink2 may be referred to as a drawing current. In addition, according to the present invention, the slew rate adjusting circuit 110 may include at least one of the slew rate adjusting circuits 110A, 110B, 110C and 110D or a combination thereof, which indicates that one or more of the slew rate adjusting circuits 110A, 110B, 110C and 110D has an effect of improving the slew rate of the adjusted output voltage Vout.

The slew rate adjusting circuit 110 is coupled to the half-bridge circuit 200 for adjusting the switching time of turning on or off the upper bridge switch QU or the lower bridge switch QL to increase the switching rate of the half-bridge circuit 200 or improve the electromagnetic interference when the switch selecting circuit 100 pulls up or pulls down the gate-source voltage of the upper bridge switch QU or the lower bridge switch QL for a period of time. Thus, according to the present invention, an optimal adjustment can be made between improving electromagnetic interference and increasing the switching rate of the switch.

The voltage difference between a high power voltage VH and a low power voltage VL (not shown) of the slew rate adjusting circuit 110 is lower than the voltage difference between a power voltage Vboot and the ground potential GND. That is, the voltage difference between the high power voltage VH and the low power voltage VL supplies power to the pulse width control unit of the slew rate adjusting circuit 110, and the pulse width control unit operates between the high power voltage and the low power voltage. The voltage difference between the high power voltage and the low power voltage has a lower voltage range relative to the voltage difference between the power supply voltage Vboot and the ground potential GND, so that the pulse width control unit of the slew rate adjusting circuit 110 operates in the lower voltage range, only the low voltage device is needed, and the high voltage device that is subjected to the high voltage is not needed. In general, a high-voltage element refers to an element that operates at higher than 5V, and a low-voltage element refers to an element that operates at not higher than 5V. In one embodiment, the high supply voltage VH is, for example and without limitation, equal to the internal voltage GVDD, and the low supply voltage VL is, for example and without limitation, equal to the ground potential GND.

According to the present invention, in the slew rate adjusting circuits 110A and 110B coupled to the upper bridge switch selecting circuit 101, the number of components required to bear high voltage is small compared with the prior art, and the slew rate adjusting circuits 110C and 110D are also operated in the low voltage range, so the half-bridge driver 10 according to the present invention has at least: the number of high voltage elements can be reduced, the circuit area can be reduced, and the manufacturing cost can be reduced. In addition, in the supply slew rate adjusting circuits 110B and 110D, when the gate-source voltages of the upper bridge switch QU and/or the lower bridge switch QL are pulled down, the generated adjusted pull-down current flows into the preset power source to recycle the electric energy, so that the power consumption can be reduced compared with the prior art. The respective structures and functions of the switch selection circuit 100 and the slew rate adjustment circuit 110 will be explained in detail below, and the arrangement manner therebetween will be explained.

Referring to fig. 2, fig. 2 is a circuit diagram of a switch selection circuit 100 according to an embodiment of the invention, wherein the switch selection circuit 100 includes an upper bridge switch selection circuit 101 and a lower bridge switch selection circuit 102. As shown in fig. 2, in some embodiments, the upper bridge switch selection circuit 101 includes switches P1 and N1 coupled to the gate UG of the upper bridge switch QU, and the lower bridge switch selection circuit 102 includes switches P2 and N2 coupled to the gate LG of the lower bridge switch QL, wherein the switches P1 and P2 are, for example and without limitation, P-type MOS devices as shown in fig. 2, and the switches N1 and N2 are, for example and without limitation, N-type MOS devices as shown in fig. 2.

With continued reference to fig. 2, the source of the switch P1 is coupled to the supply voltage Vboot, the source of the switch N1 is coupled to the node LX of the half-bridge circuit 200, the source of the switch P2 is coupled to a high supply voltage VH, and the source of the switch N2 is coupled to a low supply voltage VL. Wherein the high supply voltage VH is, for example and without limitation, equal to the internal voltage GVDD shown in fig. 1, and the low supply voltage VL is, for example and without limitation, equal to the ground potential GND shown in fig. 1. In some embodiments, the upper bridge switch selection circuit 101 is configured to determine to turn on or off the upper bridge switch QU according to a control signal Sc1, and generate the upper bridge power supply current Isrc1 to pull up or generate the upper bridge drawing current Isink1 to pull down the gate-source voltage of the upper bridge switch QU, thereby turning on or off the upper bridge switch QU. In some embodiments, the lower bridge switch selection circuit 102 is configured to determine to turn on or off the lower bridge switch QL according to a control signal Sc2, and generate the lower bridge power supply current Isrc2 to pull up or generate the lower bridge drawing current Isink2 to pull down the gate-source voltage of the lower bridge switch QL, so as to turn on or off the lower bridge switch QL.

Referring to fig. 1 again, in some embodiments, the half-bridge driver 10 further includes a level shift circuit 120 for shifting the level of the raised control signal Sc to generate the control signal Sc1, which is input to the upper bridge switch selection circuit 101 to drive the upper bridge switch QU. In some embodiments, the half-bridge driver 10 further includes an inverter INV for inverting the control signal Sc to generate the control signal Sc2 for inputting to the lower bridge switch selection circuit 102 to drive the lower bridge switch QL. The structure and function of the inverter INV are well known to those skilled in the art, and thus are not described in detail.

Referring to fig. 3, fig. 3 is a block diagram of a slew rate adjusting circuit 110 according to an embodiment of the invention. As shown in fig. 3, in some embodiments, the slew rate adjusting circuit 110 includes a pulse width control unit 111, an adjusting pull unit 112 and a stopping adjusting pull unit 113, wherein the high power voltage VH and the low power voltage VL provide power to the pulse width control unit 111, the adjusting pull unit 112 is coupled to the pulse width control unit 111 and a node X, and the stopping adjusting pull unit 113 is coupled to the adjusting pull unit 112 and a node Y, wherein the power, the voltage or the pin corresponding to the node X and the node Y will be described later. Referring to fig. 1 and 3, in some embodiments, the voltage difference between the high power voltage VH and the low power voltage VL is lower than the voltage difference between the power voltage Vboot and a ground potential GND. In some embodiments, the voltage difference between the high power voltage VH and the low power voltage VL is not higher than 5 volts, and the power voltage Vboot is not lower than 20 volts, where the low power voltage VL is, for example, 0 volts, and the ground potential GND is, for example, 0 volts.

In some embodiments, the pulse width control unit 111 is configured to generate an adjusted pull-up control signal Scs having a predetermined pulse Ppre according to the control signal Sc or the control signal Sc ', wherein the control signal Sc' is an inverse signal of the control signal Sc. Referring to fig. 4A and fig. 4B, fig. 4A is a schematic circuit diagram of the pwm control unit 111 according to an embodiment of the invention; fig. 4B is a waveform diagram of the pwm control unit 111 according to an embodiment of the invention. As shown in fig. 4A AND 4B, in some embodiments, the pulse width control unit 111 includes a delay time circuit DTC AND an AND gate AND, wherein the structures AND functions of the delay time circuit DTC AND the AND gate AND are well known to those skilled in the art, AND are not described herein. In some embodiments, the delay time circuit DTC is configured to delay the control signal Sc or the control signal Sc 'for a delay period AND generate a control signal Scd after inverting, AND the AND gate AND is configured to perform AND logic operation on the control signal Sc or the control signal Sc' AND the delayed control signal Scd to generate an adjusted pull-up control signal Scs having a predetermined pulse Ppre, wherein a pulse width of the predetermined pulse Ppre is related to the delay period AND can be adjusted according to different requirements.

In some embodiments, the slew rate adjusting circuit 110 comprises an upper-bridge-adjust-pull-up slew rate adjusting circuit 110A, an upper-bridge-adjust-pull-down slew rate adjusting circuit 110B, a lower-bridge-adjust-pull-up slew rate adjusting circuit 110C, and/or a lower-bridge-adjust-pull-down slew rate adjusting circuit 110D. Taking fig. 1 as an example, in the present embodiment, the conversion rate adjusting circuit 110 shown in fig. 1 includes at least one of the aforementioned 4 conversion rate adjusting circuits. Referring to fig. 5A to 5D, fig. 5A to 5D are schematic circuit diagrams of the slew rate adjusting circuit 110 according to some embodiments of the present invention, wherein fig. 5A shows the upper bridge adjusting pull-up slew rate adjusting circuit 110A, fig. 5B shows the upper bridge adjusting pull-down slew rate adjusting circuit 110B, fig. 5C shows the lower bridge adjusting pull-up slew rate adjusting circuit 110C, and fig. 5D shows the lower bridge adjusting pull-down slew rate adjusting circuit 110D. The respective structures and functions of the upper-bridge-adjustment pull-up conversion rate adjustment circuit 110A, the upper-bridge-adjustment pull-down conversion rate adjustment circuit 110B, the lower-bridge-adjustment pull-up conversion rate adjustment circuit 110C, and the lower-bridge-adjustment pull-down conversion rate adjustment circuit 110D will be explained in detail below, and the arrangement manner therebetween will be explained.

As shown in fig. 5A, in some embodiments, the upper bridge adjusting pull-up conversion rate adjusting circuit 110A includes a pulse width control unit 111A, an adjusting pull-up unit 112A, and a stopping adjusting pull-up unit 113A, wherein the adjusting pull-up unit 112A is coupled to a 2Vreg1 (corresponding to the node X of fig. 3), and the stopping adjusting pull-up unit 113A is coupled to the gate UG (corresponding to the node Y of fig. 3) of the upper bridge switch QU. In some embodiments, the pull-up adjustment unit 112A is configured to adjust the gate-source voltage of the pull-up switch QU according to the pull-up adjustment control signal Scs1 (corresponding to the pull-up adjustment control signal Scs of fig. 3) generated by the pulse width control unit 111A, so as to adjust a pull-up slew rate of the gate-source voltage of the pull-up switch QU, thereby adjusting the slew rate of the output voltage Vout. In some embodiments, the stop adjusting pull-up unit 113A is configured to stop adjusting the gate-source voltage of the pull-up bridge switch QU according to a predetermined threshold. In the present embodiment, only the stop adjustment pull unit 113A coupled to the gate of the upper bridge switch QU receives a high voltage, and the other pulse width control units 111A and the adjustment pull unit 112A are operated in a low voltage range, so that in the upper bridge adjustment pull-up conversion rate adjustment circuit 110A, other components except the stop adjustment pull unit 113A can be low voltage components.

As shown in fig. 5B, in some embodiments, the upper bridge adjusting and pull-down conversion rate adjusting circuit 110B includes a pulse width control unit 111B, an adjusting pull-up unit 112B, and a stopping adjusting pull-up unit 113B, wherein the adjusting pull-up unit 112B is coupled to the gate UG (corresponding to the node X of fig. 3) of the upper bridge switch QU, and the stopping adjusting pull-up unit 113B is coupled to the adjusting voltages Vreg1, vreg2, or the low power supply voltage VL (corresponding to the node Y of fig. 3). In some embodiments, the pull-up adjustment unit 112B is configured to adjust the gate-source voltage of the pull-down upper bridge switch QU according to the pull-up adjustment control signal Scs2 (corresponding to the pull-up adjustment control signal Scs of fig. 3) generated by the pulse width control unit 111B, so as to adjust an upper bridge of the gate-source voltage of the upper bridge switch QU to adjust the pull-down slew rate, thereby adjusting the slew rate of the output voltage Vout. In some embodiments, the stop adjusting pull-up unit 113B is configured to stop adjusting the gate-source voltage of the pull-down upper bridge switch QU according to the preset threshold. In some embodiments, the regulated voltage Vreg1 is, for example, 3.3 volts, and the regulated voltage Vreg2 is, for example, 1.8 volts. In the present embodiment, only the pull-up adjusting unit 112B coupled to the gate of the upper bridge switch QU receives a high voltage, and the other pulse width control units 111B and the pull-up stopping unit 113B are operated in a low voltage range, so that in the upper bridge pull-up switching rate adjusting circuit 110B, other devices except the pull-up adjusting unit 112B can use low voltage devices. Wherein the high supply voltage VH (e.g., without limitation, 5V) is not lower than the regulated voltage Vreg1 (e.g., without limitation, 3.3V), the regulated voltage Vreg1 is not lower than the regulated voltage Vreg2 (e.g., without limitation, 1.8V), and the regulated voltage Vreg2 is not lower than the low supply voltage VL (e.g., without limitation, 0V).

As shown in fig. 5C, in some embodiments, the lower-bridge-adjustment pull-up conversion rate adjustment circuit 110C includes a pulse width control unit 111C, an adjustment pull unit 112C, and a stop adjustment pull unit 113C, wherein the adjustment pull unit 112C is coupled to the adjustment voltage Vreg2 (corresponding to the node X of fig. 3), and the stop adjustment pull unit 113C is coupled to the gate LG (corresponding to the node Y of fig. 3) of the lower-bridge switch QL. In some embodiments, the pull-up unit 112C is configured to adjust the gate-source voltage of the pull-up/down switch QL according to the pull-up control signal Scs3 (corresponding to the pull-up control signal Scs of fig. 3) generated by the pulse width control unit 111C, so as to adjust the pull-up slew rate of the lower bridge switch QL, thereby adjusting the slew rate of the output voltage Vout. In some embodiments, the stop adjusting pull-up unit 113C is configured to stop adjusting the gate-source voltage of the pull-up/down bridge switch QL according to a predetermined threshold.

As shown in fig. 5D, in some embodiments, the lower bridge trim pull-down conversion rate adjusting circuit 110D includes a pulse width control unit 111D, a trim pull-up unit 112D, and a stop trim pull-up unit 113D, wherein the trim pull-up unit 112D is coupled to the gate LG (corresponding to the node X of fig. 3) of the lower bridge switch QL, and the stop trim pull-up unit 113D is coupled to the regulated voltages Vreg1, vreg2, or the low supply voltage VL (corresponding to the node Y of fig. 3). In some embodiments, the pull-down unit 112D is configured to adjust the gate-source voltage of the pull-down switch QL according to the pull-down control signal Scs4 (corresponding to the pull-down control signal Scs of fig. 3) generated by the pulse width control unit 111D, so as to adjust the pull-down slew rate of the pull-down switch QL, and further adjust the slew rate of the output voltage Vout. In some embodiments, the stop adjusting pull-up unit 113D is configured to stop adjusting the gate-source voltage of the pull-down bridge switch QL according to the preset threshold.

Referring to fig. 5B and fig. 5D again, in some embodiments, when the pull-up conversion rate adjusting circuit 110B and/or the pull-down conversion rate adjusting circuit 110D adjust the gate-source voltage of the pull-down upper bridge switch QU and/or the pull-down switch QL, an adjusted pull-down current Ipd is generated, flows through the corresponding stop adjustment pull-up units 113B and 113D, and flows to the adjustment power source (e.g. the adjustment voltage Vreg1 or the adjustment voltage Vreg 2) to reuse the electric energy of the adjusted pull-down current Ipd.

Referring to fig. 6A and 6B, fig. 6A and 6B are schematic diagrams of waveform amplification (Zoom in) of the slew rate adjusting circuit 110 according to some embodiments of the present invention, wherein fig. 6A is a waveform diagram of the pull-up slew rate adjusting circuit 110A of fig. 5A adjusting the gate-source voltage of the pull-up switch QU, and fig. 6B is a waveform diagram of the pull-up slew rate adjusting circuit 110B of fig. 5B adjusting the gate-source voltage of the pull-down pull-up switch QU. The method of driving the half-bridge circuit 200 by the half-bridge driver 10 will be described with reference to fig. 6A and 6B.

As shown in fig. 6A, in the present embodiment, at time t1, the pulse width control unit 111A generates the adjusted pull-out control signal Scs1 having the preset pulse Ppre1 according to the control signal Sc. Next, the adjustment pull unit 112A adjusts the gate-source voltage (indicated by UG) of the pull-up bridge switch QU for an adjustment period (corresponding period T1) according to the adjustment pull control signal Scs1. At time t2, since the gate-source voltage UG of the pull-up switch QU is pulled up to reach the preset threshold Vthp, the stop-adjustment pull-up unit 113A stops adjusting the gate-source voltage of the pull-up switch QU. Finally, during the period T2, the switch P1 of the upper bridge switch selection circuit 101 pulls up the gate-source voltage of the upper bridge switch QU until the gate-source voltage of the upper bridge switch QU reaches a certain value (and turns on the upper bridge switch QU) and stops pulling up the gate-source voltage of the upper bridge switch QU at the time T3. In some embodiments, the adjustment period (period T1) is related to the pulse width of the preset pulse Ppre1, the preset threshold Vthp, the level of the pull-up control signal Scs1 and/or the adjustment voltage Vreg1.

Referring to fig. 5A, in one embodiment, the adjusting pull unit 112A is, for example and not limited to, an N-type MOS device as shown in fig. 5A, the adjusting pull unit 113A is stopped, for example and not limited to, a diode as shown in fig. 5A, and when the control signal Sc generates the preset pulse Ppre1 to change the adjusting pull control signal Scs1 from the low level to the high level, the adjusting pull unit 112A is turned on to generate an adjusting pull-up current flowing through the pull unit 112A and stopping the adjusting pull unit 113A, and the adjusting pull-up current is added to the upper bridge power current Isrc1 to increase the current for charging the gate-source capacitor of the upper bridge switch QU, so as to accelerate the gate-source voltage of the upper bridge switch QU; the gate-source voltage of the pull-up accelerating switch QU continues until the gate-source voltage of the pull-up switch QU reaches a preset threshold Vthp (time t 2), at which time the adjustment voltage Vreg1 is reduced by the preset threshold Vthp not lower than the forward conduction voltage of the diode of the pull-up stopping unit 113A, so that the diode is not turned on, and the pull-up current is adjusted to zero, thereby stopping the gate-source voltage of the pull-up accelerating switch QU. In the present embodiment, the adjustment period (corresponding to the period T1) is determined by the forward turn-on voltage (corresponding to the preset threshold Vthp) of the diode and the adjustment voltage Vreg 1. In another embodiment, the adjustment period may also be determined by adjusting the level of the pull-up control signal Scs1 and/or the adjustment voltage Vreg 1. The operation mechanisms of fig. 5B, 5C and 5D can be deduced from the operation mechanism of fig. 5A, and are not described herein.

As shown in fig. 6B, in the present embodiment, at time t4, the pulse width control unit 111B generates the adjusted pull-out control signal Scs2 having the preset pulse Ppre2 according to the control signal Sc'. Next, the pull-up adjusting unit 112B adjusts the gate-source voltage of the pull-down upper bridge switch QU for an adjustment period (corresponding to the period T3) according to the pull-up adjusting control signal Scs2. At time t5, since the gate-source voltage of the pull-up switch QU is pulled down to reach the preset threshold Vthp, the stop-adjustment pull-up unit 113B stops adjusting the gate-source voltage of the pull-down pull-up switch QU. Finally, during the period T4, the switch N1 of the upper bridge switch selection circuit 101 pulls down the gate-source voltage of the upper bridge switch QU until the gate-source voltage of the upper bridge switch QU reaches the level of the output voltage Vout (e.g., 0 volts) and stops at the time T6 (the upper bridge switch QU is turned off). In some embodiments, the adjustment period (period T3) is related to the pulse width of the preset pulse Ppre2, the preset threshold Vthp, the level of the pull-up control signal Scs2, the adjustment voltages Vreg1, vreg2 and/or the low power voltage VL.

In some embodiments, the adjustment pull units 112A, 112B, 112C, 112D include at least one MOS device, and the period of adjustment is related to the number of MOS devices coupled in parallel. In some embodiments, the MOS elements in the trim pull-up unit 112B of the upper bridge trim pull-down slew rate trim circuit 110B have a withstand voltage that is higher than the voltage difference between the input voltage Vin and the ground potential GND.

In some embodiments, the stop adjustment pull units 113A, 113B, 113C, 113D include at least one diode element, and the predetermined threshold Vthp is related to the number of diode elements coupled in series, wherein the larger the number of diode elements, the larger the value of the predetermined threshold Vthp. In some embodiments, the diode elements in the stop-adjust pull-up unit 113A of the upper-bridge-adjust-up-slew-rate adjustment circuit 110A have a withstand voltage higher than the voltage difference between the input voltage Vin and the ground potential GND. In some embodiments, the stop adjustment pull units 113A, 113B, 113C, 113D are a unidirectional conductive element to prevent current flow back.

Referring to fig. 7A, fig. 7A is a schematic waveform diagram of the voltage of the gate UG of the upper bridge switch QU in an embodiment of the invention, wherein the waveform W1 ignores the parasitic inductance and employs the half-bridge driver 10 of the invention, the waveform W2 ignores the parasitic inductance and does not employ the half-bridge driver 10 of the invention, the waveform W3 considers the parasitic inductance (wherein the parasitic inductance is generated by wire bonding when the integrated circuit is packaged, for example) and employs the half-bridge driver 10 of the invention, and the waveform W4 considers the parasitic inductance and does not employ the half-bridge driver 10 of the invention. As shown in fig. 7A, in the present embodiment, since the half-bridge driver 10 of the present invention adjusts the voltage of the gate UG of the pull-up bridge switch QU (i.e. adjusts the gate-source voltage of the pull-up bridge switch QU), the waveform W1 starts to be pulled up at the time t1 as compared with the waveform W2. Similarly, the waveform W3 starts to pull up at time t2 as compared to the waveform W4. Therefore, the speed of switching the upper bridge switch QU can be improved according to the present invention.

Referring to fig. 7B, fig. 7B is a schematic diagram of waveforms of the output voltage Vout of the half-bridge circuit 200 according to an embodiment of the invention, wherein the waveform W5 ignores the parasitic inductance and employs the half-bridge driver 10 according to the invention, the waveform W6 ignores the parasitic inductance and does not employ the half-bridge driver 10 according to the invention, the waveform W7 considers the parasitic inductance and employs the half-bridge driver 10 according to the invention, and the waveform W8 considers the parasitic inductance and does not employ the half-bridge driver 10 according to the invention. As shown in fig. 7B, in the present embodiment, since the half-bridge driver 10 of the present invention adjusts the voltage of the gate UG of the pull-up bridge switch QU (as shown in fig. 7A), the slew rate of the output voltage Vout is adjusted (as shown in waveforms W5 and W7). In addition, according to the present invention, the adjustment of the voltage of the gate UG of the pull-up bridge switch QU can be terminated at a proper time, and the adjustment of the pull-up unit 113 is stopped so that the level of the output voltage Vout does not exceed a certain value (for example, an electromagnetic interference threshold Vemi), thereby avoiding the electromagnetic interference problem generated by the half-bridge circuit 200.

In summary, the half-bridge driver 10 of the present invention not only can adjust the conversion rate of the output voltage Vout by adjusting the pull-up and/or the pull-down of the upper bridge switch QU and/or the lower bridge switch QL, thereby avoiding the problem of electromagnetic interference, but also can reduce the on time or the off time of the upper bridge switch QU or the lower bridge switch QL in the half-bridge circuit 200 to improve the efficiency of converting the input signal Vin into the output signal Vout.

The present invention has been described in terms of the preferred embodiments, but the above description is only for the purpose of easily understanding the present invention by those skilled in the art, and is not intended to limit the scope of the claims of the present invention. The embodiments described are not limited to single applications but may be combined, for example, two or more embodiments may be combined, and portions of one embodiment may be substituted for corresponding components of another embodiment. In addition, various equivalent changes and various combinations will be apparent to those skilled in the art, and for example, the term "processing or calculating based on a signal or generating an output result" in the present invention is not limited to the processing or calculating based on the signal itself, but includes performing voltage-to-current conversion, current-to-voltage conversion, and/or scaling conversion of the signal, if necessary, and then processing or calculating based on the converted signal to generate an output result. It will thus be appreciated that those skilled in the art will be able to devise various arrangements which, although not explicitly described herein, embody the principles of the invention and are thus equally well suited to the particular use contemplated. Accordingly, the scope of the invention should be assessed as that of the above and all other equivalent variations.

Claims (22)

1. A half-bridge driver for driving a half-bridge circuit, wherein the half-bridge circuit includes an upper bridge switch and a lower bridge switch connected in series with each other, the half-bridge driver comprising:

The switch selection circuit is used for determining to turn on or off the upper bridge switch or the lower bridge switch according to a control signal, generating a power supply current or a drawing current, correspondingly pulling up or pulling down the gate-source voltage of the upper bridge switch or the lower bridge switch, and further turning on or off the upper bridge switch or the lower bridge switch so as to convert an input voltage into an output voltage; and

At least one slew rate adjusting circuit coupled to the half bridge circuit, the slew rate adjusting circuit comprising:

a pulse width control unit for generating an adjusting pull control signal with a preset pulse according to the control signal;

The adjusting pull unit is used for adjusting the gate-source voltage of the upper bridge switch or the lower bridge switch to be pulled up or pulled down according to the adjusting pull control signal so as to adjust the conversion rate of the output voltage; and

The pull-up stopping adjusting unit is coupled with the pull-up adjusting unit and used for stopping adjusting the pull-up or the pull-down of the upper bridge switch or the gate-source voltage of the lower bridge switch according to a preset threshold value;

wherein, the voltage difference between a high power voltage and a low power voltage of the conversion rate adjusting circuit is lower than the voltage difference between a power voltage and a ground potential;

Wherein the power supply voltage is higher than the input voltage and the output voltage.

2. The half-bridge driver of claim 1, wherein the at least one slew rate adjustment circuit comprises an upper-bridge-adjusted pull-up slew rate adjustment circuit, an upper-bridge-adjusted pull-down slew rate adjustment circuit, a lower-bridge-adjusted pull-up slew rate adjustment circuit, and/or a lower-bridge-adjusted pull-down slew rate adjustment circuit.

3. The half-bridge driver of claim 2, wherein the pull-up adjustment unit adjusts the pull-up or pull-down of the gate-source voltage of the upper bridge switch or the lower bridge switch for an adjustment period, and the adjustment period is related to the pulse width of the predetermined pulse, the predetermined threshold value and/or the level of the pull-up adjustment control signal.

4. The half-bridge driver of claim 3, wherein the trim pull-up unit comprises at least one MOS device and the period of the trim is related to the number of the at least one MOS device coupled in parallel.

5. The half-bridge driver of claim 3, wherein the stop adjustment pull-up unit comprises at least one diode element, and the predetermined threshold is related to a number of the at least one diode elements coupled in series.

6. The half-bridge driver of claim 3, wherein the slew rate adjusting circuit comprises the upper-bridge adjusting pull-down slew rate adjusting circuit and/or the lower-bridge adjusting pull-down slew rate adjusting circuit, and during the period of the segment adjustment, the upper-bridge adjusting pull-down slew rate adjusting circuit and/or the lower-bridge adjusting pull-down slew rate adjusting circuit adjusts the gate-source voltage of the pull-down upper-bridge switch and/or the lower-bridge switch to generate an adjusted pull-down current, which flows through the corresponding stop-adjusting pull-down unit and flows to a regulating power supply to reuse the electric energy of the adjusted pull-down current.

7. The half-bridge driver of claim 3, wherein the stop adjust pull unit is a unidirectional conductive element to prevent current flow back.

8. The half-bridge driver of claim 1, wherein the switch selection circuit comprises:

An upper bridge switch selection circuit for determining to turn on or off the upper bridge switch according to the control signal, and generating an upper bridge power supply current or an upper bridge current to correspondingly pull up or pull down the gate-source voltage of the upper bridge switch, so as to turn on or off the upper bridge switch; and

The lower bridge switch selection circuit is used for determining to turn on or off the lower bridge switch according to the control signal, generating a lower bridge power supply current or a lower bridge drawing current, and correspondingly pulling up or pulling down the gate-source voltage of the lower bridge switch so as to turn on or off the lower bridge switch;

Wherein the power supply current comprises the upper bridge power supply current or the lower bridge power supply current;

wherein the current draw includes the upper bridge current draw or the lower bridge current draw.

9. The half-bridge driver of claim 8, further comprising a level shift circuit for shifting a level of the control signal to be input to the upper bridge switch selection circuit.

10. The half-bridge driver of claim 4, wherein the at least one MOS device in the adjusting pull-up unit of the upper-bridge adjusting pull-down slew rate adjusting circuit has a withstand voltage higher than a voltage difference between the input voltage and the ground potential.

11. The half-bridge driver of claim 5, wherein the at least one diode element of the stop-adjust pull-up unit of the upper-bridge-adjust-up-slew-rate adjustment circuit has a withstand voltage higher than a voltage difference between the input voltage and the ground potential.

12. The half-bridge driver of claim 1, wherein a voltage difference between the high power supply voltage and the low power supply voltage is not higher than 5 volts and the power supply voltage is not lower than 20 volts.

13. A half-bridge driving method for driving a half-bridge circuit, wherein the half-bridge circuit includes an upper bridge switch and a lower bridge switch connected in series with each other, the half-bridge driving method comprising:

Determining to turn on or off the upper bridge switch or the lower bridge switch according to a control signal, and generating a power supply current or a drawing current, wherein the power supply current or the drawing current corresponds to the gate-source voltage of the upper bridge switch or the lower bridge switch to turn on or off the upper bridge switch or the lower bridge switch so as to convert an input voltage into an output voltage; and

A conversion rate adjustment step comprising:

generating an adjusting pull control signal with a preset pulse according to the control signal;

Adjusting the pull-up or the pull-down of the gate-source voltage of the upper bridge switch or the lower bridge switch according to the adjusting pull-up control signal to adjust the conversion rate of the output voltage; and

Stopping adjusting the pull-up or the pull-down of the gate-source voltage of the upper bridge switch or the lower bridge switch according to a preset threshold;

The conversion rate adjusting step is operated between a high power supply voltage and a low power supply voltage, and the voltage difference between the high power supply voltage and the low power supply voltage is lower than the voltage difference between a power supply voltage and a ground potential;

Wherein the power supply voltage is higher than the input voltage and the output voltage.

14. The method of claim 13, wherein the slew rate adjusting step is used to adjust an upper-bridge-adjusted pull-up slew rate, an upper-bridge-adjusted pull-down slew rate, a lower-bridge-adjusted pull-up slew rate, and/or a lower-bridge-adjusted pull-down slew rate.

15. The method of claim 14, wherein the step of adjusting the pull-up or the pull-down of the gate-source voltage of the upper bridge switch or the lower bridge switch according to the adjustment pull-up control signal comprises an adjustment period, and the adjustment period is related to the pulse width of the preset pulse, the preset threshold value and/or the level of the adjustment pull-up control signal.

16. The method of claim 15, wherein in the step of adjusting the pull-up or adjusting the pull-down of the gate-source voltage of the upper bridge switch or the lower bridge switch according to the adjustment pull-up control signal, the pull-up or adjusting the pull-down of the gate-source voltage of the upper bridge switch or the lower bridge switch is adjusted by at least one MOS device conducting the adjustment period, and the adjustment period is also related to the number of the at least MOS devices coupled in parallel.

17. The method of claim 15, wherein in the step of stopping adjusting the pull-up or pull-down of the gate-source voltage of the upper bridge switch or the lower bridge switch according to a predetermined threshold, the at least one diode element is coupled in series to determine to stop adjusting the pull-up or pull-down of the gate-source voltage of the upper bridge switch or the lower bridge switch, and the predetermined threshold is related to the number of the at least one diode element coupled in series.

18. The half-bridge driving method as claimed in claim 15, wherein the slew rate adjusting step is used for adjusting the upper-bridge adjusting pull-down slew rate and/or the lower-bridge adjusting pull-down slew rate, and during the period of the segment adjustment, the slew rate adjusting step generates an adjusting pull-down current flowing to an adjusting power supply to reuse the electric energy of the adjusting pull-down current.

19. The method of claim 15, wherein the step of stopping adjusting the pull-up or adjusting the pull-down of the gate-source voltage of the upper bridge switch or the lower bridge switch uses a unidirectional conductive element to prevent current from flowing backward.

20. The method of claim 16, wherein the at least one MOS device has a withstand voltage higher than a voltage difference between the input voltage and the ground potential.

21. The method of claim 17, wherein the at least one diode element used in the step of adjusting the gate-source voltage of the pull-up switch has a withstand voltage higher than a voltage difference between the input voltage and the ground potential.

22. The half-bridge driving method as claimed in claim 13, wherein a voltage difference between the high power voltage and the low power voltage is not higher than 5 volts, and the power voltage is not lower than 20 volts.