CN118069568A - External device topology configuration method, data processor, device and program product - Google Patents

Abstract

The present application relates to a method for configuring the topology of an external device, a data processor, a computer device, and a computer program product. The method includes: receiving a topology configuration request; generating a topology configuration file according to the topology configuration request; generating multiple device identifiers and resource allocation information corresponding to the device identifiers according to the topology configuration file; configuring hardware resources according to the device identifiers and the resource allocation information to obtain the corresponding external device topology. This method can be used to automatically configure the external device topology based on the topology configuration request dynamically, improve the adaptability of the data processor, and meet the needs of the actual application environment. The number of devices or the allocation of resources can be adjusted through the topology configuration request, ensuring the scalability of the data processor and the device equipped with the data processor. Through the automated configuration method, the configuration efficiency of the external device topology can be improved.

Description

External device topology configuration method, data processor, device and program product

Technical Field

The present application relates to the technical field of data processors, and in particular to an external device topology configuration method, a data processor, a computer device, and a computer program product.

Background technique

With the development of cloud computing and big data technology, massive data processing and massive data calculation have become an extremely important issue. In order to unload the pressure of the CPU (Central Processing Unit), DPU (Data Processing Unit) came into being. At present, whether it is based on FPGA (Field Programmable Gate Array) or ASIC (Application Specific Integrated Circuit) card, DPU can provide network functions and storage functions. The core of the current system framework is the management and simulation of PCIE (Peripheral Component Interconnect Express) devices. The current DPU network card can only realize fixed topology. Due to the limitation of PCIE BUS (PCIE bus) allocation on the server BIOS (Basic Input Output System) on the HOST side, the adaptability of DPU network card is poor.

Summary of the invention

Based on this, it is necessary to provide an external device topology configuration method, a data processor, a computer device, and a computer program product to address the above technical problems, which can automatically configure the external device topology based on the topology configuration request dynamically and improve the adaptability of the data processor.

In a first aspect, the present application provides a method for configuring external device topology. The method comprises:

receiving a topology configuration request;

Generate a topology configuration file according to the topology configuration request;

Generate multiple device identifiers and resource allocation information corresponding to the device identifiers according to the topology configuration file;

Hardware resources are configured according to the device identification and the resource allocation information to obtain a corresponding external device topology.

In one embodiment, the method further comprises:

intercepting a transaction layer data packet containing an external device identifier, wherein the external device identifier is obtained when a device equipped with the data processor scans an external device connected to a PCIE bus;

Binding the external device identifier with the generated device identifier to obtain mapping information;

The hardware resources are updated according to the mapping information.

In one embodiment, generating a topology configuration file according to the topology configuration request includes:

In the case that there is a topology model in the preset topology resource library that matches the topology configuration request, a topology configuration file is generated according to the matched topology model.

In one embodiment, the method further comprises:

If there is no topology model matching the topology configuration request in the preset topology resource library, analyzing based on the first performance information of the data processor, the second performance information of the device equipped with the data processor, and the topology configuration request to obtain a target topology structure;

A topology configuration file is generated according to the target topology structure.

In one embodiment, the obtaining of the target topology structure by analyzing based on the first performance information of the data processor, the second performance information of the device equipped with the data processor, and the topology configuration request includes:

When it is determined according to the first performance information that the topology configuration request does not exceed the first resource limit, and when it is determined according to the second performance information that the topology configuration request does not exceed the second resource limit, a target topology structure is generated according to the topology configuration request.

In one of the embodiments, the hardware resources include at least one of register resources, IO resources or address routing resources.

In one embodiment, after intercepting the transaction layer data packet including the external device identifier, the method further comprises:

In the case where it is determined based on the address routing resource that the transaction layer data packet is used to access the configuration space, performing a step of binding the external device identifier with the generated device identification to obtain mapping information;

When it is determined based on the address routing resource that the transaction layer data packet is used to access the doorbell address, data corresponding to the transaction layer data packet on the device equipped with the data processor is moved to a target IO queue; the target IO queue is an IO resource corresponding to the external device identifier.

In a second aspect, the present application further provides a data processor. The data processor comprises:

The scheduling center module is used to receive topology configuration requests;

A topology generation module, used to generate a topology configuration file according to the topology configuration request;

The firmware implementation module is used to generate multiple device identifiers and resource allocation information corresponding to the device identifiers according to the topology configuration file; configure hardware resources according to the device identifiers and the resource allocation information to obtain corresponding external device topology.

In one of the embodiments, the data processor further includes a hardware implementation module;

The hardware implementation module is used to intercept a transaction layer data packet containing an external device identifier, and forward the transaction layer data packet to the firmware implementation module, wherein the external device identifier is obtained when the device equipped with the data processor scans an external device connected to the PCIE bus;

The firmware implementation module is further used to bind the external device identifier with the generated device identification to obtain mapping information; and update the hardware resources according to the mapping information.

In one of the embodiments, the topology generation module is specifically configured to generate a topology configuration file according to the matched topology model when there is a topology model in a preset topology resource library that matches the topology configuration request.

In one of the embodiments, the topology generation module is specifically used to obtain a target topology structure by analyzing based on first performance information of the data processor, second performance information of a device equipped with the data processor, and the topology configuration request when there is no topology model matching the topology configuration request in a preset topology resource library; and generate a topology configuration file according to the target topology structure.

In one of the embodiments, the topology generation module is specifically used to generate a target topology structure according to the topology configuration request when it is determined according to the first performance information that the topology configuration request does not exceed the first resource limit and when it is determined according to the second performance information that the topology configuration request does not exceed the second resource limit.

In one of the embodiments, the hardware resources include at least one of register resources, IO resources or address routing resources.

In one of the embodiments, the hardware implementation module is specifically used to forward the transaction layer data packet to the firmware implementation module when it is determined based on the address routing resources that the transaction layer data packet is used to access the configuration space; when it is determined based on the address routing resources that the transaction layer data packet is used to access the doorbell address, move the data corresponding to the transaction layer data packet on the device equipped with the data processor to a target IO queue; the target IO queue is the IO resource corresponding to the external device identifier.

In a third aspect, the present application further provides a computer device, wherein the computer device comprises the data processor as described above.

In a fourth aspect, the present application further provides a computer program product, wherein the computer program product comprises a computer program, and when the computer program is executed by a processor, the steps of the external device topology configuration method described above are implemented.

The above-mentioned external device topology configuration method, data processor, computer device, and computer program product receive a topology configuration request; generate a topology configuration file according to the topology configuration request; generate multiple device identifiers and resource allocation information corresponding to the device identifiers according to the topology configuration file; configure hardware resources according to the device identifiers and resource allocation information to obtain the corresponding external device topology. Through the above-mentioned method, the external device topology can be automatically configured based on the topology configuration request dynamically, the adaptability of the data processor can be improved, and the requirements of the actual application environment can be met. The number of devices or the allocation of resources can be adjusted through the topology configuration request, which ensures the scalability of the data processor and the device equipped with the data processor. Through the automated configuration method, the configuration efficiency of the external device topology can be improved.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is an application environment diagram of a method for configuring external device topology in one embodiment;

FIG2 is a schematic diagram of a flow chart of a method for configuring a topology of an external device in one embodiment;

FIG3 is a schematic diagram of a flow chart of a method for configuring external device topology in another embodiment;

FIG4 is a schematic diagram of a topology verification process in one embodiment;

FIG5 is a block diagram of a data processor in one embodiment;

FIG6 is a block diagram of a data processor in another embodiment;

FIG. 7 is a diagram showing the internal structure of a computer device in one embodiment.

Detailed ways

In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

The external device topology configuration method provided in the embodiment of the present application can be applied to the application environment shown in Figure 1. Among them, the data processing system includes a data processor 102, and a device 104 equipped with the data processor 102. The data processor 102 is used to unload the pressure of the CPU on the device 104 so that the device 104 can exert the maximum computing power. Taking Figure 1 as an example, the data processor 102 manages multiple network interface cards (Network Interface Card, NIC) and multiple solid-state drives (Solid State Drives, SSD). These external devices communicate with the device 104 through the PCIE bus (in actual applications, they can also communicate with the PCI bus) to form an external device topology (PCIE topology or PCI topology). Traditional DPU network cards can only achieve fixed topologies. The data processor 102 of this embodiment can dynamically automatically configure the external device topology based on the topology configuration request, and adapt to the device 104 applied to different scenarios. Among them, the device 104 can be, but is not limited to, various personal computers, laptops, smart phones, servers, etc. In one implementation method, the device 104 can be implemented with an independent server or a server cluster consisting of multiple servers.

In one embodiment, as shown in FIG. 2 , a method for configuring a topology of an external device is provided, and the method is applied to the data processor 102 in FIG. 1 as an example for description, including the following steps:

Step 202: Receive a topology configuration request.

Among them, the topology configuration request is a specific setting requirement or adjustment requirement for the external device topology. In one implementation, a configuration interface is preset, and the topology configuration request input by the user is received through the configuration interface. The topology configuration request includes parameters such as the number of devices, device type, resource requirements, and device characteristics. The external device refers to a PCIE device (or PCI device) mounted on a PCIE bus (or PCI bus). It can be understood that the external device topology configuration method in this embodiment can be applied to the PCI bus and other similar buses in addition to the PCIE bus, and this embodiment does not limit this.

In one implementation, a device equipped with a data processor provides a graphical configuration management tool, and a user can select configuration options for external device topology on the interface where the configuration management tool runs according to configuration requirements, generate a topology configuration request based on the interface operation, and call the configuration interface of the data processor to pass the topology configuration request to the data processor.

Optionally, the topology configuration request is recorded in the form of a form, refer to the following Table 1, which shows a requirement form for a topology configuration request. Among them, bar is Base Address Register, which represents the base address of the device in the system address space. Sriov is Single Root I/O Virtualization, which is a hardware-based virtualization technology. VF is Virtual Function, which refers to the decomposition of device functions in hardware devices through virtualization technology so that multiple virtual machines or containers can monopolize part of the device resources. ARI refers to Alternative Routing-ID, that is, alternative routing ID, which is a mechanism that supports partial or complete replacement of Routing ID. DP is Downstream Port, which refers to a downstream device or port in the PCIE topology structure. UP is Upstream Port, which refers to an upstream device or port in the PCIE topology structure. ACS is Access Control Services, which refers to access control services.

Table 1:

Step 204: Generate a topology configuration file according to the topology configuration request.

A topology configuration file that supports software reading is generated according to the parameters carried in the topology configuration request. In one implementation, a configuration template is pre-created, the configuration template includes configuration options and parameters, and the configuration template is modified and supplemented according to the topology configuration request to generate a topology configuration file.

Optionally, the configuration parameters in the topology configuration request are integrated, and the configuration parameters are verified and analyzed for rationality, and a topology configuration file is generated based on the verified configuration parameters.

Step 206: Generate multiple device identifiers and resource allocation information corresponding to the device identifiers according to the topology configuration file.

Among them, the topology configuration file is parsed, the user's topology intention is analyzed, multiple external devices are simulated, a device identifier is generated for each simulated external device, and the resource allocation information of each simulated external device is determined according to the configuration. The resource allocation information is the specific resource details allocated to each simulated external device, ensuring that each simulated external device can obtain the resources required for its normal operation, and the allocation of these resources is reasonable, effective and does not conflict with each other.

In one implementation, the resource allocation information includes at least configuration space information and IO (input and output) resource information, and a control plane program and a data plane program are provided on the data processor, wherein the control plane program is responsible for simulating the configuration space of the external device, and the data plane program is responsible for processing the IO resources of the external device.

Step 208: configure hardware resources according to the device identification and resource allocation information to obtain a corresponding external device topology.

Among them, hardware resources are allocated to each simulated external device according to the device identification and resource allocation information, so that the hardware is abstracted into multiple PCIE devices mounted on the PCIE bus. Through the software-defined hardware method, the dynamic configuration of the PCIE topology is realized.

In one implementation, the data processor is configured to implement an upstream (UP) interface in an external device topology, and at least one PCIE switch is mounted according to configuration requirements. Each switch includes multiple downstream ports. The downstream ports of the switch can be connected to EP (Endpoint, terminal device, also known as PCIE device), bridge, or upstream port of other switches. The specific topology can be configured according to actual needs.

It can be understood that the data processor appears as a network card at the physical level. Through the configuration of this embodiment, after the data processor is loaded on the target device, the target device identifies the data processor as multiple PCIE devices on the PCIE bus. Each PCIE device has at least one function. The configuration of the PCIE topology structure can be achieved by configuring hardware resources.

In the above external device topology configuration method, a topology configuration request is received; a topology configuration file is generated according to the topology configuration request; a plurality of device identifiers and resource allocation information corresponding to the device identifiers are generated according to the topology configuration file; hardware resources are configured according to the device identifiers and resource allocation information to obtain the corresponding external device topology. Through the above method, the external device topology can be automatically configured based on the topology configuration request dynamically, the adaptability of the data processor can be improved, and the requirements of the actual application environment can be met. The number of devices or the allocation of resources can be adjusted through the topology configuration request, which ensures the scalability of the data processor and the device equipped with the data processor. Through the automated configuration method, the configuration efficiency of the external device topology can be improved.

In one embodiment, as shown in FIG3 , the method further includes:

Step 302: intercepting a transaction layer data packet containing an external device identifier, where the external device identifier is obtained when a device equipped with a data processor scans an external device connected to a PCIE bus.

Among them, the device equipped with a data processor (the server is used as an example in this embodiment) will initiate a scan of the PCIE device after power-on, and assign a device identifier to the scanned PCIE device. The device identifier is a string or code used to uniquely identify and recognize an external device. On the PCIE bus, the device identifier is BDF (Bus number, Device number, Function number).

In one implementation, the server performs PCIE device scanning through hardware resources of a data processor and allocates an external device identifier to each simulated external device.

When the server uses an external device mounted on the PCIE bus to process data, a transaction layer packet (TLP) is intercepted by the data processor.

Step 304: Bind the external device identifier with the generated device identifier to obtain mapping information.

The control plane program running on the data processor binds the external device identifier assigned by the server with the device identifier simulated and generated by the data processor to obtain mapping information (MAP).

Step 306: Update the hardware resources according to the mapping information.

Among them, by updating the mapping information on the hardware resources, the external device simulated by the data processor can determine the external device identification on the server side based on the mapping relationship, ensuring the consistency of the device identification on the data processor and the server, which is beneficial to data transmission between the server and the PCIE device.

In this embodiment, the external device identifier assigned by the server is bound to the device identifier simulated and generated by the data processor, which can improve the compatibility between the data processor and the server.

In one embodiment, step 206 includes: if there is a topology model in the preset topology resource library that matches the topology configuration request, generating a topology configuration file according to the matched topology model.

The data processor is provided with a preset topology resource library, in which at least one topology model is stored, and the parameters carried in the topology configuration request are compared with each topology model to determine whether there is a topology model in the preset topology resource library that matches the topology configuration request. In one implementation, the preset topology resource library stores topology models corresponding to multiple server types, and according to the collected current server type, at least one topology model corresponding to the current server type is obtained from the preset topology resource library, and the parameters carried in the topology configuration request are compared with each obtained topology model to determine whether there is a topology model in the preset topology resource library that matches the topology configuration request.

In one implementation, the matched topology model is parsed to extract necessary information for generating a configuration file, and the configuration template is modified and supplemented with the extracted information to generate a topology configuration file.

In one embodiment, the method also includes: when there is no topology model matching the topology configuration request in the preset topology resource library, analyzing based on the first performance information of the data processor, the second performance information of the device equipped with the data processor and the topology configuration request to obtain the target topology structure; generating a topology configuration file according to the target topology structure.

The first performance information includes at least the capability of the data processor, and the second performance information includes at least the capability of the server (ie, the device equipped with the data processor) and the number of devices that can be supported.

The data processor is provided with a collection program, and the second performance information is collected through the collection program. In one implementation, referring to Table 2 and Table 3, the second performance information includes the number of HOST BRIGEs, the number of PCI domains, the firmware type, the firmware version, and the OS (operating system). Table 3 shows the details of each host bridge.

Table 2:

table 3:

In Table 2, UEFI/BIOS refers to the computer basic input/output system (Basic Input/Output System) based on the Unified Extensible Firmware Interface (Unified Extensible Firmware Interface); centos is the Community Enterprise Operating System, which refers to the community enterprise operating system. In Table 3, Name refers to the main bridge name, Device-id refers to the device identifier; vendor-id refers to the vendor identification number; BUS refers to the bus; Cap refers to capability (Capability); ACS is the access control service; ATS is the address translation service.

The performance information of the data processor is matched with the user's needs, and the performance information of the server is matched with the user's needs, to ensure that the generated target topology structure meets the user's needs while being supported by the data processor performance and the server performance.

In one implementation, a topology branch is determined based on the number of devices and the second performance information, and topology nodes consistent with the number of devices are generated on the topology branch. Attributes of each topology node are generated based on device type, resource requirements, and device characteristics to obtain a target topology structure.

In one implementation, the target topology structure is parsed to extract necessary information for generating a configuration file, and the configuration template is modified and supplemented with the extracted information to generate a topology configuration file.

In one embodiment, a target topology structure is obtained based on analysis of first performance information of a data processor, second performance information of a device equipped with the data processor, and a topology configuration request, including: when it is determined according to the first performance information that the topology configuration request does not exceed the first resource limit, and when it is determined according to the second performance information that the topology configuration request does not exceed the second resource limit, generating the target topology structure according to the topology configuration request.

The first resource limitation refers to the resource limitation of the data processor, and the second resource limitation refers to the resource limitation of the server. Specifically, the first performance information of the data processor, the second performance information of the server, and the user's needs are integrated and rationally checked to determine whether the topology configuration request exceeds the first resource limitation, and to determine whether the topology configuration request exceeds the second resource limitation. In one implementation, a configuration template is pre-created, and the configuration template includes configuration options and parameters. After the rationality check passes, the configuration template is modified and supplemented according to the topology configuration request to generate a topology configuration file.

In one implementation, referring to FIG. 4 , the analysis process specifically includes information integration, rationality check, and topology analysis. The information integration step includes: counting the total number of devices in the topology configuration request, the total size of the BAR space, the total demand for IO queues, the CAP (i.e., Capability) characteristics of the device, counting the CAP of the data processor, counting the upper limit of the devices that the server can carry, and the maximum CAP range of the server, wherein the BAR space refers to the register area. The rationality check step includes: determining whether the total size of the BAR space, the total demand for IO queues, and the CAP of the device exceed the CAP of the data processor; if not, determining whether the total number of devices is greater than the upper limit of the devices that the server can carry; if the total number of devices does not exceed the upper limit, determining whether the CAP of the device is mutually exclusive with the CAP range of the server; if the CAP matches, performing topology analysis. The steps of topology analysis include: determining whether the total number of devices is greater than 32, determining whether the total number of devices is less than 255, determining whether the devices support sriov, and determining whether the devices support ARI. When the total number of devices is greater than 32 and less than 255, and the devices support sriov and ARI, determine whether a single bus meets the requirements; when the total number of devices is less than 32, use the Device (device number) in the BDF to mark each simulated external device; when the total number of devices is greater than 255, add a new switch to the topology.

Through the method of this embodiment, the resources of the data processor and the server can be fully utilized, and the topology of the external device simulated by the data processor can be flexibly modified to meet the needs of users while meeting hardware limitations; failures caused by unreasonable configuration can be avoided, and the stability of the data processor and the server is improved.

In one embodiment, the hardware resources include at least one of register resources, IO resources, or address routing resources.

Among them, the register resource is used to store the configuration space information of the simulated external device, the IO resource refers to the IO queue of the simulated external device, and the address routing resource is used to mark the routing or addressing mechanism related to the simulated external device.

In one implementation, the data processor is provided with a data plane program and a control plane program, and the control plane program receives a topology configuration file, determines multiple device identifiers and configuration space resources for each device identifier, configures registers in the data processor hardware, and completes the configuration and initialization of the registers. The control plane program determines the allocation of IO queues based on the topology configuration file, notifies the data plane program of the allocation of IO queues through a message queue, and the data plane program allocates a ring buffer (ring message buffer) between the firmware and the hardware, and allocates resources in the hardware's IO queue. The control plane program receives the initialization result of the data plane program, establishes a MAP (mapping) relationship between the IO queue number and the device number, and configures them in the hardware register. The control plane program is also used to configure the address routing resources in the data processor hardware.

In one embodiment, after step 302, the method further includes: executing step 304 when it is determined based on the address routing resources that the transaction layer data packet is used to access the configuration space; when it is determined based on the address routing resources that the transaction layer data packet is used to access the doorbell address, moving data corresponding to the transaction layer data packet on the device equipped with the data processor to a target IO queue; the target IO queue is the IO resource corresponding to the external device identifier.

The data processor determines whether the transaction layer data packet is used to access the configuration space or the doorbell (DB) address through the address routing resource. In the case of accessing the configuration space, the data processor calls the control plane program to process the transaction layer data packet. In the case of accessing the doorbell address, the data processor calls the preset controller to move the corresponding data of the transaction layer data packet on the server to the target IO queue for the next step of processing.

In one implementation, a TLP queue is provided, and a data processor polls (POLL) the TLP queue, receives a message sent to a PCIE device, calls a control plane program for processing, encapsulates the processing result into a TLP message, and sends the result to a server via the TLP queue.

Through the method of this embodiment, it is possible to isolate the access to the configuration space from the access to the doorbell address, reduce potential conflicts and errors, and improve the stability of the data processor and the server.

It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

Based on the same inventive concept, the embodiment of the present application also provides an external device topology configuration device for implementing the external device topology configuration method involved above. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme recorded in the above method, so the specific limitations in one or more external device topology configuration device embodiments provided below can refer to the limitations of the external device topology configuration method above, and will not be repeated here.

In one embodiment, as shown in FIG5 , a data processor is provided, including:

The scheduling center module 502 is used to receive a topology configuration request.

The topology generation module 504 is used to generate a topology configuration file according to a topology configuration request.

The firmware implementation module 506 is used to generate multiple device identifiers and resource allocation information corresponding to the device identifiers according to the topology configuration file; configure hardware resources according to the device identifiers and resource allocation information to obtain corresponding external device topology.

In the above data processor, a topology configuration request is received; a topology configuration file is generated according to the topology configuration request; a plurality of device identifiers and resource allocation information corresponding to the device identifiers are generated according to the topology configuration file; hardware resources are configured according to the device identifiers and resource allocation information to obtain the corresponding external device topology. Through the above method, the external device topology can be automatically configured based on the topology configuration request dynamically, thereby improving the adaptability of the data processor and meeting the requirements of the actual application environment. The number of devices or the allocation of resources can be adjusted through the topology configuration request, thereby ensuring the scalability of the data processor and the device equipped with the data processor. Through the automated configuration method, the configuration efficiency of the external device topology can be improved.

In one embodiment, the data processor further comprises a hardware implementation module;

A hardware implementation module, used to intercept a transaction layer data packet containing an external device identifier, and forward the transaction layer data packet to the firmware implementation module 506, wherein the external device identifier is obtained when the device equipped with the data processor scans the external device connected to the PCIE bus;

The firmware implementation module 506 is further used to bind the external device identifier with the generated device identifier to obtain mapping information; and update the hardware resources according to the mapping information.

In one embodiment, the topology generation module 504 is specifically configured to generate a topology configuration file according to the matched topology model when there is a topology model in the preset topology resource library that matches the topology configuration request.

In one embodiment, the topology generation module 504 is specifically used to obtain a target topology structure by analyzing the first performance information of the data processor, the second performance information of the device equipped with the data processor, and the topology configuration request when there is no topology model matching the topology configuration request in the preset topology resource library; and generate a topology configuration file according to the target topology structure.

In one embodiment, the topology generation module 504 is specifically used to generate a target topology structure according to the topology configuration request when it is determined according to the first performance information that the topology configuration request does not exceed the first resource limit and when it is determined according to the second performance information that the topology configuration request does not exceed the second resource limit.

In one embodiment, the hardware resources include at least one of register resources, IO resources, or address routing resources.

In one embodiment, the hardware implementation module is specifically used to forward the transaction layer data packet to the firmware implementation module 506 when it is determined based on the address routing resources that the transaction layer data packet is used to access the configuration space; when it is determined based on the address routing resources that the transaction layer data packet is used to access the doorbell address, the corresponding data of the transaction layer data packet on the device equipped with the data processor is moved to the target IO queue; the target IO queue is the IO resource corresponding to the external device identifier.

In one implementation, refer to FIG. 6 , which shows a block diagram of another data processor. The device equipped with the data processor is a server, and the data processor (hereinafter referred to as DPU) includes a scheduling center module, a topology generation module, a firmware implementation module, and a hardware implementation module. Among them:

1. The dispatch center module includes user management, resource management and equipment dispatching layer.

User management is responsible for receiving topology configuration requests from users (including topology requirements for PCIE) and forwarding them to the topology generation module. User management can also be responsible for receiving user selection instructions for topology targets. The resource management module is responsible for managing the resources of the DPU and can provide the first performance information of the DPU for topology analysis. The device scheduling layer is used to receive topology configuration files and send them to the firmware implementation module for device creation and external device topology configuration.

2. The topology generation module includes a BIOS/UEFI acquisition module, a server information acquisition module, a topology resource library, a user topology injection module, and a user topology analysis module.

The BIOS/UEFI acquisition module and the server information acquisition module are responsible for processing and analyzing the information of the server's PCI BUS resources. Optionally, use the cloud disk startup mode of the DPU to pull up the server once, execute the acquisition command through the information acquisition Agent in the test cloud disk, and output it to the Server. For example, execute the acquisition script lspci -tv in the Agent to view the current server information collection and summarize the collected information.

The topology resource library stores all topologies supported by the adapted server type. Optionally, the topology generation module sends the topology model supported by the server in the topology resource library to the dispatch center, which then feeds back to the user for the next step. The user can first query from the topology resource library. If there is a topology that meets the requirements, the topology configuration file is directly generated using the topology. If not, the topology injection and analysis are used to determine the topology that meets the user's requirements.

The user injection module organizes the topology configuration requests; the user topology analysis module verifies the rationality of user requirements, and the topology generation module determines the topology structure that meets user requirements, generates a topology configuration file and sends it to the scheduling center, which then sends it to the firmware implementation module for further processing.

3. The firmware implementation module includes a data plane unit, a control plane unit, and a hardware interface HAL layer (Hardware Abstraction Layer). The control plane unit includes a register management module, an analog module, a TLP encoding and decoding module, and a message interface layer. The data plane unit includes a storage IO management module, a network IO management module, and a message interface layer. The firmware implementation module and the hardware implementation module exchange data through an interconnect bus.

The control plane unit is used to receive the topology configuration file, analyze the topology configuration, determine multiple device identifiers and the configuration space resources of each device identifier, call the register management module to operate the hardware interface HAL layer to configure the registers in the DPU hardware, and complete the configuration and initialization of the registers.

The control plane unit notifies the data plane unit of the allocation of the IO queue through the message interface layer. Based on the received information, the storage IO management module and the network IO management module of the data plane unit allocate resources in the IO queue of the DPU hardware through the hardware interface HAL layer.

The control plane unit receives the initialization result of the data plane unit, establishes a MAP (mapping) relationship between the IO queue number and the device number, and configures it in the register of the DPU hardware.

The control plane unit configures the address routing module in the DPU hardware through the hardware interface HAL layer.

The TLP codec module is used to call the hardware interface HAL layer, receive and decode the TLP messages sent by the DPU hardware, and send the decoded messages to the simulation module; the TLP codec module is also used to assemble local messages into TLP messages of external devices and send them to the DPU hardware.

The simulation module is used to allocate configuration space resources for each simulated external device, parse the message sent by the TLP codec module, simulate the local PCIE device (or PCI device), and pass the processing result to the TLP codec module. In this way, the external device topology can be configured based on the control plane unit, and the external device can be simulated to process data.

4. The hardware implementation module includes the UP (upstream) hardware implementation layer, registers, IO queues, TLP queues, address routing modules, and DMA (Direct Memory Access) controllers. The hardware implementation module and the server exchange data through the PCIE interface.

The server initiates a scan of the PCIE device after power-on. The UP hardware implementation layer intercepts the TLP message and passes it to the address routing module. The address routing module checks whether the TLP message is an access to the configuration space of the PCIE device or an access to the Doorbell address of the PCIE device.

If it is a configuration space access, the address routing module calls the DMA controller to send the TLP message to the hardware interface HAL layer of the firmware implementation module. The TLP codec module of the DPU firmware implementation module continuously POLLs the TLP queue of the device. When it is determined that a message has arrived, the TLP message is sent to the control plane unit for processing. After processing, the control plane unit encapsulates the processing result into a TLP message and adds it to the TLP queue. Call the Doorbell interface of the hardware interface HAL layer to notify the hardware. The DPU hardware receives the notification and calls the DMA controller to send the TLP data to the server through the UP hardware implementation layer. In this way, the control plane program of the firmware implementation module simulates the PCIE device for data processing. In this process, the simulation module binds the BDF assigned by the server to each device and the device number assigned on the DPU firmware implementation module, and updates the bound MAP relationship to the register of the DPU hardware.

If it is a Doorbell address access, the address routing module recognizes that the server is sending and receiving data, and the DPU hardware calls the DMA controller to move the DMA data of the PCIE device on the server to the IO queue of the PCIE device for the next step of processing.

Each module in the above-mentioned external device topology configuration device can be implemented in whole or in part by software, hardware and a combination thereof. Each of the above-mentioned modules can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory in the computer device in the form of software, so that the processor can call and execute the operations corresponding to each of the above modules.

In one embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be shown in FIG7. The computer device includes a processor, a memory, an input/output interface (Input/Output, referred to as I/O) and a communication interface. The processor, the memory and the input/output interface are connected via a system bus, and the communication interface is connected to the system bus via the input/output interface. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The input/output interface of the computer device is used to exchange information between the processor and an external device. The communication interface of the computer device is used to communicate with an external terminal via a network connection. When the computer program is executed by the processor, a method for configuring the topology of an external device is implemented.

Those skilled in the art will understand that the structure shown in FIG. 7 is merely a block diagram of a partial structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than shown in the figure, or combine certain components, or have a different arrangement of components.

In one embodiment, a computer device is provided, comprising a data processor as described in any one of the above embodiments; the data processor comprises:

The scheduling center module is used to receive topology configuration requests;

A topology generation module, used to generate a topology configuration file according to a topology configuration request;

The firmware implementation module is used to generate multiple device identifications and resource allocation information corresponding to the device identifications according to the topology configuration file; configure hardware resources according to the device identifications and resource allocation information to obtain corresponding external device topology.

In one embodiment, the data processor further comprises a hardware implementation module;

The hardware implementation module is used to intercept the transaction layer data packet containing the external device identifier and forward the transaction layer data packet to the firmware implementation module. The external device identifier is obtained when the device equipped with the data processor scans the external device connected to the PCIE bus;

The firmware implementation module is also used to bind the external device identifier with the generated device identifier to obtain mapping information; and update the hardware resources according to the mapping information.

In one embodiment, the topology generation module is specifically configured to generate a topology configuration file according to the matched topology model when there is a topology model in a preset topology resource library that matches the topology configuration request.

In one embodiment, a topology generation module is specifically used to obtain a target topology structure by analyzing first performance information of a data processor, second performance information of a device equipped with a data processor, and a topology configuration request when there is no topology model matching a topology configuration request in a preset topology resource library; and generate a topology configuration file according to the target topology structure.

In one embodiment, the topology generation module is specifically used to generate a target topology structure according to the topology configuration request when it is determined according to the first performance information that the topology configuration request does not exceed the first resource limit and when it is determined according to the second performance information that the topology configuration request does not exceed the second resource limit.

In one embodiment, the hardware resources include at least one of register resources, IO resources, or address routing resources.

In one embodiment, the hardware implementation module is specifically used to forward the transaction layer data packet to the firmware implementation module when it is determined based on the address routing resources that the transaction layer data packet is used to access the configuration space; when it is determined based on the address routing resources that the transaction layer data packet is used to access the doorbell address, the corresponding data of the transaction layer data packet on the device equipped with the data processor is moved to the target IO queue; the target IO queue is the IO resource corresponding to the external device identifier.

In one embodiment, a computer program product is provided, including a computer program, which, when executed by a processor, implements the following steps: receiving a topology configuration request; generating a topology configuration file according to the topology configuration request; generating multiple device identifiers and resource allocation information corresponding to the device identifiers according to the topology configuration file; configuring hardware resources according to the device identifiers and the resource allocation information to obtain a corresponding external device topology.

In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: intercepting a transaction layer data packet containing an external device identifier, where the external device identifier is obtained by a device equipped with a data processor when scanning an external device connected to a PCIE bus; binding the external device identifier with the generated device identifier to obtain mapping information; and updating hardware resources according to the mapping information.

In one embodiment, when the computer program is executed by the processor, the following steps are further implemented: when there is a topology model in the preset topology resource library that matches the topology configuration request, a topology configuration file is generated according to the matched topology model.

In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: when there is no topology model matching the topology configuration request in the preset topology resource library, analyzing based on the first performance information of the data processor, the second performance information of the device equipped with the data processor, and the topology configuration request to obtain the target topology structure; generating a topology configuration file according to the target topology structure.

In one embodiment, when the computer program is executed by a processor, the following steps are also implemented: when it is determined based on the first performance information that the topology configuration request does not exceed the first resource limit, and when it is determined based on the second performance information that the topology configuration request does not exceed the second resource limit, a target topology structure is generated based on the topology configuration request.

In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: when it is determined based on the address routing resources that the transaction layer data packet is used to access the configuration space, the step of binding the external device identifier with the generated device identifier to obtain mapping information is executed; when it is determined based on the address routing resources that the transaction layer data packet is used to access the doorbell address, the data corresponding to the transaction layer data packet on the device equipped with the data processor is moved to the target IO queue; the target IO queue is the IO resource corresponding to the external device identifier.

It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant regulations.

Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., but are not limited to this.

The technical features of the above embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims (16)

1. A method for configuring external device topology, characterized in that the method is applied to a data processor, and the method comprises: receiving a topology configuration request; Generate a topology configuration file according to the topology configuration request; Generate multiple device identifiers and resource allocation information corresponding to the device identifiers according to the topology configuration file; Hardware resources are configured according to the device identification and the resource allocation information to obtain a corresponding external device topology. 2. The method according to claim 1, characterized in that the method further comprises: intercepting a transaction layer data packet containing an external device identifier, wherein the external device identifier is obtained when a device equipped with the data processor scans an external device connected to a PCIE bus; Binding the external device identifier with the generated device identifier to obtain mapping information; The hardware resources are updated according to the mapping information. 3. The method according to claim 1, wherein generating a topology configuration file according to the topology configuration request comprises: In the case that there is a topology model in the preset topology resource library that matches the topology configuration request, a topology configuration file is generated according to the matched topology model. 4. The method according to claim 3, characterized in that the method further comprises: If there is no topology model matching the topology configuration request in the preset topology resource library, analyzing based on the first performance information of the data processor, the second performance information of the device equipped with the data processor, and the topology configuration request to obtain a target topology structure; A topology configuration file is generated according to the target topology structure. 5. The method according to claim 4, characterized in that the step of analyzing based on the first performance information of the data processor, the second performance information of the device equipped with the data processor, and the topology configuration request to obtain the target topology structure comprises: When it is determined according to the first performance information that the topology configuration request does not exceed the first resource limit, and when it is determined according to the second performance information that the topology configuration request does not exceed the second resource limit, a target topology structure is generated according to the topology configuration request. 6 . The method according to claim 2 , wherein the hardware resources include at least one of register resources, IO resources or address routing resources. 7. The method according to claim 6, characterized in that after intercepting the transaction layer data packet containing the external device identifier, the method further comprises: In the case where it is determined based on the address routing resource that the transaction layer data packet is used to access the configuration space, performing a step of binding the external device identifier with the generated device identification to obtain mapping information; When it is determined based on the address routing resource that the transaction layer data packet is used to access the doorbell address, data corresponding to the transaction layer data packet on the device equipped with the data processor is moved to a target IO queue; the target IO queue is an IO resource corresponding to the external device identifier. 8. A data processor, characterized in that the data processor comprises: The scheduling center module is used to receive topology configuration requests; A topology generation module, used to generate a topology configuration file according to the topology configuration request; The firmware implementation module is used to generate multiple device identifiers and resource allocation information corresponding to the device identifiers according to the topology configuration file; configure hardware resources according to the device identifiers and the resource allocation information to obtain corresponding external device topology. 9. The data processor according to claim 8, characterized in that the data processor further comprises a hardware implementation module; The hardware implementation module is used to intercept a transaction layer data packet containing an external device identifier, and forward the transaction layer data packet to the firmware implementation module, wherein the external device identifier is obtained when the device equipped with the data processor scans an external device connected to the PCIE bus; The firmware implementation module is further used to bind the external device identifier with the generated device identification to obtain mapping information; and update the hardware resources according to the mapping information. 10. The data processor according to claim 8 is characterized in that the topology generation module is specifically used to generate a topology configuration file according to the matching topology model when there is a topology model matching the topology configuration request in a preset topology resource library. 11. The data processor according to claim 10 is characterized in that the topology generation module is specifically used to obtain a target topology structure by analyzing based on the first performance information of the data processor, the second performance information of the device equipped with the data processor, and the topology configuration request when there is no topology model matching the topology configuration request in the preset topology resource library; and generate a topology configuration file according to the target topology structure. 12. The data processor according to claim 11 is characterized in that the topology generation module is specifically used to generate a target topology structure according to the topology configuration request when it is determined according to the first performance information that the topology configuration request does not exceed the first resource limit, and when it is determined according to the second performance information that the topology configuration request does not exceed the second resource limit. 13 . The data processor according to claim 9 , wherein the hardware resources include at least one of register resources, IO resources, or address routing resources. 14. The data processor according to claim 13 is characterized in that the hardware implementation module is specifically used to forward the transaction layer data packet to the firmware implementation module when it is determined based on the address routing resources that the transaction layer data packet is used to access the configuration space; when it is determined based on the address routing resources that the transaction layer data packet is used to access the doorbell address, move the data corresponding to the transaction layer data packet on the device loaded with the data processor to a target IO queue; the target IO queue is the IO resource corresponding to the external device identifier. 15. A computer device, comprising the data processor according to any one of claims 8 to 14. 16. A computer program product, comprising a computer program, characterized in that when the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.