CN118069555A - Data transmission method, device, electronic equipment and storage medium - Google Patents
Data transmission method, device, electronic equipment and storage medium Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
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Abstract
The application provides a data transmission method, a data transmission device, electronic equipment and a storage medium, and relates to the technical field of computers. The method comprises the following steps: receiving a transmission signal sent by a processing unit through a first queue serial peripheral interface; determining a target transmission mode between the control unit and the storage unit according to the target command, wherein the target transmission mode comprises any one of the following: a unidirectional data transmission mode, a two-wire bidirectional data transmission mode, and a four-wire bidirectional data transmission mode; according to the target transmission mode, target data is transmitted to the target address through the second queue serial peripheral interface, so that the control unit can transmit the target data to the target storage unit indicated by the target address based on any one of multiple data transmission modes, the data transmission requirements of multiple scenes can be met, and the flexibility of the data transmission method is improved, wherein when the four-wire bidirectional transmission mode is adopted for data transmission, the data transmission efficiency can be remarkably improved.
Description
Technical Field
The present application relates to the field of computer technologies, and in particular, to a data transmission method, a data transmission device, an electronic device, and a storage medium.
Background
The queue serial peripheral interface (Queued SPI, QSPI) interface is a high-speed serial communication interface which is improved and enhanced on the basis of a traditional serial communication interface (SERIAL PERIPHERAL INTERFACE, SPI), and the QSPI is downward compatible with the SPI, but has obvious improvement in performance and functions.
In the prior art, for the QSPI interface, for data security, the QSPI needs to be accessed into a field programmable gate array, where the data transmission process is mainly in a unidirectional data transmission (STANDARD SPI) mode.
However, due to the requirements of different scenes, the existing transmission method has single transmission mode and cannot meet the requirements.
Disclosure of Invention
The application aims to provide a data transmission method, a device, electronic equipment and a storage medium, which can meet the data transmission requirements of various scenes and improve the flexibility of the data transmission method.
In order to achieve the above purpose, the technical scheme adopted by the embodiment of the application is as follows:
In a first aspect, the present invention provides a data transmission method applied to a control unit, where the control unit is communicatively connected to a processing unit through a first queue serial peripheral interface, and the control unit is also communicatively connected to at least one storage unit through a second queue serial peripheral interface, the method comprising:
Receiving a transmission signal sent by a processing unit through a first queue serial peripheral interface, wherein the transmission signal comprises: target command, target address and target data;
Determining a target transmission mode between the control unit and the storage unit according to the target command, wherein the target transmission mode comprises any one of the following steps: a unidirectional data transmission mode, a two-wire bidirectional data transmission mode, and a four-wire bidirectional data transmission mode;
And transmitting target data to a target address through the second queue serial peripheral interface according to the target transmission mode, wherein the target address indicates the address of a target storage unit in at least one storage unit.
In an alternative embodiment, the receiving, by the first queue serial peripheral interface, the transmission signal sent by the processing unit includes:
acquiring each chip selection signal in the first queue serial peripheral interface;
and if any chip selection signal is in a low level, receiving a transmission signal sent by the processing unit through the first queue serial peripheral interface.
In an alternative embodiment, the transmitting, according to the target transmission mode, target data to a target address through the second queue serial peripheral interface includes:
Acquiring a current transmission mode of the control unit;
judging whether the target transmission mode is the same as the current transmission mode;
if the signal transmission directions in the second queue serial peripheral interfaces are different, switching the signal transmission directions in the second queue serial peripheral interfaces, and transmitting target data to a target address through the second queue serial peripheral interfaces;
and if the data are the same, transmitting the target data to the target address through the second queue serial peripheral interface.
In an alternative embodiment, at least one of the storage units comprises a primary storage unit and at least one backup storage unit, the method further comprising:
acquiring a main chip selection signal and at least one backup chip selection signal in the first queue serial peripheral interface;
If the main chip selection signal is in a low level, determining that the target address indicates the address of the main storage unit;
and if any backup chip selection signal is in a low level, determining that the target address indicates the address of the target backup storage unit corresponding to the backup chip selection signal.
In an alternative embodiment, the determining, according to the target command, a target transmission mode between the control unit and the storage unit includes:
analyzing the target command and acquiring a transmission mode bit corresponding to the target command;
And determining a target transmission mode between the control unit and the storage unit according to the transmission mode bit corresponding to the target command and a preset mapping relation, wherein the preset mapping relation is used for indicating the mapping relation between the transmission mode bit and the transmission mode.
In an alternative embodiment, the target command is generated by the processing unit according to a backup instruction, the backup instruction including: the target address and the target data.
In an alternative embodiment, in the unidirectional data transfer mode, the second queue serial peripheral interface includes: a first pin, a second pin, a third pin and a fourth pin;
In the unidirectional data transmission mode, the first pin is used for unidirectional transmission of output signals, the second pin is used for unidirectional transmission of input signals, the third pin is used for unidirectional transmission of output signals, and the fourth pin is used for unidirectional transmission of output signals;
In the two-wire bidirectional data transmission mode, the first pin and the second pin are used for transmitting input and output signals, the third pin is used for unidirectionally transmitting output signals, and the fourth pin is used for unidirectionally transmitting output signals;
In the four-wire bidirectional data transmission mode, the first pin, the second pin, the third pin and the fourth pin are used for transmitting input and output signals.
In an alternative embodiment, if each of the chip select signals is at a high level, the receiving of the transmission signal sent by the processing unit through the first queue serial peripheral interface is stopped.
In a second aspect, the present invention provides a data transmission device applied to a control unit, the control unit being communicatively connected to a processing unit through a first queue serial peripheral interface and to at least one storage unit through a second queue serial peripheral interface, the data transmission device comprising:
the receiving module is configured to receive, through the first queue serial peripheral interface, a transmission signal sent by the processing unit, where the transmission signal includes: target command, target address and target data;
a determining module, configured to determine a target transmission mode between the control unit and the storage unit according to the target command, where the target transmission mode includes any one of the following: a unidirectional data transmission mode, a two-wire bidirectional data transmission mode, and a four-wire bidirectional data transmission mode;
And the transmission module is used for transmitting target data to a target address through the second queue serial peripheral interface according to the target transmission mode, wherein the target address indicates the address of a target storage unit in at least one storage unit.
In an optional embodiment, the receiving module is specifically configured to obtain each chip select signal in the first queue serial peripheral interface;
and if any chip selection signal is in a low level, receiving a transmission signal sent by the processing unit through the first queue serial peripheral interface.
In an alternative embodiment, the transmission module is specifically configured to obtain a current transmission mode of the control unit;
judging whether the target transmission mode is the same as the current transmission mode;
if the signal transmission directions in the second queue serial peripheral interfaces are different, switching the signal transmission directions in the second queue serial peripheral interfaces, and transmitting target data to a target address through the second queue serial peripheral interfaces;
and if the data are the same, transmitting the target data to the target address through the second queue serial peripheral interface.
In an alternative embodiment, at least one of the storage units includes a main storage unit and at least one backup storage unit, and the transmission module is further configured to obtain a main chip select signal and at least one backup chip select signal in the first queue serial peripheral interface;
If the main chip selection signal is in a low level, determining that the target address indicates the address of the main storage unit;
and if any backup chip selection signal is in a low level, determining that the target address indicates the address of the target backup storage unit corresponding to the backup chip selection signal.
In an optional embodiment, the determining module is specifically configured to parse the target command, and obtain a transmission mode bit corresponding to the target command;
And determining a target transmission mode between the control unit and the storage unit according to the transmission mode bit corresponding to the target command and a preset mapping relation, wherein the preset mapping relation is used for indicating the mapping relation between the transmission mode bit and the transmission mode.
In an alternative embodiment, the target command is generated by the processing unit according to a backup instruction, the backup instruction including: the target address and the target data.
In an alternative embodiment, in the unidirectional data transfer mode, the second queue serial peripheral interface includes: a first pin, a second pin, a third pin and a fourth pin;
In the unidirectional data transmission mode, the first pin is used for unidirectional transmission of output signals, the second pin is used for unidirectional transmission of input signals, the third pin is used for unidirectional transmission of output signals, and the fourth pin is used for unidirectional transmission of output signals;
In the two-wire bidirectional data transmission mode, the first pin and the second pin are used for transmitting input and output signals, the third pin is used for unidirectionally transmitting output signals, and the fourth pin is used for unidirectionally transmitting output signals;
In the four-wire bidirectional data transmission mode, the first pin, the second pin, the third pin and the fourth pin are used for transmitting input and output signals.
In an alternative embodiment, the receiving module is further configured to stop receiving, if each of the chip select signals is at a high level, the transmission signal sent by the processing unit through the first queue serial peripheral interface.
In a third aspect, the present invention provides an electronic device comprising: a processor, a storage medium, and a bus, the storage medium storing machine-readable instructions executable by the processor, the processor in communication with the storage medium via the bus when the electronic device is running, the processor executing the machine-readable instructions to perform the steps of the data transmission method according to any of the preceding embodiments.
In a fourth aspect, the present invention provides a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, performs the steps of a data transmission method according to any of the preceding embodiments.
The beneficial effects of the application are as follows:
The data transmission method, the device, the electronic equipment and the storage medium provided by the embodiment of the application are applied to a control unit, the control unit is in communication connection with a processing unit through a first queue serial peripheral interface, and the control unit is also in communication connection with at least one storage unit through a second queue serial peripheral interface, and the method comprises the following steps: receiving, by the first queue serial peripheral interface, a transmission signal sent by the processing unit, the transmission signal including: target command, target address and target data; determining a target transmission mode between the control unit and the storage unit according to the target command, wherein the target transmission mode comprises any one of the following: a unidirectional data transmission mode, a two-wire bidirectional data transmission mode, and a four-wire bidirectional data transmission mode; according to the target transmission mode, the target data is transmitted to the target address through the second queue serial peripheral interface, wherein the target address indicates the address of the target storage unit in at least one storage unit.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of a data transmission system according to an embodiment of the present application;
fig. 2 is a schematic flow chart of a data transmission method according to an embodiment of the present application;
fig. 3 is a flow chart of another data transmission method according to an embodiment of the present application;
fig. 4 is a flow chart of another data transmission method according to an embodiment of the present application;
Fig. 5 is a schematic diagram of another data transmission system according to an embodiment of the present application;
fig. 6 is a flowchart of another data transmission method according to an embodiment of the present application;
Fig. 7 is a flowchart of another data transmission method according to an embodiment of the present application;
Fig. 8 is a schematic diagram of a functional module of a data transmission device according to an embodiment of the present application;
Fig. 9 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments of the present application. The components of the embodiments of the present application generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the application, as presented in the figures, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.
In the prior art, for a Queue serial peripheral interface (Queue SERIAL PERIPHERAL INTERFACE, QSPI) interface, for data security, the data transmission process is mainly in a unidirectional data transmission (STANDARD SPI) mode, and the data needs to be connected to a field programmable gate array (Field Programmable GATE ARRAY, FPGA) through the QSPI interface. However, due to the requirements of different scenes, the FPGA is required to support four-wire bidirectional data transmission (Quad SPI mode) or other transmission modes, but the existing transmission method cannot meet the requirements.
In view of this, the embodiment of the present application provides a data transmission method, which may be applied to a control unit, and the application of the embodiment of the present application makes it possible for the control unit to transmit target data to a target storage unit indicated by a target address based on any one of a plurality of data transmission modes, so as to satisfy the data transmission requirements of a plurality of scenarios and improve the flexibility of the data transmission method.
Fig. 1 is a schematic diagram of a data transmission system according to an embodiment of the present application, where, as shown in fig. 1, the data transmission system includes: the control unit 101, the processing unit 102 and the at least one storage unit 105, wherein the control unit 101 is communicatively connected to the processing unit 102 via a first queue serial peripheral interface, and the control unit 101 is also communicatively connected to the at least one storage unit 105 via a second queue serial peripheral interface.
Alternatively, the control unit may be a field programmable gate array (Field Programmable GATE ARRAY, FPGA), a microcontroller unit (Microcontroller Unit, MCU), or the like, without limitation. Optionally, the at least one memory unit may include: FLASH Memory (FLASH), read-Only Memory (ROM), random access Memory (Random Access Memory, RAM), and the like, are not limited herein. Of course, the present application is not limited to the type of FLASH, and may be NOR FLASH, or NAND FLASH.
It should be noted that, when the data transmission system includes a plurality of storage units, each storage unit may be optionally configured to store data in different scenes, or storage content types of each storage unit may be set, for example, one storage unit is mainly configured to store video data, another storage unit is mainly configured to store text data, and the like, which is not limited herein.
Fig. 2 is a schematic flow chart of a data transmission method according to an embodiment of the present application, where the method may be applied to a control unit in the data transmission system, and as shown in fig. 2, the data transmission method according to an embodiment of the present application may include:
s101, receiving a transmission signal sent by a processing unit through a first queue serial peripheral interface, wherein the transmission signal comprises: target command, target address, and target data.
Alternatively, the processing unit may be a central processing unit (Central Processing Unit, CPU), an image processing unit (Image Processing Unit, IPU), or the like, which is not limited herein.
Wherein the first queue serial peripheral interface may comprise: a plurality of first device pins, a plurality of chip select pins, and a first clock signal pin, wherein the first clock signal pin may be used to transmit a clock signal between the processing unit and the control unit, such as ft_sck; the plurality of chip select pins may be used to transmit a plurality of chip select signals, which may be used to determine whether the control unit receives the transmission signal sent by the processing unit, and in some embodiments, the plurality of chip select pins may include a first peripheral chip select pin and a second peripheral chip select pin.
Of course, the present application is not limited to the number of first device pins herein, and in some embodiments, the plurality of first device pins may include: the first peripheral pin, the second peripheral pin, the third peripheral pin and the fourth peripheral pin. In the different target transmission modes, each pin can correspondingly transmit different signals, for example, the pins are used for unidirectional transmission of input signals, unidirectional transmission of output signals, transmission of input and output signals and the like.
In some embodiments, a first peripheral pin may be used to transmit a master output slave input signal between the processing unit and the control unit; the second external pin can be used for transmitting a host input and slave output signal; the third peripheral pin may be used to transmit a write protect signal; the fourth external pin may be used to transmit a hold signal. Wherein the write protect signal may be used to prevent a status register of a memory cell in communication therewith from being written with erroneous data; the hold signal may be used to suspend operation of the memory cell.
In some embodiments, the control unit may obtain a corresponding transmission signal through the first queue serial peripheral interface, and decompose the transmission signal according to a data sequence corresponding to the transmission signal and a communication specification corresponding to a command, an address and data, so as to obtain a target command, a target address and target data respectively. The command, the address and the data in the transmission signal are displayed in the data sequence according to a preset sequence, and occupy a section of position in the data sequence respectively. Alternatively, if the transmission signal is derived in the form of a waveform, it may be presented in the form of a QSPI timing diagram.
Alternatively, the target data may be generated by the control unit itself, or may be forwarded to the control unit by another external device, or may be obtained from a storage unit, which is not limited herein.
S102, determining a target transmission mode between the control unit and the storage unit according to the target command.
Wherein the target transmission mode includes any one of the following: unidirectional data transmission mode, two-wire bidirectional data transmission mode, four-wire bidirectional data transmission mode. The target transmission mode may indicate the way in which data is interacted between the control unit and the storage unit, i.e. the target transmission mode may be direction-identified. In the unidirectional data transmission mode, commands, addresses and data are unidirectional transmission; in the two-wire bidirectional data transmission mode, the command is single-wire unidirectional transmission, the address is single-wire unidirectional transmission, and the data is two-wire bidirectional transmission; in the four-wire bidirectional data transmission mode, the command is single-wire or four-wire unidirectional transmission, the address is single-wire or four-wire unidirectional transmission, and the data is four-wire bidirectional transmission.
Alternatively, different target commands may correspond to different transmission modes. The specific examples include different bits, different contents, and different bits and contents, which are not limited herein.
S103, transmitting target data to a target address through a second queue serial peripheral interface according to a target transmission mode, wherein the target address indicates the address of a target storage unit in at least one storage unit.
The second serial peripheral interface may include a plurality of second device pins, where each pin may correspondingly transmit different signals in different target transmission modes, for example, for unidirectional transmission of an input signal, unidirectional transmission of an output signal, transmission of an input/output signal, and the like, which is not limited herein.
Based on the above description, after determining the target transmission mode, the control unit may transmit the target data to the target storage unit through the second queue serial peripheral interface, so as to implement data transmission between the processing unit and the storage unit.
In some embodiments, the target address may also indicate a target area in the target storage unit, e.g., the target area may be a read-only data area, a data copy area, a data storage area, a user storage area, etc., without limitation.
In summary, an embodiment of the present application provides a data transmission method, applied to a control unit, where the control unit is communicatively connected to a processing unit through a first queue serial peripheral interface, and the control unit is also communicatively connected to at least one storage unit through a second queue serial peripheral interface, where the method includes: receiving, by the first queue serial peripheral interface, a transmission signal sent by the processing unit, the transmission signal including: target command, target address and target data; determining a target transmission mode between the control unit and the storage unit according to the target command, wherein the target transmission mode comprises any one of the following: a unidirectional data transmission mode, a two-wire bidirectional data transmission mode, and a four-wire bidirectional data transmission mode; according to the target transmission mode, the target data is transmitted to the target address through the second queue serial peripheral interface, wherein the target address indicates the address of the target storage unit in at least one storage unit.
Fig. 3 is a flowchart of another data transmission method according to an embodiment of the present application. In an alternative embodiment, as shown in fig. 3, the receiving, by the first queue serial peripheral interface, the transmission signal sent by the processing unit includes:
S201, each chip selection signal in the serial peripheral interface of the first queue is obtained.
S202, if any one of the selection signals is at a low level, the transmission signals sent by the processing unit are received through the first queue serial peripheral interface.
The processing unit can determine whether data transmission is required by the processing unit by acquiring each chip selection signal in the first queue serial peripheral interface, and if any chip selection signal is determined to be low level, the processing unit is ready for data transmission, at this time, the transmission signal sent by the processing unit is received through the first queue serial peripheral interface, that is, the transmission signal is transmitted through the cooperation among a plurality of first device pins, a plurality of chip selection pins and a first clock signal pin in the first queue serial peripheral interface.
Fig. 4 is a flowchart of another data transmission method according to an embodiment of the present application. In an alternative embodiment, as shown in fig. 4, the transmitting, according to the target transmission mode, the target data to the target address through the second queue serial peripheral interface includes:
S301, acquiring a current transmission mode of the control unit.
S302, judging whether the target transmission mode is the same as the current transmission mode.
The current transmission mode of the control unit can be a unidirectional data transmission mode or a four-wire bidirectional data transmission mode; the target transmission mode may be a unidirectional data transmission mode or a four-wire bidirectional data transmission mode.
S303, if the signal transmission directions in the second queue serial peripheral interfaces are different, the signal transmission directions in the second queue serial peripheral interfaces are switched, and target data are transmitted to the target addresses through the second queue serial peripheral interfaces.
S304, if the data are the same, transmitting the target data to the target address through the second queue serial peripheral interface.
Optionally, whether the transmission direction of the signal in the second queue serial peripheral interface needs to be switched or not may be determined by comparing whether the target transmission mode is the same as the current transmission mode, if so, it is determined that the switching is not needed, the current transmission mode is kept for data transmission, if not, it is determined that the switching is needed, at this time, the transmission direction of the signal in the second queue serial peripheral interface is switched, and the target data is transmitted to the target address through the second queue serial peripheral interface.
In some embodiments, the second queue serial peripheral interface may include a plurality of second device pins, e.g., may include: the first pin, the second pin, the third pin and the fourth pin can be used for switching the transmission directions of signals in the first pin, the second pin, the third pin and the fourth pin during specific switching. Optionally, if the current transmission mode is a unidirectional data transmission mode and the target transmission mode is a four-wire bidirectional data transmission mode, the first pin, the second pin, the third pin and the fourth pin may be respectively configured to transmit the input/output signals.
In an alternative embodiment, the at least one storage unit includes a primary storage unit and at least one backup storage unit.
In some embodiments, the second queue serial peripheral interface may further include: a second clock signal pin and a plurality of chip select pins, wherein the second clock signal pin may be used to transmit a clock signal between the control unit and the memory unit, such as fpga_sck; the number of chip select pins may be the same as the number of memory cells, the chip select pins may be used to transmit chip select signals, and each chip select signal (e.g., FPGA CSNx, where x represents the number of memory cells) may be used to indicate a target memory cell in communication with the control unit.
The main memory unit and the at least one backup memory unit may share a second clock signal pin, a first pin, a second pin, a third pin, and a fourth pin in the second queue serial peripheral interface, and use each chip select pin independently.
For example, the primary storage unit may be connected to a first primary chip select pin in the second queue serial peripheral interface, and each backup storage unit may be connected to a second backup chip select pin in the second queue serial peripheral interface. In some embodiments, the number of second spare chip select pins may be the same as the number of spare memory cells.
Fig. 5 is a block diagram of another data transmission system according to an embodiment of the present application. As shown in fig. 5, the control unit 101 is an FPGA, and the data transmission system includes a main storage unit 106 and a backup storage unit 107. Of course, it should be noted that the present application is not limited to the number of memory cells in the data transmission system.
The first serial peripheral interface 103 of the FPGA comprises 7 pins and the second serial peripheral interface 104 comprises 7 pins. Referring to fig. 5, in the first serial peripheral interface 103, the first clock signal pin, the 2 chip select pins, and the 4 first device pins are sequentially connected to the first clock signal pin, the 2 chip select pins, and the 4 first device pins of the processing unit 102, where the transmitted signals are sequentially: QSPI_SCK, QSPI_CSN0, QSPI_CSN1, QSPI_MOSI/IO0, QSPI_MISO/IO1, QSPI_WP/IO2, QSPI_HOLD/IO3.
With continued reference to fig. 5, in the second serial peripheral interface 104 of the FPGA, the second clock signal pin, the 2 chip select pins, and the 4 second device pins are sequentially connected to the clock signal pins and the 4 pins of the main memory unit 106 and the backup memory unit 107, respectively, in a direction from top to bottom, where the transmitted signals are sequentially: FPGA_SCK, FPGA_MOSI/IO0, FPGA_MISO/IO1, FPGA_WP/IO2, FPGA_HOLD/IO3; the 2 chip selection pins are respectively connected with chip selection signal pins of the main memory unit 106 and the backup memory unit 107, and the transmitted signals are respectively FPGA_CSN0 and FPGA_CSN1.
Fig. 6 is a flowchart of another data transmission method according to an embodiment of the present application. In an alternative embodiment, as shown in fig. 6, the method further includes:
s401, acquiring a main chip selection signal and at least one backup chip selection signal in a first queue serial peripheral interface.
S402, if the main chip selection signal is at a low level, determining that the target address indicates the address of the main memory unit.
S403, if any backup chip selection signal is at a low level, determining that the target address indicates the address of the target backup storage unit corresponding to the backup chip selection signal.
The target backup memory cell is a memory cell corresponding to a low-level backup chip selection signal.
Optionally, during the data transmission process, the processing unit may pull down a chip selection signal corresponding to the memory unit in communication with the processing unit, that is, even if the chip selection signal is at a low level, the control unit obtains a main chip selection signal and at least one backup chip selection signal in the first serial peripheral interface, and determines, according to the level condition of each chip selection signal, whether the memory unit in communication with the processing unit is the main memory unit or the target backup memory unit.
In some embodiments, if the master slice signal is low, determining that the processing unit requests communication with the master storage unit; if any backup chip selection signal is at a low level, the processing unit is determined to request communication with the corresponding target storage unit.
Fig. 7 is a flowchart of another data transmission method according to an embodiment of the present application. In an alternative embodiment, as shown in fig. 7, determining the target transmission mode between the control unit and the storage unit according to the target command includes:
s501, analyzing the target command and obtaining a transmission mode bit corresponding to the target command.
S502, determining a target transmission mode between the control unit and the storage unit according to the transmission mode bit corresponding to the target command and a preset mapping relation, wherein the preset mapping relation is used for indicating the mapping relation between the transmission mode bit and the transmission mode.
Alternatively, different transmission modes may correspond to different transmission mode bit numbers.
The target transmission mode can be obtained by analyzing the target command, and optionally, during specific analysis, the transmission mode bit corresponding to the target command can be recorded; and determining a corresponding target transmission mode by inquiring a preset mapping relation according to the transmission mode bit corresponding to the target command.
Of course, in some embodiments, the command content may also be differentiated, that is, different commands are set to correspond to different transmission modes, which is not limited herein.
In an alternative embodiment, the target command is generated by the processing unit according to a backup instruction, the backup instruction comprising: a destination address and destination data.
In some embodiments, the backup instruction may be triggered and generated by the processing unit according to an actual application scenario, or may be forwarded to the control unit by another external device, which is not limited herein. By applying the embodiment of the application, the object which is communicated with the main storage unit or the backup storage unit can be dynamically switched according to the actual application scene, the flexible backup can be realized, and the data safety is improved.
It should be noted that, the signal received by the control unit may be continuous, and according to a predetermined configuration, it may be: the first several bits are used to indicate the target command, the next several bits are used to indicate the target address, and the last remaining bits are used to carry the target data, which can, of course, be flexibly configured according to specific transmission requirements, without limitation.
For example, the method and the device can be applied to scenes with high requirements on data security, such as aerospace scenes, navigation scenes and the like.
In an alternative embodiment, the second queue serial peripheral interface comprises: the first pin, the second pin, the third pin and the fourth pin.
In unidirectional data transmission mode, the first pin is used for unidirectional transmission of output signals (e.g., MOSI signals), the second pin is used for unidirectional transmission of input signals (e.g., MISO signals), the third pin is used for unidirectional transmission of output signals (e.g., write protection signals), and the fourth pin is used for unidirectional transmission of output signals (e.g., hold signals);
in the two-wire bidirectional data transmission mode, the first pin and the second pin are used for transmitting input and output signals (i.e. IO signals), the third pin is used for unidirectionally transmitting output signals (e.g. write protection signals), and the fourth pin is used for unidirectionally transmitting output signals (e.g. hold signals);
In the four-wire bidirectional data transmission mode, the first pin, the second pin, the third pin and the fourth pin are used for transmitting input/output signals (i.e., IO signals).
When the input and output signals are transmitted through the first pin, the second pin, the third pin and the fourth pin, the transmitted signals can be specifically commands, addresses and data communicated between the control unit and the storage unit; when signals are unidirectionally transmitted through the first pin, the second pin, the third pin, and the fourth pin, the transmitted signals may specifically be addresses, commands, etc. communicated between the control unit and the memory unit, which are not limited herein. It can be seen that the embodiment of the application provides various communication modes of communication between the control unit and the storage unit, and the communication modes can be flexibly selected according to actual application scenes, so that the applicability of the method of the application is improved.
Based on the above description, comparing the unidirectional data transmission mode with the two-wire bidirectional data transmission mode and the four-wire bidirectional data transmission mode, it can be seen that, in the two-wire bidirectional data transmission mode and the four-wire bidirectional data transmission mode, at least two pins for transmitting input and output signals exist in the serial peripheral interface of the second queue, and compared with the transmission mode in the unidirectional data transmission mode, the data transmission rate can be improved.
In an alternative embodiment, if each chip select signal is at a high level, the receiving of the transmission signal sent by the processing unit through the first queue serial peripheral interface is stopped.
In the data transmission process, if the control unit detects that each chip selection signal in the first serial peripheral interface is at a high level, that is, there is no low level, the processing unit can be considered to stop data communication with each storage unit, and then the control unit can stop receiving the transmission signal sent by the processing unit through the first serial peripheral interface, so that unnecessary power consumption of the control unit is avoided.
By applying the embodiment of the application, the time for flexibly controlling the data transmission can be realized through switching the high level and the low level, and the flexibility of the method can be improved.
Fig. 8 is a schematic diagram of a functional module of a data transmission device according to an embodiment of the present application, where the control unit is communicatively connected to the processing unit through a first serial peripheral interface and communicatively connected to at least one storage unit through a second serial peripheral interface, and the basic principle and the technical effects of the device are the same as those of the corresponding method embodiment, and for brevity, no reference is made to the corresponding contents of the method embodiment in this embodiment. As shown in fig. 8, the data transmission apparatus 100 includes:
A receiving module 110, configured to receive, through a first queue serial peripheral interface, a transmission signal sent by the processing unit, where the transmission signal includes: target command, target address and target data;
A determining module 120, configured to determine a target transmission mode between the control unit and the storage unit according to the target command, where the target transmission mode includes any one of the following: a unidirectional data transmission mode, a two-wire bidirectional data transmission mode, and a four-wire bidirectional data transmission mode;
And a transmission module 130, configured to transmit target data to a target address through the second queue serial peripheral interface according to the target transmission mode, where the target address indicates an address of a target storage unit in at least one storage unit.
In an alternative embodiment, the receiving module 110 is specifically configured to obtain each chip select signal in the first queue serial peripheral interface;
and if any chip selection signal is in a low level, receiving a transmission signal sent by the processing unit through the first queue serial peripheral interface.
In an alternative embodiment, the transmission module 130 is specifically configured to obtain a current transmission mode of the control unit;
judging whether the target transmission mode is the same as the current transmission mode;
if the signal transmission directions in the second queue serial peripheral interfaces are different, switching the signal transmission directions in the second queue serial peripheral interfaces, and transmitting target data to a target address through the second queue serial peripheral interfaces;
and if the data are the same, transmitting the target data to the target address through the second queue serial peripheral interface.
In an alternative embodiment, at least one of the storage units includes a main storage unit and at least one backup storage unit, and the transmission module 130 is further configured to obtain a main chip select signal and at least one backup chip select signal in the first queue serial peripheral interface;
If the main chip selection signal is in a low level, determining that the target address indicates the address of the main storage unit;
and if any backup chip selection signal is in a low level, determining that the target address indicates the address of the target backup storage unit corresponding to the backup chip selection signal.
In an optional implementation manner, the determining module 120 is specifically configured to parse the target command, and obtain a transmission mode bit corresponding to the target command;
And determining a target transmission mode between the control unit and the storage unit according to the transmission mode bit corresponding to the target command and a preset mapping relation, wherein the preset mapping relation is used for indicating the mapping relation between the transmission mode bit and the transmission mode.
In an alternative embodiment, the target command is generated by the processing unit according to a backup instruction, the backup instruction including: the target address and the target data.
In an alternative embodiment, in the unidirectional data transfer mode, the second queue serial peripheral interface includes: a first pin, a second pin, a third pin and a fourth pin;
In the unidirectional data transmission mode, the first pin is used for unidirectional transmission of output signals, the second pin is used for unidirectional transmission of input signals, the third pin is used for unidirectional transmission of output signals, and the fourth pin is used for unidirectional transmission of output signals;
In the two-wire bidirectional data transmission mode, the first pin and the second pin are used for transmitting input and output signals, the third pin is used for unidirectionally transmitting output signals, and the fourth pin is used for unidirectionally transmitting output signals;
In the four-wire bidirectional data transmission mode, the first pin, the second pin, the third pin and the fourth pin are used for transmitting input and output signals.
In an alternative embodiment, the receiving module 110 is further configured to stop receiving, if each of the chip select signals is at a high level, the transmission signal sent by the processing unit through the first queue serial peripheral interface.
The foregoing apparatus is used for executing the method provided in the foregoing embodiment, and its implementation principle and technical effects are similar, and are not described herein again.
The above modules may be one or more integrated circuits configured to implement the above methods, for example: one or more Application SPECIFIC INTEGRATED Circuits (ASIC), or one or more microprocessors, or one or more field programmable gate arrays (Field Programmable GATE ARRAY FPGA), etc. For another example, when a module above is implemented in the form of a processing element scheduler code, the processing element may be a general-purpose processor, such as a central processing unit (Central Processing Unit, CPU) or other processor that may invoke the program code. For another example, the modules may be integrated together and implemented in the form of a system-on-a-chip (SOC).
Fig. 9 is a schematic structural diagram of an electronic device according to an embodiment of the present application, where the electronic device may be integrated in the data transmission apparatus. As shown in fig. 9, the electronic device may include: processor 210, storage medium 220, and bus 230, storage medium 220 storing machine-readable instructions executable by processor 210, processor 210 executing machine-readable instructions to perform steps of the method embodiments described above when the electronic device is operating, processor 210 communicating with storage medium 220 via bus 230. The specific implementation manner and the technical effect are similar, and are not repeated here.
Optionally, the present application further provides a storage medium, on which a computer program is stored, which when being executed by a processor performs the steps of the above-described method embodiments. The specific implementation manner and the technical effect are similar, and are not repeated here.
In the several embodiments provided by the present application, it should be understood that the disclosed apparatus and method may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of elements is merely a logical functional division, and there may be additional divisions of actual implementation, e.g., multiple elements or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in hardware plus software functional units.
The integrated units implemented in the form of software functional units described above may be stored in a computer readable storage medium. The software functional unit is stored in a storage medium, and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor (english: processor) to perform part of the steps of the methods of the embodiments of the application. And the aforementioned storage medium includes: u disk, mobile hard disk, read-Only Memory (ROM), random access Memory (Random Access Memory, RAM), magnetic disk or optical disk, etc.
It should be noted that in this document, relational terms such as "first" and "second" and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises an element.
The above is only a preferred embodiment of the present application, and is not intended to limit the present application, but various modifications and variations can be made to the present application by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application. It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures. The above is only a preferred embodiment of the present application, and is not intended to limit the present application, but various modifications and variations can be made to the present application by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.
Claims (11)
1. A data transmission method, applied to a control unit, the control unit being communicatively connected to a processing unit via a first queue serial peripheral interface, the control unit also being communicatively connected to at least one memory unit via a second queue serial peripheral interface, the method comprising:
Receiving a transmission signal sent by a processing unit through a first queue serial peripheral interface, wherein the transmission signal comprises: target command, target address and target data;
Determining a target transmission mode between the control unit and the storage unit according to the target command, wherein the target transmission mode comprises any one of the following steps: a unidirectional data transmission mode, a two-wire bidirectional data transmission mode, and a four-wire bidirectional data transmission mode;
And transmitting target data to a target address through the second queue serial peripheral interface according to the target transmission mode, wherein the target address indicates the address of a target storage unit in at least one storage unit.
2. The method of claim 1, wherein receiving the transmission signal sent by the processing unit through the first queued serial peripheral interface comprises:
acquiring each chip selection signal in the first queue serial peripheral interface;
and if any chip selection signal is in a low level, receiving a transmission signal sent by the processing unit through the first queue serial peripheral interface.
3. The method of claim 1, wherein transmitting the target data to the target address via the second queued serial peripheral interface in accordance with the target transmission mode comprises:
Acquiring a current transmission mode of the control unit;
judging whether the target transmission mode is the same as the current transmission mode;
if the signal transmission directions in the second queue serial peripheral interfaces are different, switching the signal transmission directions in the second queue serial peripheral interfaces, and transmitting target data to a target address through the second queue serial peripheral interfaces;
and if the data are the same, transmitting the target data to the target address through the second queue serial peripheral interface.
4. The method of claim 2, wherein at least one of the storage units comprises a primary storage unit and at least one backup storage unit, the method further comprising:
acquiring a main chip selection signal and at least one backup chip selection signal in the first queue serial peripheral interface;
If the main chip selection signal is in a low level, determining that the target address indicates the address of the main storage unit;
and if any backup chip selection signal is in a low level, determining that the target address indicates the address of the target backup storage unit corresponding to the backup chip selection signal.
5. The method of claim 1, wherein determining a target transmission mode between the control unit and the storage unit based on the target command comprises:
analyzing the target command and acquiring a transmission mode bit corresponding to the target command;
And determining a target transmission mode between the control unit and the storage unit according to the transmission mode bit corresponding to the target command and a preset mapping relation, wherein the preset mapping relation is used for indicating the mapping relation between the transmission mode bit and the transmission mode.
6. The method of claim 1, wherein the target command is generated by the processing unit in accordance with a backup instruction, the backup instruction comprising: the target address and the target data.
7. The method of claim 1, wherein the second queue serial peripheral interface comprises: a first pin, a second pin, a third pin and a fourth pin;
In the unidirectional data transmission mode, the first pin is used for unidirectional transmission of output signals, the second pin is used for unidirectional transmission of input signals, the third pin is used for unidirectional transmission of output signals, and the fourth pin is used for unidirectional transmission of output signals;
In the two-wire bidirectional data transmission mode, the first pin and the second pin are used for transmitting input and output signals, the third pin is used for unidirectionally transmitting output signals, and the fourth pin is used for unidirectionally transmitting output signals;
In the four-wire bidirectional data transmission mode, the first pin, the second pin, the third pin and the fourth pin are used for transmitting input and output signals.
8. The method of claim 2, wherein if each of the chip select signals is high, ceasing to receive the transmission signal sent by the processing unit via the first queued serial peripheral interface.
9. A data transmission device for a control unit, the control unit being communicatively coupled to a processing unit via a first queue serial peripheral interface and to at least one memory unit via a second queue serial peripheral interface, the data transmission device comprising:
the receiving module is configured to receive, through the first queue serial peripheral interface, a transmission signal sent by the processing unit, where the transmission signal includes: target command, target address and target data;
a determining module, configured to determine a target transmission mode between the control unit and the storage unit according to the target command, where the target transmission mode includes any one of the following: a unidirectional data transmission mode, a two-wire bidirectional data transmission mode, and a four-wire bidirectional data transmission mode;
And the transmission module is used for transmitting target data to a target address through the second queue serial peripheral interface according to the target transmission mode, wherein the target address indicates the address of a target storage unit in at least one storage unit.
10. An electronic device, comprising: a processor, a storage medium and a bus, the storage medium storing machine-readable instructions executable by the processor, the processor and the storage medium communicating over the bus when the electronic device is running, the processor executing the machine-readable instructions to perform the steps of the data transmission method according to any one of claims 1-8.
11. A computer-readable storage medium, characterized in that the computer-readable storage medium has stored thereon a computer program which, when executed by a processor, performs the steps of the data transmission method according to any of claims 1-8.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN118245405A (en) * | 2024-05-27 | 2024-06-25 | 上海泰矽微电子有限公司 | Single-wire downloading method, communication module, upper computer and system |
| CN118245405B (en) * | 2024-05-27 | 2024-08-09 | 上海泰矽微电子有限公司 | Single-wire downloading method, communication module, upper computer and system |
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