CN118068918A

CN118068918A - Clock domain control method, device, equipment and storage medium

Info

Publication number: CN118068918A
Application number: CN202410288791.6A
Authority: CN
Inventors: 姚春忆; 崔瑶瑶; 刘善高
Original assignee: New H3C Information Technologies Co Ltd
Current assignee: New H3C Information Technologies Co Ltd
Priority date: 2024-03-13
Filing date: 2024-03-13
Publication date: 2024-05-24

Abstract

The embodiment of the application provides a clock domain control method, a device, equipment and a storage medium. According to the embodiment, the BMC, the CPLD and more than two MUXs are deployed on the server, at least two input ports are arranged on any one MUX, the BMC is used for informing the CPLD of the obtained target clock domain control mode of the target clock generator used for indicating each component with clock domain requirements in the server, the CPLD is used for controlling the input ports of at least one MUX to switch, so that the clock generator used by the component connected with the MUXs is the target clock generator required by the component indicated by the target clock domain control mode, automatic switching control of the clock domain scheme according to the obtained target clock domain control mode can be realized, and the problems of long development period and high development cost caused by realizing clock domain switching through a modification mode are avoided.

Description

Clock domain control method, device, equipment and storage medium

Technical Field

The present application relates to the field of network communications, and in particular, to a clock domain control method, apparatus, device, and storage medium.

Background

In practical applications, most electronic devices, such as servers, can only be compatible with one clock scheme, such as a full-page clock domain homologous scheme, or a scheme of separating uplink and downlink clock domains, on a hardware link. However, in the above application, since the clock scheme of the device is single, the requirements of chips of different manufacturers on clock domains cannot be met, and therefore, when different clock domain schemes are needed to be used, the clock schemes are realized in a modification mode, so that the development period is longer and the development cost is higher.

Disclosure of Invention

In view of this, the application provides a clock domain control method, a device and a storage medium, so as to realize automatic control of a clock domain scheme, and avoid the problems of longer development period and higher development cost caused by realizing clock domain switching in a modification mode.

The embodiment of the application provides a clock domain control method, which is applied to a server, wherein the server is provided with at least two clock generators; the server is also deployed: a baseboard management controller (Baseboard Management Controller, BMC), a complex programmable logic device (Complex Programmable Logic Device, CPLD), and two or more multiplexers (muxes); the input port of any MUX comprises at least two ports, and only one port is used as the input port to work normally at the same time; the server is further deployed with at least one component having clock domain requirements;

The method comprises the following steps:

Obtaining a target clock domain control mode through the BMC, and informing the CPLD of the target clock domain control mode; the target clock domain control mode is used for indicating a target clock generator used by each component with clock domain requirements in the server; wherein the target clock generators required by different components are the same or different;

and controlling the input port of at least one MUX to switch through the CPLD so that the clock generator used by the assembly connected with the MUX is the target clock generator required by the assembly indicated by the target clock domain control mode.

The embodiment of the application also provides a clock domain control device, which is configured on a server, wherein the server is provided with at least two clock generators; the server is also deployed: BMC, CPLD, and more than two MUXs; the input port of any MUX comprises at least two ports, and only one port is used as the input port to work normally at the same time; the server is further deployed with at least one component having clock domain requirements;

the device comprises:

The obtaining module is used for obtaining a target clock domain control mode through the BMC and notifying the CPLD of the target clock domain control mode; the target clock domain control mode is used for indicating a target clock generator used by each component with clock domain requirements in the server; wherein the target clock generators required by different components are the same or different;

And the control module is used for controlling the input port of at least one MUX to switch through the CPLD so that the clock generator used by the assembly connected with the MUX is the target clock generator required by the assembly indicated by the target clock domain control mode.

The embodiment of the application also provides electronic equipment, which comprises:

a processor and a memory for storing computer program instructions which, when executed by the processor, cause the processor to perform the steps of the method as above.

Embodiments of the present application also provide a computer readable storage medium storing computer program instructions which, when executed, enable the steps of the method as above to be carried out.

According to the technical scheme, in the embodiment, the BMC, the CPLD and more than two MUXs are deployed on the server, at least two input ports are arranged on any MUX, the BMC is used for informing the CPLD of the obtained target clock domain control mode of the target clock generator used for indicating each component with clock domain requirements in the server, the CPLD is used for controlling the input port of at least one MUX to switch, so that the clock generator used by the component connected with the MUX is the target clock generator required by the component indicated by the target clock domain control mode, the automatic switching control of the clock domain scheme according to the obtained target clock domain control mode can be realized, the problems of long development period and high development cost caused by realizing the clock domain switching in a modification mode are avoided, and the clock domain control efficiency is effectively improved.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application as claimed.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.

Fig. 1 is a flow chart of a clock domain control method according to an embodiment of the present application.

Fig. 2 is a schematic diagram of a topology structure for implementing clock domain control according to an embodiment of the present application.

Fig. 3 is a schematic diagram of another topology structure for implementing clock domain control according to an embodiment of the present application.

Fig. 4 is a schematic diagram of a topology structure for implementing clock domain control according to an embodiment of the present application.

Fig. 5A is a schematic diagram of a topology structure for implementing clock domain control according to an embodiment of the present application.

Fig. 5B is a schematic diagram of a topology structure for implementing clock domain control according to an embodiment of the present application.

Fig. 5C is a schematic diagram of a topology structure for implementing clock domain control according to an embodiment of the present application.

Fig. 6 is a schematic structural diagram of a clock domain control device according to an embodiment of the present application.

Fig. 7 is a schematic structural diagram of an electronic device according to an embodiment of the present application.

Detailed Description

Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the application. Rather, they are merely examples of apparatus and methods consistent with aspects of the application as detailed in the accompanying claims.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any or all possible combinations of one or more of the associated listed items.

It should be understood that although the terms first, second, third, etc. may be used herein to describe various information, these information should not be limited by these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the application. The word "if" as used herein may be interpreted as "at … …" or "at … …" or "in response to a determination" depending on the context.

In order to better illustrate the present solution, the following terms will now be explained.

BMC: the baseboard management controller is a special microcontroller integrated on a computer server or other network equipment main board and used for monitoring, managing and controlling the operation and state of hardware equipment.

A MUX: a multiple-select-one-pass switch, also known as a multiplexer, is a digital circuit element that is used to select and concentrate multiple input signals to an output signal; it is generally described as a "one-out-of-many" pass switch, capable of selecting one of the inputs based on a control signal and passing it to the output.

CLOCK EXPANDER: the clock expansion chip is an integrated circuit for expanding and distributing clock signals; clock expansion chips are commonly used to expand a single clock source to multiple devices or modules, thereby simplifying the system design and improving the stability and reliability of the clock signal.

Switch: a data switching circuit chip (SW), which typically contains a series of ports for connection to different devices in the network.

PCIe SW: PCIe switch chips (switches) may also be considered as data switching circuit chips based on peripheral component interconnect expansion buses. PCIe switch chips refer to devices for extending the PCIe bus, allowing multiple PCIe devices to share a single PCIe slot or to connect to a single root complex PCIe architecture.

PCIe: the peripheral component interconnect expansion bus (PERIPHERAL COMPONENT INTERCONNECT EXPRESS) is a computer bus standard for connecting expansion cards to slots on a motherboard to achieve high-speed data transmission and communication.

S5: the S5 state of the server system, namely the CPU, the system, the BIOS, the peripheral equipment and the like do not work, and only the BMC, the CPLD and the like work.

BIOS (Basic Input Output System): a basic input output system.

GPU (Graphics Processing Unit): a graphics processor.

CPU (Central Processing Unit): and a central processing unit.

CPLD: a complex programmable logic device is an integrated circuit chip which can be used for realizing digital logic functions and timing control.

MOTHER BOARD: and a main board.

SWITCH BOARD: commonly referred to as a "switch board" and may also be referred to simply as a SW board. In the computer and network fields, it refers to a board card or module for connecting and managing a plurality of network devices, which may be switches, routers, servers, etc.

Clock Generator: a clock generator for generating a stable clock signal; in digital systems and electronic devices, clock signals are used to synchronize the operation of the various components, ensuring that they operate in proper timing.

GPU BOARD: and the GPU main board.

Clock domain: refers to a set of logic elements or registers driven by the same clock signal in a digital system. In one clock domain, all logic operations are synchronized in accordance with the beats of the clock signal. The clock signal is a periodic electrical signal that is used to synchronize the operation of the various components in the digital system.

Clock source: refers to a physical or logical source that provides a clock signal, such as typically a stable oscillator or clock generator.

The embodiments of the present application will be described in detail.

Referring to fig. 1, fig. 1 is a schematic flow chart of a clock domain control method according to an embodiment of the present application. Optionally, the method is applied to a server, the server being deployed with at least two clock generators; the server is also deployed: BMC, CPLD, and more than two MUXs; the input port of any MUX comprises at least two ports, and only one port is used as the input port to work normally at the same time; the server is also deployed with at least one component having clock domain requirements.

As shown in fig. 1, the process may include the steps of:

In step 101, a target clock domain control mode is obtained through the BMC, and the target clock domain control mode is notified to the CPLD; the target clock domain control mode is used for indicating a target clock generator used by each component with clock domain requirements in the server; wherein the target clock generators required by the different components are the same or different.

In this embodiment, at least one component having a clock domain requirement on the server is not specifically limited, and may include a CPU, GPU, PCIe SW chip, and the like.

Alternatively, as an embodiment, the target clock domain control mode may be obtained from an external instruction (such as an instruction including the target clock domain control mode input by the user) received.

In this embodiment, as an embodiment, after the server obtains the target clock domain control manner through the BMC, in order to avoid the influence of clock domain switching on the component operation, the server may be controlled to enter the S5 state (i.e., the BMC, the CPLD, and the devices used for clock domain control, such as the MUX, are in an operating state, and other devices on the server (such as the CPU, the BIOS, the system, and the peripheral devices) are in a non-operating state). Correspondingly, after the clock domain control is finished, the server can exit the S5 state and restore to the normal working state.

In step 102, the input port of at least one MUX is controlled by the CPLD to switch, so that the clock generator used by the MUX-connected component is the target clock generator required to be used by the component indicated by the target clock domain control mode.

In this embodiment, the CPLD controls the switching of different input ports on the MUX to enable the selection of different clock generators to achieve switching of the clock generators used by the components connected to the MUX.

In this embodiment, the CPLD controls the input port of at least one MUX to switch, so that the clock generator used by the MUX-connected component is a specific implementation manner of the target clock generator required to be used by the component indicated by the target clock domain control manner, which is not limited herein.

For example, as one embodiment, when at least one component having a clock domain requirement is a CPU and a first designated SW chip, respectively, the first MUX is connected to the CPU through a second port of the first MUX, the first MUX is connected to the first designated SW chip through a first output port, the second MUX is connected to the CPU through a first port of the second MUX, and the second MUX is connected to the first designated SW chip through a second output port;

If the target clock generators of the CPU and the first designated SW chip are both first clock generators, the first clock generators are connected with the CPU, the first MUX is connected with the first clock generators through a first port of the first MUX, and the second MUX is connected with the first clock generators through a second port of the second MUX; the CPLD controls the input port of the first MUX to be switched into the first port of the first MUX; or the CPLD is used for controlling the input port of the second MUX to be switched into the second port of the second MUX;

If the target clock generator of the CPU and the first designated SW chip are both the second clock generator, the second clock generator is the CPU; the CPLD controls the input port of the first MUX to be switched to the second port of the first MUX; or the CPLD controls the input port of the second MUX to be switched into the first port of the second MUX.

As one embodiment, when at least one component having a clock domain requirement is a first designated SW chip and a GPU, respectively, the first MUX is connected to the first designated SW chip through a first output port, the second MUX is connected to the first designated SW chip through a second output port, and the second MUX is also connected to the GPU through a second output port;

If the target clock generator of the first designated SW chip and the target clock generator of the GPU are both the first clock generator, the first MUX is connected with the first clock generator through a first port of the first MUX, and the second MUX is connected with the first clock generator through a second port of the second MUX; the CPLD controls the input port of the first MUX to be switched to the first port of the first MUX, and controls the input port of the second MUX to be switched to the second port of the second MUX; or the CPLD is used for controlling the input port of the second MUX to be switched into the second port of the second MUX;

If the target clock generator of the first designated SW chip and the target clock generator of the GPU are both second clock generators, the second clock generators are CPUs, the first MUX is connected with the CPUs through a second port of the first MUX, and the second MUX is connected with the CPUs through a first port of the second MUX; the CPLD controls the input port of the first MUX to be switched to the second port of the first MUX, and controls the input port of the second MUX to be switched to the first port of the second MUX; or the CPLD is used for controlling the input port of the second MUX to be switched into the first port of the second MUX;

If the target clock generator of the first designated SW chip and the target clock generator of the GPU are both the third clock generator, the second MUX is connected with the third clock generator through a third port of the second MUX; the input port of the second MUX is controlled by the CPLD to switch to the third port of the second MUX.

As an embodiment, when at least one component having a clock domain requirement is a CPU and a second designated SW chip, respectively, the first MUX is connected to the CPU through a second port of the first MUX, the first MUX is connected to a third port of the third MUX through a first output port, the second MUX is connected to the CPU through a first port of the second MUX, the second MUX is connected to a first port of the third MUX through a second output port, and the third MUX is connected to the second designated SW chip through a third output port;

if the target clock generators of the CPU and the second designated SW chip are both first clock generators, the first clock generators are connected with the CPU, the first MUX is connected with the first clock generators through a first port of the first MUX, and the second MUX is connected with the first clock generators through a second port of the second MUX; the CPLD controls the input port of the first MUX to be switched to the first port of the first MUX, and controls the input port of the third MUX to be switched to the third port of the third MUX; or the CPLD controls the input port of the second MUX to be switched to the second port of the second MUX, and controls the input port of the third MUX to be switched to the first port of the third MUX;

If the target clock generator of the CPU and the second designated SW chip are both the second clock generator, the second clock generator is the CPU; the CPLD controls the input port of the first MUX to be switched to the second port of the first MUX, and controls the input port of the third MUX to be switched to the third port of the third MUX; or the CPLD controls the input port of the second MUX to be switched to the first port of the second MUX, and controls the input port of the third MUX to be switched to the first port of the third MUX.

As one embodiment, when at least one component requiring a clock domain is a CPU and a GPU, respectively, the first MUX is connected to the CPU through a second port of the first MUX, the second MUX is connected to the CPU through a first port of the second MUX, and the second MUX is connected to the GPU through a second output port;

if the target clock generators of the CPU and the GPU are both the first clock generator, the first clock generator is connected with the CPU, and the second MUX is connected with the first clock generator through a second port of the second MUX; the CPLD controls the input port of the second MUX to be switched to the second port of the second MUX;

if the target clock generators of the CPU and the GPU are both second clock generators, the second clock generator is the CPU; the input port of the second MUX is controlled by the CPLD to switch to the first port of the second MUX.

As one embodiment, when at least one component having a clock domain requirement is a first designated SW chip and a second designated SW chip, respectively, the first MUX is connected to the first designated SW chip through a first output port, the first MUX is connected to a third port of a third MUX through the first output port, the second MUX is connected to the first designated SW chip through a second output port, the second MUX is connected to the first port of the third MUX through the second output port, and the third MUX is connected to the second designated SW chip through the third output port;

If the target clock generators of the first designated SW chip and the second designated SW chip are both first clock generators, the first MUX is connected with the first clock generators through a first port of the first MUX, and the second MUX is connected with the first clock generators through a second port of the second MUX; the CPLD controls the input port of the first MUX to be switched to the first port of the first MUX, and controls the input port of the third MUX to be switched to the third port of the third MUX; or the CPLD controls the input port of the second MUX to be switched to the second port of the second MUX, and controls the input port of the third MUX to be switched to the first port of the third MUX;

If the target clock generators of the first designated SW chip and the second designated SW chip are both second clock generators, the second clock generators are CPUs, the first MUX is connected with the CPUs through a second port of the first MUX, and the second MUX is connected with the CPUs through a first port of the second MUX; the CPLD controls the input port of the first MUX to be switched to the second port of the first MUX, and controls the input port of the third MUX to be switched to the third port of the third MUX; or the CPLD controls the input port of the second MUX to be switched to the first port of the second MUX, and controls the input port of the third MUX to be switched to the first port of the third MUX.

Thus, the flow shown in fig. 1 is completed.

As can be seen from the flow shown in fig. 1, in this embodiment, by disposing a BMC, a CPLD, and two or more muxes on a server, where any one MUX includes at least two input ports, notifying, by the BMC, an obtained target clock domain control manner of a target clock generator used for indicating each component having a clock domain requirement in the server to the CPLD, and controlling, by the CPLD, the input port of at least one MUX to switch, so that the clock generator used by the component connected to the MUX is the target clock generator required to be used by the component indicated by the target clock domain control manner, thereby implementing automatic switching control of the clock domain scheme according to the obtained target clock domain control manner, avoiding the problems of long development period and high development cost caused by implementing clock domain switching by the board-modifying manner, and effectively improving the efficiency of clock domain control.

The clock domain control method of the present application will be described by way of example with reference to specific embodiments.

The embodiment of the application provides a multi-clock domain implementation scheme based on an SW chip, which can be compatible with the requirements of chips of different manufacturers on clock domains on a server and can be flexibly adjusted to a corresponding clock scheme according to actual conditions.

In the embodiment of the application, the server can control the switching of a plurality of clock routing chips (namely MUX chips) through the BMC management chip, so that PCIe devices on the server (namely components with clock domain requirements on the server) can provide required clock sources for the PCIe devices when different clock scheme requirements exist. After the BMC management chip reads the specific configuration of the system (such as configuration information of PCIe devices and clock domains required by the PCIe devices) and writes the configuration information into a route selection switch chip (i.e. a MUX chip) on the CPLD control single board, different clock schemes are switched. In CPLD control single board design, different clock sources are provided for each PCIe device through a channel selection switch chip, so that a plurality of clock domain compatible schemes on hardware are realized.

Referring to fig. 2, in the first aspect, in this embodiment, there are three Clock sources configured on an electronic device (such as a server), that is, a Clock Generator1 (Clock Generator 1) on a motherboard (MOTHER BOARD), a Clock generated by a CPU itself (that is, the CPU itself acts as a Clock Generator), and a Clock Generator2 (Clock Generator 2) on a SW BOARD (SWITCH BOARD). In a second aspect, the architecture PCIe lanes shown in fig. 2 may include 2 types, e.g., CPU-, PCIe SW chip-, GPU-, CPU-, SW chip, respectively, where PCIe SW chip supports up and down clock separation. In short, the same clock domain must be used for the CPU and PCIe SW chip upstream PCIe (PCIe SW chip upstream PCIe is an interface end connected to the CPU on the PCIe SW chip), and PCIe SW chip downstream PCIe (PCIe SW chip downstream PCIe is an interface end connected to the GPU on the PCIe SW chip) and the GPU need to keep the same clock domain, and the CPU needs to keep the same clock domain as the SW chip. In a third aspect, referring to fig. 2, the MUX chip may be inputted by one of the 3 input ports A, B, C through the external pin control output out.

For one embodiment, referring to FIG. 3, scenario one (all PCIe devices (i.e., CPU, PCIe SW chip, GPU and SW chip) use Clock of Clock Generator1, when implemented MUX0 switches to A port, MUX1 switches to B port, MUX2 switches to A port (or C port), where CPU, PCIe SW, GPU, SW all use Clock Generator1 as Clock source.

As an embodiment, referring to fig. 4, in a second scenario (where all PCIe devices use clocks output by the CPU), MUX0 is switched to the B port, MUX1 is switched to the a port, and MUX2 is switched to the a port (or the C port) when implemented, where the CPU, PCIe SW, GPU, SW all use the clocks output by the CPU itself as clock sources.

As one embodiment, in the third scenario (where the CPU and PCIe SW chip use the same clock domain for PCIe upstream and PCIe SW chip use the same clock domain for PCIe downstream and GPU, and the CPU and SW use the same clock domain), there are three cases:

a) Referring to FIG. 5A, PCIe SW chip upstream PCIe uses CPU Clock, PCIe SW chip downstream PCIe uses Clock Generator1, SW uses CPU output Clock, in which case MUX0 switches to B port, MUX1 switches to B port, MUX2 switches to C port;

b) Referring to FIG. 5B, PCIe SW chip upstream PCIe uses CPU Clock, PCIe SW chip downstream PCIe uses Clock Generator2, SW uses CPU output Clock, in which case MUX0 switches to B port, MUX1 switches to C port, MUX2 switches to C port;

c) Referring to FIG. 5C, PCIe SW chip upstream PCIe uses Clock Generator1, PCIe SW chip downstream PCIe uses Clock Generator2, SW uses Clock Generator1 to output clocks, in which case MUX0 switches to A port, MUX1 switches to C port, MUX2 switches to C port.

In this embodiment, the MUX switching policy states: in the S5 state, the BMC acquires information such as PCIe devices indicated in the external instructions and clock sources to which the PCIe devices need to be switched, so that the situation of which clock scheme is used is judged, then the BMC writes the information into a CPLD in a server, and the CPLD outputs signals to control clock routing chips MUX0-MUX2 to switch clock channels so as to realize the switching of the clock sources.

The embodiment of the application can effectively solve the problem of compatibility of various clock schemes required by PCIe equipment, can flexibly switch the clock schemes through BMC, CPLD, MUX and the like, does not need to change edition, and greatly reduces the development cost. The embodiment can realize various PCIe topology requirements on the same product, provide more clock source scheme configuration choices for users, and improve the satisfaction degree of the users.

Thus, the description of the method provided in this embodiment is completed, and the following describes the device provided in this embodiment of the present application:

referring to fig. 6, fig. 6 is a schematic structural diagram of a clock domain control device according to an embodiment of the present application. The device is configured on a server, and the server is provided with at least two clock generators; the server is also deployed: BMC, CPLD, and more than two MUXs; the input port of any MUX comprises at least two ports, and only one port is used as the input port to work normally at the same time; the server is also deployed with at least one component having clock domain requirements. As shown in fig. 6, the clock domain control apparatus 600 includes: the obtaining module 601 and the control module 602.

The obtaining module 601 is configured to obtain a target clock domain control manner through the BMC, and notify the CPLD of the target clock domain control manner; the target clock domain control mode is used for indicating a target clock generator used by each component with clock domain requirements in the server; wherein the target clock generators required by different components are the same or different;

the control module 602 is configured to control, by using the CPLD, the input port of at least one MUX to switch, so that the clock generator used by the component connected to the MUX is the target clock generator required to be used by the component indicated by the target clock domain control manner.

As an embodiment, when at least one component having a clock domain requirement is a CPU and a first designated SW chip, respectively, the first MUX is connected to the CPU through a second port of the first MUX, the first MUX is connected to the first designated SW chip through a first output port, the second MUX is connected to the CPU through a first port of the second MUX, and the second MUX is connected to the first designated SW chip through a second output port;

The switching of the input port of at least one MUX is controlled by the CPLD, comprising:

The implementation process of the functions and roles of each module in the above device is specifically shown in the implementation process of the corresponding steps in the above method, and will not be described herein again.

For the device embodiments, reference is made to the description of the method embodiments for the relevant points, since they essentially correspond to the method embodiments. The apparatus embodiments described above are merely illustrative, wherein the modules illustrated as separate components may or may not be physically separate, and the components shown as modules may or may not be physical, i.e., may be located in one place, or may be distributed over a plurality of network modules. Some or all of the modules may be selected according to actual needs to achieve the purposes of the present application. Those of ordinary skill in the art will understand and implement the present application without undue burden.

Referring to fig. 7, a schematic hardware structure of an electronic device according to an exemplary embodiment of the application is shown. The electronic device may include a processor 701, a communication interface 702, a memory 703, and a communication bus 704. The processor 701, the communication interface 702, and the memory 703 perform communication with each other via the communication bus 704. Wherein the memory 703 has stored thereon a computer program; the processor 701 can execute the steps of the method described in the above embodiment by executing a program stored on the memory 703. The electronic device may further include other hardware according to the actual function of the electronic device, which will not be described in detail.

Embodiments of the subject matter and functional operations described in this disclosure may be implemented in the following: digital electronic circuitry, tangibly embodied computer software or firmware, computer hardware including the structures disclosed in this application and structural equivalents thereof, or a combination of one or more of them. Embodiments of the subject matter described in this specification can be implemented as one or more computer programs, i.e., one or more modules of computer program instructions encoded on a tangible, non-transitory program carrier for execution by, or to control the operation of, data processing apparatus. Alternatively or additionally, the program instructions may be encoded on a manually-generated propagated signal, e.g., a machine-generated electrical, optical, or electromagnetic signal, that is generated to encode and transmit information to suitable receiver apparatus for execution by data processing apparatus. The computer storage medium may be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or a combination of one or more of them.

The processes and logic flows described in this application can be performed by one or more programmable computers executing one or more computer programs to perform corresponding functions by operating on input data and generating output. The processes and logic flows can also be performed by, and apparatus can also be implemented as, special purpose logic circuitry, e.g., an FPGA (field programmable gate array) or an ASIC (application-specific integrated circuit).

Computers suitable for executing computer programs include, for example, general purpose and/or special purpose microprocessors, or any other type of central processing unit. Typically, the central processing unit will receive instructions and data from a read only memory and/or a random access memory. The essential elements of a computer include a central processing unit for carrying out or executing instructions and one or more memory devices for storing instructions and data. Typically, a computer will also include, or be operatively coupled to receive data from or transfer data to, or both, one or more mass storage devices for storing data, e.g., magnetic, magneto-optical disks, or optical disks, etc. However, a computer does not have to have such a device. Furthermore, the computer may be embedded in another device, such as a mobile phone, a Personal Digital Assistant (PDA), a mobile audio or video player, a game console, a Global Positioning System (GPS) receiver, or a portable storage device such as a Universal Serial Bus (USB) flash drive, to name a few.

Computer readable media suitable for storing computer program instructions and data include all forms of non-volatile memory, media and memory devices including, for example, semiconductor memory devices (e.g., EPROM, EEPROM, and flash memory devices), magnetic disks (e.g., internal hard disk or removable disks), magneto-optical disks, and CD-ROM and DVD-ROM disks. The processor and the memory can be supplemented by, or incorporated in, special purpose logic circuitry.

While this application contains many specific implementation details, these should not be construed as limitations on the scope of any application or of what may be claimed, but rather as features of specific embodiments of particular applications. Certain features that are described in this application in the context of separate embodiments can also be implemented in combination in a single embodiment. On the other hand, the various features described in the individual embodiments may also be implemented separately in the various embodiments or in any suitable subcombination. Furthermore, although features may be acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.

Similarly, although operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In some cases, multitasking and parallel processing may be advantageous. Moreover, the separation of various system modules and components in the embodiments described above should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

Thus, particular embodiments of the subject matter have been described. Other embodiments are within the scope of the following claims. In some cases, the actions recited in the claims can be performed in a different order and still achieve desirable results. Furthermore, the processes depicted in the accompanying drawings are not necessarily required to be in the particular order shown, or sequential order, to achieve desirable results. In some implementations, multitasking and parallel processing may be advantageous.

The foregoing description of the preferred embodiments of the application is not intended to be limiting, but rather to enable any modification, equivalent replacement, improvement or the like to be made within the spirit and principles of the application.

Claims

1. A clock domain control method, characterized in that the method is applied to a server, which is deployed with at least two clock generators; the server is also configured to: a baseboard management controller BMC, a complex programmable logic device CPLD, and more than two multiplexers MUX; the input port of any MUX comprises at least two ports, and only one port is used as the input port to work normally at the same time; the server is further deployed with at least one component having clock domain requirements;

The method comprises the following steps:

Obtaining a target clock domain control mode through the BMC, and informing the target clock domain control mode to the CPLD; the target clock domain control mode is used for indicating a target clock generator used by each component with clock domain requirements in the server; wherein the target clock generators required by different components are the same or different;

And controlling the input port of at least one MUX to switch through the CPLD so that the clock generator used by the component connected with the MUX is the target clock generator required by the component indicated by the target clock domain control mode.

2. The method of claim 1, wherein the step of determining the position of the substrate comprises,

When at least one component with clock domain requirement is a central processing unit CPU and a first appointed data exchange circuit SW chip respectively, a first MUX is connected with the CPU through a second port of the first MUX, the first MUX is connected with the first appointed SW chip through a first output port, a second MUX is connected with the CPU through a first port of the second MUX, and the second MUX is connected with the first appointed SW chip through a second output port;

the switching of the input port of the at least one MUX controlled by the CPLD includes:

If the target clock generator of the CPU and the target clock generator of the first designated SW chip are both first clock generators, the first clock generator is connected with the CPU, the first MUX is connected with the first clock generator through a first port of the first MUX, and the second MUX is connected with the first clock generator through a second port of the second MUX; controlling the input port of the first MUX to be switched to the first port of the first MUX through the CPLD; or the CPLD controls the input port of the second MUX to be switched to the second port of the second MUX;

if the target clock generator of the CPU and the target clock generator of the first designated SW chip are both second clock generators, the second clock generator is the CPU; controlling the input port of the first MUX to be switched to the second port of the first MUX through the CPLD; or the CPLD controls the input port of the second MUX to be switched to the first port of the second MUX.

3. The method of claim 1, wherein the step of determining the position of the substrate comprises,

When at least one component with clock domain requirement is a first designated SW chip and a graphics processor GPU respectively, a first MUX is connected with the first designated SW chip through a first output port, a second MUX is connected with the first designated SW chip through a second output port, and the second MUX is also connected with the GPU through a second output port;

If the first designated SW chip and the target clock generator of the GPU are both first clock generators, the first MUX is connected with the first clock generators through a first port of the first MUX, and the second MUX is connected with the first clock generators through a second port of the second MUX; controlling the input port of the first MUX to be switched to the first port of the first MUX and controlling the input port of the second MUX to be switched to the second port of the second MUX by the CPLD; or the CPLD controls the input port of the second MUX to be switched to the second port of the second MUX;

If the first designated SW chip and the target clock generator of the GPU are both second clock generators, the second clock generator is a CPU, the first MUX is connected with the CPU through a second port of the first MUX, and the second MUX is connected with the CPU through a first port of the second MUX; controlling the input port of the first MUX to be switched to the second port of the first MUX through the CPLD, and controlling the input port of the second MUX to be switched to the first port of the second MUX; or the CPLD controls the input port of the second MUX to be switched to the first port of the second MUX;

If the target clock generator of the GPU and the first designated SW chip are both third clock generators, the second MUX is connected with the third clock generators through a third port of the second MUX; the input port of the second MUX is controlled by the CPLD to switch to the third port of the second MUX.

4. The method of claim 1, wherein the step of determining the position of the substrate comprises,

When at least one component with clock domain requirement is a CPU and a second designated SW chip respectively, a first MUX is connected with the CPU through a second port of the first MUX, the first MUX is connected with a third port of a third MUX through a first output port, a second MUX is connected with the CPU through a first port of the second MUX, the second MUX is connected with the first port of the third MUX through a second output port, and the third MUX is connected with the second designated SW chip through a third output port;

If the target clock generator of the CPU and the target clock generator of the second designated SW chip are both first clock generators, the first clock generators are connected with the CPU, the first MUX is connected with the first clock generators through a first port of the first MUX, and the second MUX is connected with the first clock generators through a second port of the second MUX; controlling the input port of the first MUX to be switched to the first port of the first MUX and controlling the input port of the third MUX to be switched to the third port of the third MUX by the CPLD; or the CPLD controls the input port of the second MUX to be switched to the second port of the second MUX, and controls the input port of the third MUX to be switched to the first port of the third MUX;

If the target clock generator of the CPU and the target clock generator of the second designated SW chip are both second clock generators, the second clock generator is the CPU; controlling the input port of the first MUX to be switched to the second port of the first MUX and controlling the input port of the third MUX to be switched to the third port of the third MUX by the CPLD; or the CPLD controls the input port of the second MUX to be switched to the first port of the second MUX, and controls the input port of the third MUX to be switched to the first port of the third MUX.

5. The method of claim 1, wherein the step of determining the position of the substrate comprises,

When at least one component with the clock domain requirement is a CPU and a GPU respectively, a first MUX is connected with the CPU through a second port of the first MUX, a second MUX is connected with the CPU through a first port of the second MUX, and the second MUX is connected with the GPU through a second output port;

If the target clock generator of the CPU and the target clock generator of the GPU are both first clock generators, the first clock generator is connected with the CPU, and the second MUX is connected with the first clock generator through a second port of the second MUX; controlling the input port of the second MUX to be switched to the second port of the second MUX through the CPLD;

if the target clock generator of the CPU and the target clock generator of the GPU are both second clock generators, the second clock generator is the CPU; the input port of the second MUX is controlled by the CPLD to switch to the first port of the second MUX.

6. The method of claim 1, wherein the step of determining the position of the substrate comprises,

When at least one component with clock domain requirement is a first designated SW chip and a second designated SW chip respectively, a first MUX is connected with the first designated SW chip through a first output port, the first MUX is connected with a third port of a third MUX through the first output port, a second MUX is connected with the first designated SW chip through a second output port, the second MUX is connected with the first port of the third MUX through the second output port, and the third MUX is connected with the second designated SW chip through the third output port;

If the target clock generators of the first designated SW chip and the second designated SW chip are both first clock generators, the first MUX is connected with the first clock generators through a first port of the first MUX, and the second MUX is connected with the first clock generators through a second port of the second MUX; controlling the input port of the first MUX to be switched to the first port of the first MUX and controlling the input port of the third MUX to be switched to the third port of the third MUX by the CPLD; or the CPLD controls the input port of the second MUX to be switched to the second port of the second MUX, and controls the input port of the third MUX to be switched to the first port of the third MUX;

if the target clock generators of the first designated SW chip and the second designated SW chip are both second clock generators, the second clock generator is a CPU, the first MUX is connected with the CPU through a second port of the first MUX, and the second MUX is connected with the CPU through a first port of the second MUX; controlling the input port of the first MUX to be switched to the second port of the first MUX and controlling the input port of the third MUX to be switched to the third port of the third MUX by the CPLD; or the CPLD controls the input port of the second MUX to be switched to the first port of the second MUX, and controls the input port of the third MUX to be switched to the first port of the third MUX.

7. A clock domain switching apparatus, wherein the apparatus is configured in a server, the server being provided with at least two clock generators; the server is also configured to: a baseboard management controller BMC, a complex programmable logic device CPLD, and more than two multiplexers MUX; the input port of any MUX comprises at least two ports, and only one port is used as the input port to work normally at the same time; the server is further deployed with at least one component having clock domain requirements;

the device comprises:

8. The apparatus of claim 7, wherein the device comprises a plurality of sensors,

If the target clock generator of the CPU and the target clock generator of the first designated SW chip are both second clock generators, the second clock generator is the CPU; controlling the input port of the first MUX to be switched to the second port of the first MUX through the CPLD; or the CPLD controls the input port of the second MUX to be switched to the first port of the second MUX;

and/or the number of the groups of groups,

If the first designated SW chip and the target clock generator of the GPU are both second clock generators, the second clock generator is the CPU, the first MUX is connected with the CPU through a second port of the first MUX, and the second MUX is connected with the CPU through a first port of the second MUX; controlling the input port of the first MUX to be switched to the second port of the first MUX through the CPLD, and controlling the input port of the second MUX to be switched to the first port of the second MUX; or the CPLD controls the input port of the second MUX to be switched to the first port of the second MUX;

If the target clock generator of the GPU and the first designated SW chip are both third clock generators, the second MUX is connected with the third clock generators through a third port of the second MUX; controlling the input port of the second MUX to be switched to the third port of the second MUX through the CPLD;

and/or the number of the groups of groups,

If the target clock generator of the CPU and the target clock generator of the second designated SW chip are both second clock generators, the second clock generator is the CPU; controlling the input port of the first MUX to be switched to the second port of the first MUX and controlling the input port of the third MUX to be switched to the third port of the third MUX by the CPLD; or the CPLD controls the input port of the second MUX to be switched to the first port of the second MUX, and controls the input port of the third MUX to be switched to the first port of the third MUX;

and/or the number of the groups of groups,

If the target clock generator of the CPU and the target clock generator of the GPU are both second clock generators, the second clock generator is the CPU; controlling the input port of the second MUX to be switched to the first port of the second MUX through the CPLD;

and/or the number of the groups of groups,

When at least one component with clock domain requirement is a first designated SW chip and a second designated SW chip respectively, a first MUX is connected with the first designated SW chip through a first output port, the first MUX is connected with a third port of a third MUX through the first output port, a second MUX is connected with the first designated SW chip through the second output port, the second MUX is connected with the first port of the third MUX through the second output port, and the third MUX is connected with the second designated SW chip through the third output port;

if the target clock generators of the first designated SW chip and the second designated SW chip are both second clock generators, the second clock generator is the CPU, the first MUX is connected with the CPU through a second port of the first MUX, and the second MUX is connected with the CPU through a first port of the second MUX; controlling the input port of the first MUX to be switched to the second port of the first MUX and controlling the input port of the third MUX to be switched to the third port of the third MUX by the CPLD; or the CPLD controls the input port of the second MUX to be switched to the first port of the second MUX, and controls the input port of the third MUX to be switched to the first port of the third MUX.

9. An electronic device, comprising:

A processor; and

A memory in which computer program instructions are stored which, when executed by the processor, cause the processor to perform the steps of the method of any one of claims 1 to 6.

10. A computer readable storage medium, characterized in that it has stored thereon computer program instructions which, when executed by a processor, cause the processor to perform the steps of the method according to any of claims 1 to 6.