CN118068166A - Method and device for detecting abnormal running state of chip pins - Google Patents
Method and device for detecting abnormal running state of chip pins Download PDFInfo
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Abstract
The invention relates to a method and a device for detecting abnormal running state of a chip pin, wherein the device comprises the following steps: a plurality of detection operation and processing units, an abnormality detection configuration unit, and a control unit; the plurality of detection operation and processing units form a detection operation and processing unit array; the detection operation and processing unit includes: a configurable digital filter, an input logic operation module, two or more input selection modules; the invention supports to continuously detect the input value and the output value of the chip pin in a hardware mode by configuring the hardware module constructed by the digital filter so as to judge whether the current pin output state works normally or not, and has high instantaneity and low resource occupation. Meanwhile, software and hardware mode judgment is also optionally supported, so that the optimal balance between resources and efficiency is achieved, and the efficiency and the effect of anomaly detection are greatly improved.
Description
Technical Field
The invention belongs to the technical field of chip abnormality detection, and particularly relates to a method and a device for detecting the abnormal running state of a chip pin.
Background
The chip test has very important functions in the development, production and use processes of the integrated circuit, and the reliable test of the chip is very necessary. In particular, for the vehicle-gauge chip, in order to meet the output signals required in the design of the automotive electronic system, an application scenario in which verification must be read back and forth in some way appears. And such a scene is a common scene.
As automotive electronics develop more and more complex, so too does the need for functional pins of microprocessors in automotive electronics, so too does the monitoring of the operating conditions of these pins. Traditional monitoring based on software mode, as more pins need to be detected, software is more and more complex, and the computational power consumption of a processor is more and more. Specifically, on the one hand, as the productivity of the circuit chip field is gradually increased, the damage and maintenance of the circuit chip are increased. And for a large number of circuit chips, the number of pins of the circuit chips is in an exponentially growing situation. On the other hand, with the increasing number of application scenes of chips, the number of scenes that need to be tested is also increasing exponentially. In the third aspect, the conventional solution can only detect the input and output problems of a chip overall, but cannot or does not detect whether each pin of the chip has a problem or not. That is, in the process of detecting a circuit fault problem, only one fault cause is usually identified, all fault causes cannot be identified, and a circuit fault problem cannot be removed by repairing a single fault cause. The traditional scheme is generally used for detecting only by means of software readback judgment, is low in efficiency, occupies processor time and is low in instantaneity. Many situations in the emerging scenes of automobile applications and the like require read-back detection of the state of an external circuit, for example, the external circuit is controlled through a pin A, and the working state of the external circuit is fed back through a pin B. If there is no hardware detection mode, the software needs to periodically read back the signal on pin B and compare it with the expected signal.
Under the situation of the rapid increase caused by the above factors, the comprehensive detection by adopting the traditional method cannot be completed. Therefore, the abnormal detection of the pin operation state of the stacked chip of various factors brings great challenges, and the invention supports the continuous detection of the input value and the output value of the pin of the chip in a hardware mode by configuring the hardware module constructed by the digital filter so as to judge whether the current pin output state works normally or not, and has high instantaneity and low resource occupation. The monitoring scheme based on the hardware mode does not need real-time participation of software and a processor, so that the software design can be very effectively simplified, and the load of the processor is reduced. Meanwhile, software and hardware mode judgment is optionally supported, so that the optimal balance between resources and efficiency is achieved, the efficiency and the effect of abnormality detection are greatly improved, and the abnormal detection of the running state of the large-scale chip pin test is possible.
Disclosure of Invention
In order to solve the above problems in the prior art, the present invention provides a method and an apparatus for detecting abnormal operation states of chip pins, where the apparatus includes: the chip pin operation state abnormality detection device comprises: a plurality of detection operation and processing units, an abnormality detection configuration unit, and a control unit; the plurality of detection operation and processing units form a detection operation and processing unit array; the abnormality detection configuration unit is used for configuring the functions, inputs and/or connection relations of the detection operation and processing unit according to the configuration information; the control unit is used for determining configuration information according to the abnormality detection task;
the detection operation and processing unit includes: a configurable digital filter, an input logic operation module, two or more input selection modules;
the configurable digital filter is used for filtering the result, preventing the delay jitter of the external circuit from generating abnormal signal trigger and compensating the delay of the external circuit of the signal;
the input logic operation module is used for realizing AND, OR, NOT, XOR and/or AND or combination logic operation, carrying out logic processing on the input signals, extracting target signals and filtering external noise, and supporting at least two paths of input from the input selection module;
The input selection module is used for accessing multiple paths of input signals and supporting the selection of the multiple paths of input signals; the multi-path input signals are different types of input signals, and comprise two or more pin inputs, internally generated signals and other channel cascade signals;
the other channel cascade signals are used for realizing multi-channel complex combination logic signals; the cascade connection of the detectors is carried out through other channel cascade signals to realize complex combinational logic signals; the channel cascade signal is used for expanding and realizing multi-channel complex combinational logic;
Each detection operation and processing unit can be configured in a plurality of modes, corresponding to configurations of different functions, inputs and/or connection relationships; wherein: the mode comprises a pin abnormality detection mode, an external circuit detection mode and/or an external noise filtering mode; specific:
Pin anomaly detection mode: in the mode, when the input of the detection operation and processing unit is configured into an output control signal and an input readback signal of the pin and the logic operation module realizes an exclusive or function, the digital filter is responsible for the delay processing of the pin signal; at this time, the detection operation and processing unit can complete detection of open circuit, short circuit and/or overcurrent abnormality for one pin;
External circuit detection mode: in the mode, the input of the detection operation and processing unit is configured into a feedback signal read back by a pin B and an expected pin A signal, and when the logic operation module realizes an exclusive OR function, the feedback signal read back by the pin B and the expected pin A signal are directly compared in hardware in real time to realize the work detection of an external circuit;
external noise filtering mode: in this mode, the input of the detection operation and processing unit is configured as a feedback signal read back at pin B and a filter window signal generated internally by the chip controller, and the logic operation module implements the AND operation function to achieve the generation of the desired output signal.
Further, when an abnormal state is detected, the detection operation and processing unit directly notifies the control unit or the chip processor in an interrupt mode.
Further, the digital filter avoids erroneous judgment of external circuit delay by realizing delay compensation.
Further, the external circuit detection mode is detection of an external circuit state in an automotive application.
Further, the feedback signal read back by pin B is noisy.
Further, the noise is periodic or regular noise.
Further, the control unit determines one or more configuration information according to the abnormality detection task and forms a configuration information sequence; the arrangement order of the configuration information in the sequence corresponds to the arrangement order of the test nodes defined by the abnormality detection task.
A chip comprises the chip pin running state abnormality detection device.
A chip pin operation state abnormality detection method uses the chip pin operation state abnormality detection device to detect an abnormality detection task.
A test chip comprises the chip pin running state abnormality detection device.
The beneficial effects of the invention include:
(1) By setting the special hardware module with various working modes, the continuous detection of the input value and the output value of the chip pin in a hardware mode is supported, the instantaneity is high, and the resource occupation is low. In the independent filter, the support expansion realizes simple hardware signal processing, noise shielding of hardware signals, hardware operation of input signals and complex operation in a cascade mode; the configurable delay and the filter setting can flexibly adapt to different external delay configuration scenes; the multi-channel and multi-input selection mode can flexibly adapt to a large number of pins and various application scenes;
(2) The method supports complex scenes, performs multidimensional description on application scenes or test scenes when abnormality detection is performed, supports dynamic software and hardware mode judgment under different scenes, and quantitatively considers complex scene parameters brought by the complex scenes, so that the efficiency and effect of abnormality detection are greatly improved, and the abnormal detection of the running state of the large-scale chip pin test is possible;
(3) The configuration information sequence is introduced to support global optimization, the prediction judgment is carried out on the configuration information in advance based on the noise distribution of priori signals and the inherent characteristics of the signals, the software and hardware judgment is carried out by using the filter configuration with N steps dynamically, the introduced judgment coefficient indicates the amount of hardware configuration cost aiming at a detection operation and processing unit and brought by adapting to new configuration information, so that the real-time judgment is carried out directionally, the optimal balance between resources and efficiency is sought, the efficiency and the effect of abnormality detection are improved greatly, and the abnormal detection of the running state of the large-scale chip pin test becomes possible.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate and together with the description serve to explain the application, if necessary:
FIG. 1 is a schematic diagram of a device for detecting abnormal operation states of chip pins according to the present invention;
FIG. 2 is a schematic diagram of a detecting operation and processing unit according to the present invention;
FIG. 3 is a schematic diagram of the present invention implementing a multi-channel complex combinational logic signal via cascaded signals;
FIG. 4 is a schematic diagram of a configuration of the detecting operation and processing unit of the present invention when the detecting operation and processing unit is configured in a pin abnormality detecting mode;
FIG. 5 is a schematic diagram of the configuration of the detection operation and processing unit of the present invention when it is configured in an external operation detection mode;
fig. 6 is a schematic diagram of the structure of the detection operation and processing unit of the present invention when the detection operation and processing unit is configured in the external noise filtering mode.
Detailed Description
The present invention will now be described in detail with reference to the drawings and the specific embodiments thereof, wherein the exemplary embodiments and the description are for the purpose of illustrating the invention only and are not to be construed as limiting the invention.
As shown in fig. 1, the present invention provides a device for detecting abnormal operation state of a chip pin, the device for detecting abnormal operation state of a chip pin includes: a plurality of detection operation and processing units, an abnormality detection configuration unit, and a control unit; the plurality of detection operation and processing units form a detection operation and processing unit array; the abnormality detection configuration unit is used for configuring the functions, inputs and/or connection relations of the detection operation and processing unit according to the configuration information; the control unit is used for determining configuration information according to the abnormality detection information; the abnormality monitoring information includes an abnormality detection task queue, an abnormality detection node, a schedule of abnormality detection, and the like;
Preferably: the control unit determines one or more pieces of configuration information according to the abnormality detection task and forms a configuration information sequence; the arrangement order of the configuration information in the sequence corresponds to the arrangement order of the test nodes defined by the abnormality detection task.
As shown in fig. 2, the detection operation and processing unit includes: a configurable digital filter, an input logic operation module, two or more input selection modules;
The configurable digital filter is used for filtering the result, preventing the delay jitter of the external circuit from generating abnormal signal trigger, and compensating the delay of the external circuit of the signal;
The input logic operation module is used for realizing and, OR, NOT, XOR, AND, OR and the like combined logic operation, and can realize logic processing on input signals so as to extract target signals and filter external noise, and the logic operation module can support at least two paths of input from the input selection module;
The input selection module is used for accessing multiple paths of input signals and supporting the selection of the multiple paths of input signals; the multiple signals are different types of input signals, including two or more pin inputs, internally generated signals, and other channel cascade signals, etc.
As shown in fig. 3, the other channel cascade signals are used for realizing multi-channel complex combinational logic signals; cascading detectors through other channel cascading signals to realize complex combinational logic signals; the channel cascade signal can realize multi-channel complex combinational logic, for example, combinational logic ((A|B) & C) & lt D) of the pins A/B/C/D is realized, three detection operation and processing units are needed for realizing the logic, namely a first detection operation and processing unit, a second detection operation and processing unit and a third detection operation and processing unit, wherein the port pin A and the port pin B are selected, and the OR' is logically selected; select port pin C AND 'cascade channel input' in the second detection operation AND processing unit (originating from the third detection operation AND processing unit), logically select 'AND'; the selection port pin D and the 'cascade channel input' in the first detection operation and processing unit (originating from the second detection operation and processing unit) logically select 'XOR'.
Preferably: each detection operation and processing unit can be configured in a plurality of modes, corresponding to configurations of different functions, inputs and/or connection relationships; when an abnormal state is detected, the detection operation and processing unit directly informs the control unit or the chip processor in an interrupt mode; wherein: the mode comprises a pin abnormality detection mode, an external circuit detection mode and an external noise filtering mode; specific:
pin anomaly detection mode: as shown in fig. 4, in this mode, the input of the detection operation and processing unit is configured as an output control signal and an input readback signal of the pin, and when the logic operation module implements the exclusive or function, the digital filter is responsible for the delay processing of the pin signal; at this time, the detection operation and processing unit can complete detection of abnormality such as open circuit, short circuit, overcurrent, etc. for one pin.
External circuit detection mode: as shown in fig. 5, in the mode, the input of the detection operation and processing unit is configured into a feedback signal read back by a pin B and an expected pin a signal, and when the logic operation module realizes an exclusive or function, the feedback signal read back by the pin B and the expected pin a signal are directly compared in hardware in real time to realize the detection of the external circuit operation;
preferably: the digital filter realizes delay compensation to avoid delay misjudgment of an external circuit;
Preferably: the external circuit detection mode is the detection of the external circuit state in automotive applications.
External noise filtering mode: as shown in fig. 6, the input of the detection operation AND processing unit is configured as a feedback signal read back at pin B AND a filter window signal generated inside the microprocessor, AND the logic operation module implements the AND operation (AND) function to achieve the generation of the desired output signal;
preferably: the feedback signal read back by the pin B is noisy;
Preferably: the noise is periodic noise.
It can be seen that the configurable digital filtering unit has a plurality of working modes, and the special hardware module with the plurality of working modes is arranged to support the continuous detection of the input value and the output value of the chip pin in a hardware mode; the real-time performance is high, and the resource occupation is low. In the independent filter, the support expansion realizes simple hardware signal processing, noise shielding of hardware signals, hardware operation of input signals and complex operation in a cascade mode; the configurable delay and the filter setting can flexibly adapt to different external delay configuration scenes; the multi-channel and multi-input selection mode can flexibly adapt to a large number of pins and various application scenes.
The control unit also comprises a judging module; because how to perform large-scale and efficient anomaly detection is a problem to be considered under the condition that application scenes are continuously complicated; by supporting complex scenes, multidimensional description is carried out on application scenes or test scenes when abnormality detection is carried out, dynamic software and hardware mode judgment under different scenes is supported, complex scene parameters brought by the complex scenes are quantitatively considered, and therefore the efficiency and effect of abnormality detection are greatly improved, and large-scale chip pin test running state abnormality detection can be enabled to be possible.
The judging module is used for making a decision on an abnormality detection mode to be adopted according to a scene; wherein: the abnormality detection mode comprises a software mode and a hardware mode; compared with a software mode, the hardware mode can respond more timely, and an external hardware circuit can be protected timely; the software mode is more flexible, and is suitable for the conditions of complex configuration information and complex scene, but the chip is slowed down due to the occupation of processor resources.
Preferably; when the judgment result is in a hardware mode, configuring the functions, inputs and/or connection relations of the detection operation and processing units in the detection operation and processing unit array according to the current configuration information; when the software mode is adopted, the signals described in the configuration information are operated by adopting a logic operation mode described in the configuration information in a software program mode, and a detection result is obtained;
preferably: the decision module makes decisions each time a new scenario is entered or a configuration is required during task execution according to the new configuration information.
The judging module is specifically used for realizing the following steps:
The method comprises the following steps of sub A1, acquiring scene parameters corresponding to a current scene in real time; each scene corresponds to one or more scene parameters, and the scene parameters corresponding to different scenes are the same, partially the same or different;
Preferably: the scenes comprise one or a combination of role scenes, hardware scenes (distinguished from the types of hardware and the like), application scenes (PWM test, communication IO test, limit test), environment scenes (high-temperature environment and extremely cold environment) and the like; the scene parameters are numerical expression parameters, including: administrator authority, user authority, chip response speed, chip temperature, chip frequency, complex configuration, and the like.
Step sub A2, calculating a first judgment value according to scene parameters;
Preferably: the standard value interval is preset; presetting standard value intervals corresponding to different abnormality detection modes; different tendency of abnormal detection modes corresponding to standard value intervals are fallen or not fallen; different scene parameters correspond to different standard value intervals; the standard value interval is one or more;
said calculating a first decision value based on the scene parameters The method specifically comprises the following steps: calculating a first decision value on the basis of the field Jing Canshu and the standard value interval to which the first decision value belongs by adopting a weighted summation mode; further: calculating a first judgment value/>, by adopting the following steps (1) - (2); Wherein: /(I)Is the kth scene parameter; /(I)Is the standard value interval of the kth scene parameter,/>The lower and upper limit values are respectively; /(I)Is the adjustment coefficient of the kth scene parameter; /(I)Is an intermediate calculated value; the first decision value points to two directions corresponding to different anomaly detection modes respectively; therefore, trade-off can be made among real-time performance, processor busyness, hardware configuration overhead and flexibility, and different directions of abnormality detection modes are moved;
(1);
(2);
alternatively, the following is used: fitting function by using the following formula (3) Calculating a first decision value; wherein: /(I)Fitting based on historical data; of course, if the decision model can be trained in an artificial intelligence model manner to obtain the first decision value according to the scene parameters, there will be a finer and more accurate decision; but for existing application scenarios, the existing configuration parameters can be set directly if there is already a fixed decision criterion. Otherwise, a large amount of historical data needs to be statistically analyzed to obtain an effective configuration result, which inevitably introduces more calculation cost and training cost;
(3)。
Determining the corresponding abnormality detection mode according to the first judgment value; the method comprises the following steps: the first judgment value is larger than the demarcation value, a hardware mode is adopted, otherwise, a software mode is adopted;
Preferably: the demarcation value is a preset value;
Alternatively, the following is used: the first judgment value is smaller than or equal to the demarcation value, a hardware mode is adopted, otherwise, a software mode is adopted; the specific decision mode is corresponding to the setting mode of the standard value interval;
Alternatively, the following is used: the step sub A3 specifically comprises the following steps: calculating a judgment coefficient, and determining a corresponding abnormal detection mode according to the first judgment value and the judgment coefficient; wherein: the decision coefficients indicate how much hardware configuration overhead is incurred for the detection operation and processing unit in order to accommodate the new configuration information.
The calculating judgment coefficient is specifically as follows: determining conversion cost for reconfiguration according to the difference condition between the current configuration information and the next configuration information (and a plurality of subsequent configuration information); determining a decision coefficient to indicate the size of hardware configuration overhead caused by adaptively reconfiguring the detection operation and processing unit under the configuration field condition corresponding to the current configuration information; the method specifically comprises the following steps:
step SubB1: acquiring current configuration information ; That is, the site situation is configured, including the function of each detection operation and processing unit, the number or filtering length of each detection operation and processing unit, the connection relation and the input situation.
Step SubB2: acquiring a configuration information sequence, wherein the configuration information sequence comprises one or more pieces of configuration information arranged according to a time sequence; in the process of realizing the abnormal detection of the running state of the pins of the whole chip, the configuration is carried out according to the sequence, so that the whole detection process or detection plan is realized; the final implementation of this configuration information, of course, may be in software or hardware depending on the decision result.
Step SubB3: calculating conversion overhead of first N configuration information in configuration information sequence; The method specifically comprises the following steps:
step SubB31: sequentially acquiring unprocessed configuration information from the head of the configuration information sequence I is the scene information number in the sequence,/>; Calculating the unprocessed configuration information/>Conversion overhead/>, between the previous neighbor configuration information; Setting the initial value of i to be 1;
Preferably: when the judging time arrives, the unprocessed configuration information is acquired from the head of the configuration information sequence in turn;
Alternatively, the following is used: when scene switching is performed each time, uniformly performing one-time judgment;
alternatively, the following is used: after finishing the execution of the configuration information for N times, carrying out one-time judgment;
the method comprises the following steps: calculating the unprocessed configuration information according to the following (4) Adjacent transition overhead/>, between and previous adjacent configuration information; Wherein: /(I)、/>The difference between the i-th configuration information and the i-1-th configuration information in function difference, input difference and/or connection relation; the functional difference, the input difference and the connection relation difference can be quantitatively described by a plurality of angles such as the reconfiguration area size, the reconfiguration time, the number of the reconfigured digital filter units, the number of the reconfigured communication switches, the number of the reconfigured connecting lines and the like; /(I)Is the differential balance coefficient;
(4);
Preferably: is a preset value, for example: set/> ；
Further, the unprocessed configuration information is calculated according to the formula (4) and the following formulas (5) - (7)Adjacent transition overhead/>, between and previous adjacent configuration information; Wherein: /(I)And/>The number of p-th type functions in the i-th and i-1-th configuration information, respectively; /(I)The number of the q type input modes in the i-th configuration information and the i-1-th configuration information respectively; /(I)The i < th >, respectively in the i < th > and i < th > -1 < th > configuration informationThe number of type connection modes;
(5);
(6);
(7)；
Step SubB32: setting i=i+1; if it is Entering the next step, otherwise returning to the step SubB;
Step SubB33: based on neighbor conversion overhead Calculate conversion overhead/>; The method comprises the following steps: by non-uniform linear coefficientsCalculate conversion overhead/>；
For example: calculating conversion cost by using the following steps (8) - (10)；/>，/>Are all intermediate calculations; wherein:
(8);
(9);
(10);
Preferably: a1 and a2 are preset values, and ；
Preferably:；
More specifically, n=1 may be set directly, that is, ；
Alternatively, the following is used: the cost is converted according to the adjacent conversionCalculate conversion overhead/>; The method comprises the following steps: by non-linear reduction coefficientsConversion overhead/>, by fast descent calculation; For example: conversion overhead/>, is calculated by the following formulas (11) - (13); Wherein:
(11);
(12);
(13);
(14);
Preferably: n=2 to 10.
Step SubB4: based on the conversion overheadAnd average overhead/>Determining a decision coefficient/>; Wherein: the average overhead/>Is the average value of the historical conversion overhead; of course, the average value may be empirically given; it can be seen that the larger the decision coefficient is, the larger the conversion overhead is, and the less suitable for the hardware mode is;
Preferably: calculating a decision coefficient using the following (15) ；
(15)。
Step SubB: determining the corresponding abnormality detection mode according to the first judgment value and the judgment coefficient; the method comprises the following steps: if it isIf the value is larger than the boundary value, adopting a hardware mode, otherwise adopting a software mode;
Alternatively, the following is used: if it is If the value is smaller than or equal to the demarcation value, adopting a hardware mode, otherwise adopting a software mode; the specific decision mode is corresponding to the setting mode of the standard value interval.
The whole detection view can be known by introducing the configuration information sequence according to the detection plan, and the configuration information sequence can be obtained based on prediction, but on the basis, global optimization can be supported, and the software and hardware judgment is dynamically carried out globally by using N step steps through the predictive judgment of the configuration information, so that the optimal balance between resources and efficiency is achieved, the efficiency and effect of abnormality detection are greatly improved, and the abnormal detection of the running state of the large-scale chip pin test becomes possible.
The abnormality detection configuration unit is used for configuring the functions, the inputs and the connection relations of the detection operation and processing unit according to the configuration information; the method comprises the following steps: the abnormality detection configuration unit realizes configuration of connection relations by setting connection relations of other channel cascade signals of each detection operation and processing unit.
The terms "control unit", "chip", "test terminal" encompass all kinds of devices, apparatus and machines for processing data, including by way of example a programmable processor, a computer, a system on a chip, or a plurality of or a combination of the foregoing. The apparatus can comprise dedicated logic circuits, such as an FPGA (field programmable gate array) or an ASIC (application specific integrated circuit). In addition to hardware, the apparatus may include code to create an execution environment for the computer program, e.g., code that constitutes processor firmware, a protocol stack, a database management system, an operating system, a cross-platform runtime environment, a virtual machine, or a combination of one or more of the foregoing. The apparatus and execution environment may implement a variety of different computing model infrastructures, such as web services, distributed computing, and grid computing infrastructures.
A computer program (also known as a program, software application, script, or code) can be written in any form of programming language, including compiled or interpreted languages, declarative or procedural languages, and it can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, object or other unit suitable for use in a computing environment. The computer program may, but need not, correspond to a file in a file system. A program can be stored in a portion of a file that holds other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program, or in multiple coordinated files (e.g., files that store one or more modules, subroutines, or portions of code). A computer program can be deployed to be executed on one computer or on multiple computers at one site or distributed across multiple sites and interconnected by a communication network.
It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
Finally, it should be noted that: the above embodiments are only for illustrating the technical aspects of the present invention and not for limiting the same, and although the present invention has been described in detail with reference to the above embodiments, it should be understood by those of ordinary skill in the art that: modifications and equivalents may be made to the specific embodiments of the invention without departing from the spirit and scope of the invention, which is intended to be covered by the claims.
Claims (10)
1. The utility model provides a chip pin running state anomaly detection device which characterized in that includes:
The chip pin operation state abnormality detection device comprises: a plurality of detection operation and processing units, an abnormality detection configuration unit, and a control unit; the plurality of detection operation and processing units form a detection operation and processing unit array; the abnormality detection configuration unit is used for configuring the functions, inputs and/or connection relations of the detection operation and processing unit according to the configuration information; the control unit is used for determining configuration information according to the abnormality detection task;
the detection operation and processing unit includes: a configurable digital filter, an input logic operation module, two or more input selection modules;
the configurable digital filter is used for filtering the result, preventing the delay jitter of the external circuit from generating abnormal signal trigger and compensating the delay of the external circuit of the signal;
the input logic operation module is used for realizing AND, OR, NOT, XOR and/or AND or combination logic operation, carrying out logic processing on the input signals, extracting target signals and filtering external noise, and supporting at least two paths of input from the input selection module;
The input selection module is used for accessing multiple paths of input signals and supporting the selection of the multiple paths of input signals; the multi-path input signals are different types of input signals, and comprise two or more pin inputs, internally generated signals and other channel cascade signals;
the other channel cascade signals are used for realizing multi-channel complex combination logic signals; the cascade connection of the detectors is carried out through other channel cascade signals to realize complex combinational logic signals; the channel cascade signal is used for expanding and realizing multi-channel complex combinational logic;
Each detection operation and processing unit can be configured in a plurality of modes, corresponding to configurations of different functions, inputs and/or connection relationships; wherein: the mode comprises a pin abnormality detection mode, an external circuit detection mode and/or an external noise filtering mode; specific:
Pin anomaly detection mode: in the mode, when the input of the detection operation and processing unit is configured into an output control signal and an input readback signal of the pin and the logic operation module realizes an exclusive or function, the digital filter is responsible for the delay processing of the pin signal; at this time, the detection operation and processing unit can complete detection of open circuit, short circuit and/or overcurrent abnormality for one pin;
external circuit detection mode: in the mode, the input of the detection operation and processing unit is configured into a feedback signal of pin readback and an expected pin signal, and when the logic operation module realizes an exclusive OR function, the feedback signal of pin readback and the expected pin signal are directly compared in hardware in real time to realize the work detection of an external circuit;
External noise filtering mode: in this mode, the input of the detection operation and processing unit is configured as a feedback signal for pin readback and a filter window signal generated internally by the chip controller, and the logic operation module implements and operates the function to achieve the generation of the desired output signal.
2. The device according to claim 1, wherein the detection operation and processing unit directly notifies the control unit or the chip processor by interrupt mode when the abnormal state is detected.
3. The device for detecting abnormal operation of a chip pin according to claim 2, wherein the digital filter prevents erroneous judgment of delay of an external circuit by implementing delay compensation.
4. The device of claim 3, wherein the external circuit detection mode is detection of an external circuit state in an automotive application.
5. The device of claim 4, wherein the feedback signal from the pin read back is noisy.
6. The device for detecting abnormal operation of a chip pin according to claim 4, wherein the noise is periodic or regular noise.
7. The device according to claim 6, wherein the control unit determines one or more configuration information based on the abnormality detection task and constructs a configuration information sequence; the arrangement order of the configuration information in the sequence corresponds to the arrangement order of the test nodes defined by the abnormality detection task.
8. A chip, characterized in that the chip comprises the chip pin operation state abnormality detection device according to any one of claims 1 to 7.
9. A chip-pin-operation-state abnormality detection method, characterized in that the method uses the chip-pin-operation-state abnormality detection device according to any one of claims 1 to 7 for detection of an abnormality detection task.
10. A test chip, characterized in that the test chip comprises the chip pin operation state abnormality detection device according to any one of claims 1 to 7.
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Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR960042354A (en) * | 1995-05-13 | 1996-12-21 | 김주용 | Memory device with multiple input / output test |
| US20100146338A1 (en) * | 2008-12-05 | 2010-06-10 | Schalick Christopher A | Automated semiconductor design flaw detection system |
| US20110119646A1 (en) * | 2009-11-19 | 2011-05-19 | David Murray | Integrated circuits design |
| CN107422255A (en) * | 2017-07-13 | 2017-12-01 | 南京信息工程大学 | A kind of digit chip fault detection system and its detection method |
| CN113296430A (en) * | 2021-04-13 | 2021-08-24 | 东风汽车集团股份有限公司 | Method and system for monitoring logical operation data flow fault of master-slave chip processing unit |
| US20230090760A1 (en) * | 2021-09-23 | 2023-03-23 | Hewlett Packard Enterprise Development Lp | Fpga chip with protected jtag interface |
| WO2023130797A1 (en) * | 2022-01-10 | 2023-07-13 | 珠海格力电器股份有限公司 | Abnormality detection circuit and method |
| CN116880316A (en) * | 2023-08-02 | 2023-10-13 | 珠海格力电器股份有限公司 | Main control chip pin fault processing circuit |
| CN117011260A (en) * | 2023-07-28 | 2023-11-07 | 西安电子科技大学重庆集成电路创新研究院 | Automatic chip appearance defect detection method, electronic equipment and storage medium |
| CN117636996A (en) * | 2023-11-28 | 2024-03-01 | 苏州元脑智能科技有限公司 | Method and device for detecting memory pin state |
-
2024
- 2024-04-22 CN CN202410480850.XA patent/CN118068166B/en active Active
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR960042354A (en) * | 1995-05-13 | 1996-12-21 | 김주용 | Memory device with multiple input / output test |
| US20100146338A1 (en) * | 2008-12-05 | 2010-06-10 | Schalick Christopher A | Automated semiconductor design flaw detection system |
| US20110119646A1 (en) * | 2009-11-19 | 2011-05-19 | David Murray | Integrated circuits design |
| CN107422255A (en) * | 2017-07-13 | 2017-12-01 | 南京信息工程大学 | A kind of digit chip fault detection system and its detection method |
| CN113296430A (en) * | 2021-04-13 | 2021-08-24 | 东风汽车集团股份有限公司 | Method and system for monitoring logical operation data flow fault of master-slave chip processing unit |
| US20230090760A1 (en) * | 2021-09-23 | 2023-03-23 | Hewlett Packard Enterprise Development Lp | Fpga chip with protected jtag interface |
| WO2023130797A1 (en) * | 2022-01-10 | 2023-07-13 | 珠海格力电器股份有限公司 | Abnormality detection circuit and method |
| CN117011260A (en) * | 2023-07-28 | 2023-11-07 | 西安电子科技大学重庆集成电路创新研究院 | Automatic chip appearance defect detection method, electronic equipment and storage medium |
| CN116880316A (en) * | 2023-08-02 | 2023-10-13 | 珠海格力电器股份有限公司 | Main control chip pin fault processing circuit |
| CN117636996A (en) * | 2023-11-28 | 2024-03-01 | 苏州元脑智能科技有限公司 | Method and device for detecting memory pin state |
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