CN118057518A

CN118057518A - Pixel circuit and driving method thereof, display panel and driving method thereof, and display device

Info

Publication number: CN118057518A
Application number: CN202211456521.9A
Authority: CN
Inventors: 贺家煜; 周天民; 胡合合; 杨维; 宁策; 李正亮; 姚念琦; 赵坤; 曲燕; 温芳卿
Original assignee: BOE Technology Group Co Ltd
Current assignee: BOE Technology Group Co Ltd
Priority date: 2022-11-21
Filing date: 2022-11-21
Publication date: 2024-05-21

Abstract

The embodiment of the disclosure provides a pixel circuit, a driving method thereof, a display panel, a driving method thereof and a display device. The pixel circuit comprises a first switch module, a second switch module, a third switch module, a fourth switch module, a first storage module, a second storage module and a driving module, wherein the first storage module is configured to store the threshold voltage of the driving module, the second storage module is configured to store the data voltage of the data signal end, and the driving module is configured to provide the signal of the third node to the fourth node under the control of the first node; the driving module is further configured to provide a preset voltage to the fourth node based on the signal of the first node and the signal of the third node to cause the first storage module to store the threshold voltage. According to the technical scheme, the defects caused by threshold voltage drift can be avoided, and the image quality is improved.

Description

Pixel circuit and driving method thereof, display panel and driving method thereof, and display device

Technical Field

The disclosure relates to the technical field of display, and in particular relates to a pixel circuit, a driving method thereof, a display panel, a driving method thereof and a display device.

Background

An active matrix Organic Light-Emitting Diode (OLED) display device has received attention because of its high contrast ratio, short response time, wide viewing angle, and wide color gamut. The back-sheet of an OLED display device can generally employ three Thin Film Transistors (TFTs): hydrogenated amorphous silicon (a-Si: H) TFTs, low Temperature Polysilicon (LTPS) TFTs, and amorphous indium gallium zinc oxide (a-IGZO) TFTs. Among them, a-IGZO TFT is mainstream in terms of its advantages of high mobility, good stability, extremely low off-current, low processing temperature, and the like.

Although the uniformity of the a-IGZO TFT is relatively good, it is insufficient to meet the demand for high quality display images. Further, the characteristics of the TFT may be changed by the gate voltage bias, thereby causing image distortion. In order to achieve high image quality, threshold voltage (V _TH) compensation and mobility (μ) compensation are required for the TFT to improve image quality.

Disclosure of Invention

Embodiments of the present disclosure provide a pixel circuit and a driving method thereof, a display panel and a driving method thereof, and a display device, so as to solve or alleviate one or more technical problems in the prior art.

As a first aspect of the embodiments of the present disclosure, the embodiments of the present disclosure provide a pixel circuit including:

The first switch module is coupled with the data signal end, the first control signal end and the first node respectively and is configured to provide signals of the data signal end for the first node under the control of the first control signal end;

the second switch module is coupled with the first node, the third control signal end and the second node respectively and is configured to provide signals of the first node for the second node under the control of the third control signal end;

The third switch module is coupled with the first power supply end, the second control signal end and the third node respectively and is configured to provide signals of the first power supply end for the third node under the control of the second control signal end;

The fourth switch module is coupled with the third power supply end, the scanning signal end and the second node respectively and is configured to provide signals of the third power supply end for the second node under the control of the scanning signal end;

A first storage module coupled to the second node and the fourth node, respectively, configured to store a threshold voltage of the driving module;

The second storage module is coupled with the first node and the second node respectively and is configured to store the data voltage of the data signal end;

The driving module is respectively coupled with the first node, the third node and the fourth node and is configured to provide a signal of the third node for the fourth node under the control of the first node; the driving module is further configured to provide a preset voltage to the fourth node based on the signal of the first node and the signal of the third node to cause the first storage module to store the threshold voltage; the driving module is further configured to provide a driving signal to the fourth node to drive the light emitting module to emit light based on a voltage difference between the first node and the fourth node and a signal of the third node.

In one embodiment, in a case where the data signal terminal provides the reference voltage and the first power terminal provides the first voltage, the driving module is configured to provide the first voltage of the third node to the fourth node under control of the reference voltage of the first node, so that the first storage module stores the reference voltage.

In one embodiment, in a case that the data signal terminal provides the reference voltage and the first power terminal provides the second voltage, the driving module is further configured to provide a preset voltage to the fourth node based on the reference voltage of the first node and the second voltage of the third node so that the first memory module stores the threshold voltage.

In one embodiment, in the case that the data signal terminal provides the reference voltage and the first power terminal provides the second voltage, the driving module is further configured to provide the current signal to the fourth node for mobility compensation based on the reference voltage of the first node for a preset period of time and the second voltage of the third node.

In one embodiment, the predetermined time period is 0.05 μs to 0.15 μs.

In one embodiment, the pixel circuit includes at least one of:

The first switch module comprises a third transistor, a control end of the third transistor is coupled with the first control signal end, and a first pole and a second pole of the third transistor are respectively coupled with the data signal end and the first node;

The second switch module comprises a fourth transistor, a control end of the fourth transistor is coupled with the third control signal end, and a first pole and a second pole of the fourth transistor are respectively coupled with the first node and the second node;

The third switch module comprises a first transistor, a control end of the first transistor is coupled with a second control signal end, and a first pole and a second pole of the first transistor are respectively coupled with a first power supply end and a third node;

The fourth switch module comprises a fifth transistor, a control end of the fifth transistor is coupled with the scanning signal end, and a first pole and a second pole of the fifth transistor are respectively coupled with the second node and the third power end;

the first storage module comprises a first storage capacitor, and a first polar plate and a second polar plate of the first storage capacitor are respectively coupled with the second node and the fourth node;

the second storage module comprises a second storage capacitor, and a first polar plate and a second polar plate of the second storage capacitor are respectively coupled with the first node and the second node;

The driving module comprises a second transistor, wherein a control end of the second transistor is coupled with the first node, and a first pole and a second pole of the second transistor are respectively coupled with a third node and a fourth node.

In one embodiment, the material of the active layer of the second transistor includes amorphous indium gallium zinc oxide or low-temperature polycrystalline oxide.

In one embodiment of the present invention, in one embodiment,

The signal provided by the first power supply end is a first voltage or a second voltage, and the voltage value of the first voltage is smaller than that of the second voltage; and/or the number of the groups of groups,

The signal provided by the data signal terminal is a reference voltage or a data voltage, and the voltage value of the reference voltage is smaller than that of the data voltage.

As a second aspect of the embodiments of the present disclosure, the embodiments of the present disclosure provide a display panel including a display area, and further including a plurality of pixel circuits as in the embodiments of the present disclosure, each pixel circuit being located in the display area.

In one embodiment, the display area comprises a plurality of sub-display areas, the plurality of sub-display areas are in one-to-one correspondence with the pixel circuits, the pixel circuits are positioned in the corresponding sub-display areas, and the plurality of sub-display areas are distributed in an array manner;

The display panel further comprises a plurality of grid lines and a plurality of data lines, wherein the grid lines extend along a first direction, the grid lines are distributed along a second direction, the data lines extend along a second direction, the data lines are distributed along the first direction, scanning signal ends corresponding to pixel circuits in the same row are coupled with the same grid line, data signal ends corresponding to pixel circuits in the same column are coupled with the same data line, the first direction is a row direction, and the second direction is a column direction;

The display panel further comprises a first control signal line, a second control signal line and a third control signal line, wherein the first control signal end corresponding to each pixel circuit is coupled with the first control signal line, the second control signal end corresponding to each pixel circuit is coupled with the second control signal line, and the third control signal end corresponding to each pixel circuit is coupled with the third control signal line.

As a third aspect of the embodiments of the present disclosure, the embodiments of the present disclosure provide a driving method of a pixel circuit, which is applied to the pixel circuit in the embodiments of the present disclosure, the method including:

A reset stage, wherein reference voltages of data signal ends are provided for the first node and the second node, and first voltages of a first power supply end are provided for the third node and the fourth node so as to reset the first memory module and the second memory module;

A threshold compensation stage, wherein a reference voltage is provided for the first node and the second node, a second voltage of the first power supply terminal is provided for the third node, and a preset voltage is provided for the fourth node so that the first storage module stores the threshold voltage of the driving module;

a data writing stage, which is to provide the data voltage of the data signal end for the first node, and provide the voltage signal of the third power end for the second node, so as to write the data voltage into the second memory module;

And a light-emitting stage for providing a second voltage of the first power supply end to the third node to drive the light-emitting module to emit light.

In one embodiment, the method further comprises:

And a mobility compensation stage, wherein a reference voltage with preset duration is provided for the first node, a second voltage of the first power supply terminal is provided for the third node, a current signal is provided for the fourth node for mobility compensation, and the mobility compensation stage is positioned after the data writing stage.

As a fourth aspect of the embodiments of the present disclosure, the embodiments of the present disclosure provide a driving method of a display panel, which is applied to the display panel in the embodiments of the present disclosure, one frame time includes a non-light emitting period and a light emitting period, the non-light emitting period including:

A reset stage for providing effective level signals to the first control signal line, the second control signal line and the third control signal line, providing reference voltages to the data signal lines, and providing a first voltage to the first power supply end to reset the pixel circuits;

A threshold compensation stage, wherein effective level signals are provided for a first control signal line, a second control signal line and a third control signal line, reference voltages are provided for all data signal lines, and a second voltage is provided for a first power end, so that a first storage module in each pixel circuit stores threshold voltages of a driving module;

A data writing stage for providing corresponding data voltages to the data lines, providing effective level signals to the first control signal lines, and sequentially providing gate driving signals to the gate lines along the second direction so as to write the data voltages of the data lines into the second storage modules in the pixel circuits row by row;

And a light-emitting stage for providing a second voltage to the first power supply terminal and providing an effective level signal to the second control signal line to drive the light-emitting modules in the pixel circuits to emit light.

In one embodiment, the non-light emitting phase further comprises:

and a mobility compensation stage, wherein a reference voltage is provided for each data line, an effective level signal with preset duration is provided for the first control signal line, an effective level signal is provided for the second control signal line, and a second voltage is provided for the first power supply end, so that each pixel circuit performs mobility compensation, and the mobility compensation stage is positioned after the data writing stage.

As a fifth aspect of the embodiments of the present disclosure, the embodiments of the present disclosure provide a display device including the pixel circuit in the embodiments of the present disclosure, or including the display panel in the embodiments of the present disclosure.

According to the technical scheme, in the light-emitting stage, the voltage difference between the first node and the fourth node is the voltage after threshold voltage compensation, and when the driving module drives the light-emitting module to emit light based on the voltage difference between the first node and the fourth node and the second voltage of the third node, the defect caused by threshold voltage drift of the driving module can be avoided, the brightness of the light-emitting module is improved, and the image quality is improved.

The foregoing summary is for the purpose of the specification only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features of the present disclosure will become apparent by reference to the drawings and the following detailed description.

Drawings

In the drawings, the same reference numerals refer to the same or similar parts or elements throughout the several views unless otherwise specified. The figures are not necessarily drawn to scale. It is appreciated that these drawings depict only some embodiments according to the disclosure and are not to be considered limiting of its scope.

FIG. 1 is a schematic diagram of a pixel circuit according to an embodiment of the disclosure;

FIG. 2 is a schematic diagram of a pixel circuit according to another embodiment of the disclosure;

FIG. 3 is a timing diagram illustrating operation of a pixel circuit according to one embodiment of the disclosure;

fig. 4 is a transfer characteristic of an oxide TFT;

FIG. 5 is a flow chart illustrating a driving method of a pixel circuit according to an embodiment of the disclosure;

FIG. 6 is a schematic plan view of a display panel according to an embodiment of the disclosure;

fig. 7 is a flowchart illustrating a driving method of a display panel according to an embodiment of the disclosure.

Reference numerals illustrate:

11. A first switch module; 12. a second switch module; 13. a third light-on module; 14. a fourth switch module; 15. a first storage module; 16. a second storage module; 17. a driving module, 18, a light emitting module.

Detailed Description

Hereinafter, only certain exemplary embodiments are briefly described. As will be recognized by those of skill in the pertinent art, the described embodiments may be modified in various different ways without departing from the spirit or scope of the present disclosure. Accordingly, the drawings and description are to be regarded as illustrative in nature and not as restrictive.

The transistors used in all embodiments of the present invention may be thin film transistors or field effect transistors or other devices of the same characteristics, and the transistors used in embodiments of the present invention are mainly switching transistors according to the role in the circuit. Since the source and drain of the switching transistor used herein are symmetrical, the source and drain are interchangeable. In the embodiment of the present invention, the source (source electrode) is referred to as a first pole, the drain (drain electrode) is referred to as a second pole, or the drain may be referred to as a first pole, and the source is referred to as a second pole. In the embodiment shown in the drawings, the middle terminal of the transistor is defined as a gate (may also be called a gate electrode), the signal input terminal is defined as a source, and the signal output terminal is defined as a drain. The switching transistor adopted by the embodiment of the invention can be a P-type switching transistor or an N-type switching transistor, wherein the P-type switching transistor is turned on when the grid electrode is in a low level, and turned off when the grid electrode is in a high level; the N-type transistor is turned on when the gate is high and turned off when the gate is low. In addition, the plurality of signals in the various embodiments of the present invention each correspond to a first potential and a second potential. The first potential and the second potential only represent 2 different potential state quantities of the signal, and do not represent that the first potential or the second potential has a specific value in the whole text. In the embodiment of the present invention, the first potential is taken as an effective potential as an example.

Wherein the coupling may comprise: the two ends are in direct physical contact or are connected indirectly (such as by a signal line). The coupling manner between the two ends is not limited in the embodiment of the invention.

In the related art, the external compensation method is used to compensate the threshold voltage Vth of the TFT, which requires additional logic circuits and memory, and only extracts the compensation value after the power is turned off, so that the compensation method is not suitable for small and medium-sized display devices. The pixel circuit adopting the internal compensation mode can compensate the threshold voltage of the TFT in real time without additional circuits or memories. However, the pixel circuit in the related art compensates only the threshold voltage of the TFT, and does not consider the variation in the mobility of the TFT. In order to achieve uniformity of high gradation in a display device, mobility compensation is required for TFTs.

Fig. 1 is a schematic structural diagram of a pixel circuit according to an embodiment of the disclosure. In one embodiment, as shown in fig. 1, the pixel circuit includes a first switching module 11, a second switching module 12, a third switching module 13, a fourth switching module 14, a first storage module 15, a second storage module 16, and a driving module 17.

As shown in fig. 1, the first switch module 11 is coupled to the data signal terminal DA, the first control signal terminal S1 and the first node N1, respectively, and is configured to provide the signal of the data signal terminal DA to the first node N1 under the control of the first control signal terminal S1.

As shown in fig. 1, the second switch module 12 is coupled to the first node N1, the third control signal terminal S3, and the second node N2, respectively, and is configured to provide the signal of the first node N1 to the second node N2 under the control of the third control signal terminal S3.

As shown in fig. 1, the third switch module 13 is coupled to the first power terminal VDD, the second control signal terminal S2 and the third node N3, respectively, and is configured to provide the signal of the first power terminal VDD to the third node N3 under the control of the second control signal terminal S2.

As shown in fig. 1, the fourth switch module 14 is coupled to the third power supply terminal GND, the SCAN signal terminal SCAN and the second node N2, respectively, and is configured to provide the signal of the third power supply terminal GND to the second node N2 under the control of the SCAN signal terminal SCAN.

As shown in fig. 1, the first memory module 15 is coupled to the second node N2 and the fourth node N3, respectively, and is configured to store a threshold voltage V _TH of the driving module 17.

As shown in fig. 1, the second storage module 16 is coupled to the first node N1 and the second node N2, respectively, and is configured to store the data voltage V _DATA of the data signal terminal DA.

As shown in fig. 1, the driving module 17 is coupled to the first node N1, the third node N3 and the fourth node N3, respectively, and the driving module 17 is configured to provide the signal of the third node N3 to the fourth node N3 under the control of the first node N1; the driving module 17 is further configured to provide a preset voltage to the fourth node N3 based on the signal of the first node N1 and the signal of the third node N3 to cause the first storage module 15 to store the threshold voltage V _TH; the driving module 17 is further configured to provide a driving signal to the fourth node N3 to drive the light emitting module 18 to emit light based on the signal of the first node N1 and the signal of the third node N3.

In one embodiment, as shown in fig. 1, the pixel circuit may further include a light emitting module 18, where one end of the light emitting module 18 is coupled to the fourth node N3, and the other end is coupled to the second power source terminal VSS. For example, the light emitting module 18 may include an anode and a cathode, the anode of the light emitting module 18 being coupled to the fourth node N3, and the cathode of the light emitting module 18 being coupled to the second power source terminal VSS.

Illustratively, the light emitting module 18 includes at least one light emitting device DL, which in an embodiment of the present application may be an OLED or a QLED (quantum dot light emitting diode), but the present application is not limited thereto. In other embodiments, the light emitting device DL may be other light emitting devices whose display brightness is affected by both current and time, such as Micro LEDs or Mini LEDs. The light emitting module 18 may include a plurality of light emitting devices connected in series or a plurality of light emitting devices connected in parallel or a plurality of light emitting devices combined in series and parallel.

In the pixel circuit of the embodiment of the disclosure, the first switch module 11 provides the reference voltage V _REF of the data signal end DA to the first node N1 under the control of the first control signal end S1, the second switch module 12 provides the reference voltage V _REF of the first node N1 to the second node N2 under the control of the third control signal end S3, and the driving module 17 provides the preset voltage to the fourth node N3 based on the signal of the first node N1 and the signal of the third node N3, so that the first storage module 15 stores the threshold voltage V _TH of the driving module 17; the first switch module 11 provides the data voltage V _DATA of the data signal terminal DA to the first node N1 under the control of the first control signal terminal S1, and the fourth switch module 14 provides the signal of the third power terminal GND to the second node N2 under the control of the SCAN signal terminal SCAN, so that the second storage module 16 stores the data voltage V _DATA of the data signal terminal DA. Therefore, in the light emitting stage, the voltage difference between the first node N1 and the fourth node N3 is the voltage compensated by the threshold voltage V _TH, and when the driving module 17 drives the light emitting module 18 to emit light based on the voltage difference between the first node N1 and the fourth node N3 and the second voltage V2 of the third node N3, the defect caused by the drift of the threshold voltage V _TH of the driving module 17 can be avoided, the brightness of the light emitting module 18 is improved, and the image quality is improved.

In one embodiment, the signal provided by the first power supply terminal VDD is a first voltage V1 or a second voltage V2, and the voltage value of the first voltage V1 is smaller than the voltage value of the second voltage V2. For example, the first voltage V1 is about 0V. The second voltage V2 is 8VDC to 12VDC, for example, the second voltage V2 may be 10VDC.

In one embodiment, the signal provided by the data signal terminal DA is a reference voltage V _REF or a data voltage V _DATA, and the voltage value of the reference voltage V _REF is smaller than the voltage value of the data voltage V _DATA. For example, the voltage value of the reference voltage V _REF may be greater than the voltage value of the first voltage V1. The reference voltage V _REF may be 0.8VDC to 1.2VDC, for example, the reference voltage V _REF may be 1VDC. The data voltage V _DATA may be, for example, 2VDC to 7VDC.

In one embodiment, in the case that the data signal terminal DA provides the reference voltage V _REF and the first power terminal VDD provides the first voltage V1, the driving module 17 is configured to provide the first voltage V1 of the third node N3 to the fourth node N3 under the control of the reference voltage V _REF of the first node N1, so that the first storage module 15 stores the reference voltage V _REF.

Illustratively, during the reset phase, the data signal terminal DA provides the reference voltage V _REF and the first power terminal VDD provides the first voltage V1. The first switch module 11 provides the reference voltage V _REF of the data signal terminal DA to the first node N1 under the control of the first control signal line; the second switching module 12 supplies the reference voltage V _REF of the first node N1 to the second node N2 under the control of the third control signal line. The first and second plates of the second memory module 16 have the same potential, and the voltage stored by the second memory module 16 is initialized to 0. The third switch module 13 provides the first voltage V1 of the first power supply terminal VDD to the third node N3 under the control of the second control signal line; the driving module 17 provides the first voltage V1 of the third node N3 to the fourth node N3 under the control of the reference voltage V _REF of the first node N1, so that the potential of the first plate of the first memory module 15 is the reference voltage V _REF and the potential of the second plate is the first voltage V1. In the case where the first voltage V1 is 0, the voltage stored in the first memory module 15 is initialized to the reference voltage V _REF.

In the reset stage, the first storage module 15 and the second storage module 16 are initialized, so that the data of the last frame remained in the first storage module 15 and the second storage module 16 can be eliminated, and the influence of the data of the last frame remained in the first storage module 15 and the second storage module 16 on the picture of the frame can be avoided.

In one embodiment, in the case that the data signal terminal DA provides the reference voltage V _REF and the first power terminal VDD provides the second voltage V2, the driving module 17 is further configured to provide the preset voltage to the fourth node N3 to cause the first storage module 15 to store the threshold voltage V _TH based on the reference voltage V _REF of the first node N1 and the second voltage V2 of the third node N3.

Illustratively, during the threshold compensation phase, the data signal terminal DA provides the reference voltage V _REF and the first power supply terminal VDD provides the second voltage V2. The first switch module 11 provides the reference voltage V _REF of the data signal terminal DA to the first node N1 under the control of the first control signal line; the second switching module 12 supplies the reference voltage V _REF of the first node N1 to the second node N2 under the control of the third control signal line. The first and second plates of the second memory module 16 have the same potential, and the voltage stored by the second memory module 16 is still 0. The third switch module 13 provides the second voltage V2 of the first power supply terminal VDD to the third node N3 under the control of the second control signal line; the driving module 17 supplies a current signal to the fourth node N3 based on the reference voltage V _REF of the first node N1 and the second voltage V2 of the third node N3 until the voltage of the fourth node N3 becomes a preset voltage, so that the driving module 17 is turned off. Therefore, in the threshold compensation phase, the first memory module 15 is written into the threshold voltage V _TH of the driving module 17, that is, the voltage stored in the first memory module 15 is the threshold voltage V _TH of the driving module 17, so as to implement the compensation of the threshold voltage V _TH.

In one embodiment, in the case that the data signal terminal DA provides the reference voltage V _REF and the first power terminal VDD provides the second voltage V2, the driving module 17 is further configured to provide a current to the fourth node N3 for mobility compensation based on the reference voltage V _REF of the first node N1 for a preset period of time and the second voltage V2 of the third node N3.

In the mobility compensation phase, the data signal terminal DA provides the reference voltage V _REF, the first power supply terminal VDD provides the second voltage V2, and the first control signal terminal S1 provides the active level signal with a preset duration, so that the first switch module 11 provides the reference voltage V _REF with the preset duration to the first node N1 under the control of the first control signal terminal S1. The third switch module 13 provides the second voltage V2 of the first power supply terminal VDD to the third node N3 under the control of the second control signal terminal S2. The driving module 17 provides a current signal to the fourth node N3 based on the reference voltage V _REF of the preset duration of the first node N1 and the second voltage V2 of the third node N3. The current signal can perform current compensation on the second transistor T2, so that the uniformity of the middle-low gray level image is improved, and the image quality is further improved.

It should be noted that, for the pixel circuit including the oxide transistor in the driving module 17, the mobility of the oxide transistor generally changes in the image with middle or low gray scale, for example, 32 gray scales to 50 gray scales, so in one embodiment, the mobility compensation stage may be applied to the gray scales of the light emitting module 18 from 32 gray scales to 50 gray scales, and for other gray scales, there may be no mobility compensation stage in one frame time.

In one embodiment, the predetermined time period may be 0.05 μs to 0.15 μs. Experiments prove that the defects caused by the mobility change of the driving module 17 can be compensated by adopting the time length, and the operation of the pixel circuit is not influenced. The preset time period may be set to one of, for example, 0.05 μs, 0.08 μs, 0.1 μs, 0.12 μs, 0.15 μs, as an example.

Fig. 2 is a schematic structural diagram of a pixel circuit according to another embodiment of the disclosure. In one embodiment, as shown in fig. 2, the first switch module 11 includes a third transistor T3, a control terminal of the third transistor T3 is coupled to the first control signal terminal S1, and a first pole and a second pole of the third transistor T3 are coupled to the data signal terminal DA and the first node N1, respectively.

In one embodiment, as shown in fig. 2, the second switch module 12 includes a fourth transistor T4, a control terminal of the fourth transistor T4 is coupled to the third control signal terminal S3, and a first pole and a second pole of the fourth transistor T4 are coupled to the first node N1 and the second node N2, respectively.

In one embodiment, as shown in fig. 2, the third switch module 13 includes a first transistor T1, a control terminal of the first transistor T1 is coupled to the second control signal terminal S2, and a first pole and a second pole of the first transistor T1 are respectively coupled to the first power supply terminal VDD and the third node N3.

In one embodiment, as shown in fig. 2, the fourth switch module 14 includes a fifth transistor T5, a control terminal of the fifth transistor T5 is coupled to the SCAN signal terminal SCAN, and a first pole and a second pole of the fifth transistor T5 are respectively coupled to the second node N2 and the third power terminal GND.

In one embodiment, as shown in fig. 2, the first memory module 15 includes a first memory capacitor C _ST, and a first plate and a second plate of the first memory capacitor C _ST are coupled to the second node N2 and the fourth node N3, respectively.

In one embodiment, as shown in fig. 2, the second memory module 16 includes a second memory capacitor C _DATA, and a first plate and a second plate of the second memory capacitor C _DATA are coupled to the first node N1 and the second node N2, respectively.

In one embodiment, as shown in fig. 2, the driving module 17 includes a second transistor T2, and the second transistor T2 is a driving transistor of the pixel circuit. The control terminal of the second transistor T2 is coupled to the first node N1, and the first and second poles of the second transistor T2 are coupled to the third and fourth nodes N3 and N3, respectively.

In fig. 2, an exemplary structure of the first switch module 11, the second switch module 12, the third switch module 13, the fourth switch module 14, the first memory module 15, the second memory module 16, and the driving module 17 is shown. It will be appreciated by those skilled in the art that the first switch module 11, the second switch module 12, the third switch module 13, the fourth switch module 14, the first storage module 15, the second storage module 16, and the driving module 17 are not limited to the structure shown in fig. 2 as long as the functions thereof can be realized.

In one embodiment, the types of the first transistor T1, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 may be the same, or the types of the first transistor T1, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 may be different. Illustratively, the first, third, fourth, and fifth transistors T1, T3, T4, and T5 may be NMOS, or the first, third, fourth, and fifth transistors T1, T3, T4, and T5 may be PMOS. The same type of transistor is adopted in the pixel circuit, so that the process flow can be simplified, the process difficulty is reduced, and the product yield is improved.

In the pixel circuit of the embodiment of the disclosure, the types of the transistors are not limited, so long as the functions of the modules can be realized under the corresponding control signals.

In one embodiment, the material of the active layer of the second transistor T2 may include amorphous indium gallium zinc oxide (a-IGZO) or low temperature poly-oxide (Low Temperature Polycrystalline Oxide, LTPO). Such a second transistor T2 has high mobility and good stability, and can further improve image quality.

Fig. 3 is a timing diagram illustrating operation of a pixel circuit according to an embodiment of the disclosure. The pixel circuit shown in fig. 2 may employ the operation timing shown in fig. 3. The operation timing diagram shown in fig. 3 may include a non-light-emitting phase and a light-emitting phase, where the non-light-emitting phase may include a reset phase t1, a threshold compensation phase t2, a data writing phase t3, a mobility compensation phase t4, and the light-emitting phase is t5. The operation of the pixel circuit according to the embodiment of the present disclosure is described in detail below with reference to fig. 2 and 3.

In the reset stage t1, the first control signal end S1, the second control signal end S2 and the third control signal end S3 all provide effective level signals, and the SCAN signal end SCAN provides ineffective level signals; the first power terminal VDD provides a first voltage V1, and the data signal terminal DA provides a reference voltage V _REF. The first transistor T1, the third transistor T3, and the fourth transistor T4 are all on, and the fifth transistor T5 is off. It should be noted that, although the first control signal terminal S1, the second control signal terminal S2, and the third control signal terminal S3 all provide the effective level signal, the effective level signals provided by the first control signal terminal S1, the second control signal terminal S2, and the third control signal terminal S3 are not the same, and the specific values of the effective level signals may be determined according to the corresponding transistors.

Illustratively, the third transistor T3 is turned on under the control of the active level signal of the first control signal terminal S1, and provides the reference voltage V _REF of the data signal terminal DA to the first node N1. The fourth transistor T4 is turned on under the control of the active level signal of the third control signal terminal S3, and provides the reference voltage V _REF of the first node N1 to the second node N2. The first transistor T1 is turned on under the control of the active level signal of the second control signal terminal S2, and provides the first voltage V1 of the first power supply terminal VDD to the third node N3. The second transistor T2 functions as a switching transistor in the reset stage, and the second transistor T2 is turned on under the control of the reference voltage V _REF of the first node N1, providing the first voltage V1 of the third node N3 to the fourth node N3. The first and second plates of the second storage capacitor C _DATA have equal potential, and the voltage stored in the second storage capacitor C _DATA is initialized to 0. The first plate of the first storage capacitor C _ST is the reference voltage V _REF, the second plate is the first voltage V1, and when the first voltage V1 is 0, the voltage stored in the first storage capacitor C _ST is initialized to the reference voltage V _REF.

In the threshold compensation stage t2, the first control signal end S1, the second control signal end S2 and the third control signal end S3 all provide effective level signals, and the SCAN signal end SCAN provides ineffective level signals; the first power terminal VDD provides the second voltage V2, and the data signal terminal DA provides the reference voltage V _REF. The first transistor T1, the third transistor T3, and the fourth transistor T4 are all on, and the fifth transistor T5 is off.

The third transistor T3 is turned on under the control of the active level signal of the first control signal terminal S1, and provides the reference voltage V _REF of the data signal terminal DA to the first node N1. The fourth transistor T4 is turned on under the control of the active level signal of the third control signal terminal S3, so that the second node N2 and the first node N1 are turned on. The first transistor T1 is turned on under the control of the active level signal of the second control signal terminal S2, and provides the second voltage V2 of the first power supply terminal VDD to the third node N3. The second transistor T2 generates a current I _D1 based on the reference voltage V _REF of the first node N1 (gate G) and the second voltage V2 of the third node N3, and the current I _D1 flows from the first pole (drain D) of the second transistor T2 to the second pole (source S) of the second transistor T2, charging the fourth node N3 until the voltage of the fourth node N3 becomes V _REF-V_TH. At this time, the voltage of the gate G of the second transistor T2 is V _REF, the voltage of the source S of the second transistor T2 is V _REF-V_TH, the voltage of V _GS of the second transistor T2 is the threshold voltage V _TH, and the second transistor T2 is turned off. The voltage of the first polar plate of the first storage capacitor C _ST is V _REF, the voltage of the second polar plate of the first storage capacitor C _ST is V _REF-V_TH, the voltage stored in the first storage capacitor C _ST is V _TH, that is, the voltage stored in the first storage capacitor C _ST is the threshold voltage V _TH of the second transistor T2, so as to implement the compensation of the threshold voltage V _TH.

In the compensation phase of the threshold voltage V _TH, a source follower method is adopted, and in the process of writing the threshold voltage V _TH into the first storage capacitor C _ST, the potential of the gate G of the second transistor T2 is fixed, and the potential of the source S is changed by passing a current between the drain D and the source S, so that the voltage between the gate G and the source S automatically approaches the threshold voltage V _TH, thereby storing the threshold voltage V _TH in the first storage capacitor C _ST. The source follower has an advantage in that even when the voltage between the gate G and the source S is 0, the threshold voltage V _TH of the recess transistor in which a current flows can be detected, and thus, writing of the threshold voltage V _TH of the second transistor T2 into the first storage capacitor C _ST can be ensured.

In the data writing stage t3, the first control signal terminal S1 provides an active level signal, the second control signal terminal S2 and the third control signal terminal S3 provide an inactive level signal, and the SCAN signal terminal SCAN provides an active level signal. The fourth transistor T4, the first transistor T1 and the second transistor T2 are all turned off. The data signal terminal DA supplies the data voltage V _DATA of the current frame.

The third transistor T3 is turned on under the control of the active level signal of the first control signal terminal S1, and provides the data voltage V _DATA of the data signal terminal DA to the first node N1; the fifth transistor T5 is turned on under the control of the active level signal of the SCAN signal terminal SCAN, and provides the voltage of the third power supply terminal GND to the second node N2, charges the second storage capacitor C _DATA, writes the data voltage V _DATA into the second storage capacitor C _DATA, and the voltage stored in the second storage capacitor C _DATA is the data voltage V _DATA. In the data writing stage, since the second transistor T2 is turned off, the storage voltage of the first storage capacitor C _ST is conserved, and thus the voltage stored in the first storage capacitor C _ST is still V _TH. After the data voltage V _DATA is written into the second storage capacitor C _DATA, the first control signal terminal S1 provides an inactive level signal, and the SCAN signal terminal SCAN provides an inactive level signal, so that the third transistor T3 is turned off and the fifth transistor T5 is turned off.

After the data writing phase, the voltage stored in the first storage capacitor C _ST is V _TH, and the voltage stored in the second storage capacitor C _DATA is V _DATA. If the voltage at the second node N2 is V _N2, the voltage at the first node N1 (i.e., the gate G of the second transistor T2) is V _N2+V_DATA, the voltage at the fourth node N3 (i.e., the source S of the second transistor T2) is V _N2-V_TH, and V _GS of the second transistor T2 is (V _N2+V_DATA)-(V_N2-V_TH), i.e., V _GS＝V_DATA+V_TH.

In the mobility compensation stage t4, the third control signal terminal S3 and the SCAN signal terminal SCAN provide an inactive level signal, the second control signal terminal S2 provides an active level signal, and the first control signal terminal S1 provides an active level signal with a preset duration. The data signal terminal DA provides the reference voltage V _REF, and the first power terminal VDD provides the second voltage V2. The fourth transistor T4 and the fifth transistor T5 are both turned off.

The first transistor T1 is turned on under the control of the active level signal of the second control signal terminal S2, and provides the second voltage V2 of the first power supply terminal VDD to the third node N3. The third transistor T3 supplies the reference voltage V _REF for a preset duration to the first node N1 under the control of an active level signal for a preset duration. The preset duration may be, for example, 0.1 mus. The second transistor T2 is instantaneously turned on for mobility compensation based on the reference voltage V _REF of 0.1 mus of the gate G and the second voltage V2 of the third node N3. The principle of mobility compensation is such that V _GS loses higher voltage when mobility is high and lower voltage when mobility is low.

Fig. 4 is a transfer characteristic of an oxide TFT. As can be seen from the transfer characteristic of the oxide TFT, the higher the mobility, the higher the corresponding on-current I _D; the higher the V _GS, the higher the I _D and the higher the mobility. V _TH of the oxide TFT is prone to negative bias, so that the transfer characteristic of the TFT shifts left. When V _TH is negatively biased, the same turn-on current corresponding to V _GS will be higher. That is, if V _TH is negatively biased, then the corresponding current I _D' for V _GS is greater than the current I _D for V _TH when not negatively biased. In fig. 2, the second transistor T2 is turned on in a light emitting period due to the negative bias of the second transistor T2, so that the actual current value flowing through the light emitting module 18 in the light emitting period is larger than the designed current value.

Before the light emitting stage, the second transistor T2 is turned on in advance, and the corresponding capacitor leaks. Referring to fig. 2 and 3, illustratively, during the mobility compensation phase, the reference voltage V _REF is about 1VDC and the second voltage V2 is about 10VDC, such that the second transistor T2 is turned on instantaneously, with a current I _D flowing through the source S of the second transistor T2. When the first control signal terminal S1 is changed from the active level signal to the inactive level signal, the third transistor T3 is turned off, and at this time, the corresponding first storage capacitor C _ST and the second storage capacitor C _DATA have a discharging process, the greater the current I _D flowing through the second transistor T2, the easier the discharging process, the more the value of V _GS decreases from V _DATA+V_TH, and the variable value of V _GS may be set to Δv _m. V _TH of the oxide TFT is prone to negative bias, resulting in corresponding capacitance leakage. According to the ampere-second balance distance of the capacitor, through the instant on of the second transistor T2, the capacitor can release more charges under the same condition, so that the value of I _D is ensured to maintain a higher level. Since the mobility value of the second transistor T2 varies according to the gate G electric field, mobility compensation is effective after the second storage capacitor C _DATA stores the data voltage V _DATA. That is, the mobility compensation stage is provided after the data writing stage, and mobility compensation can be effectively performed.

The initial voltage of V _GS before mobility compensation is V _DATA+V_TH, and the voltage after mobility compensation is V _DATA+V_TH-ΔV_m after V _GS compensation. Where DeltaV _m is proportional to mobility, the higher the mobility, the greater DeltaV _m, i.e. the more V _GS drops, the lower the mobility, the smaller DeltaV _m, i.e. the less V _GS drops. Thus, in the mobility compensation phase, the more charges are discharged from the first storage capacitor C _ST and the second storage capacitor C _DATA, the larger the voltage drop of V _GS.

In the light emitting stage t5, the first power supply terminal VDD provides the second level, the SCAN signal terminal SCAN provides the inactive level signal, the first control signal terminal S1 and the third control signal terminal S3 provide the inactive level signal, and the second control signal terminal S2 provides the active level signal. The third transistor T3, the fourth transistor T4, and the fifth transistor T5 are all off, and the first transistor T1 is on.

The first transistor T1 is turned on under the control of the active level signal of the second control signal terminal S2, and provides the second voltage V2 of the first power supply terminal VDD to the third node N3. The second transistor T2 is turned on based on the voltage difference V _GS between the first node N1 and the fourth node N3 and the second voltage V2 of the third node N3, and provides a driving current signal to the fourth node N3 to drive the light emitting module 18 to emit light.

In the light emitting stage, the voltage of the source S of the second transistor T2 is V _SS+V_DL, where V _SS is the voltage of the second power source terminal VSS, V _DL is the voltage between the cathode and the anode of the light emitting device DL, then the voltage of the source G of the second transistor T2 is V _DATA+V_TH-ΔV_m+V_SS+V_DL, then V _GS is V _DATA+V_TH-ΔV_m, and the current flowing through the light emitting device DL is:

Where DeltaV _m is proportional to mobility, I _DL is the current flowing through the light emitting module 18DL,

For the transconductance parameters of the driving transistor (in the embodiment of the present disclosure, the second transistor T2), C _ox, μ, W, L are the channel capacitance per unit area, channel mobility, channel width, and channel length of the driving transistor, respectively. /(I)

Wherein C _ox, μ, W, L are the channel capacitance per unit area, channel mobility, channel width, and channel length of the drive transistor, respectively.

Equation (2) is a current value flowing through the light emitting device DL after being compensated by the threshold voltage V _TH in the related art. As can be seen from equation (2), I _DL is a current value that is not mobility compensated.

In the embodiment of the disclosure, the current I _DL flowing through the light-emitting device DL can be calculated by using the formula (1), the Δv _m in the formula (1) is in a proportional relationship with the mobility, and the formula (1) compensates the mobility; and formula (1) is independent of the threshold voltage V _TH, that is, formula (1) compensates the threshold voltage V _TH for the threshold voltage V _TH so that the current flowing through the light emitting device DL is not affected by the threshold voltage V _TH.

According to the embodiment of the disclosure, partial electric quantity is released by the capacitor corresponding to the driving transistor in the mobility compensation stage, so that V _GS is changed from V _DATA+V_TH before compensation to V _DATA+V_TH-ΔV_m after compensation, and therefore, in the light-emitting stage, the problem of high current caused by negative bias of the driving transistor can be solved by V _GS after compensation, and the current flowing through the light-emitting device DL in the light-emitting stage is more in accordance with the design requirement.

In the pixel circuit using the oxide TFT for the driving transistor, the mobility of the driving transistor is changed to affect the uniformity of the screen of the middle or low gray scale, for example, 32 to 50 gray scales.

In one embodiment, the mobility compensation stage may be used in one frame time for middle-low gray scale, e.g., 32 gray scale to 50 gray scale pictures, and may not be used for other gray scale pictures.

The pixel circuit of the embodiment of the disclosure can carry out internal real-time compensation on the threshold voltage V _TH and the mobility, can use display devices with various sizes, has simple structure and reduces the compensation cost. The pixel circuit can be applied to a driving transistor of amorphous indium gallium zinc oxide and a driving transistor of low-temperature polycrystalline oxide. By adopting the pixel circuit disclosed by the embodiment of the invention, the image quality effect can be improved.

Fig. 5 is a flow chart illustrating a driving method of a pixel circuit according to an embodiment of the disclosure. The embodiment of the disclosure also provides a driving method of the pixel circuit, which is applied to the pixel circuit in the embodiment of the disclosure. As shown in fig. 5, the driving method of the pixel circuit may include a reset phase, a threshold compensation phase, a data writing phase, and a light emitting phase.

And a reset stage for providing the reference voltage V _REF of the data signal terminal DA to the first node N1 and the second node N2, and providing the first voltage V1 of the first power terminal VDD to the third node N3 and the fourth node N3 to reset the first memory module 15 and the second memory module 16.

In the threshold compensation stage, the reference voltage V _REF is provided to the first node N1 and the second node N2, the second voltage V2 of the first power supply terminal VDD is provided to the third node N3, and the preset voltage is provided to the fourth node N3 so that the first memory module 15 stores the threshold voltage V _TH of the driving module 17.

In the data writing stage, the data voltage V _DATA of the data signal terminal DA is provided to the first node N1, and the voltage signal of the third power terminal GND is provided to the second node N2 to write the data voltage V _DATA into the second memory module 16.

In the light emitting stage, the second voltage V2 of the first power terminal VDD is supplied to the third node N3 to drive the light emitting module 18 to emit light.

In one embodiment, the driving method of the pixel circuit may further include a mobility compensation stage. In the mobility compensation phase, a reference voltage V _REF with a preset duration is provided to the first node N1, a second voltage V2 of the first power supply terminal VDD is provided to the third node N3, so as to provide a current signal to the fourth node N3 for mobility compensation, and the mobility compensation phase is located after the data writing phase.

The detailed process of the driving method of the pixel circuit may refer to the description of the working process of the pixel circuit hereinabove, and will not be repeated here.

Fig. 6 is a schematic plan view of a display panel according to an embodiment of the disclosure. The disclosed embodiments also provide a display panel, as shown in fig. 6, which may include a display area and a non-display area. The display panel further includes a plurality of pixel circuits in embodiments of the present disclosure, each pixel circuit being located in the display area.

In one embodiment, as shown in fig. 6, the display area includes a plurality of sub-display areas, where the plurality of sub-display areas are in one-to-one correspondence with the pixel circuits, the pixel circuits are located in the corresponding sub-display areas, and the plurality of sub-display areas are distributed in an array. Fig. 6 shows a boundary 21 of the display panel and a boundary 22 of the display area, the area within the boundary 22 being the display area, and the area between the boundary 21 and the boundary 22 being the non-display area.

As shown in fig. 6, the display panel further includes a plurality of gate lines GL extending in the first direction X and a plurality of data lines DL arranged in the second direction Y. The data lines DL extend in the second direction Y, and the plurality of data lines DL are arranged in the first direction X. The SCAN signal terminals SCAN corresponding to the pixel circuits in the same row are coupled to the same gate line GL, and the data signal terminals DA corresponding to the pixel circuits in the same column are coupled to the same data line DL. The first direction X is the row direction and the second direction Y is the column direction.

The display panel further comprises a first control signal line, a second control signal line and a third control signal line, wherein the first control signal end S1 corresponding to each pixel circuit is coupled with the first control signal line, the second control signal end S2 corresponding to each pixel circuit is coupled with the second control signal line, and the third control signal end S3 corresponding to each pixel circuit is coupled with the third control signal line.

Illustratively, the display panel may include m rows and n columns of sub-display areas, and correspondingly, the display panel includes m rows and n columns of pixel circuits. The display panel comprises m gate lines GL and n data lines DL, wherein the gate lines GL corresponding to the ith row of pixel circuits are GLi, and the gate lines GLi are coupled with scanning signal ends SCAN of all the pixel circuits in the ith row of pixel circuits. The data line DL corresponding to the pixel circuit in the j-th row is DLj, and the data line DLj is coupled to the data signal terminal DA of each pixel circuit in the j-th row. Wherein m, n, i, j are natural numbers, i is more than or equal to 1 and less than or equal to m, and j is more than or equal to 1 and less than or equal to n.

Note that, fig. 6 schematically illustrates the wiring patterns of the first control signal line, the second control signal line, and the third control signal line, and it is understood that the first control signal line, the second control signal line, and the third control signal line are not limited to the wiring patterns illustrated in fig. 6. In the implementation process, the wiring modes of the first control signal line, the second control signal line and the third control signal line can be set according to the needs, so long as the coupling relation between each control signal end and each control signal line in the pixel circuit is ensured.

Fig. 7 is a flowchart illustrating a driving method of a display panel according to an embodiment of the disclosure. In one implementation, the driving method of the display panel is applied to the display panel in the embodiment of the present disclosure, and one frame time may include a non-light emitting period T1 and a light emitting period T2, referring to fig. 3. The non-light emitting period may include a reset period t1, a threshold compensation period t2, a data writing period t3, and a light emitting period t5.

In the reset stage t1, active level signals are supplied to the first control signal line, the second control signal line and the third control signal line, a reference voltage V _REF is supplied to each data signal line, and a first voltage V1 is supplied to the first power supply terminal VDD, so that each pixel circuit is reset. Regarding the reset procedure of the pixel circuit, reference may be made to the description of the reset phase procedure of the pixel circuit hereinabove.

In the threshold compensation stage t2, active level signals are provided to the first control signal line, the second control signal line and the third control signal line, a reference voltage V _REF is provided to each data signal line, and a second voltage V2 is provided to the first power supply terminal VDD, so that the first memory module 15 in each pixel circuit stores the threshold voltage V _TH of the driving module 17. For the description of the threshold compensation phase of the pixel circuit, reference may be made to the description of the threshold compensation phase procedure of the pixel circuit hereinabove.

In the data writing stage t3, the corresponding data voltages V _DATA are supplied to the data lines, the active level signal is supplied to the first control signal line, and the gate driving signal is sequentially supplied to the gate lines along the second direction, so that the data voltages V _DATA of the data lines are written into the second memory module 16 in the pixel circuit row by row. As for the description of the data writing stage of the pixel circuit, reference may be made to the description of the data writing stage procedure of the pixel circuit hereinabove.

In the light emitting stage t5, the second voltage V2 is supplied to the first power terminal VDD, and the active level signal is supplied to the second control signal line to drive the light emitting module 18 in each pixel circuit to emit light. Regarding the description of the light emission stage of the pixel circuit, reference may be made to the description of the light emission stage process of the pixel circuit hereinabove.

In one embodiment, referring to fig. 3, the non-light emitting phase further includes a mobility compensation phase t4.

In the mobility compensation stage t4, a reference voltage V _REF is provided to each data line, an active level signal with a preset duration is provided to the first control signal line, an active level signal is provided to the second control signal line, and a second voltage V2 is provided to the first power supply terminal VDD, so that each pixel circuit performs mobility compensation, and the mobility compensation stage is located after the data writing stage. For the description of the mobility compensation phase of the pixel circuit, reference may be made to the description of the mobility compensation phase procedure of the pixel circuit hereinabove.

As can be seen from the driving method of the display panel, the reset phase, the threshold compensation phase, the mobility compensation phase and the light emitting phase of each pixel circuit in the display panel are performed simultaneously, and the data writing phase is performed row by row within one frame time.

Illustratively, the non-light emitting phase may further include a stop write data phase t6, the stop write data phase t6 being located between the data write phase t3 and the mobility compensation phase t4. In the data writing stop stage t6, after the pixel circuits of all rows are written with the data voltages V _DATA, the first control signal line, the second control signal line, the third control signal line, and each gate line are supplied with the inactive level signals of the second period, and each data line is supplied with the reference voltage V _REF of the second period. After the end of the second period of time, the mobility compensation phase t4 is entered.

The embodiment of the disclosure also provides a display device, which comprises the pixel circuit in the embodiment of the disclosure or comprises the display panel in the embodiment of the disclosure.

The display device may be an OLED display device, an LED display device, a QLED display device, or the like. The display device may be: any product or component with display function such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.

In the description of the present specification, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element being referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present disclosure.

Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present disclosure, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.

In the present disclosure, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed; the device can be mechanically connected, electrically connected and communicated; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the terms in this disclosure will be understood by those of ordinary skill in the art as the case may be.

In this disclosure, unless expressly stated or limited otherwise, a first feature being "above" or "below" a second feature may include both the first and second features being in direct contact, as well as the first and second features not being in direct contact but being in contact with each other by way of additional features therebetween. Moreover, a first feature being "above," "over" and "on" a second feature includes the first feature being directly above and obliquely above the second feature, or simply indicating that the first feature is higher in level than the second feature. The first feature being "under", "below" and "beneath" the second feature includes the first feature being directly above and obliquely above the second feature, or simply indicating that the first feature is less level than the second feature.

The above disclosure provides many different embodiments or examples for implementing different structures of the disclosure. The components and arrangements of specific examples are described above in order to simplify the present disclosure. Of course, they are merely examples and are not intended to limit the present disclosure. Furthermore, the present disclosure may repeat reference numerals and/or letters in the various examples, which are for the purpose of brevity and clarity, and which do not themselves indicate the relationship between the various embodiments and/or arrangements discussed.

The above is merely a specific embodiment of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think of various changes or substitutions within the technical scope of the disclosure, which should be covered in the protection scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A pixel circuit, comprising:

A second switch module coupled to the first node, the third control signal terminal and the second node, respectively, and configured to provide a signal of the first node to the second node under the control of the third control signal terminal;

a fourth switch module coupled to a third power supply terminal, a scan signal terminal, and a second node, respectively, and configured to provide a signal of the third power supply terminal to the second node under control of the scan signal terminal;

A second storage module coupled to the first node and the second node, respectively, and configured to store a data voltage of the data signal terminal;

The driving module is coupled with the first node, the third node and the fourth node respectively, and is configured to provide signals of the third node to the fourth node under the control of the first node; the driving module is further configured to provide a preset voltage to the fourth node based on the signal of the first node and the signal of the third node to cause the first storage module to store the threshold voltage; the driving module is further configured to provide a driving signal to the fourth node to drive the light emitting module to emit light based on a voltage difference between the first node and the fourth node and a signal of the third node.

2. The pixel circuit of claim 1, wherein, in the case where the data signal terminal provides a reference voltage and the first power terminal provides a first voltage, the driving module is configured to provide the first voltage of the third node to the fourth node under control of the reference voltage of the first node, so that the first storage module stores the reference voltage.

3. The pixel circuit of claim 1, wherein, in the case where the data signal terminal provides a reference voltage and the first power terminal provides a second voltage, the driving module is further configured to provide a preset voltage to the fourth node based on the reference voltage of the first node and the second voltage of the third node to cause the first storage module to store the threshold voltage.

4. A pixel circuit according to any one of claims 1-3, wherein in case the data signal terminal provides a reference voltage and the first power terminal provides a second voltage, the driving module is further configured to provide a current signal to the fourth node for mobility compensation based on the reference voltage of the first node for a preset duration and the second voltage of the third node.

5. The pixel circuit according to claim 4, wherein the predetermined period is 0.05 μs to 0.15 μs.

6. The pixel circuit of claim 1, comprising at least one of:

The third switch module comprises a first transistor, a control end of the first transistor is coupled with the second control signal end, and a first pole and a second pole of the first transistor are respectively coupled with the first power end and the third node;

the driving module comprises a second transistor, a control end of the second transistor is coupled with the first node, and a first pole and a second pole of the second transistor are respectively coupled with the third node and the fourth node.

7. The pixel circuit according to claim 6, wherein the material of the active layer of the second transistor comprises amorphous indium gallium zinc oxide or low temperature poly-oxide.

8. The pixel circuit according to claim 1, wherein,

9. A display panel comprising a display area and further comprising a plurality of pixel circuits according to any one of claims 1-8, each of the pixel circuits being located in the display area.

10. The display panel according to claim 9, wherein the display area includes a plurality of sub display areas, the plurality of sub display areas are in one-to-one correspondence with the pixel circuits, the pixel circuits are located in the corresponding sub display areas, and the plurality of sub display areas are distributed in an array;

The display panel further comprises a plurality of grid lines and a plurality of data lines, wherein the grid lines extend along a first direction, the grid lines are distributed along a second direction, the data lines extend along the second direction, the data lines are distributed along the first direction, scanning signal ends corresponding to pixel circuits in the same row are coupled with the same grid lines, data signal ends corresponding to pixel circuits in the same column are coupled with the same data lines, the first direction is a row direction, and the second direction is a column direction;

The display panel further comprises a first control signal line, a second control signal line and a third control signal line, wherein a first control signal end corresponding to each pixel circuit is coupled with the first control signal line, a second control signal end corresponding to each pixel circuit is coupled with the second control signal line, and a third control signal end corresponding to each pixel circuit is coupled with the third control signal line.

11. A driving method of a pixel circuit, characterized in that it is applied to the pixel circuit according to any one of claims 1 to 8, the method comprising:

A reset stage, wherein reference voltages of data signal ends are provided for a first node and a second node, and first voltages of a first power supply end are provided for a third node and a fourth node so as to reset the first memory module and the second memory module;

A threshold compensation stage, wherein the reference voltage is provided for the first node and the second node, the second voltage of the first power supply terminal is provided for the third node, and the preset voltage is provided for the fourth node so that the first storage module stores the threshold voltage of the driving module;

A data writing stage, wherein a data voltage of the data signal end is provided for the first node, and a voltage signal of the third power end is provided for the second node so as to write the data voltage into the second storage module;

and a light-emitting stage, wherein the second voltage of the first power supply terminal is provided for the third node so as to drive the light-emitting module to emit light.

12. The driving method according to claim 11, characterized in that the method further comprises:

And a mobility compensation stage for providing the reference voltage with a preset duration to the first node, providing the second voltage of the first power supply terminal to the third node, and providing a current signal to the fourth node for mobility compensation, wherein the mobility compensation stage is positioned after the data writing stage.

13. A driving method of a display panel, applied to the display panel of claim 10, wherein one frame time includes a non-light-emitting period and a light-emitting period, the non-light-emitting period including:

A threshold compensation stage, wherein an effective level signal is provided for the first control signal line, the second control signal line and the third control signal line, the reference voltage is provided for each data signal line, and a second voltage is provided for the first power supply end, so that a first storage module in each pixel circuit stores a threshold voltage of a driving module;

A data writing stage, wherein corresponding data voltages are provided for each data line, an effective level signal is provided for the first control signal line, and a gate driving signal is sequentially provided for each gate line along a second direction so as to write the data voltages of each data line into a second storage module in the pixel circuit row by row;

And the light-emitting stage is used for providing the second voltage for the first power supply end and providing an effective level signal for the second control signal line so as to drive the light-emitting modules in the pixel circuits to emit light.

14. The driving method according to claim 13, wherein the non-light emitting stage further comprises:

And a mobility compensation stage, wherein the reference voltage is provided for each data line, an effective level signal with preset duration is provided for the first control signal line, an effective level signal is provided for the second control signal line, and the second voltage is provided for the first power supply end, so that each pixel circuit performs mobility compensation, and the mobility compensation stage is positioned after the data writing stage.

15. A display device comprising the pixel circuit according to any one of claims 1 to 8, or comprising the display panel according to claim 9 or 10.