CN118057241A

CN118057241A - Machine learning for mask optimization in reverse photolithography

Info

Publication number: CN118057241A
Application number: CN202311531774.2A
Authority: CN
Inventors: 杨浩宇; 任昊星
Original assignee: Nvidia Corp
Current assignee: Nvidia Corp
Priority date: 2022-11-21
Filing date: 2023-11-16
Publication date: 2024-05-21

Abstract

Machine learning for mask optimization in reverse photolithography is disclosed. In the semiconductor industry, lithography refers to the process of manufacturing light projected through a geometric design on a mask to illuminate the design on a semiconductor wafer. The wafer surface has a photosensitive material (i.e., photoresist) that, when illuminated by light, causes the design to be etched into the wafer. However, such a lithographic process does not allow perfect transfer of the design to the wafer, particularly because some diffracted light inevitably distorts the pattern etched onto the wafer (i.e., the photoresist image). To address this problem in photolithography, a reverse photolithography technique has been developed that optimizes a mask to match a desired shape on a wafer. The present disclosure improves upon current reverse lithography techniques by employing machine learning for mask optimization.

Description

Machine learning for mask optimization in reverse photolithography

RELATED APPLICATIONS

The application claims that the title submitted at 2022, 11 and 21 is "ILILT: implicit learning of reverse photolithography "(ILILT: IMPLICIT LEARNING of Inverse Lithography Technologies), the benefit of U.S. provisional application No. 63/427,001, the entire contents of which are incorporated herein by reference.

Technical Field

The present disclosure relates to reverse photolithography processes.

Background

In the semiconductor industry, photolithography refers to one such manufacturing process: in this process, light is projected through a geometric design on a mask to illuminate the design on a semiconductor wafer. The wafer surface has a photosensitive material (i.e., photoresist) that, when illuminated by light, causes the design to be etched onto the wafer. However, such photolithographic processes do not transfer the design perfectly onto the wafer, particularly because some diffracted light may inevitably distort the pattern etched onto the wafer (i.e., photoresist image (RESIST IMAGE)).

To address this problem in photolithography, a reverse photolithography technique has been developed that basically reverse engineering or optimizing a mask to match a desired shape on a wafer. Early reverse lithography techniques involved a numerical solver that would start with an initialized mask (typically the design pattern plus some assist features) and then iteratively perform forward and backward calculations until converged. The forward path will calculate the photoresist image of the current mask and the backward path will apply the gradient of the photoresist image error to update the mask. Unfortunately, this early solution is slow because each forward path is time consuming and, furthermore, results are not optimal because they are highly dependent on the initial conditions of the mask.

To address the limitations of numerical solvers, more current solutions employ machine learning. But in general these current solutions still require a lot of intervention by the numerical solver. For example, one solution uses machine learning to calculate the initial mask, but then relies on a forward/backward process of a numerical solver. Thus, the current solutions also exhibit some of the same limitations of earlier solutions, as they all rely to some extent on numerical solvers.

There is a need to address these and/or other problems associated with the prior art. For example, mask optimization using machine learning in reverse lithography is required.

Disclosure of Invention

A method, computer-readable medium, and system for mask optimization using machine learning in reverse photolithography are disclosed. During an iteration of at least one iteration of the inverse photolithography process, the input mask image and the input design image are processed using the machine learning model to predict an output mask image, and the output mask image is output.

Drawings

FIG. 1 illustrates a method for mask optimization using machine learning in a reverse photolithography technique, in accordance with an embodiment.

FIG. 2 illustrates a system for mask optimization using machine learning in a reverse photolithography technique, according to an embodiment.

FIG. 3 illustrates a pipeline of a machine learning model in the system of FIG. 2, according to an embodiment.

Fig. 4 shows an expanded view of the pipeline of fig. 3, according to an embodiment.

FIG. 5 illustrates an algorithm for training a machine learning model in the system of FIG. 2, according to an embodiment.

FIG. 6A illustrates inference and/or training logic in accordance with at least one embodiment.

FIG. 6B illustrates inference and/or training logic in accordance with at least one embodiment.

Fig. 7 illustrates training and deployment of a neural network in accordance with at least one embodiment.

FIG. 8 illustrates an example data center system in accordance with at least one embodiment.

Detailed Description

FIG. 1 illustrates a method for mask optimization in reverse photolithography using machine learning, according to an embodiment. The method 100 may be performed by a device, which in embodiments may include a processing unit, a program, custom circuitry, or a combination thereof. In another embodiment, a system comprising a non-transitory memory containing instructions stores and one or more processors in communication with the memory, executable instructions to perform method 100. In another embodiment, a non-transitory computer-readable medium may store computer instructions that, when executed by one or more processors of a device, cause the device to perform the method 100.

The method 100 may be performed during an iteration of a reverse photolithography process. The reverse photolithography process refers to a process of calculating a mask for a target pattern to be etched onto a semiconductor wafer. Reverse photolithography processes are employed to address imperfect design-to-wafer transfer (e.g., distortion of the design due to diffracted light impinging on the wafer). For example, the mask may be calculated such that when the mask is used in a photolithographic process to etch a pattern onto a semiconductor wafer, the etched pattern matches the target pattern as closely as possible.

The reverse photolithography process may comprise a single iteration in an embodiment, or multiple iterations in another embodiment. The method 100 may be repeated for each iteration of the reverse photolithography process. Generally, each iteration runs to generate a finer mask for the target pattern. For example, during each iteration, the mask may be continually optimized for the target pattern. In an embodiment, the reverse photolithography process may target a defined error (i.e. a minimized threshold difference from the target pattern) and iterate accordingly until a defined (minimized) error of the mask and the target pattern is achieved. In another embodiment, the reverse photolithography process may include a predefined number of iterations. As described herein, the inverse photolithography process may predict an optimized mask image for a given (input) design image.

With respect to iterations of the reverse photolithography process, and in particular with respect to method 100, in operation 102, the input mask image and the input design image are processed using a machine learning model to predict an output mask image. The input mask image refers to an image of a previously calculated mask that is input into the machine learning model. Masks, sometimes referred to as photomasks or photolithographic masks, are physical components (e.g., plates) having a geometric design through which light may be transmitted.

In embodiments where the current iteration of the reverse photolithography process is the initial (i.e., first) iteration of the process, the input mask image may be an initialized mask image. In embodiments where the current iteration of the reverse photolithography process is the second or later iteration of the process, the input mask image may be a mask image calculated in a previous iteration of the process. For example, as described in detail below, the previously calculated input mask image may be an output mask image predicted in a previous iteration of the process.

Also for the purposes of this description, an input design image refers to an image of a design input to a machine learning model. The design is a target pattern to be etched onto a semiconductor wafer. Further, the machine learning model predicted output mask image refers to an image of a mask that the machine learning model outputs (i.e., predicts) from the input mask image and the input design image. In an embodiment, the output mask image is a refinement or optimization of the input mask image for the input design image.

The machine learning model is a model that uses machine learning training to predict a mask image from a given mask image and a given design image. In an embodiment, the machine learning model may be an implicit layer. In an embodiment, the machine learning model may be trained using or in a predefined number of iterations. In an embodiment, the machine learning model may be trained using back propagation through a predefined number of iterations. In an embodiment, the machine learning model may be trained using the truth (ground truth) optimized mask.

In an embodiment, the machine learning model may also process the input photoresist image to predict the output mask image. Inputting a photoresist image refers to inputting a photoresist image of a machine learning model. In an embodiment, the input photoresist image is generated or calculated as a function of the input mask image. In an embodiment, the input photoresist image may be generated by a forward photolithography estimator. In various embodiments, the forward photolithography estimator may be a second machine learning model, an existing physical model, or a pre-trained function.

Returning to the iteration of the reverse photolithography process, in operation 104, an output mask image is output. As described above, the output mask image predicted by the machine learning model may be output into the next iteration of the inverse photolithography process. On the other hand, when the current iteration of the reverse photolithography process is the last iteration of the process, then the output mask image may be the final output of the reverse photolithography process. This final output may be a mask that is optimized for a given design. Further, such a mask may be used in a photolithographic process to etch a given design on a semiconductor wafer.

Example embodiment of method 100

In an embodiment, the method 100 may be implemented in the context of fabricating a semiconductor device from an original design image. With respect to this example, implementations may include: receiving an original design image (e.g., an input design image having a target pattern), defining (e.g., initializing) a mask image of the original design image, providing the mask image and the original design image as initial inputs to a reverse photolithography machine learning model, iterating at least two times the steps of: the inverse lithographic machine learning model generates a current output mask image optimized for the original design image from its current input, and the inverse lithographic machine learning model outputs the current output mask image, wherein the current output mask image is output in each iteration of the steps preceding the last iteration of the steps so as to serve as a next input to the inverse lithographic machine learning model with the original design image, and performs lithography in physically manufacturing the semiconductor device using the final current output mask image (i.e., the current output mask image produced by the last iteration of the steps).

Further embodiments will now be provided in the description of the subsequent figures. It should be noted that the embodiments disclosed herein with reference to method 100 of fig. 1 may be applicable to and/or used in conjunction with any of the remaining figures below.

FIG. 2 illustrates a system 200 for mask optimization using machine learning in a reverse photolithography technique, in accordance with embodiments. In an embodiment, the system 200 may be implemented for performing the method 100 of fig. 1. However, of course, the system 200 may be implemented in any desired context. The above definitions and embodiments apply equally to the description of this embodiment.

As shown, the input is provided to the machine learning model 202. The machine learning model 202 executes on a computing device (e.g., a server). In an embodiment, the machine learning model 202 may be executed in the cloud. The machine learning model 202 is trained to predict mask images of a target design, as described in more detail below.

The input may be received from an application. In an embodiment, the application may execute on the same computing device on which the machine learning model 202 executes. In another embodiment, the application may execute on a remote computing device, so the machine learning model 202 may receive input from the application over a network.

In this embodiment, the input includes at least a mask image and a design image. In an embodiment, the input further comprises a photoresist image generated from the mask image. The machine learning model 202 processes the input to predict the mask image based on the input. The predicted mask image may be refined based on the input mask image.

The machine learning model 202 outputs a predicted mask image. The machine learning model 202 may output the predicted mask image for the next iteration of the machine learning model 202. In another embodiment, the machine learning model 202 may output the predicted mask image as the final optimized mask for the given design. Another system for performing a photolithographic process may then use the final optimized mask.

In a further embodiment described below, the following notations will be referred to:

m _t: optimizing mask images at time stamp t

Z _t：M_t photoresist image

Z ^*: target design image

M ^*：Z^* optimization mask

J: jacobian matrix (Jacobian matrix)

|| _F: Frobenius norm of matrix Luo Beini

F _o: optical modeling function

F _r: photoresist modeling function

F _d: measuring a function of error between a photoresist image and a design

Machine learning model as implicit layer

In embodiments where the machine learning model 202 is an implicit layer, the implicit layer may be defined as finding M according to equation 1.

Equation 1

f(M,Z^*)＝f_d(f_r(f_o(M)),Z^*)＝∈

Where e is some minimum achievable by equation 1.

Since equation 1 is a composite of a set of nonlinear functions, it is difficult to explicitly solve, so it can be assumed that equation 1 has a solution M ^* that follows the form of equation 2.

Equation 2

M^*＝g(M^*,Z^*),

This results in a fixed-point layer representation (fixed-point layer representation) of the machine learning model 202.

Equation 2 can then be solved by weight binding (weight-tied approach) according to equations 3 and 4.

Equation 3

M_t+1＝g(M_t,Z^*,w),

t＝1,2,…,

Equation 4

lim_t→∞M_t＝lim_t→∞g(M_t,Z^*,w)＝g(M^*,Z^*,w)＝M^*

To land the machine learning model 202, a lithography estimator may be included in g so that equation 3 may be rewritten as equation 5.

Equation 5

M_t+1＝g(M_t,Z_t,Z^*,w),

t＝1,2,…,

Where Z _t＝g_l(M_t,w_l) is the photoresist image of M _t at time stamp t, g _l is some forward photolithography estimator. Equation 5 formulates the core of the reverse photolithography process framework. The use of equation 5 is the embedding condition of the lithography estimator, which implicitly conveys to g the physical meaning of each step in the process.

Fig. 3 illustrates a pipeline 300 of the machine learning model 202 in the system 200 of fig. 2. Thus, in an embodiment, pipeline 300 may be implemented in the context of machine learning model 202 of fig. 2. The above definitions and embodiments apply equally to the description of this embodiment.

The illustrated pipeline 300 follows the basic structure described by equation 5, which includes a specially designed lithographic path g _l. At time stamp t, there are three inputs into g, M _t、Z^* and Z _t, respectively, and M _t+1.Z_t is generated by feeding M _t to a lithography estimator.

This process can also be extended until an equilibrium state is reached, as shown in fig. 4. Theoretically, the expansion depth can reach infinity, thereby realizing higher level feature abstraction and time feature learning. However, based on specific hardware limitations, only a fixed deployment depth may be allowed.

The master network g will obtain knowledge of how well the mask at the current timestamp is (for implementing a given design). This feature enables automatic learning of fixed point iterations.

Machine learning model training-examples

As described above, equation 5 defines a fixed-point model representing the weight binding of the machine learning model 202 of FIG. 2. The training architecture described herein can efficiently and effectively solve the model.

During the training process, the model is expanded to a fixed depth T, training the final output M _T toward the truth mask M ^*. In other words, the model is trained in a predefined number of iterations according to equation 6.

Equation 6

s.t.M_t+1＝g(M_t,Z_t,Z^*,w),t＝0,1,…,T-1,

Z_t＝g_l(M_t,w_l),t＝0,1,…,T

Equation 6 can be solved directly by time back-propagation (back-propagation through time, BPTT). Taking w as an example, algorithm 1 in fig. 5 shows how w is updated during training. In various embodiments, g _l may be a pre-training function or a real lithography model. Therefore, we do not discuss the update of w _l. Note that the key step of algorithm 1 is the gradient computation along the different time stamps (lines 5-8) computed according to the chained rules. After model training is completed, the optimized mask may be obtained at a time stamp T in the inference sequence.

Machine learning

Deep Neural Networks (DNNs), including deep learning models, developed on processors have been used for a variety of use cases, from automated driving automobiles to faster drug development, from automated image captioning in online image databases to intelligent real-time language translation in video chat applications. Deep learning is a technique that simulates the human brain neural learning process, which constantly learns, constantly becomes more clever, and provides more accurate results faster over time. The child is initially taught by the adult to correctly recognize and classify various shapes, ultimately without any instruction to recognize the shapes. Also, deep learning or neural learning systems also need to be trained in object recognition and classification to become more clever, efficient in recognizing basic objects, occluded objects, etc., while also giving context to the objects.

At the simplest level, neurons in the human brain will look at the various inputs received, assign a degree of importance to each of these inputs, and pass the outputs to other neurons to act on. Artificial neurons or perceptrons are the most basic model of neural networks. In one example, the perceptron may receive one or more inputs representing various features of the object that the perceptron is being trained to identify and classify, and assign a weight to each of these features based on the importance of that feature in defining the shape of the object.

The Deep Neural Network (DNN) model includes multiple layers of multiple connected nodes (e.g., perceptron, boltzmann machine, radial basis function, convolutional layer, etc.), which can be trained with massive input data to quickly solve complex problems with high accuracy. In one example, a first layer of the DNN model breaks up the input image of the car into different parts and looks for basic patterns such as lines and angles. The second layer combines the lines to find higher level patterns such as wheels, windshields and rearview mirrors. The next layer identifies the type of vehicle and the last layer generates a tag for the input image identifying the model of the particular make of car.

Once the DNNs are trained, the DNNs may be deployed and used to identify and classify objects or patterns in a process known as reasoning. Examples of reasoning (the process by which DNNs extract useful information from a given input) include: identifying handwritten numbers on checks deposited in ATM, identifying images of friends in photos, providing movie recommendations to 5000 tens of thousands of users, identifying and classifying different types of car, pedestrian and road hazards in unmanned cars, or translating human speech in real time.

During training, data flows through the DNN in the forward propagation phase until the predictions produced indicate the labels corresponding to the inputs. If the neural network does not label the input correctly, the error between the correct label and the predicted label is analyzed and the weights of each feature are adjusted during the backward propagation phase until the DNN labels the input correctly and other inputs in the training dataset. Training complex neural networks requires a large amount of parallel computational performance, including floating point multiplications and additions. Inference is less computationally intensive than training, which is a delay-sensitive process in which a trained neural network is applied to new inputs that it has not seen before to classify images, interpret speech, and generally infer new information.

Inference and training logic

As described above, deep learning or neural learning systems require training to generate inferences from input data. Detailed information regarding the inference and/or training logic 615 of the deep learning or neural learning system is provided below in connection with fig. 6A and/or 6B.

In at least one embodiment, the inference and/or training logic 615 can include, but is not limited to, a data store 601 for storing forward and/or output weights and/or input/output data corresponding to neurons or layers of a neural network trained in aspects of one or more embodiments and/or used for inference. In at least one embodiment, the data store 601 stores weight parameters and/or input/output data for layers of a neural network that are trained during forward propagation of input/output data and/or weight parameters during training and/or reasoning using aspects of one or more embodiments. In at least one embodiment, any portion of data store 601 may be included with other on-chip or off-chip data stores, including the processor's L1, L2, or L3 cache or system memory.

In at least one embodiment, any portion of the data store 601 may be internal or external to one or more processors or other hardware logic devices or circuitry. In at least one embodiment, the data store 601 may be a cache memory, dynamic random-access memory (DRAM), static random-access memory (SRAM), non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether the data store 601 is internal or external to the processor, e.g., whether it includes DRAM, SRAM, flash, or other storage types, may depend on the latency requirements of the available on-chip storage versus off-chip storage, the training being performed, and/or the inference function, the data batch size for neural network reasoning and/or training, or some combination of these factors.

In at least one embodiment, the inference and/or training logic 615 can include, but is not limited to, a data store 605 for storing backward and/or output weights and/or input/output data corresponding to neurons or layers of a neural network trained in aspects of one or more embodiments and/or used for inference. In at least one embodiment, the data store 605 stores weight parameters and/or input/output data for various layers of the neural network that are trained in or used in connection with the one or more embodiments during back propagation of input/output data and/or weight parameters during training and/or reasoning using aspects of the one or more embodiments. In at least one embodiment, any portion of the data store 605 may be included with other on-chip or off-chip data stores, including the processor's L1, L2, or L3 cache or system memory. In at least one embodiment, any portion of the data store 605 may be internal or external to one or more processors or other hardware logic devices or circuitry. In at least one embodiment, the data store 605 can be a cache memory, DRAM, SRAM, nonvolatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether the data store 605 is internal or external to the processor, e.g., whether it includes DRAM, SRAM, flash, or other storage type composition, may depend on the latency requirements of the available on-chip storage versus off-chip storage, the training and/or reasoning functions being performed, the data batch size for reasoning and/or neural network training, or some combination of these factors.

In at least one embodiment, data store 601 and data store 605 may be separate storage structures. In at least one embodiment, data store 601 and data store 605 may be the same storage structure. In at least one embodiment, data store 601 and data store 605 may be partially identical storage structures as well as partially independent storage structures. In at least one embodiment, any portion of data store 601 and data store 605 may be included with other on-chip or off-chip data stores, including the processor's L1, L2, or L3 cache or system memory.

In at least one embodiment, the inference and/or training logic 615 may include, but is not limited to, one or more Arithmetic Logic Units (ALUs) 610 to perform logical and/or mathematical operations based at least in part on or indicated by training and/or reasoning codes, the results of which may result in activations (e.g., output values of layers or neurons within a neural network) stored in an activation store 620 that are a function of input/output and/or weight parameter data stored in the data store 601 and/or the data store 605. In at least one embodiment, the activations stored in the activation store 620 are generated from linear algebra or matrix-based mathematical operations performed by the ALU 610 in response to executing instructions or other code, where weight values stored in the data store 605 and/or 601 are used as operands along with other values (e.g., bias values, gradient information, momentum values, or other parameters or superparameters), any or all of which may be stored in the data store 605 or 601 or another memory area on-chip or off-chip. In at least one embodiment, the ALUs 610 are contained in one or more processors or other hardware logic devices or circuits, while in another embodiment, the ALUs 610 may be external (e.g., coprocessors) to the processor or other hardware logic device or circuit in which they are used. In at least one embodiment, the ALU 610 may be contained in an execution unit of a processor or otherwise contained in an ALU bank accessible to an execution unit of a processor, may be in the same processor, or distributed among different types of processors (e.g., central processing units, graphics processing units, fixed function units, etc.). In at least one embodiment, data store 601, data store 605, and activation store 620 may reside within the same processor or other hardware logic device or circuit, and in another embodiment they may reside within different processors or other hardware logic devices or circuits, or some combination of the same and different processors or other hardware logic devices or circuits. In at least one embodiment, any portion of the activation store 620 may be included with other on-chip or off-chip data stores, including the processor's L1, L2, or L3 cache or system memory. In addition, the inference and/or training code can be stored with other code accessible to a processor or other hardware logic or circuitry, and can be obtained and/or processed using processor acquisition, decoding, scheduling, execution, retirement (retrieval), and/or other logic circuitry.

In at least one embodiment, the active storage 620 may be cache memory, DRAM, SRAM, nonvolatile memory (e.g., flash memory), or other storage. In at least one embodiment, the activation store 620 may be located entirely or partially internal or external to one or more processors or other logic circuits. In at least one embodiment, the selection of whether the activation store 620 is internal or external to the processor, e.g., whether it includes DRAM, SRAM, flash, or other memory types, may depend on the latency requirements of the available on-chip storage versus off-chip storage, the training being performed, and/or the inference function, the data batch size for neural network reasoning and/or training, or some combination of these factors. In at least one embodiment, the inference and/or training logic 615 shown in FIG. 6A may be used in conjunction with an Application Specific Integrated Circuit (ASIC), such as Google corporationProcessing unit, graphcore ^TM company's reasoning processing unit (IPU) or Intel company(E.g., "LAKE CREST") processors. In at least one embodiment, the inference and/or training logic 615 shown in FIG. 6A can be used in conjunction with central processing unit ("CPU") hardware, graphics processing unit ("GPU") hardware, or other hardware, such as a field programmable gate array ("FPGA").

Fig. 6B illustrates inference and/or training logic 615 in accordance with at least one embodiment. In at least one embodiment, the inference and/or training logic 615 can include, but is not limited to, hardware logic in which computing resources are dedicated or otherwise used exclusively in connection with weight values or other information corresponding to one or more neuron layers within a neural network. In at least one embodiment, the inference and/or training logic 615 shown in FIG. 6B may be used in conjunction with an Application Specific Integrated Circuit (ASIC), such as googleProcessing units, graphcore ^TM Inferencing Processing Units (IPUs) or Intel corporation(E.g., "LAKE CREST") processors. In at least one embodiment, the inference and/or training logic 615 shown in FIG. 6B can be used in conjunction with Central Processing Unit (CPU) hardware, graphics Processing Unit (GPU) hardware, or other hardware, such as a Field Programmable Gate Array (FPGA). In at least one embodiment, the inference and/or training logic 615 includes, but is not limited to, a data store 601 and a data store 605, which may be used to store weight values and/or other information, including bias values, gradient information, momentum values, and/or other parameter or hyper-parameter information. In at least one embodiment shown in FIG. 6B, each of data store 601 and data store 605 is associated with a dedicated computing resource, such as computing hardware 602 and computing hardware 606, respectively. In at least one embodiment, each computing hardware 606 includes one or more ALUs that perform mathematical functions (e.g., linear algebraic functions) on only the information stored in data store 601 and data store 605, respectively, the results of which are stored in activation store 620.

In at least one embodiment, each of the data stores 601 and 605 and the respective computing hardware 602 and 606 correspond to a different layer of the neural network, respectively, such that the resulting activation from one "store/compute pair 601/602" of the data store 601 and the computing hardware 602 is provided as input to the next "store/compute pair 605/606" of the data store 605 and the computing hardware 606, reflecting the conceptual organization of the neural network. In at least one embodiment, each of the storage/computation pairs 601/602 and 605/606 may correspond to more than one neural network layer. In at least one embodiment, additional storage/computation pairs (not shown) after or in parallel with storage/computation pairs 601/602 and 605/606 may be included in inference and/or training logic 615.

Neural network training and deployment

Fig. 7 illustrates another embodiment of training and deploying a deep neural network. In at least one embodiment, the training data set 702 is used to train an untrained neural network 706. In at least one embodiment, training frame 704 is a PyTorch frame, while in other embodiments training frame 704 is Tensorflow, boost, caffe, microsoft Cognitive Toolkit/CNTK, MXNet, chainer, keras, deeplearning4j or other training frames. In at least one embodiment, training framework 704 trains untrained neural network 706 and enables it to be trained using the processing resources described herein to generate trained neural network 708. In at least one embodiment, the weights may be selected randomly or by pre-training using a deep belief network. In at least one embodiment, training may be performed in a supervised, partially supervised, or unsupervised manner.

In at least one embodiment, the untrained neural network 706 is trained using supervised learning, where the training data set 702 includes inputs paired with desired outputs of the inputs, or the training data set 702 includes inputs having known outputs, and the outputs of the neural network are manually ranked. In at least one embodiment, the untrained neural network 706 is trained in a supervised manner, processes the input from the training dataset 702, and compares the resulting output to a set of expected or desired outputs. In at least one embodiment, the error may back propagate through the untrained neural network 706. In at least one embodiment, training framework 704 adjusts weights that control untrained neural network 706. In at least one embodiment, training framework 704 includes tools for monitoring how well untrained neural network 706 converges to a model (e.g., trained neural network 708) that is suitable for generating a correct answer (such as in results 714) from known input data (e.g., new data 712). In at least one embodiment, training framework 704 iteratively trains untrained neural network 706 while adjusting weights using an impairment function and an adjustment algorithm (e.g., random gradient descent) to refine the output of untrained neural network 706. In at least one embodiment, the training framework 704 trains the untrained neural network 706 until the untrained neural network 706 reaches a desired accuracy. In at least one embodiment, the trained neural network 708 may then be deployed to implement any number of machine learning operations.

In at least one embodiment, the untrained neural network 706 is trained using unsupervised learning, wherein the untrained neural network 706 attempts to self-train using untagged data. In at least one embodiment, the unsupervised learning training data set 702 will include input data without any associated output data or "true" data. In at least one embodiment, the untrained neural network 706 can learn the groupings in the training data set 702 and determine how the various inputs relate to the untrained data set 702. In at least one embodiment, the unsupervised training can be used to generate an ad hoc graph, which is a trained neural network 708 capable of performing operations that help reduce the dimensionality of the new data 712. In at least one embodiment, unsupervised training may also be used to perform anomaly detection, thereby enabling identification of data points in the new data set 712 that deviate from the normal mode of the new data set 712.

In at least one embodiment, semi-supervised learning, a technique that includes a mix of labeled and unlabeled data in the training dataset 702, may be used. In at least one embodiment, training framework 704 may be used to perform incremental learning, such as through transfer learning techniques. In at least one embodiment, incremental learning enables trained neural network 708 to adapt to new data 712 without forgetting knowledge infused into the network during initial training.

Data center

FIG. 8 illustrates an example data center 800 in which at least one embodiment may be used. In at least one embodiment, data center 800 includes a data center infrastructure layer 810, a framework layer 820, a software layer 830, and an application layer 840.

In at least one embodiment, as shown in fig. 8, the data center infrastructure layer 810 can include a resource coordinator 812, packet computing resources 814, and node computing resources (node c.r.) 816 (1) -816 (N), where N represents any integer, positive integer. In at least one embodiment, nodes c.r.816 (1) -816 (N) may include, but are not limited to, any number of Central Processing Units (CPUs) or other processors (including accelerators, field Programmable Gate Arrays (FPGAs), graphics processors, etc.), memory devices (e.g., dynamic read only memory), storage devices (e.g., solid state or disk drives), network input/output ("NW I/O") devices, network switches, virtual Machines (VMs), power modules, cooling modules, and the like. In at least one embodiment, one or more of the nodes c.r.816 (1) -816 (N) may be a server having one or more of the above-described computing resources.

In at least one embodiment, the group computing resources 814 may include individual groups of nodes c.r. located within one or more racks (not shown), or multiple racks housed within data centers (also not shown) in different geographic locations. Individual packets of node c.r. in packet computing resource 814 may include computing, network, memory, or storage resources of the packet that may be configured or allocated to support one or more workloads. In at least one embodiment, several nodes c.r. including CPUs or processors may be grouped within one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches in any combination.

In at least one embodiment, the resource coordinator 822 may configure or otherwise control one or more nodes c.r.816 (1) -816 (N) and/or grouping computing resources 814. In at least one embodiment, the resource coordinator 822 can include a Software Design Infrastructure (SDI) management entity of the data center 800. In at least one embodiment, the resource coordinator may include hardware, software, or some combination thereof.

In at least one embodiment, as shown in FIG. 8, the framework layer 820 includes a job scheduler 832, a configuration manager 834, a resource manager 836, and a distributed file system 838. In at least one embodiment, the framework layer 820 may include a framework of one or more applications 842 supporting software 832 and/or application layers 840 of the software layer 830. In at least one embodiment, software 832 or application 842 may include web-based service software or applications, such as Amazon Web Services, google Cloud, and Microsoft Azure, respectively. In at least one embodiment, framework layer 820 can be, but is not limited to, a free open source Web application framework such as APACHE SPARK ^TM (Spark) that can utilize distributed file system 838 for large-scale data processing (e.g., big data). In at least one embodiment, job scheduler 832 may include Spark drivers to facilitate scheduling the workload supported by the layers of data center 800. In at least one embodiment, the configuration manager 834 may be capable of configuring different layers, such as the software layer 830 and the framework layer 820, including Spark and distributed file systems 838 for supporting large-scale data processing. In at least one embodiment, the resource manager 836 may be capable of managing cluster or group computing resources mapped to the distributed file system 838 and job scheduler 832 or allocated for supporting the distributed file system 838 and job scheduler 832. In at least one embodiment, the clustered or grouped computing resources may include grouped computing resources 814 on the data center infrastructure layer 810. In at least one embodiment, the resource manager 836 may coordinate with the resource coordinator 812 to manage these mapped or allocated computing resources.

In at least one embodiment, the software 832 included in the software layer 830 may include software used by at least a portion of the nodes c.r.816 (1) -816 (N), the packet computing resources 814, and/or the distributed file system 838 of the framework layer 820. One or more types of software may include, but are not limited to, internet web search software, email virus scanning software, database software, and streaming video content software.

In at least one embodiment, the applications 842 included in the application layer 840 may include one or more types of applications used by at least portions of the distributed file systems 838 of the nodes c.r.816 (1) -816 (N), the packet computing resources 814, and/or the framework layer 820. One or more types of applications may include, but are not limited to, any number of genomics applications, cognitive computing and machine learning applications, including training or reasoning software, machine learning framework software (e.g., pyTorch, tensorFlow, caffe, etc.), or other machine learning applications used in connection with one or more embodiments.

In at least one embodiment, any of configuration manager 834, resource manager 836, and resource coordinator 812 can implement any number and type of self-modifying changes based on any number and type of data acquired in any technically feasible manner. In at least one embodiment, the self-modifying action may free a data center operator of the data center 800 from making configuration decisions that may be poor, and may avoid portions of the data center that are poorly utilized and/or perform poorly.

In at least one embodiment, the data center 800 may include tools, services, software, or other resources to train one or more machine learning models or predictive or inferential information using one or more machine learning models in accordance with one or more embodiments described herein. For example, in at least one embodiment, the machine learning model may be trained from neural network architecture computing weight parameters using the software and computing resources described above with respect to the data center 800. In at least one embodiment, the trained machine learning model corresponding to one or more neural networks may be used to infer or predict information using the resources described above with respect to the data center 800 by using the weight parameters calculated by one or more training techniques described herein.

In at least one embodiment, the data center may use a CPU, application Specific Integrated Circuit (ASIC), GPU, FPGA, or other hardware to perform training and/or reasoning using the resources described above. Further, one or more of the software and/or hardware resources described above may be configured as a service, allowing a user to train or perform information reasoning, such as image recognition, speech recognition, or other artificial intelligence services.

The inference and/or training logic 615 is employed to perform inference and/or training operations related to one or more embodiments. In at least one embodiment, the inference and/or training logic 615 can be employed in the system fig. 8 for an inference or predictive operation based at least in part on weight parameters calculated using neural network training operations, neural network functions and/or architectures, or neural network use cases described herein.

As described herein with reference to fig. 1-5, a method, computer-readable medium, and system for mask optimization using machine learning in reverse photolithography techniques are disclosed. As shown in fig. 6A and 6B, the machine learning model may be stored (partially or wholly) in one or both of the data stores 601 and 605 in the inference and/or training logic 615. The training and deployment of machine learning may be performed as shown in fig. 7 and described herein. The distribution of machine learning may be performed using one or more servers in a data center 800 as shown in fig. 8 and described herein.

Claims

1. A method, comprising:

At the apparatus, during an iteration of at least one iteration of the reverse photolithography process:

Processing the input mask image and the input design image using a machine learning model to predict an output mask image; and

And outputting the output mask image.

2. The method of claim 1, wherein the reverse photolithography process comprises a plurality of iterations.

3. The method of claim 2, wherein a number of iterations included in the plurality of iterations is predefined.

4. The method of claim 2, wherein for an initial iteration of the reverse photolithography process, the input mask image is an initialized mask image.

5. The method of claim 4, wherein for each subsequent iteration of the reverse photolithography process, the input mask image is the output mask image predicted during a previous iteration.

6. The method of claim 1, wherein during the iteration, the machine learning model further processes an input photoresist image.

7. The method of claim 6, wherein the input photoresist image is generated as a function of the input mask image.

8. The method of claim 6, wherein the input photoresist image is generated by a forward photolithography estimator.

9. The method of claim 8, wherein the forward photolithography estimator is a second machine learning model or an existing physical model.

10. The method of claim 8, wherein the forward photolithography estimator is a pre-trained function.

11. The method of claim 1, wherein the inverse photolithography process predicts an optimized mask image for the input design image.

12. The method of claim 1, wherein the machine learning model is an implicit layer.

13. The method of claim 1, wherein the machine learning model is trained using a predefined number of iterations.

14. The method of claim 13, wherein the machine learning model is trained using back propagation through the predefined number of iterations.

15. The method of claim 13, wherein the machine learning model is trained using truth-optimized mask images.

16. A system, comprising:

a non-transitory memory containing instructions; and

One or more processors in communication with the memory, wherein the one or more processors execute the instructions to perform an iteration of at least one iteration of a reverse photolithography process, including during the iteration:

And outputting the output mask image.

17. The system of claim 16, wherein the reverse photolithography process comprises a plurality of iterations.

18. The system of claim 17, wherein for an initial iteration of the reverse photolithography process, the input mask image is an initialized mask image, and wherein for each subsequent iteration of the reverse photolithography process, the input mask image is the output mask image predicted during a previous iteration.

19. The system of claim 16, wherein the inverse photolithography process predicts an optimized mask image for the input design image.

20. A non-transitory computer-readable medium storing computer instructions that, when executed by one or more processors of an apparatus, cause the apparatus to perform an iteration of at least one iteration of a reverse photolithography process, comprising during the iteration:

And outputting the output mask image.

21. A method of manufacturing a semiconductor device from an original design image, the method comprising:

Receiving the original design image;

Defining a mask image for the original design image;

providing the mask image and the original design image as initial inputs to a reverse photolithography machine learning model;

at least two iterations of the following steps:

The inverse lithographic machine learning model generates a current output mask image optimized for the original design image from its current input, and

The inverse lithographic machine learning model outputs the current output mask image,

Wherein for each iteration of the step preceding the last iteration of the step, outputting the current output mask image for use with the original design image as a next input to the inverse lithographic machine learning model; and

Photolithography is performed when the semiconductor device is physically manufactured using the final current output mask image.