CN118054662A - Device, power supply control method, storage medium and electronic equipment - Google Patents
Device, power supply control method, storage medium and electronic equipment Download PDFInfo
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Abstract
The embodiment of the application provides a device, a power supply control method, a storage medium and electronic equipment, relates to the technical field of circuits, and aims to reduce wiring cost while meeting the power supply requirements of a plurality of processing cores in the device; each of the plurality of first power supply circuits is connected to one of the plurality of processing cores; each processing core is connected with a second power supply circuit through a switching circuit; each first power supply circuit is used for outputting a first voltage to a corresponding one of the processing cores; the second power supply circuit is used for outputting a second voltage to at least one processing core when the switching circuit is conducted on the second power supply circuit and at least one processing core in the plurality of processing cores, and the second voltage is higher than the first voltage. Based on the above, the same second power supply circuit is used for providing high transient voltage and current, so that the use amount of components is reduced, and the wiring cost is reduced.
Description
Technical Field
The present application relates to the field of circuit technologies, and in particular, to an apparatus, a power supply control method, a storage medium, and an electronic device.
Background
A system on chip (SoC) is a system in which various functional blocks such as a central processing unit (central processing unit, CPU), a memory, an interface, a digital processor (digital signalprocessing, DSP), a network processor (neural network processing unit, NPU), and a graphics processor (graphics processing unit, GPU) are integrated onto one semiconductor to realize computation or other functions. In recent years, with the increase of the number of processing cores and the increase of the operating frequency in the SoC, the number of processing core voltages is increased, and the supply current of each processing core is also increased, which has an increasing requirement on the transient characteristics of the processing core voltages in the SoC. To meet the increasing load current demand, a power manager (power management unit, PMU) in the processor is conventionally implemented using a BUCK chopper (BUCK chopper, BUCK circuit for short). However, when different processing cores work, the peak current is different, so that the power supply circuit with a plurality of different output parameters is required to be arranged, the number of phases of the power supply circuit is too large, the number of used inductors, load capacitors and the like is also relatively large, the wiring area on the printed circuit board (printed circuitboard, PCB) is finally large, and the wiring cost and difficulty of the PCB are increased. In addition, in order to cope with the situation of instantaneous heavy current of a load, the conventional power supply circuit meets the requirement of high transient characteristic of processing nuclear voltage, prevents falling, and the output voltage of each power supply circuit is always very high, so that the static voltage is set to be higher, and further, the static leakage of the SoC is larger, and the loss is increased. In order to meet the requirement of high transient current, the output phase number of the nuclear voltage and the capacity of low Equivalent Series Resistance (ESR) capacitor of the power supply output need to be increased, so that the wiring area of the PCB board is further increased. Accordingly, there is a need to provide a solution to the above-mentioned problems.
Disclosure of Invention
The application aims to provide a device, a power supply control method, a storage medium and an electronic device, so as to meet the power supply requirements of a plurality of processing cores and reduce wiring cost.
In order to solve the above problems, the embodiment of the application provides the following technical scheme.
In a first aspect, an apparatus is provided that includes a plurality of first power supply circuits, a plurality of processing cores, a switching circuit, and a second power supply circuit. Wherein each of the plurality of first power circuits is coupled to one of the plurality of processing cores. Each processing core is connected with a second power supply circuit through a switching circuit. Each first power supply circuit is used for outputting a first voltage to one processing core corresponding to each first power supply circuit; the second power supply circuit is used for outputting a second voltage to at least one processing core when the switching circuit is conducted with the second power supply circuit and at least one processing core in the plurality of processing cores, and the second voltage is higher than the first voltage. When a certain processing core is in a light load state, the first power supply circuit can be used for supplying power so as to meet the minimum power supply requirement when the processing core runs. When a certain processing core is in a heavy-load state, the second power supply circuit can be started, and then the second power supply circuit is conducted with the processing core through the switching circuit to provide high transient voltage and current for the processing core; when the processing core is re-operated in the light load state, the second power supply circuit can be disconnected from the processing core through the switching circuit. In this way, the power supply capability requirement of the power supply circuit for directly supplying power to each core can be reduced, so that the number of capacitors and the number of inductors in the power supply circuit are reduced, and the wiring area is further reduced; meanwhile, the same power supply circuit can be used for providing high-transient voltage and current for a plurality of processing cores by controlling the switching circuit, and a power supply circuit capable of providing the high-transient voltage and current is not required to be independently arranged for each processing core, so that the number of capacitors and the number of inductors in the power supply circuit are further reduced, and the wiring area is further reduced.
It will be appreciated that when multiple processing cores have different power requirements, multiple second power circuits may be provided, where each second power circuit provides, through a switching circuit, voltages and currents required for the processing cores with the same or similar power requirements in a heavy load state, so as to implement packet power, and further reduce circuit loss.
In one possible implementation manner, the apparatus further includes: and a control circuit connected to the plurality of processing cores and the switching circuit, the control circuit outputting a control signal to the switching circuit based on a predicted reload state of at least one processing core. The switching circuit turns on the second power supply circuit and the at least one processing core in response to the control signal. Based on the above, the control circuit can control the second power supply circuit to be conducted with the corresponding processing core through the predicted overload state of the processing core, so that the voltage and the current required by the overload state can be provided for the processing core, the switching circuit can be controlled better, and the loss of the circuit can be reduced.
In one possible implementation, the predicted reload status of the at least one processing core is determined when an operating parameter of the at least one processing core exceeds a reference threshold. Wherein the operating parameters include at least two of an operating voltage, an operating current, an operating frequency, or a memory bandwidth. When at least two of the parameters exceed the corresponding reference threshold values, the control circuit determines the predicted overload state of the processing core, so that the problem of misjudgment is solved, and the loss of the circuit is increased.
It will be appreciated that the control circuitry is not limited to the several parameters described above in predicting the reload status of the processing core. For example, when predicting the overload state of the processing core, the temperature of the processing core may be used as one of the judgment bases, and the detected temperature of the processing core may be compared with a set reference threshold; and the number of parameters for determining the predicted reload state of the processing core may be adjusted according to the actual requirement, and is not limited to determining the predicted reload state of the processing core when two of the plurality of parameters exceed the corresponding reference threshold.
In a possible implementation, the control circuit is specifically configured to output the control signal to the switching circuit before the at least one processing core is in an actual reload state. Based on this, the required voltage and current can be provided to the processing before the processing core is in an actual heavy load state, enabling the processing core to operate more reliably.
In one possible implementation, the control circuit is further connected to a second power supply circuit; wherein the control circuit enables the second power circuit when one or more of the plurality of processing cores is enabled. Based on this, the control circuit can put the second power supply circuit in a ready state in advance. When the switching circuit is conducted, the second power circuit can immediately supply power to the corresponding processing core, and the voltage and the current required by the heavy load state can be provided for the corresponding processing core in time.
Optionally, the control circuit may also activate the second power supply circuit when one of an operating voltage, an operating current, an operating frequency, and a memory bandwidth of the processing core exceeds a reference threshold. Based on this, the standby time of the second power supply circuit can be reduced.
In one possible implementation, the control circuit includes a processing core. Based on this, the switching circuit, the second power supply circuit, and the like are controlled by one processing core of the plurality of processing cores, and an additional control circuit is not required, so that the number of components used on the device can be reduced, the cost can be reduced, and the wiring area can be reduced.
In one possible implementation, the second power supply circuit may be a buck chopper circuit. When the second power supply circuit is a single-phase step-down chopper circuit, constant high-transient voltage and current can be provided for the processing core. When the second power supply circuit adopts the multiphase step-down chopper circuit, the high transient current of the processing core can be adjusted by controlling the conducting phase number of the multiphase step-down chopper circuit, so that the requirement of the processing core for power supply current is more fully met.
In a second aspect, a power supply control method is provided, which is applied to the apparatus in the first aspect, and when the power supply control method is executed on the apparatus, the first power supply circuits are started first, and a first voltage is output to one processing core corresponding to each first power supply circuit. Then starting a second power supply circuit, and outputting a second voltage to at least one processing core when the switching circuit turns on the second power supply circuit and at least one processing core of the plurality of processing cores; wherein the second voltage is higher than the first voltage. Based on this, each processing core can be supplied with power by the corresponding first power circuit independently, and then supply the voltage and current required by the heavy load state by the second power circuit when the switching circuit is turned on.
In one possible implementation, the second power supply circuit and the at least one processing core may be turned on by outputting a control signal to the corresponding switching circuit based on a predicted reload state of the at least one processing core. In this way, the switching circuit can be turned on according to the predicted overload state, and the second power supply circuit can provide the voltage and current required by the overload state for the corresponding processing core in time.
In one possible implementation, the predicted reload status of the at least one processing core may be determined when an operating parameter of the at least one processing core exceeds a reference threshold. The operating parameters include at least two of an operating voltage, an operating current, an operating frequency, or a memory bandwidth. The corresponding reference threshold value can be set according to the change trend of parameters such as working voltage, working current, working frequency, memory bandwidth and the like in the process of converting the processing core from the light load state to the heavy load state. When at least two of the parameters exceed the corresponding reference threshold values, determining a predicted reload state of the processing core, and outputting a control signal to the switching circuit according to the predicted reload state, so as to timely conduct the second power supply circuit with the corresponding processing core when the processing core is in the reload state.
In one possible implementation, the control signals may be output to the corresponding switching circuits before the processing cores are in an actual reload state.
In one possible implementation, the second power supply circuit is activated when one or more of the plurality of processing cores is activated. Based on the above, the second power supply circuit can be started before the switching circuit is conducted, so that the voltage and the current required by the heavy load state can be provided for the corresponding processing core more timely when the switching circuit is conducted.
In one possible implementation manner, the second power supply circuit is a multiphase step-down chopper circuit, and when the second power supply circuit is started, the number of conducting phases of the multiphase step-down chopper circuit can be determined based on the working current of the processing core in an actual heavy-load state. Based on the method, the working current of the processing core can be adjusted by adjusting the number of conducting phases of the multiphase step-down chopper circuit, and the requirement of the processing core on the power supply current in a heavy-load state can be better met.
In a third aspect, a computer-readable storage medium having computer program instructions stored therein is provided; the computer program instructions, when run on a computer, perform the method of any one of the possible implementations of the second aspect described above.
In a fourth aspect, an electronic device is provided, which comprises an apparatus according to any one of the possible implementations of the first aspect.
In a fifth aspect, a computer program product is provided which, when run on a computer, implements the method of any one of the possible implementations of the second aspect described above.
In a sixth aspect, there is provided a controller which, when running a computer program, implements the method of any one of the possible implementations of the second aspect described above.
In a seventh aspect, a control device is provided, comprising a controller and a memory for storing a computer program, which when run by the controller implements the method of any one of the possible implementations of the second aspect.
The technical effects of the third aspect to the seventh aspect may be seen in the first aspect and the second aspect, and are not described herein.
Drawings
FIG. 1 is a schematic diagram of an electronic device;
FIG. 2 is a schematic diagram of a power supply circuit of a system-on-chip;
FIG. 3 is a schematic diagram of a power supply circuit of another system-on-chip;
fig. 4 is a schematic diagram of a power supply circuit according to an embodiment of the present application;
fig. 5 is a schematic diagram of another power supply circuit according to an embodiment of the present application;
FIG. 6 is a schematic diagram of a power supply circuit according to an embodiment of the present application;
Fig. 7 is a schematic flow chart of a power supply control method according to an embodiment of the present application;
FIG. 8 is a timing diagram of power control of a processing core according to an embodiment of the present application;
fig. 9 is a timing diagram of power control of another processing core according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings in the embodiments of the present application.
In the description of the present application, unless otherwise indicated, "/" means that the objects associated in tandem are in a "or" relationship, e.g., A/B may represent A or B; the "and/or" in the present application is merely an association relationship describing the association object, and indicates that three relationships may exist, for example, a and/or B may indicate: there are three cases, a alone, a and B together, and B alone, wherein a, B may be singular or plural. Also, in the description of the present application, unless otherwise indicated, "a plurality" means two or more than two. "at least one of" or the like means any combination of these items, including any combination of single item(s) or plural items(s). For example, at least one (one) of a, b, or c may represent: a, b, c, a-b, a-c, b-c, or a-b-c, wherein a, b, c may be single or plural. In addition, in order to facilitate the clear description of the technical solution of the embodiments of the present application, in the embodiments of the present application, the words "first", "second", etc. are used to distinguish the same item or similar items having substantially the same function and effect. It will be appreciated by those of skill in the art that the words "first," "second," and the like do not limit the amount and order of execution, and that the words "first," "second," and the like do not necessarily differ. Meanwhile, in the embodiments of the present application, words such as "exemplary" or "such as" are used to mean serving as examples, illustrations or explanations. Any embodiment or design described herein as "exemplary" or "e.g." in an embodiment should not be taken as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete fashion that may be readily understood.
The application is described in detail below with reference to the attached drawings and examples:
As shown in fig. 1, in order to meet the requirements of computing power and multifunction, many electronic devices 100 currently have a plurality of processing cores 111, where the processing cores 111 are connected through a communication bus. In some embodiments, the plurality of processing cores 111 may be integrated in the same system-on-chip 110. In order to meet the power requirements of the multiple processing cores 111, a power management unit 120 (powermanagement unit, PMU) is further disposed inside the electronic device 100 to control power to each processing core, and the PMU may also control power to other loads 140 on the electronic device 100. In addition, the PMU may be further connected to a peripheral power circuit 130, where the peripheral power circuit 130 may perform voltage conversion, filtering, etc. on the power input, and then input the processed power to the input terminal of the PMU, and the PMU supplies power to the corresponding processing cores according to the power supply requirements of each processing core. In some embodiments, the PMU and the system on chip 110 may be integrated or may be provided separately. Peripheral power circuit 130 and the PMU may be provided separately or may be integrated. In addition, the electronic device 100 may be a wearable device such as a mobile phone, a tablet computer, an electronic watch, or a smart bracelet; other loads 140 include sensors, cameras, displays, etc., as embodiments of the application are not specifically limited in this regard.
In the electronic device 100, as the number of the processing cores 111 increases and the operating frequency increases, the number of the processing cores 111 increases, and the power supply current of each processing core 111 increases, which makes the requirements on the transient characteristics of the processing core 111 voltage higher. For example, taking the system on chip 110 as an example, as shown in fig. 2, the PMU includes a plurality of power supply devices (power supply devices 1 to n), where each power supply device is connected to one processing core in the system on chip 110 in a one-to-one correspondence manner (for example, the processing cores 1 to n in fig. 2 are connected to the power supply devices 1 to n in a one-to-one correspondence manner). The power supply device can independently supply power to each processing core, and each power supply device can meet the power supply requirement of the corresponding processing core.
It is understood that the power supply device corresponding to each processing core may be independently provided, and is not limited to being provided in the same PMU. The processing cores may be provided in separate processing devices, and are not limited to being provided on the same system-on-chip 110. Alternatively, the individual power supply devices may be integrated with the corresponding processing cores. The specific arrangement modes of the power supply device and the processing core can be selected according to actual requirements, and the embodiment of the application is not particularly limited.
As shown in fig. 3, in order to meet the power supply requirement of the processing core in the heavy load state, many existing power supply devices use a step-down chopper circuit to supply power to the processing core. Some power supply devices (such as the power supply device 2) supply power to the corresponding processing core (the processing core 2) in a single-phase power supply mode, and the power supply device 2 adopts a single-phase BUCK circuit, but the power supply mode can enable the processing core to always work under a higher voltage, so that the capacity of a low Equivalent Series Resistance (ESR) capacitor of the power supply output is increased; meanwhile, if the processing core is in a light load state, the loss of the circuit is increased. Some power supply devices (such as the power supply device 1 and the power supply device n) supply power to corresponding processing cores (the processing cores 1 and the processing cores n) in a multiphase power supply mode, wherein the power supply device 1 and the power supply device n can select a plurality of BUCK circuits to form a multiphase BUCK circuit. When the processing core is in a light load state, the processing core is powered by a single BUCK circuit, and when the processing core is in a heavy load state, the processing core is powered by a plurality of BUCK circuits. However, in this way, each processing core is provided with a multiphase power supply circuit, which results in a large number of power supply units, and increases the wiring area and wiring difficulty of the PCB. The above problems may also occur when the processing cores are respectively disposed in an independent processing device and/or the power supply device is independently disposed, which is not described herein in detail.
In order to solve the above-mentioned problems, as shown in fig. 4, an embodiment of the present application provides an apparatus 300, where the apparatus 300 includes a plurality of first power circuits 321, a plurality of processing cores 311, a switching circuit 330, and a second power circuit 322. Wherein, each first power circuit 321 is connected to one processing core 311 in a one-to-one correspondence. Each first power circuit 321 is connected to one processing core 311; each processing core 311 is connected to the second power supply circuit 322 through the switching circuit 330. Each of the first power supply circuits 321 is configured to output a first voltage to a corresponding one of the processing cores. The second power supply circuit 322 is configured to output a second voltage to at least one processing core when the switching circuit 330 turns on the second power supply circuit 322 and the at least one processing core.
Illustratively, the switching circuit 330 includes a plurality of switches (K1-Kn); each processing core 311 is connected to a second power supply circuit 322 via a switch. Wherein the first processing core is connected with the second power circuit 322 through the switch K1; the second processing core is connected with a second power circuit 322 through a switch K2; the nth processing core is connected to the second power supply circuit 322 through the switch Kn. Each of the first power supply circuits 321 is configured to output a first voltage to the corresponding processing core 311. The second power circuit 322 is configured to output a second voltage to the at least one processing core 311 when the corresponding switch turns on the second power circuit 322 and the at least one processing core 311, and the second voltage is higher than the first voltage; meanwhile, the second voltage can meet the maximum voltage requirement and the transient drop requirement of each processing core.
For example, when a certain processing core needs to run, the corresponding first power circuit 321 may be started to supply power to the processing core, so as to meet the basic power supply requirement of the processing core during running. Then, when the processing core needs to operate in a heavy load state, the second power circuit 322 may be started first, and then the switch is turned on, so that the first power circuit 321 is used to supply power to the processing core, and meanwhile, the second power circuit 322 is used to supply power to the processing core to provide high transient voltage and current. Finally, the switch may be opened when the processing core does not need to operate in a heavy load state.
Based on this, each first power circuit 321 can only guarantee the requirement of the lowest work output capability of the corresponding processing core, so that the requirement on the power supply capability of the first power circuit 321 is reduced, the usage amount of components can be reduced, and the wiring area of a single power circuit on the PCB board is reduced. When the multiple processing cores are required to work in a heavy load state, the corresponding switches can be turned on, and high transient voltage and current are provided for each processing core through the second power circuit 322. In this way, the power supply requirement of a plurality of processing cores in the heavy load state can be met through one second power circuit 322, the usage amount of components is further reduced, and the wiring area can be further reduced; meanwhile, the second power circuit 322 is restarted when the processing core is in a heavy load state, so that the loss of the circuit can be reduced.
In the above embodiment, the control signal of the switch may be generated internally in the apparatus or may be obtained from the outside by providing a communication interface.
In one embodiment, as shown in fig. 4, a plurality of processing cores 311 may be integrated in the system on chip 310, and a plurality of first power circuits 321 and second power circuits 322 may also be integrated in the same power management unit 320. The switching circuit 330 may be integrated with the processing core in the system on chip 310 or may be separately disposed on a PCB board.
It will be appreciated that the processing cores may also be provided in separate processing devices, and are not limited to being integrated into the system-on-chip 310. The second power supply circuit 322 and each of the first power supply circuits 321 may be provided independently, and are not limited to being provided in the same power management unit 320. The specific arrangement of the processing core 311, the first power circuit 321 and the second power circuit 322 may be selected according to practical situations, which is not limited in the implementation of the present application.
In one embodiment, the control signals of the switches may be output by setting the control circuit 312, the control circuit 312 may output control signals to the corresponding switches based on the predicted reload status of at least one processing core, and the switches may be turned on when receiving the control signals, to provide the voltage and current output by the second power circuit 322 to the corresponding processing core. The control circuit 312 may control the switch according to operating parameters such as operating voltage, operating current, operating frequency, and memory bandwidth during the operation of the processing core.
Alternatively, the control circuit 312 may be provided on the system on chip 310 or may be provided separately on a PCB board. In addition, the switches corresponding to the processing cores may be integrated on the system on chip 310 (as shown in fig. 4), or may be independently disposed on the PCB, which is not particularly limited in the embodiment of the present application.
Further, to reduce the use of components and reduce the wiring area, the control circuit 312 may include one of a plurality of processing cores.
In one embodiment, control circuitry 312 may determine a predicted reload status of at least one processing core when an operating parameter of the at least one processing core exceeds a reference threshold. Wherein the operating parameters include at least two of an operating voltage, an operating current, an operating frequency, or a memory bandwidth.
For example, control circuitry 312 may determine a predicted reload state for a processing core when at least two of an operating voltage, an operating current, an operating frequency, and a memory bandwidth of the processing core exceeds corresponding reference thresholds. The reference threshold corresponding to the working voltage, the working current, the working frequency and the memory bandwidth of each processing core may be set according to the boundary value between the light load state and the heavy load state of each processing core, then the parameters fed back by the processing core are compared with the corresponding reference thresholds by using the control circuit 312 when each processing core is operated, when at least two of the working voltage, the working current, the working frequency and the memory bandwidth of a certain processing core exceed the corresponding reference thresholds, the moment when the processing core is in the heavy load state is determined according to the change curve of each parameter, and then the switch corresponding to the processing core is turned on before the moment, and the corresponding processing core is powered by the second power circuit 322.
Optionally, when obtaining the predicted heavy load state of the processing core, a prediction model may be constructed according to the change condition of each parameter in the process that each processing core is switched from the light load state to the heavy load state, then each parameter fed back by the processing core in the running process is input into the prediction model, so as to obtain the predicted heavy load state of the processing core, and the switch corresponding to the processing core is turned on before the corresponding time or the corresponding time of the predicted heavy load state, so that the corresponding processing core is powered through the second power circuit 322. The prediction model can be constructed by using a convolutional neural network. Specifically, the data of each parameter at different moments can be used as input, the corresponding load state is used as output, and the convolutional neural network is used for training to obtain a corresponding prediction model; and then determining the predicted heavy load state of the processing core according to the acquired parameters through the prediction model.
It can be understood that when predicting the load state of the processing cores, considering that each processing core has a corresponding trigger program to control, and each processing core has a corresponding phase-locked loop to provide a clock signal, the load state of the processing cores may also be predicted by data such as a software code, a control frequency of the phase-locked loop, etc., and the number of parameters specifically used may be adjusted according to the correlation between the parameters and the load state of the processing cores.
In one embodiment, the control circuit 312 may activate the second power circuit 322 upon activation of one or more of the plurality of processing cores, thereby preparing the second power circuit 322 in advance to facilitate powering the corresponding processing core through the second power circuit 322 in time after the predicted heavy load state of the processing core is obtained.
Optionally, as shown in fig. 5, the first power circuit 321 connected to each processing core may be a single-phase BUCK circuit, when the second power circuit is connected to a plurality of processing cores, the second power circuit 322 may be configured as a multi-phase BUCK circuit according to the power supply requirement of the processing core, and by adjusting the number of conducting phases of the multi-phase BUCK circuit, the magnitude of the current output by the second power circuit 322 may be adjusted, so as to better meet the requirement of the processing core on the working current in the heavy load state.
It will be appreciated that the number of processing cores connected to each of the second power circuits 322 via the switch may be adjusted according to the number of processing cores having the same power requirements, and the embodiment of the present application is not limited in this regard. The BUCK circuit can also select other voltage converters, and the voltage converters can be used for effectively outputting fixed voltage after inputting voltage. The voltage converter can be a buck-type DC/DC converter or a boost-type DC/DC converter.
In one embodiment, there may be a case where the power supply voltages required by some processing cores are the same in the system on chip 310, but there is a difference in the power supply currents, so the second power supply circuit 322 may be configured as a multiphase step-down chopper circuit, and the control circuit may control the number of on phases of the multiphase step-down chopper circuit according to the current requirement of the corresponding processing core in the heavy load state, so as to adjust the current output by the second power supply circuit 322.
Optionally, when multiple processing cores have different power supply requirements, multiple second power circuits 322 may be provided, where each second power circuit 322 provides the voltage and current required by the heavy load state for the processing core with the same or similar power supply requirements, so as to implement packet power supply, and further reduce the loss of the circuit.
Illustratively, as shown in FIG. 6, assume that system-on-chip 310 includes five processing cores; the first processing core is connected with a first power circuit a; the second processing core is connected with the first power supply circuit b; the third processing core is connected with the first power supply circuit c; the fourth processing core is connected with the first power circuit d; the fifth processing core is connected to the first power supply circuit e. When the power supply requirements of the first processing core and the second processing core in the heavy load state are the same, the first processing core is connected with the second power supply circuit A through the switch K1; the second processing core is connected to the second power supply circuit a through a switch K2. When the power supply requirements of the third processing core and the fourth processing core in the heavy load state are the same, the third processing core is connected with the second power supply circuit B through a switch K3; the fourth processing core is connected to the second power supply circuit B through a switch K4. When the power supply requirements of the fifth processing core and the first processing core to the fourth processing core in the heavy load state are different, the fifth processing core is connected with the second power supply circuit C through the switch K5. The switches K1 to K5 may be controlled by a control signal output from the control circuit 312, or may receive an input control signal through a communication interface.
It will be appreciated that each of the second power circuits 322 in the above embodiments may also use the multi-phase BUCK circuit of fig. 5 according to the actual power requirements of the processing cores, and the number of phases of the BUCK circuit may also be adjusted according to the specific power requirements.
As shown in fig. 7, the embodiment of the present application further provides a power supply control method applied to the above device 300, and the specific flow thereof is as follows.
S710, starting the first power supply circuits, and outputting a first voltage to one processing core corresponding to each first power supply circuit.
The first power supply circuit may also be controlled by the control circuit, where the control circuit may include one of the processing cores, where the processing core is coupled to a memory, and the memory stores computer program instructions, and the processing core may receive a trigger program on the electronic device and call the computer program instructions corresponding to the operation from the memory, so as to start the corresponding first power supply circuit to supply power to the corresponding processing core.
S720, starting a second power supply circuit, and outputting a second voltage to at least one processing core when the switching circuit is conducted with the second power supply circuit and at least one processing core of the plurality of processing cores.
The second power supply circuit can be controlled by the control circuit, and the control circuit can start the second power supply circuit when one or more first power supply circuits are started, so that the second power supply circuit enters a preparation state in advance, at the moment, the switch is not conducted, and no loss exists in the circuit. When at least two of the working voltage, the working current, the working frequency and the memory bandwidth of a certain processing core exceed corresponding reference thresholds, the control circuit determines a predicted reloading state of the processing core, and when the switch is controlled to be on before the predicted reloading state is not reached, namely before the moment corresponding to the actual reloading state is entered, the second power supply circuit outputs a second voltage to the corresponding processing core in advance, and the second voltage is larger than the first voltage so as to meet the power supply requirement of the processing core in the reloading state.
Further, when the processing core is restored to the light load state, the corresponding switch can be disconnected, and the corresponding processing core is powered by the first power supply circuit. For example, when each parameter in the working voltage, the working current, the working frequency and the memory bandwidth of the processing core is lower than the corresponding reference threshold value, it may be determined that the processing core is restored to the light load state; and when only one of the parameters such as the working voltage, the working current, the working frequency and the memory bandwidth of the processing core is higher than the corresponding reference threshold value, the processing core is determined to be restored to the light load state.
It is understood that the parameters used in determining the light load state of the processing core are not limited to the above parameters, and may be adjusted according to the correlation between various parameters and the load state of the processing core. In addition, the time for the processing core to recover to the light load state can also be predicted according to the change trend of each parameter, and then the corresponding switch is turned off according to the predicted time.
In order to facilitate understanding of the power supply control method provided in the embodiment of the present application, the following embodiment describes a corresponding control flow by taking two processing cores connected to the same second power circuit as an example.
As shown in fig. 8, when two processing cores enter a heavy load state at different timings, control timings corresponding to the two processing cores at a certain period of time are as follows:
At the time of T1, a first power circuit corresponding to the first processing core is started to supply power for the first processing core. At this time, the first processing core is in a light load state, the working voltage is 0.65V, and the working current is 0.5A; the second power supply circuit is simultaneously activated.
At time T2, switch K1 is turned on. The time T2 is determined by a predicted overload state determined by parameters such as working voltage, working current, working frequency, memory bandwidth and the like of the processing core; the time T2 can be earlier than the time corresponding to the predicted heavy load state, so that high transient voltage and current can be provided for the processing core in advance before the processing core enters the heavy load state, and the power supply requirement of the processing core can be met more timely, wherein the interval time between the time T2 and the time corresponding to the predicted heavy load state can be set according to the actual requirement.
At time T3, the first processing core is in a predicted reload state, and the operating voltage of the first processing core is switched to 0.8V, and the operating current becomes 9A.
At the time T4, the first processing core is restored to a light load state, the working voltage of the first processing core is 0.65V, the working current is 0.5A, and the K1 is closed after a period of time delay.
At time T5, the first power circuit corresponding to the second processing core is started to supply power to the second processing core, the second processing core is in a light-load state, at the moment, the working voltage of the second processing core is 0.6V, and the working current is 0.5A.
At time T6, switch K1 is turned on. The time T6 is determined by a predicted reload state determined by parameters such as a working voltage, a working current, a working frequency, a memory bandwidth and the like of the first processing core, and the time T6 is earlier than a time corresponding to the predicted reload state, and the specific time can be set according to actual requirements.
At time T7, the first processing core is in the predicted reload state, and the operating voltage of the first processing core is switched to 0.8V, and the operating current becomes 9A.
At time T8, switch K2 is turned on. The time T8 is determined by a predicted reload state determined by parameters such as a working voltage, a working current, a working frequency, a memory bandwidth and the like of the second processing core, and the time T8 is earlier than a time corresponding to the predicted reload state, and the specific time can be set according to actual requirements.
At time T9, the second processing core is in the predicted reload state, and the operating voltage of the second processing core is switched to 0.8V, and the operating current becomes 8A.
At the time T10, the first processing core is restored to a light load state, the working voltage of the first processing core is 0.65V, the working current is 0.5A, and the K1 is closed after a period of time delay.
At the time T11, the second processing core is restored to a light load state, the working voltage of the second processing core is 0.6V, the working current is 0.5A, and the K2 is closed after a period of time delay.
At the time of T12, the first power circuit corresponding to the first processing core is closed, and the first processing core stops running.
At the moment T13, the second power circuit is turned off, and the second processing core stops running; at this time, the first power circuit corresponding to the second processing core is turned off.
As shown in fig. 9, when two processing cores connected to the same second power supply circuit enter a heavy load state at the same timing, control timings corresponding to a certain period of time by the two processing cores are as follows:
At time T1, a first power circuit corresponding to the first processing core is started to supply power to the first processing core, and a first power circuit corresponding to the second processing core is started to supply power to the second processing core.
At this time, the first processing core and the second processing core are both in a light load state; the working voltage of the first processing core is 0.65V, and the working current is 0.5A; the operating voltage of the first processing core was 0.6V and the operating current was 0.5A.
At the time T2, the switches K1 and K2 are turned on; the time T2 is determined by a predicted overload state determined by parameters such as working voltage, working current, working frequency, memory bandwidth and the like of the processing core; the time T2 can be earlier than the time corresponding to the predicted heavy load state, so that high transient voltage and current can be provided for the processing core in advance before the processing core enters the heavy load state, and the power supply requirement of the processing core can be met more timely, wherein the interval time between the time T2 and the time corresponding to the predicted heavy load state can be set according to the actual requirement.
At the time T3, the first processing core and the second processing core are both in a predicted heavy load state, at the moment, the working voltage of the first processing core is switched to 0.8V, and the working current is changed to 9A; the operating voltage of the second processing core was switched to 0.8V and the operating current was changed to 9A.
Optionally, when the working voltages of the first processing core and the second processing core are the same, and the working currents are very close (for example, the working current of the first processing core is 9A, the working current of the second processing core is 8A), the second power supply circuit may be set to be a multiphase step-down chopper circuit, and then the output current of the second power supply circuit is adjusted to be a larger one by controlling the conduction phase number of the multiphase step-down chopper circuit, and at this time, although the processing core with a small working current has a loss, the loss is very small, and the overall power consumption of the circuit can be reduced.
It will be appreciated that when the operating voltages and operating currents of the plurality of processing cores are relatively close, the same second power supply circuit may also be used to supply power, thereby reducing the wiring area.
At the time T4, the first processing core and the second processing core are both restored to a light-load state, the working voltage of the first processing core is 0.65V, the working current is 0.5A, the working voltage of the first processing core is 0.6V, the working current is 0.5A, and K1 and K2 are closed after a period of time delay.
At the time T5, closing a first power circuit corresponding to the first processing core and the second processing core, and stopping the operation of the first processing core and the second processing core; while the second power supply circuit is turned off.
It should be understood that the working current and the working voltage of each processing core are merely reference values provided for the sake of understanding the embodiments of the present application in the examples, and the actual working voltage and the working current of the processing core in the light load state and the heavy load state are used in actual operation.
When the second power supply circuit is connected with one processing core, the power supply time sequence of the first power supply circuit and the second power supply circuit can be controlled by referring to the control mode of the first processing core. When the second power circuit is connected to three or more processing cores, the power supply timing of the processing cores can be controlled by referring to the control manner of fig. 8 or fig. 9, which is not described herein.
Further, it is considered that the time when the processing core enters the reload state has randomness in actual running. The control sequences described above are thus only a few exemplary embodiments of the present application, and the specific power supply sequence of the processing core is determined by the time corresponding to the predicted heavy load state of the processing core.
In one implementation, the present embodiments also provide a computer-readable storage medium having computer program instructions stored therein; the computer program instructions, when run on a computer, may implement the power supply control method described above. The above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, or the like.
In one embodiment, the present embodiments also provide a computer program product that, when run on a computer, implements the power control method described above.
In one embodiment, the present examples also provide a controller that, when running a computer program, can implement the method of any of the above embodiments. Wherein a processing core may be selected as the controller.
In an embodiment, the present example also provides a control device comprising a controller and a memory, wherein the memory is for storing a computer program, which when run by the controller, implements the method of any of the above embodiments.
The memory mentioned in the above embodiments may be volatile memory or nonvolatile memory, or may include both volatile and nonvolatile memory. The nonvolatile memory may be a read-only memory (ROM), a Programmable ROM (PROM), an erasable programmable ROM (erasable PROM), an electrically erasable programmable EPROM (EEPROM), or a flash memory. The volatile memory may be random access memory (random access memory, RAM) which acts as external cache memory. By way of example, and not limitation, many forms of RAM are available, such as static random access memory (STATIC RAM, SRAM), dynamic random access memory (DYNAMIC RAM, DRAM), synchronous Dynamic Random Access Memory (SDRAM), double data rate synchronous dynamic random access memory (double DATA RATESDRAM, DDR SDRAM), enhanced synchronous dynamic random access memory (ENHANCED SDRAM, ESDRAM), synchronous link dynamic random access memory (SYNCHLINK DRAM, SLDRAM), and direct memory bus random access memory (directrambus RAM, DR RAM). It should be noted that the memory of the systems and methods described herein is intended to comprise, without being limited to, these and any other suitable types of memory.
The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (15)
1. An apparatus, comprising:
A plurality of first power supply circuits, a plurality of processing cores, a switching circuit, and a second power supply circuit; each of the plurality of first power circuits is connected to one of the plurality of processing cores; each processing core is connected with the second power supply circuit through the switching circuit;
each first power supply circuit is used for outputting a first voltage to the corresponding processing core;
The second power supply circuit is configured to output a second voltage to at least one processing core of the plurality of processing cores when the switching circuit turns on the second power supply circuit and the at least one processing core, and the second voltage is higher than the first voltage.
2. The apparatus as recited in claim 1, further comprising:
a control circuit coupled to the plurality of processing cores and the switching circuit for outputting a control signal to the switching circuit based on a predicted reload state of the at least one processing core;
the switching circuit is used for responding to the control signal and conducting the second power supply circuit and the at least one processing core.
3. The apparatus of claim 2, wherein the device comprises a plurality of sensors,
The control circuit is configured to determine a predicted reload state of the at least one processing core when an operating parameter of the at least one processing core exceeds a reference threshold, where the operating parameter includes at least two of an operating voltage, an operating current, an operating frequency, or a memory bandwidth.
4. A device according to claim 2 or 3, wherein,
The control circuit is specifically configured to output the control signal to the switching circuit before the at least one processing core is in an actual reload state.
5. The apparatus of any one of claims 2 to 4, wherein,
The control circuit is also connected with the second power supply circuit;
The control circuit is further configured to start the second power supply circuit when one or more of the plurality of processing cores is started.
6. The apparatus of claim 5, wherein the device comprises a plurality of sensors,
The control circuit includes a processing core.
7. The device according to any one of claims 1 to 6, wherein,
The second power supply circuit is a step-down chopper circuit.
8. A power supply control method for powering a device comprising a plurality of first power supply circuits, a plurality of processing cores, a switching circuit, and a second power supply circuit; each of the plurality of first power circuits is connected to one of the plurality of processing cores; each processing core is connected to the second power supply circuit through the switching circuit, the method comprising:
Starting the first power supply circuits, and outputting a first voltage to the processing core corresponding to each first power supply circuit;
Starting the second power supply circuit, and outputting a second voltage to at least one processing core of the plurality of processing cores when the switching circuit turns on the second power supply circuit and the at least one processing core; wherein the second voltage is higher than the first voltage.
9. The method as recited in claim 8, further comprising:
and outputting a control signal to the switching circuit based on the predicted reload state of the at least one processing core, and switching on the second power supply circuit and the at least one processing core.
10. The method of claim 9, wherein the step of determining the position of the substrate comprises,
And determining a predicted reload state of the at least one processing core when an operating parameter of the at least one processing core exceeds a reference threshold, the operating parameter including at least two of an operating voltage, an operating current, an operating frequency, or a memory bandwidth.
11. The method according to claim 9 or 10, wherein,
The control signal is output to the switching circuit before the processing core is in an actual reload state.
12. The method according to any one of claims 8 to 11, wherein,
The second power circuit is enabled when one or more of the plurality of processing cores is enabled.
13. The method according to any one of claims 8 to 12, wherein,
The second power supply circuit is a multiphase step-down chopper circuit;
The method further comprises the steps of:
and determining the number of conducting phases of the multiphase step-down chopper circuit based on the working current of the processing core in the actual heavy load state.
14. A computer readable storage medium having stored thereon computer program instructions; computer program instructions for performing the method of any of claims 8-13 when run on a computer.
15. An electronic device comprising the apparatus of any one of claims 1-7.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211430894.9A CN118054662A (en) | 2022-11-15 | 2022-11-15 | Device, power supply control method, storage medium and electronic equipment |
| PCT/CN2023/102922 WO2024103735A1 (en) | 2022-11-15 | 2023-06-27 | Apparatus, power supply control method, storage medium, and electronic device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202211430894.9A CN118054662A (en) | 2022-11-15 | 2022-11-15 | Device, power supply control method, storage medium and electronic equipment |
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| CN118054662A true CN118054662A (en) | 2024-05-17 |
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| CN202211430894.9A Pending CN118054662A (en) | 2022-11-15 | 2022-11-15 | Device, power supply control method, storage medium and electronic equipment |
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| WO (1) | WO2024103735A1 (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8261102B2 (en) * | 2008-04-28 | 2012-09-04 | Delta Electronics, Inc. | Power management system capable of saving power and optimizing operating efficiency of power supplies for providing power with back-up or redundancy to plural loads |
| CN103869924B (en) * | 2012-12-10 | 2017-05-17 | 宏碁股份有限公司 | Electric power supply device |
| CN206060348U (en) * | 2016-09-09 | 2017-03-29 | 北京集创北方科技股份有限公司 | Power supply switch circuit |
| US10432007B2 (en) * | 2017-05-03 | 2019-10-01 | Dell Products L.P. | Circuits, systems and methods for balancing power for system load components |
| CN113778211A (en) * | 2021-08-24 | 2021-12-10 | 联想(北京)有限公司 | Control method and device of power supply circuit and electronic equipment |
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- 2022-11-15 CN CN202211430894.9A patent/CN118054662A/en active Pending
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