CN118053846A - Integrated circuit comprising an array of cells and a backside power rail - Google Patents

Abstract

An integrated circuit including an array of cells and a backside power rail is disclosed. The integrated circuit includes: a cell array including a plurality of cells, each cell including a transistor; a power rail in a power rail layer under the cell array, the power rail providing power to the cell array; and a plurality of contacts between the cell array and the power rail. Each contact extends from the source of the transistor of a respective one of the plurality of cells down to the power rail.

Description

Integrated circuit comprising an array of cells and a backside power rail

The present application claims priority from korean patent application No. 10-2022-0154879 and korean patent application No. 10-2023-0003035, filed in the korean intellectual property office on day 11, month 17 and day 1, month 9 of 2022, respectively, the disclosures of each of which are incorporated herein by reference in their entirety.

Technical Field

The present disclosure relates to Integrated Circuits (ICs), and more particularly, to ICs including an array of cells and a backside power rail.

Background

Due to the demand for high integration density and the development of semiconductor processes, the width, spacing, and/or height between wirings (wires) included in an IC can be reduced, and thus, the influence of parasitic elements of the wirings can be increased. In addition, in order to reduce power consumption and increase operation speed, the power supply voltage of the IC may be reduced, and thus, the influence of parasitic elements of wiring on the IC may be further increased. Although parasitic elements exist, an IC including a cell array including cells having the same structure may be required to stably provide high integration density and performance according to requirements of various applications.

Disclosure of Invention

One aspect is to provide an Integrated Circuit (IC) including an array of cells configured to receive power through a backside power rail.

According to an aspect of one or more embodiments, there is provided an integrated circuit comprising: a cell array including a plurality of cells, each of the plurality of cells including at least one transistor; a power rail in a power layer below the cell array, the power rail configured to provide power to the cell array; and a plurality of contacts between the array of cells and the power rail, wherein each of the plurality of contacts extends from a source of a transistor of a respective one of the plurality of cells down to the power rail.

According to another aspect of one or more embodiments, there is provided an integrated circuit comprising: a cell array including a plurality of cells, each of the plurality of cells including at least one transistor; a power rail in a power rail layer below the cell array, the power rail configured to provide power to the cell array; and a plurality of contacts between the cell array and the power rail, wherein each of the plurality of contacts has a top surface connected to a source of a transistor of a corresponding one of the plurality of cells and a bottom surface connected to the power rail.

According to yet another aspect of one or more embodiments, there is provided an integrated circuit comprising: a cell array including a plurality of cells, each cell including two inverters cross-coupled to each other; a power rail in a power rail layer below the cell array; and a plurality of contacts between the cell array and the power rail, wherein each of the plurality of contacts extends from a source of a transistor of a respective one of the two inverters down to the power rail.

Drawings

The various embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which:

FIGS. 1A and 1B are layout diagrams of an Integrated Circuit (IC) according to some embodiments;

Fig. 2A-2D are diagrams of examples of devices according to some embodiments;

FIG. 3 is a block diagram of an IC according to some embodiments;

FIG. 4 is a circuit diagram of a memory cell according to some embodiments;

fig. 5A and 5B are plan views showing a layout of an IC according to some embodiments;

fig. 6A-6C are plan views showing a layout of an IC according to some embodiments;

fig. 7A-7D are plan views of examples of backside power rails according to some embodiments;

Fig. 8A and 8B are diagrams of examples of layouts of ICs according to some embodiments; and

Fig. 9 is a block diagram of a system on a chip (SoC) in accordance with some embodiments.

Detailed Description

Fig. 1A and 1B are layout diagrams of an Integrated Circuit (IC) according to some embodiments. Fig. 1A and 1B show both a plan view of an IC and a sectional view of the IC taken along line X1-X1'.

As used herein, the X-axis direction and the Y-axis direction may be referred to as a first horizontal direction and a second horizontal direction, respectively, and the Z-axis direction may be referred to as a vertical direction or a third direction. The plane formed by the X-axis and the Y-axis may be referred to as a horizontal plane. A component that is located in the +z direction relative to another component may be referred to as being above the other component, and a component that is located in the-Z direction relative to the other component may be referred to as being below the other component. The area of the component may refer to the dimension occupied by the component in a plane parallel to the horizontal plane, and the width of the component may refer to the length of the component in a direction orthogonal to the direction in which the component extends. The surface exposed in the +z direction may be referred to as a top surface, the surface exposed in the-Z direction may be referred to as a bottom surface, and the surface exposed in the ±x direction or the ±y direction may be referred to as a side surface. In the drawings, only some layers may be shown for clarity, although a via (via) configured to connect a top pattern to a bottom pattern is below the top pattern, the via may be shown for clarity. In addition, a pattern including a conductive material (e.g., a pattern of a wiring layer) may be referred to as a conductive pattern, or may be simply referred to as a pattern.

The IC may include a power supply line configured to provide a positive or negative supply voltage to a device (e.g., a transistor). For example, as shown in fig. 1A, the first power supply line PL1 may supply a positive power supply voltage to a p-channel field effect transistor (PFET) formed in a PFET region and extend in a Y-axis direction, and the second power supply line PL2 may supply a negative power supply voltage to an n-channel FET (NFET) formed in an NFET region and extend in the Y-axis direction. The power line may include a conductive material. The power cord may be collectively referred to as a power rail. As used herein, the layer at which the power line is formed may be referred to as a power line layer or a power rail layer.

In some embodiments, the IC may include a power line extending below the transistor, and the transistor may be formed above the power line layer. For example, as shown in fig. 1A and 1B, the IC may include a backside power rail (BSPR). Unlike the configuration shown in fig. 1A and 1B, in a configuration in which a power line extends over a transistor, the power line may consume line (routing) space for signals, and thus, line congestion may occur. On the other hand, the line space for signals may be increased due to BSPR, and thus, the IC may have a reduced area and/or an efficient structure. As used herein, BSPR may be referred to simply as a power rail.

Referring to fig. 1a, the ic 10a may include PFET and NFET regions extending in the Y-axis direction and a gate extending in the X-axis direction. Source/drains may be formed on both sides of the gate, and contacts may be formed on the source/drains. A channel may be formed between the source/drain under the gate. Examples of the channel will be described below with reference to fig. 2A to 2D. The first power line PL1 may extend in the Y-axis direction under the PFET region, and the second power line PL2 may extend in the Y-axis direction under the NFET region. In some embodiments, a positive power supply voltage may be applied to the first power supply line PL1, and a negative power supply voltage may be applied to the second power supply line PL2. A backside interlayer dielectric (BILD) may be between the first power line PL1 and the second power line PL2.

IC 10a may include vias connected to the pattern of power lines and routing layers. For example, as shown in fig. 1A, a first through silicon via (TSV, also referred to as a through silicon via) TV1 may have a bottom surface connected to the first power line PL1 and a top surface connected to the first pattern M11 of the M1 layer. The second TSV TV2 may have a bottom surface connected to the second power line PL2 and a top surface connected to the second pattern M12 of the M1 layer.

The first pattern M11 of the M1 layer may be connected to the first source/drain electrode SD1 through the first via V01 and the first contact CT 1. When a positive power supply voltage is applied to the first power supply line PL1, the first source/drain SD1 may be a source of the PFET. The positive power supply voltage may be supplied from the first power supply line PL1 to the first source/drain SD1 through the first TSV TV1, the first pattern M11, the first via V01, and the first contact CT 1. The second pattern M12 of the M1 layer may be connected to the second source/drain electrode SD2 through the second via hole V02 and the second contact CT 2. When a negative supply voltage is applied to the second supply line PL2, the second source/drain SD2 may be the source of the NFET. The negative power supply voltage may be supplied from the second power supply line PL2 to the second source/drain SD2 through the second TSV TV2, the second pattern M12, the second via V02, and the second contact CT 2.

Referring to fig. 1b, the ic 10b may include PFET and NFET regions extending in the Y-axis direction and a gate extending in the X-axis direction. Source/drains may be formed on both sides of the gate, and contacts may be formed on the source/drains. A channel may be formed between the source/drain under the gate. Examples of the channel will be described below with reference to fig. 2A to 2D. The first power line PL1 may extend in the Y-axis direction under the PFET region, and the second power line PL2 may extend in the Y-axis direction under the NFET region. In some embodiments, a positive power supply voltage may be applied to the first power supply line PL1, and a negative power supply voltage may be applied to the second power supply line PL2.BILD may be between first power supply line PL1 and second power supply line PL2.

IC 10b may include contacts connected to power lines and source/drain. For example, as shown in fig. 1B, the first back side contact (BC) BC1 may have a bottom surface connected to the first power line PL1 and a top surface connected to the first source/drain SD 1. The second BC2 may have a bottom surface connected to the second power line PL2 and a top surface connected to the second source/drain SD 2. As used herein, as with the first BC1 and the second BC2, contacts configured to connect the source/drain to the backside power supply line may be referred to as Direct Backside Contacts (DBCs).

When the positive power supply voltage is applied to the first power supply line PL1, the first source/drain SD1 may be a source of PFET, and the positive power supply voltage may be supplied from the first power supply line PL1 to the first source/drain SD1 through the first BC 1. The positive power supply voltage may be supplied to the first source/drain SD1 through a path shorter than that in the IC 10a of fig. 1A, and thus, a low voltage drop (or IR drop) may occur. When a negative supply voltage is applied to the second supply line PL2, the second source/drain SD2 may be a source of an NFET, and the negative supply voltage may be supplied from the second supply line PL2 to the second source/drain SD2 through the second BC 2. The negative power supply voltage may be supplied to the second source/drain SD2 through a path shorter than that in the IC 10a of fig. 1A, and thus, a low IR drop may occur.

In some embodiments, the BSPR may be used to supply power to a cell array in which a plurality of cells having the same structure are arranged. For example, the cell array may be a pixel array of a display panel, a pixel array of an image sensor, and/or a memory cell array of a memory device. Accordingly, power can be supplied to the cells of the cell array through the shortened path, and the IC can have high operation reliability. In some embodiments, the pattern for the power supply line may be removed from the wiring layer. As a result, parasitic components of the signal path can be reduced, and thus, the IC can have a high operation speed. Furthermore, due to the line space ensured by the BSPR, signals may be efficiently line-transferred (routed), and the IC may have a reduced area and/or an efficient structure. Although the memory cell array is described below as an example of a cell array, it should be noted that the embodiments are applicable to other cell arrays.

Fig. 2A-2D are diagrams of examples of devices according to some embodiments. For example, fig. 2A shows a fin field effect transistor (FiNFET) 20a, fig. 2B shows a Gate All Around Field Effect Transistor (GAAFET) 20B, fig. 2C shows a multi-bridge channel field effect transistor (MBCFET) 20C, and fig. 2D shows a Vertical Field Effect Transistor (VFET) 20D. For simplicity and ease of explanation, fig. 2A-2C each show a state in which one of the two source/drain regions is removed, and fig. 2D shows a cross-section of the VFET 20D taken along a plane parallel to the plane formed by the X-axis and the Z-axis and passing through the channel CH of the VFET 20D.

Referring to fig. 2a, finfet 20a may be formed of a fin-type active pattern extending in a Y-axis direction between Shallow Trench Isolations (STI) and a gate G extending in an X-axis direction. The source/drain regions S/D may be formed at both sides of the gate electrode G, and thus, the source and drain electrodes may be separated from each other in the Y-axis direction with the gate electrode G therebetween. An insulating film may be formed between the channel CH and the gate G. In some embodiments, fiNFET a may be formed of the gate G and a plurality of active patterns separated from each other in the X-axis direction.

Referring to fig. 2b, the gaafet 20b may be formed of an active pattern (i.e., nanowire) and a gate G, the active pattern (i.e., nanowire) being separated from each other in the Z-axis direction and extending in the Y-axis direction, the gate G extending in the X-axis direction. The source/drain regions S/D may be formed on both sides of the gate electrode G, and thus, the source and drain electrodes may be separated from each other in the Y-axis direction with the gate electrode G therebetween. An insulating film may be formed between the channel CH and the gate G. In some embodiments, the channel CH may include a plurality of nanowires. It should be noted, however, that the number of nanowires in GAAFET B is not limited to the three shown in fig. 2B.

Referring to fig. 2c, the mbcfet 20c may be formed of an active pattern (i.e., a nano-sheet) and a gate G, the active pattern (i.e., the nano-sheet) being separated from each other in the Z-axis direction and extending in the Y-axis direction, the gate G extending in the X-axis direction. The source/drain regions S/D may be formed on both sides of the gate electrode G, and thus, the source and drain electrodes may be separated from each other in the Y-axis direction. An insulating film may be formed between the channel CH and the gate G. In some embodiments, the channel may include a plurality of nanoplates. It should be noted, however, that the number of nanoplatelets in MBCFET C is not limited to the three shown in fig. 2C.

Referring to fig. 2D, the vfet 20D may include a top source/drain region t_s/D and a bottom source/drain region b_s/D, which are separated from each other in the Z-axis direction, with a channel CH between the top source/drain region t_s/D and the bottom source/drain region b_s/D. The VFET 20D may include a gate G between a top source/drain region t_s/D and a bottom source/drain region b_s/D, the gate G surrounding a channel CH between the top source/drain region t_s/D and the bottom source/drain region b_s/D. An insulating film may be formed between the channel CH and the gate G.

Although an IC including FiNFET a or MBCFET c is mainly described below, it is noted that elements included in the IC are not limited to the examples shown in fig. 2A to 2D. For example, in some embodiments, the IC may include a fork FET (fork FET) having the following structure: the N-type transistor and the P-type transistor are formed relatively tightly to each other by separating the nano-sheets of the P-type transistor from the nano-sheets of the N-type transistor by a dielectric wall. In some embodiments, the IC may include not only FETs, such as Complementary FETs (CFETs), negative Capacitance FETs (NCFETs), and Carbon Nanotube (CNT) FETs, but also bipolar junction transistors.

Fig. 3 is a block diagram of an IC according to some embodiments. For example, the block diagram of fig. 3 shows a memory device 30 included in an IC. In some embodiments, memory device 30 may store data based on commands and addresses provided from outside of the IC, and memory device 30 may be a stand-alone memory device. In some embodiments, as described below with reference to fig. 9, the IC may also include other components configured to write data to the memory device 30 or read data from the memory device 30, and the memory device 30 may be an embedded memory device. As shown in fig. 3, the memory device 30 may include a cell array 32, a row driver 34, a column driver 36, and control logic 38. Although not shown in fig. 3, in some embodiments, memory device 30 may also include address buffers, data input/output (I/O) circuitry, and an internal voltage generator.

The memory device 30 may receive the command CMD, the address, and the data DAT. For example, the memory device 30 may receive a command CMD, an address, and data DAT indicating a write operation, and store the received data DAT in an area of the cell array 32 corresponding to the address. The memory device 30 may receive a command CMD and an address indicating a read operation, and output data stored in an area of the cell array 32 corresponding to the address to the outside.

The cell array 32 may include a plurality of memory cells, each of which is accessed through a word line and a bit line. In some embodiments, the memory cells included in the cell array 32 may be volatile memory cells (such as Static Random Access Memory (SRAM) cells and Dynamic RAM (DRAM) cells). In some embodiments, the memory cells included in the cell array 32 may be nonvolatile memory cells (such as flash memory cells and Resistive RAM (RRAM) cells). Although embodiments are described primarily with reference to SRAM cells as described below with reference to fig. 4, it should be noted that embodiments are not limited thereto. As used herein, a memory cell may be referred to simply as a cell.

The row driver 34 may be connected to the cell array 32 through a plurality of word lines WL. The ROW driver 34 may enable one of the plurality of word lines WL based on the ROW address a_row. Thus, among the memory cells included in the cell array 32, the memory cells connected to the activated word line (i.e., the memory cells in the row corresponding to the activated word line) may be selected. By the column driver 36, which will be described below, data DAT can be written to a selected memory cell during a write operation, and data DAT can be read from the selected memory cell during a read operation.

The column driver 36 may be connected to the cell array 32 through a plurality of bit lines BL. During a read operation, column driver 36 may detect the current and/or voltage received through the plurality of bit lines BL, identify the value stored in the selected memory cell connected to the activated word line, and output data DAT based on the identified value. During a write operation, column driver 36 may apply current and/or voltage to the plurality of bit lines BL based on data DAT and write a value to the selected memory cell connected to the activated word line.

The control logic 38 may receive the command CMD and generate a first control signal CTR1 and a second control signal CTR2. For example, the control logic 38 may identify the read command by decoding the command CMD, and generate the first control signal CTR1 and the second control signal CTR2 to read the data DAT from the cell array 32. The control logic 38 may identify the write command by decoding the command CMD, and generate the first control signal CTR1 and the second control signal CTR2 to write the data DAT to the cell array 32. In some embodiments, the row driver 34 may activate or deactivate the word line at a point in time determined based on the first control signal CTR 1. In some embodiments, the column driver 36 may sense current and/or voltage from or apply current and/or voltage to the plurality of bit lines BL at a point in time determined based on the second control signal CTR2.

In some embodiments, the memory device 30 may include a BSPR under the cell array 32, and the memory cells included in the cell array 32 may receive power from the BSPR. Accordingly, power can be supplied to the memory cells of the cell array 32 through the shortened path, and the memory device 30 can have high operation reliability. In some embodiments, the pattern for the power line may be removed from the wiring layer. Accordingly, parasitic components of the signal path may be reduced, and thus, the memory device 30 may have a high operating speed. Due to the line resources ensured by the BSPR, signals may be efficiently line transferred and the memory device 30 may have a reduced area and/or an efficient structure.

Fig. 4 is a circuit diagram of a memory cell according to some embodiments. For example, the circuit diagram of fig. 4 shows an equivalent circuit 40 corresponding to four memory cells C11, C12, C21, and C22 adjacent to each other in the cell array 32 of fig. 3. As shown in fig. 4, each of the memory cells C11, C12, C21, and C22 may have the same structure.

Referring to fig. 4, memory cells C11 and C12 in the same row may be commonly connected to a word line WL [ k ], and memory cells C21 and C22 in the same row may be commonly connected to a word line WL [ k+1] (k is an integer greater than 0). Memory cell C11 and memory cell C21 in the same column may be connected to first bit line BL1 and first complementary bit line BLB1, and memory cell C12 and memory cell C22 in the same column may be connected to second bit line BL2 and second complementary bit line BLB2.

Referring to fig. 4, the memory cell C11 may include a first PFET P11, a second PFET P12, and first, second, third, and fourth NFETs N11, N12, N13, and N14, and is referred to as a six-transistor (6T) SRAM cell. The memory cell C11 may include a pair of inverters cross-coupled between a node to which the positive power supply voltage VDD is applied and a node to which the negative power supply voltage (or ground potential) VSS is applied. In some embodiments, the memory cell C11 may include two inverters that are cross-coupled between a node to which the positive power supply voltage VDD is applied and a node to which the negative power supply voltage (or ground potential) VSS is applied. For example, among a pair of cross-coupled inverters, a first inverter may include a first PFET P11 and a first NFET N11, and a second inverter may include a second PFET P12 and a second NFET N12. The third and fourth NFETs N13 and N14 may be referred to as pass transistors (pass transistors) configured to connect the first and second inverters to the first bit line BL1 and the first complementary bit line BLB1, respectively, through the word line WL [ k ] that is activated (e.g., has a high level voltage).

The memory cell C12 may include a first PFET P21, a second PFET P22, and a first NFET N21, a second NFET N22, a third NFET N23, and a fourth NFET N24, and is referred to as a 6T SRAM cell. The memory cell C21 may include a pair of inverters cross-coupled between a node to which the positive power supply voltage VDD is applied and a node to which the negative power supply voltage (or ground potential) VSS is applied. In some embodiments, memory cell C21 may include two inverters that are cross-coupled between a node to which positive supply voltage VDD is applied and a node to which negative supply voltage (or ground potential) VSS is applied. For example, among a pair of cross-coupled inverters, a first inverter may include a first PFET P21 and a first NFET N21, and a second inverter may include a second PFET P22 and a second NFET N22. The third and fourth NFETs N23 and N24 may be referred to as channel transistors configured to connect the first and second inverters to the second bit line BL2 and the second complementary bit line BLB2, respectively, through the word line WL [ k ] that is activated (e.g., has a high level voltage).

The memory cell C21 may include a first PFET P31, a second PFET P32, and a first NFET N31, a second NFET N32, a third NFET N33, and a fourth NFET N34, and is referred to as a 6T SRAM cell. The memory cell C21 may include a pair of inverters cross-coupled between a node to which the positive power supply voltage VDD is applied and a node to which the negative power supply voltage (or ground potential) VSS is applied. In some embodiments, memory cell C21 may include two inverters that are cross-coupled between a node to which positive supply voltage VDD is applied and a node to which negative supply voltage (or ground potential) VSS is applied. For example, among a pair of cross-coupled inverters, a first inverter may include a first PFET P31 and a first NFET N31, and a second inverter may include a second PFET P32 and a second NFET N32. The third and fourth NFETs N33 and N34 may be referred to as channel transistors configured to connect the first and second inverters to the first bit line BL1 and the first complementary bit line BLB1, respectively, through the word line WL [ k+1] that is activated (e.g., has a high level voltage).

The memory cell C22 may include a first PFET P41, a second PFET P42, and a first NFET N41, a second NFET N42, a third NFET N43, and a fourth NFET N44, and is referred to as a 6T SRAM cell. The memory cell C41 may include a pair of inverters cross-coupled between a node to which the positive power supply voltage VDD is applied and a node to which the negative power supply voltage (or ground potential) VSS is applied. In some embodiments, memory cell C41 may include two inverters that are cross-coupled between a node to which positive supply voltage VDD is applied and a node to which negative supply voltage (or ground potential) VSS is applied. For example, among a pair of cross-coupled inverters, a first inverter may include a first PFET P41 and a first NFET N41, and a second inverter may include a second PFET P42 and a second NFET N42. The third and fourth NFETs N43 and N44 may be referred to as channel transistors configured to connect the first and second inverters to the second bit line BL2 and the second complementary bit line BLB2, respectively, through the word line WL [ k+1] that is activated (e.g., has a high level voltage).

When IR drop occurs at the node to which the positive power supply voltage VDD is applied or at the node to which the negative power supply voltage VSS is applied, the memory cell C11 may not properly output signals corresponding to the values latched in the pair of cross-coupled inverters to the first bit line BL1 and the first complementary bit line BLB1, and may not properly latch values corresponding to the signals applied to the first bit line BL1 and the first complementary bit line BLB1 to the pair of cross-coupled inverters. As the number of memory cells in a row increases, the word line may extend and the effect of parasitic resistance of the word line may increase. Thus, memory cells remote from the row driver 34 of FIG. 3 may recognize the activation of the word line at a delay time point, and the operating speed of the memory device 30 of FIG. 3 may be limited.

Fig. 5A and 5B are plan views illustrating a layout of an IC according to some embodiments. For example, the plan views of fig. 5A and 5B show a layout 50 including memory cells C11', C12', C21', and C22' corresponding to the four memory cells C11, C12, C21, and C22, respectively, included in the equivalent circuit 40 of fig. 4. The plan view of fig. 5A shows the cell array in the layout 50, and the plan view of fig. 5B shows the power supply rail disposed under the cell array and the TSVs disposed under the power supply rail in the layout 50. In fig. 5A and 5B, the names written on the patterns represent lines electrically connected to the patterns and/or voltages applied to the patterns. The illustration of the source/drain is omitted in fig. 5A for simplicity. Note that the equivalent circuit 40 of fig. 4 is not limited to the layout 50 shown in fig. 5A and 5B.

Referring to fig. 5A, each of the four memory cells C11', C12', C21', and C22' may have the same occupied space (footprint). That is, each of the four memory cells C11', C12', C21', and C22' may have the same area, the same horizontal length, and the same vertical length. Memory cell C11 'and memory cell C12' in the same row may be commonly connected to word line WL [ k ]. Memory cell C21 'and memory cell C22' in the same row may be commonly connected to word line WL [ k+1]. The memory cells C11 'and C21' in the same column may be commonly connected to the first bit line BL1 and the first complementary bit line BLB1. The memory cells C12 'and C22' in the same column may be commonly connected to the second bit line BL2 and the second complementary bit line BLB2.

The memory cell C11' may include NFET regions and PFET regions extending in the Y-axis direction. For example, as shown in fig. 5A, the NFET regions may extend in the Y-axis direction between the PFET regions, which extend in the Y-axis direction in the memory cell C11'. The memory cell C11' may include a gate electrode extending in the X-axis direction. The gate electrode may form NFETs (i.e., the first to fourth NFETs N11 to N14 of fig. 4) in the NFET region and PFETs (i.e., the first and second PFETs P11 and P12 of fig. 4) in the PFET region. Source/drains may be formed on both sides of the gate electrode, and the source/drains may be connected to the pattern of the M1 layer through contacts (referred to as source/drain contacts) and vias. The gate electrode may be connected to the pattern of the M1 layer through a contact (referred to as a gate contact) and a via.

The memory cell C12' may include NFET and PFET regions extending in the Y-axis direction. For example, as shown in fig. 5A, the NFET regions may extend in the Y-axis direction between the PFET regions, which extend in the Y-axis direction in the memory cell C12'. The memory cell C12' may include a gate electrode extending in the X-axis direction. The gate electrode may form NFETs (i.e., the first to fourth NFETs N21 to N24 of fig. 4) in the NFET region and PFETs (i.e., the first and second PFETs P21 and P22) in the PFET region. Source/drains may be formed on both sides of the gate electrode, and the source/drains may be connected to the pattern of the M1 layer through contacts (referred to as source/drain contacts) and vias. The gate electrode may be connected to the pattern of the M1 layer through the contact and the via.

The memory cell C21' may include NFET regions and PFET regions extending in the Y-axis direction. For example, as shown in fig. 5A, the NFET regions may extend in the Y-axis direction between the PFET regions, which extend in the Y-axis direction in the memory cell C21'. The memory cell C21' may include a gate electrode extending in the X-axis direction. The gate electrode may form NFETs (i.e., the first to fourth NFETs N31 to N34 of fig. 4) in the NFET region and PFETs (i.e., the first and second PFETs P31 and P32 of fig. 4) in the PFET region. Source/drain electrodes may be formed on both sides of the gate electrode, and the source/drain electrodes may be connected to the pattern of the M1 layer through contacts and vias. The gate electrode may be connected to the pattern of the M1 layer through the contact and the via.

The memory cell C22' may include NFET and PFET regions extending in the Y-axis direction. For example, as shown in fig. 5A, the NFET regions may extend in the Y-axis direction between the PFET regions, which extend in the Y-axis direction in the memory cell C22'. The memory cell C22' may include a gate electrode extending in the X-axis direction. The gate electrode may form NFETs (i.e., the first to fourth NFETs N41 to N44 of fig. 4) in the NFET region and PFETs (i.e., the first and second PFETs P41 and P42 of fig. 4) in the PFET region. Source/drain electrodes may be formed on both sides of the gate electrode, and the source/drain electrodes may be connected to the pattern of the M1 layer through contacts and vias. The gate electrode may be connected to the pattern of the M1 layer through the contact and the via.

In some embodiments, the memory cells included in layout 50 may have a layout that is flipped with respect to each other. For example, the layout of memory cell C11 'may be symmetrical with respect to the layout of memory cell C12' with respect to the boundary between memory cell C11 'and memory cell C12'. That is, the layout of the memory cell C11 'may correspond to a layout obtained by flipping the layout of the memory cell C12' about an axis parallel to the Y axis. The layout of the memory cell C11 'may be symmetrical with respect to the layout of the memory cell C21' with respect to the boundary between the memory cell C11 'and the memory cell C21'. That is, the layout of the memory cell C11 'may correspond to a layout obtained by flipping the layout of the memory cell C21' about an axis parallel to the X axis. The layout of memory cell C12 'may be symmetrical about the boundary between memory cell C12' and memory cell C22 'and the layout of memory cell C22'. That is, the layout of the memory cell C12 'may correspond to a layout obtained by flipping the layout of the memory cell C22' about an axis parallel to the X axis.

Referring to fig. 5B, a power supply rail PR5 to which the negative power supply voltage VSS is applied may be under the cell array of fig. 5A, and first, second, third, fourth, and fifth TSVs TV51, 52, 53, 54, and 55 may be arranged on the power supply rail PR 5. In some embodiments, the TSV may have a top surface connected to the pattern of the M1 layer and a bottom surface connected to the BSPR as described above with reference to fig. 1A. For example, each of the first to fifth TSVs TVs 51 to 55 may have a bottom surface connected to the power supply rail PR5 and a top surface connected to the pattern of the M1 layer, and the negative power supply voltage VSS is applied to the M1 layer in fig. 5A.

In some embodiments, TSVs may be on boundaries between memory cells that are adjacent to each other. For example, as shown in fig. 5B, the first to fifth TSV TVs 51 to 55 may overlap with the boundary of at least one of the memory cells C11', C12', C21', and C22'. In some embodiments, TSVs may be shared by memory cells that are adjacent to each other. For example, the fifth TSV TV55 may be shared between the memory cells C11', C12', C21', and C22'. As in the non-limiting examples presented with reference to fig. 7A-7D, the power rail PR5 may have various shapes not limited to fig. 5B. In some embodiments, similar to the memory cells described with reference to fig. 5A, the portions divided by the boundaries of the memory cells in the power supply rail PR5 may have a layout that is flipped with respect to each other.

Fig. 6A-6C are plan views of layouts of ICs according to some embodiments. For example, the plan view of fig. 6A shows a layout 60 including memory cells C11", C12", C21", and C22" and backside contacts, the memory cells C11", C12", C21", and C22" corresponding to the four memory cells C11, C12, C21, and C22, respectively, included in the equivalent circuit 40 of fig. 4. The plan view of fig. 6A shows the cell array in layout 60, and the plan views of fig. 6B and 6C show layouts 60a and 60B that include power rails and backside contacts that may be disposed below the cell array. In fig. 6A to 6C, names written on patterns represent lines electrically connected to the patterns and/or voltages applied to the patterns. The illustration of the source/drain is omitted in fig. 6A for simplicity. Note that the equivalent circuit 40 of fig. 4 is not limited to the layouts 60, 60a, and 60b shown in fig. 6A to 6C.

Referring to fig. 6A, each of the four memory cells C11", C12", C21", and C22" may have the same occupied space. That is, each of the four memory cells C11", C12", C21", and C22" may have the same area, the same horizontal length, and the same vertical length. Memory cell C11 "and memory cell C12" in the same row may be commonly connected to word line WL [ k ]. Memory cell C21 "and memory cell C22" in the same row may be commonly connected to word line WL [ k+1]. The memory cell C11 "and the memory cell C21" in the same column may be commonly connected to the first bit line BL1 and the first complementary bit line BLB1. Memory cell C12 "and memory cell C22" in the same column may be commonly connected to second bit line BL2 and second complementary bit line BLB2.

The memory cell C11 "may include NFET and PFET regions extending in the Y-axis direction. For example, as shown in fig. 6A, the NFET regions may extend in the Y-axis direction between the PFET regions, which extend in the Y-axis direction in the memory cell C11 ". The memory cell C11″ may include a gate electrode extending in the X-axis direction. The gate electrode may form NFETs (i.e., the first to fourth NFETs N11 to N14 of fig. 4) in the NFET region and PFETs (i.e., the first and second PFETs P11 and P12 of fig. 4) in the PFET region. Source/drains may be formed on both sides of the gate electrode, and the source/drains may be connected to the pattern of the M1 layer through contacts (referred to as source/drain contacts) and vias. The gate electrode may be connected to the pattern of the M1 layer through a contact (referred to as a gate contact) and a via.

The memory cell C12 "may include NFET and PFET regions extending in the Y-axis direction. For example, as shown in fig. 6A, the NFET regions may extend in the Y-axis direction between the PFET regions, which extend in the Y-axis direction in the memory cell C12 ". The memory cell C12″ may include a gate electrode extending in the X-axis direction. The gate electrode may form NFETs (i.e., the first to fourth NFETs N21 to N24 of fig. 4) in the NFET region and PFETs (i.e., the first and second PFETs P21 and P22 of fig. 4) in the PFET region. Source/drain electrodes may be formed on both sides of the gate electrode, and the source/drain electrodes may be connected to the pattern of the M1 layer through contacts and vias. The gate electrode may be connected to the pattern of the M1 layer through the contact and the via.

The memory cell C21 "may include NFET and PFET regions extending in the Y-axis direction. For example, as shown in fig. 6A, the NFET regions may extend in the Y-axis direction between the PFET regions, which extend in the Y-axis direction in the memory cell C21 ". The memory cell C21″ may include a gate electrode extending in the X-axis direction. The gate electrode may form NFETs (i.e., the first to fourth NFETs N31 to N34 of fig. 4) in the NFET region and PFETs (i.e., the first and second PFETs P31 and P32 of fig. 4) in the PFET region. Source/drain electrodes may be formed on both sides of the gate electrode, and the source/drain electrodes may be connected to the pattern of the M1 layer through contacts and vias. The gate electrode may be connected to the pattern of the M1 layer through the contact and the via.

The memory cell C22 "may include NFET and PFET regions extending in the Y-axis direction. For example, as shown in fig. 6A, the NFET regions may extend in the Y-axis direction between the PFET regions, which extend in the Y-axis direction in the memory cell C22 ". The memory cell C22 "may include a gate electrode extending in the X-axis direction. The gate electrode may form NFETs (i.e., the first to fourth NFETs N41 to N44 of fig. 4) in the NFET region and PFETs (i.e., the first and second PFETs P41 and P42 of fig. 4) in the PFET region. Source/drain electrodes may be formed on both sides of the gate electrode, and the source/drain electrodes may be connected to the pattern of the M1 layer through contacts and vias. The gate electrode may be connected to the pattern of the M1 layer through the contact and the via.

In some embodiments, the memory cells included in layout 60 may have a layout that is flipped with respect to each other. For example, the layout of memory cell C11 "may be symmetrical about the boundary between memory cell C11" and memory cell C12 "and the layout of memory cell C12". That is, the layout of the memory cell C11 "may correspond to a layout obtained by flipping the layout of the memory cell C12" about an axis parallel to the Y-axis. The layout of memory cell C11 "may be symmetrical about the boundary between memory cell C11" and memory cell C21 "and the layout of memory cell C21". That is, the layout of the memory cell C11 "may correspond to a layout obtained by flipping the layout of the memory cell C21" about an axis parallel to the X-axis. The layout of memory cell C12 "may be symmetrical about the boundary between memory cell C12" and memory cell C22 "and the layout of memory cell C22". That is, the layout of the memory cell C12 "may correspond to a layout obtained by flipping the layout of the memory cell C22" about an axis parallel to the X-axis.

In comparison with the layout 50 of fig. 5A, in the layout 60, the pattern of the M1 layer to which the negative power supply voltage VSS is applied may be omitted. As shown in fig. 6A, a negative supply voltage VSS may be provided to the source/drain of the transistor through a back side contact. Therefore, the pattern of the M1 layer to which the negative power supply voltage VSS is applied may be omitted.

Referring to fig. 6B, a power supply rail PR6 to which the negative power supply voltage VSS is applied may be under the cell array of fig. 6A, and first, second, third, fourth, fifth, and sixth back contacts BC61, BC62, BC63, BC64, BC65, and BC66 may be arranged on the power supply rail PR 6. In some embodiments, the backside contacts may have a top surface connected to the source/drain and a bottom surface connected to the BSPR, as described above with reference to fig. 1B. For example, each of the first to sixth back side contacts BC61 to BC66 may have a bottom surface connected to the power supply rail PR6 and a top surface connected to the source/drain (or source) of the transistor in fig. 6A.

In some embodiments, the backside contacts can be on boundaries between memory cells that are adjacent to each other. For example, as shown in fig. 6B, the first to sixth back side contacts BC61 to BC66 may overlap with the boundary of at least one of the memory cells C11", C12", C21", and C22". In some embodiments, the backside contacts can be shared by memory cells that are adjacent to each other. For example, the fifth back side contact BC65 may be shared by the memory cell C11 "and the memory cell C21", and the sixth back side contact BC66 may be shared by the memory cell C12 "and the memory cell C22".

Referring to fig. 6C, a power supply rail PR6 to which the negative power supply voltage VSS is applied may be under the cell array of fig. 6A, and first, second, third, fourth, fifth, and sixth back contacts BC61, BC62, BC63, BC64, BC65, and BC66 may be arranged on the power supply rail PR 6. In some embodiments, the backside contacts may have a top surface connected to the source/drain and a bottom surface connected to the BSPR, as described above with reference to fig. 1B. For example, each of the first to sixth back side contacts BC61 to BC66 may have a bottom surface connected to the power supply rail PR6 and a top surface connected to the source/drain (or source) of the transistor in fig. 6A.

In some embodiments, the backside contacts can be on boundaries between memory cells that are adjacent to each other. For example, as shown in fig. 6B and 6C, the first to sixth back-side contacts BC61 to BC66 may overlap with the boundary of at least one of the memory cells C11", C12", C21", and C22". In some embodiments, the backside contacts can be shared by memory cells that are adjacent to each other. For example, the fifth back side contact BC65 may be shared by the memory cell C11 "and the memory cell C21", and the sixth back side contact BC66 may be shared by the memory cell C12 "and the memory cell C22". As in the non-limiting examples presented with reference to fig. 7A-7D, the power supply rail PR6 may have various shapes not limited to fig. 6B and 6C. In some embodiments, similar to the memory cells described with reference to fig. 6A, the portions divided by the boundaries of the memory cells in the power supply rail PR6 may have a layout that is flipped with respect to each other.

Fig. 7A-7D are plan views of examples of BSPR according to some embodiments. As described above with reference to the drawings, the BSPR may be under the cell array, and the TSV or backside contact may be on the BSPR. Note that BSPR is not limited to the examples shown in fig. 7A to 7D.

Referring to fig. 7A, the power rail 70a may have a shape according to a cell boundary. For example, the power rail 70a may include a first portion P1, a second portion P2, a third portion P3, a fourth portion P4, a fifth portion P5, a sixth portion P6, a seventh portion P7, and an eighth portion P8 divided according to cell boundaries, and the first portion P1 to the eighth portion P8 may have shapes that are inverted with respect to each other, respectively. The first portion P1 may be symmetrical with the second portion P2 about a cell boundary between the first portion P1 and the second portion P2. That is, the first portion P1 may correspond to a shape in which the second portion P2 is flipped about an axis parallel to the Y axis. The first portion P1 may be symmetrical with the third portion P3 about a cell boundary between the first portion P1 and the third portion P3. That is, the first portion P1 may correspond to a shape in which the third portion P3 is flipped about an axis parallel to the X axis. The second portion P2 may be symmetrical with the fourth portion P4 about a cell boundary between the second portion P2 and the fourth portion P4. That is, the second portion P2 may correspond to a shape in which the fourth portion P4 is flipped about an axis parallel to the X axis. The fifth to eighth portions P5 to P8 may have the same shape as the first to fourth portions P1 to P4, respectively, and thus, repeated descriptions of the fifth to eighth portions P5 to P8 are omitted for the sake of brevity.

Referring to fig. 7B, the power rail 70B may have a shape according to a cell boundary. For example, the power supply rail 70b may include a first portion P1, a second portion P2, a third portion P3, a fourth portion P4, a fifth portion P5, a sixth portion P6, a seventh portion P7, and an eighth portion P8 divided according to cell boundaries, and the first portion P1 to the eighth portion P8 may have shapes that are inverted with respect to each other, respectively. The first portion P1 may be symmetrical with the second portion P2 about a cell boundary between the first portion P1 and the second portion P2. That is, the first portion P1 may correspond to a shape in which the second portion P2 is flipped about an axis parallel to the Y axis. The first portion P1 may be symmetrical with the third portion P3 about a cell boundary between the first portion P1 and the third portion P3. That is, the first portion P1 may correspond to a shape in which the third portion P3 is flipped about an axis parallel to the X axis. The second portion P2 may be symmetrical with the fourth portion P4 about a cell boundary between the second portion P2 and the fourth portion P4. That is, the second portion P2 may correspond to a shape in which the fourth portion P4 is flipped about an axis parallel to the X axis. The fifth to eighth portions P5 to P8 may have the same shape as the first to fourth portions P1 to P4, respectively, and thus, repeated descriptions of the fifth to eighth portions P5 to P8 are omitted for the sake of brevity.

Referring to fig. 7C, the power rail 70C may have a shape according to a cell boundary. For example, the power supply rail 70c may include a first portion P1, a second portion P2, a third portion P3, a fourth portion P4, a fifth portion P5, a sixth portion P6, a seventh portion P7, and an eighth portion P8 divided according to cell boundaries, and the first portion P1 to the eighth portion P8 may have shapes that are inverted with respect to each other, respectively. The first portion P1 may be symmetrical with the second portion P2 about a cell boundary between the first portion P1 and the second portion P2. That is, the first portion P1 may correspond to a shape in which the second portion P2 is flipped about an axis parallel to the Y axis. The first portion P1 may be symmetrical with the third portion P3 about a cell boundary between the first portion P1 and the third portion P3. That is, the first portion P1 may correspond to a shape in which the third portion P3 is flipped about an axis parallel to the X axis. The second portion P2 may be symmetrical with the fourth portion P4 about a cell boundary between the second portion P2 and the fourth portion P4. That is, the second portion P2 may correspond to a shape in which the fourth portion P4 is flipped about an axis parallel to the X axis. The fifth to eighth portions P5 to P8 may have the same shape as the first to fourth portions P1 to P4, respectively, and thus, repeated descriptions of the fifth to eighth portions P5 to P8 are omitted for the sake of brevity.

Referring to fig. 7D, the power rail 70D may have a shape according to a cell boundary. For example, the power rail 70d may include a first portion P1, a second portion P2, a third portion P3, a fourth portion P4, a fifth portion P5, a sixth portion P6, a seventh portion P7, and an eighth portion P8 divided according to cell boundaries, and the first portion P1 to the eighth portion P8 may have shapes that are inverted with respect to each other, respectively. The first portion P1 may be symmetrical with the second portion P2 about a cell boundary between the first portion P1 and the second portion P2. That is, the first portion P1 may correspond to a shape in which the second portion P2 is flipped about an axis parallel to the Y axis. The first portion P1 may be symmetrical with the third portion P3 about a cell boundary between the first portion P1 and the third portion P3. That is, the first portion P1 may correspond to a shape in which the third portion P3 is flipped about an axis parallel to the X axis. The second portion P2 may be symmetrical with the fourth portion P4 about a cell boundary between the second portion P2 and the fourth portion P4. That is, the second portion P2 may correspond to a shape in which the fourth portion P4 is flipped about an axis parallel to the X axis. The fifth to eighth portions P5 to P8 may have the same shape as the first to fourth portions P1 to P4, respectively, and thus, repeated descriptions of the fifth to eighth portions P5 to P8 are omitted for the sake of brevity.

Fig. 8A and 8B are diagrams of examples of layouts of ICs according to some embodiments. For example, fig. 8A and 8B show a layout 80a and a layout 80B, each of the layout 80a and the layout 80B including word lines extending over the memory cell array. As shown in fig. 8A and 8B, the second pattern M22 corresponding to the word line may extend in the X-axis direction and be electrically connected to the plurality of memory cells.

Referring to fig. 8A, when BSPR is not used, a negative power supply voltage VSS may be supplied to the memory cells through the pattern of the wiring layer. For this, as shown in fig. 8A, in the M2 layer, the first pattern M21 and the third pattern M23 to which the negative power supply voltage VSS is applied may extend in the X-axis direction, and the second pattern M22 corresponding to the word line may extend between the first pattern M21 and the third pattern M23 in the M2 layer. In the M3 layer, the pattern M31 to which the negative power supply voltage VSS is applied may extend in the Y-axis direction. Accordingly, as shown in fig. 8A, the first parasitic capacitance C1 may occur between the second pattern M22 and the first pattern M21, the second parasitic capacitance C2 may occur between the second pattern M22 and the third pattern M23, and the third parasitic capacitance C3 may occur between the second pattern M22 and the pattern M31. Due to the parasitic capacitances including the first to third parasitic capacitances C1 to C3, activation (e.g., voltage rise) and deactivation (e.g., voltage fall) of the word line through the second pattern M22 may be delayed.

Referring to fig. 8B, as described above with reference to the drawings, when BSPR is used, a pattern configured to supply the negative power supply voltage VSS may be omitted in the wiring layer. For example, as shown in fig. 8B, in the M2 layer, only the second pattern M22 corresponding to the word line may extend in the X-axis direction. That is, in the M2 layer, the pattern may be omitted between adjacent patterns corresponding to the word lines. In addition, in the M3 layer, the pattern to which the negative power supply voltage VSS is applied may be omitted. As a result, parasitic capacitance between the second pattern M22 and the patterns adjacent thereto can be significantly reduced, and activation and deactivation of the word line by the second pattern M22 can be performed at high speed.

Fig. 9 is a block diagram of a system on a chip (SoC) in accordance with some embodiments. A SoC may refer to an IC in which components of a computing system or another electronic system are integrated. For example, an Application Processor (AP), which is an example of a SoC, may include processors and components for other functions. As shown in fig. 9, soC 90 may include a core 91, a Digital Signal Processor (DSP) 92, a Graphics Processor (GPU) 93, an embedded memory 94, a communication interface (I/F) 95, and a memory interface (I/F) 96. The components of SoC 90 may communicate with each other via bus 97.

Core 91 may handle instruction and control operations of components included in SoC 90. For example, core 91 may drive an operating system and execute applications on the operating system by processing a series of instructions. DSP 92 may generate data by processing digital signals, such as those provided by communication interface 95. The GPU 93 may generate data corresponding to an image output by the display device based on image data provided by the embedded memory 94 or the memory interface 96, or encode the image data. In some embodiments, the memory devices described above with reference to fig. 1A-7D may be included as caches and/or memory in core 91, DSP 92, and/or GPU 93. Thus, the core 91, DSP 92, and/or GPU 93 may also have high reliability and efficiency due to the high reliability and efficiency of the memory device.

The embedded memory 94 may store data required for the operation of the core 91, DSP 92 and GPU 93. In some embodiments, embedded memory 94 may include the memory devices described above with reference to fig. 1A-7D. Thus, the embedded memory 94 may provide reliable write operations and have a reduced area and reduced power consumption. As a result, the operational reliability and efficiency of SoC 90 may be improved.

Communication interface 95 may provide an interface for a communication network or one-to-one communication. Memory interface 96 may provide an interface to external memory (e.g., DRAM and flash) of SoC 90.

While various embodiments have been particularly shown and described with reference to the drawings, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims (20)

1. An integrated circuit, comprising:

A cell array including a plurality of cells, each of the plurality of cells including at least one transistor;

a power rail in a power rail layer below the cell array, the power rail configured to provide power to the cell array; and

A plurality of contacts, between the cell array and the power rail,

Wherein each of the plurality of contacts extends from a source of a transistor of a respective one of the plurality of cells down to a power rail.

2. The integrated circuit of claim 1, wherein each of the plurality of contacts is at a boundary between adjacent ones of the plurality of cells and shared by the adjacent cells.

3. The integrated circuit of claim 1, wherein each of the plurality of cells has the same footprint, and

The plurality of contacts are disposed on the power rail.

4. The integrated circuit of claim 1, wherein the plurality of cells includes a first cell and a second cell adjacent to the first cell, and

The first cell and the second cell are symmetrical to each other about a boundary between the first cell and the second cell.

5. The integrated circuit of claim 4, wherein the power rail comprises a first portion under the first cell and a second portion under the second cell, and

The first portion and the second portion are symmetrical to each other about a boundary between the first portion and the second portion.

6. The integrated circuit of claim 4, wherein the plurality of cells further comprises a third cell adjacent to the first cell and a fourth cell adjacent to the second cell,

The first cell and the third cell are symmetrical to each other about a boundary between the first cell and the third cell, and

The second cell and the fourth cell are symmetrical to each other about a boundary between the second cell and the fourth cell.

7. The integrated circuit of claim 6, wherein the power rail includes a first portion under the first cell and a second portion under the second cell,

The first portion and the second portion are symmetrical to each other about a boundary between the first portion and the second portion,

The power rail further includes a third portion below the third unit and a fourth portion below the fourth unit,

The first portion and the third portion are symmetrical to each other about a boundary between the first portion and the third portion, and

The second portion and the fourth portion are symmetrical to each other about a boundary between the second portion and the fourth portion.

8. The integrated circuit of any of claims 1-7, wherein the plurality of cells are configured to operate based on a positive supply voltage and a negative supply voltage, and

The power rail is configured to receive a negative supply voltage.

9. The integrated circuit of any one of claims 1 to 7, further comprising: a plurality of word lines extending parallel to each other in a first horizontal direction in a first wiring layer above the cell array,

Wherein, in the first wiring layer, the pattern between adjacent word lines among the plurality of word lines is omitted.

10. An integrated circuit, comprising:

A cell array including a plurality of cells, each of the plurality of cells including at least one transistor;

a power rail in a power rail layer below the cell array, the power rail configured to provide power to the cell array; and

A plurality of contacts, between the cell array and the power rail,

Wherein each of the plurality of contacts has a top surface connected to a source of a transistor of a respective one of the plurality of cells and a bottom surface connected to a power rail.

11. The integrated circuit of claim 10, wherein each of the plurality of contacts is at a boundary between adjacent ones of the plurality of cells and shared by the adjacent cells.

12. The integrated circuit of claim 10, wherein each of the plurality of cells has the same footprint and the plurality of contacts are arranged on a power rail.

13. The integrated circuit of any of claims 10 to 12, wherein the plurality of cells are each configured to operate based on a positive supply voltage and a negative supply voltage, and

The power rail is configured to receive a negative supply voltage.

14. The integrated circuit of any of claims 10 to 12, further comprising: a plurality of word lines extending parallel to each other in a first horizontal direction in a first wiring layer above the cell array,

Wherein, in the first wiring layer, the pattern between adjacent word lines in the plurality of word lines is omitted.

15. An integrated circuit, comprising:

a cell array including a plurality of cells, each cell including two inverters cross-coupled to each other;

a power rail in a power rail layer below the cell array; and

A plurality of contacts, between the cell array and the power rail,

Wherein each of the plurality of contacts extends from a source of a transistor of a respective one of the two inverters down to a power rail.

16. The integrated circuit of claim 15, wherein each of the plurality of contacts is at a boundary between adjacent ones of the plurality of cells and shared by the adjacent cells.

17. The integrated circuit of claim 15, wherein each of the plurality of cells has the same footprint and the plurality of contacts are arranged on a power rail.

18. The integrated circuit of claim 15, wherein the plurality of cells includes a first cell and a second cell adjacent to the first cell, and

The first cell and the second cell are symmetrical to each other about a boundary between the first cell and the second cell.

19. The integrated circuit of claim 18, wherein the plurality of cells further comprises a third cell adjacent to the first cell and a fourth cell adjacent to the second cell,

The first cell and the third cell are symmetrical to each other about a boundary between the first cell and the third cell, and

The second cell and the fourth cell are symmetrical to each other about a boundary between the second cell and the fourth cell.

20. The integrated circuit of claim 19, wherein the power rail includes a first portion under the first cell and a second portion under the second cell,

The first portion and the second portion are symmetrical to each other about a boundary between the first portion and the second portion,

The power rail further includes a third portion below the third unit and a fourth portion below the fourth unit,

The first portion and the third portion are symmetrical to each other about a boundary between the first portion and the third portion, and

The second portion and the fourth portion are symmetrical to each other about a boundary between the second portion and the fourth portion.