CN118053809A - Dual damascene process - Google Patents
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- CN118053809A CN118053809A CN202410330053.3A CN202410330053A CN118053809A CN 118053809 A CN118053809 A CN 118053809A CN 202410330053 A CN202410330053 A CN 202410330053A CN 118053809 A CN118053809 A CN 118053809A
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- 238000000034 method Methods 0.000 title claims abstract description 79
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- 229910052751 metal Inorganic materials 0.000 claims abstract description 93
- 239000002184 metal Substances 0.000 claims abstract description 93
- 238000005530 etching Methods 0.000 claims abstract description 76
- 239000011229 interlayer Substances 0.000 claims abstract description 47
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims abstract description 22
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims abstract description 20
- 229910010271 silicon carbide Inorganic materials 0.000 claims abstract description 20
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims abstract description 19
- 238000001039 wet etching Methods 0.000 claims abstract description 19
- 238000001312 dry etching Methods 0.000 claims abstract description 8
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 18
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 16
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 15
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 14
- 239000000463 material Substances 0.000 claims description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 13
- 229910052710 silicon Inorganic materials 0.000 claims description 13
- 239000010703 silicon Substances 0.000 claims description 13
- 230000003647 oxidation Effects 0.000 claims description 10
- 238000007254 oxidation reaction Methods 0.000 claims description 10
- 239000010949 copper Substances 0.000 claims description 9
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 7
- 229910052802 copper Inorganic materials 0.000 claims description 7
- 238000009713 electroplating Methods 0.000 claims description 4
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- 239000011248 coating agent Substances 0.000 claims 1
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- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 abstract description 7
- 239000006117 anti-reflective coating Substances 0.000 description 8
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 7
- 229910017107 AlOx Inorganic materials 0.000 description 6
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- 238000004519 manufacturing process Methods 0.000 description 3
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- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a dual damascene process method, which comprises the following steps: and forming a first etching stop layer, an interlayer film and a metal hard mask layer, wherein the first etching stop layer comprises an aluminum nitride layer, a first ODC layer and an aluminum oxide layer which are sequentially overlapped. And performing first graphical etching on the metal hard mask layer. And forming a through hole hard mask layer and performing second graphical etching on the through hole hard mask layer. AIO etching stopped at the surface of the alumina layer is performed to simultaneously form a trench and a via opening in the interlayer film. And removing the aluminum oxide layer by adopting a first wet etching. And removing the first oxygen-doped silicon carbide layer by adopting a first dry etching, wherein the metal hard mask layer is continuously used as a hard mask to protect the interlayer film in the first dry etching. And removing the metal hard mask layer by adopting a second wet etching. And removing the aluminum nitride layer by adopting a third wet etching process. Forming a metal layer. The invention can prevent the interlayer film from being damaged when the first etching stop layer is removed and thus prevent the through hole and the metal line from being shorted.
Description
Technical Field
The invention relates to a method for manufacturing a semiconductor integrated circuit, in particular to a dual damascene process method.
Background
The partial Trench first etching (PARTIAL TRENCH FIRST AT TRENCH LEVEL) double-Marsdenia copper process at the Trench level based on a metal hard mask is used for preparing a rear-section interconnection wiring of a development platform of a smaller process node, which takes TiN as a pattern transfer layer of a metal wire and a self-aligned hard mask during the etching (etching) of a through hole (Via) opening and a Trench (Trench), namely integrated etching (AIO etching), so that the Via opening and the Trench pattern can be etched to form, and simultaneously, in order to prevent damage to lower-layer metal during the AIO etching, a three-layer Etching Stop Layer (ESL), namely an Alumina (ALO), an oxygen-doped silicon carbide layer (ODC) and an aluminum nitride (ALN) is newly added to the node, after the AIO etching, the hard mask TiN is firstly removed by a Wet method, and then the ALO/ODC/ALN is removed by a Wet etching (Dry) -Wet method. However, certain non-uniformity exists at the center and the edge of the wafer during AIO etching, on one hand, the growing thickness of the edge TiN is relatively thin, on the other hand, the etching selectivity of the edge etching gas to the TiN and the Low dielectric constant (Low-k, LK) layer of the lower layer of the interlayer film is relatively Low, namely, the etching rates of the two layers are close, so that the selective etching is not easy to realize, the TiN at the weak point of the edge of the wafer is easy to consume, the Via is bridged with the adjacent metal wire pattern, a circuit short circuit is formed, and the chip yield is greatly reduced. This shorting phenomenon is exacerbated if the wire size is too large or the Via shape is tapered prior to AIO etch.
FIG. 1 is a flow chart of a prior art dual damascene process; 2A-2H are schematic views of device structures in the steps of the prior dual damascene process; the existing dual damascene process method comprises the following steps:
As shown in fig. 2A, a first etch stop layer 101, an interlayer film 103, and a metal hard mask layer (HM) 105 are formed on an underlying structure (not shown), the first etch stop layer 101 including an aluminum nitride layer 101a, a first oxygen-doped silicon carbide layer 101b, and an aluminum oxide layer 101c stacked in this order.
In FIG. 2A, the first etch stop layer 101 is denoted by ESL, the alumina layer 101c is denoted by AlOx, the first oxygen-doped silicon carbide layer 101b is denoted by ODC, the aluminum nitride layer 101a is denoted by AlN, and the thicknesses of AlOx, ODC and AlN are respectively shownAnd/>I.e. ESL (AlOx 50A/ODC 50A/AlN 25A)
The material of the metal hard mask layer 105 includes TiN, and in fig. 2A, the metal hard mask layer 105 is also denoted by TiN.
A nitrogen-free anti-reflective coating (NFDARC) 104 is further formed between the metal hard mask layer 105 and the interlayer film 103. In FIG. 2A, the nitrogen-free anti-reflective coating 104 is also denoted by NFDARC, and in FIG. 2A, the nitrogen-free anti-reflective coating 104 is also shown as
A first oxide layer 106 is further formed on the surface of the metal hard mask layer 105. The first oxide layer 106 is formed by a PECVD process and the silicon source is TEOS, so that the first oxide layer 106 is a TEOS oxide, and in FIG. 2A, the first oxide layer 106 is also indicated by TEOS.
The interlayer film 103 includes a low dielectric constant (LK) layer. In the field of semiconductor fabrication, a low dielectric constant layer is generally referred to as a dielectric layer having a dielectric constant lower than that of silicon oxide. In some preferred embodiments, the interlayer film 103 is made of ultra low dielectric constant (ULK) material, and in fig. 2A, the interlayer film 103 is also denoted by ULK, and in fig. 2A, the thickness of the interlayer film 103 is also shown as
A bottom silicon oxide layer 102 is also formed between the aluminum oxide layer 101c and the low dielectric constant layer.
The bottom silicon oxide layer 102 is formed using a PECVD process and the silicon source is TEOS. In fig. 2A, the bottom silicon oxide layer 102 is also denoted by TEOS. The thickness of the bottom silicon oxide layer 102 is also shown in FIG. 2A as
The underlying structure includes an underlying interlayer film and an underlying metal layer, and each of the subsequently formed through holes 112 is in contact with the underlying metal layer at the bottom.
As shown in fig. 2A, the metal hard mask layer 105 is subjected to a first patterning etching to open the trench 108 forming region.
As shown in fig. 2B, a via hard mask layer 107 is formed and the via hard mask layer 107 is subjected to a second patterning etching to open a via 112 formation region.
In fig. 2B, the Via hard mask layer 107 is also denoted by Via HM.
The via hard mask layer 107 includes a second oxide layer 107a, a second oxygen-doped silicon carbide layer 107b, and a third oxide layer 107c stacked in sequence.
The third oxide layer 107c serves as a cap layer (cap).
The surface of the second oxide layer 107a is flat, and the second oxide layer 107a completely fills and covers the open area of the metal hard mask layer 105 on the surface of the metal hard mask layer 105.
In the second patterned etching, the second oxide layer 107a serves as an etching stop layer.
The second oxide layer 107a is formed using a Low Temperature Oxidation (LTO) process. Unlike the high temperature oxidation process, in which oxidation is performed between silicon to form an oxide layer using high temperature, the low temperature oxidation process uses decomposition and recombination of compounds at a decomposition temperature of the compounds, which is lower than a temperature required for directly thermally oxidizing silicon.
In step S101, AIO etc, as shown in fig. 2C, an integrated etching is performed to simultaneously form a trench 108 and a via opening 109 in the interlayer film 103, the integrated etching is stopped on the surface of the alumina layer 101C, the via hard mask layer 107 is removed in the integrated etching, and the surface of the alumina layer 101C at the bottom of the via opening 109 is exposed.
In step S102, tiN remove is to remove (remove) the metal hard mask layer 105, and as shown in fig. 2D, wet etching is used to remove the metal hard mask layer 105.
Step S103, ALO remove removes the alumina layer 101c. As shown in fig. 2E, the aluminum oxide layer 101c exposed at the bottom of the via opening 109 is removed by wet etching.
Step S104, ODC etch is performed to etch the first oxygen doped silicon carbide layer 101b; as shown in fig. 2F, the first silicon-doped oxide layer 101b exposed at the bottom of the via opening 109 is removed by dry etching. Since the etching selectivity of the first oxygen-doped silicon carbide layer 101b and the interlayer film 103, i.e., the low dielectric constant layer such as SiOCH material is poor, as in etching the first oxygen-doped silicon carbide layer 101b, more loss is generated in the interlayer film 103 in some regions such as the region shown by the dotted line 110, so that the via opening 109 and the adjacent trench 108 in this region are interconnected.
Step S105, ALN remove removes the aluminum nitride layer 101a. As shown in fig. 2G, the aluminum nitride layer 101a is removed by a wet etching process.
In step S106, cu ECP AND CMP, a metal layer such as a Cu layer is formed by an electroplating process and Chemical Mechanical Polishing (CMP) is performed on the Cu layer. As shown in fig. 2H, a metal layer fills the trench 108 and the via opening 109, a metal line 111 is formed from the metal layer filled in the trench 108, and a via 112 is formed from the metal layer filled in the via opening 109. It can be seen that in the area shown by the dashed circle 110, the via 112 is shorted to the adjacent metal line 111.
Disclosure of Invention
The invention aims to solve the technical problem of providing a dual damascene process method which can prevent the interlayer film from being damaged when an etching stop layer adopted by integrated etching, namely a first etching stop layer is removed, thereby preventing the defect of short circuit between a through hole and an adjacent metal pattern caused by the damage of the interlayer film.
In order to solve the technical problems, the dual damascene process method provided by the invention comprises the following steps:
And forming a first etching stop layer, an interlayer film and a metal hard mask layer on the bottom layer structure, wherein the first etching stop layer comprises an aluminum nitride layer, a first oxygen-doped silicon carbide layer and an aluminum oxide layer which are sequentially overlapped.
And performing first graphical etching on the metal hard mask layer to open the groove forming area.
And forming a through hole hard mask layer and performing second graphical etching on the through hole hard mask layer to open a through hole forming area.
And performing integrated etching to simultaneously form a groove and a through hole opening in the interlayer film, wherein the integrated etching is stopped on the surface of the aluminum oxide layer, the through hole hard mask layer is removed in the integrated etching, and the surface of the aluminum oxide layer at the bottom of the through hole opening is exposed.
And removing the aluminum oxide layer exposed at the bottom of the through hole opening by adopting first wet etching.
And removing the first oxygen-doped silicon carbide layer exposed at the bottom of the through hole opening by adopting a first dry etching, wherein in the first dry etching, the metal hard mask layer is continuously used as a hard mask to protect the interlayer film and reduce the interlayer film loss.
And removing the metal hard mask layer by adopting a second wet etching.
And removing the aluminum nitride layer by adopting a third wet etching process.
And forming a metal layer to fill the groove and the through hole opening, wherein a metal line is formed by the metal layer filled in the groove, and a through hole is formed by the metal layer filled in the through hole opening.
A further improvement is that the material of the metal hard mask layer comprises TiN.
A further improvement is that a nitrogen-free anti-reflective coating is also formed between the metal hard mask layer and the interlayer film.
The further improvement is that a first oxide layer is also formed on the surface of the metal hard mask layer.
A further improvement is that the first oxide layer is formed using a PECVD process and the silicon source is TEOS.
Further improvement is that the interlayer film includes a low dielectric constant layer.
A further improvement is that a bottom silicon oxide layer is also formed between the aluminum oxide layer and the low dielectric constant layer.
A further improvement is that the bottom silicon oxide layer is formed using a PECVD process and the silicon source is TEOS.
The further improvement is that the through hole hard mask layer comprises a second oxide layer, a second oxygen-doped silicon carbide layer and a third oxide layer which are sequentially overlapped.
The third oxide layer serves as a cap layer.
The surface of the second oxide layer is flat, and the second oxide layer completely fills and covers the opening area of the metal hard mask layer on the surface of the metal hard mask layer.
In the second patterned etching, the second oxide layer is used as an etching stop layer.
A further improvement is that the second oxide layer is formed by a low temperature oxidation process.
In a further improvement, the bottom layer structure comprises a bottom interlayer film and a bottom metal layer, and each through hole is in contact with the bottom metal layer at the bottom.
A further improvement is that the material of the metal layer comprises copper.
A further improvement is to form the metal layer using a copper electroplating process (ECP) followed by planarizing the metal layer using a Chemical Mechanical Polishing (CMP) process.
A further improvement is that the via is located at the bottom of a partial region of the metal line.
In the invention, the trench and the through hole opening are formed simultaneously by adopting integrated etching, the first etching stop layer at the bottom of the interlayer film is required to be introduced simultaneously by the integrated etching, the first etching stop layer at the bottom of the through hole opening is required to be removed after the integrated etching, and meanwhile, the metal hard mask layer introduced for defining the pattern of the trench is also required to be removed, so that the loss of the interlayer film is prevented from being generated in the process of removing the first etching stop layer exposed at the bottom of the through hole opening.
Drawings
The invention is described in further detail below with reference to the attached drawings and detailed description:
FIG. 1 is a flow chart of a prior art dual damascene process;
FIGS. 2A-2H are schematic views of a device structure at various steps of a conventional dual damascene process;
FIG. 3 is a flow chart of a dual damascene process method in accordance with an embodiment of the present invention;
FIG. 4 is a flow chart of a dual damascene process method in accordance with a preferred embodiment of the present invention;
Fig. 5A-5H are schematic views of device structures in steps of a dual damascene process method according to an embodiment of the present invention.
Detailed Description
FIG. 3 is a flow chart of a dual damascene process method in accordance with an embodiment of the present invention; FIG. 4 is a flow chart of a dual damascene process method in accordance with a preferred embodiment of the present invention; 5A-5H are schematic views of device structures in the steps of the dual damascene process method according to the embodiment of the invention; the dual damascene process method of the embodiment of the invention comprises the following steps:
In step S201, as shown in fig. 5A, a first etching stop layer 201, an interlayer film 203 and a metal hard mask layer 205 are formed on an underlying structure (not shown), where the first etching stop layer 201 includes an aluminum nitride layer 201a, a first oxygen-doped silicon carbide layer 201b and an aluminum oxide layer 201c stacked in this order.
In FIG. 5A, the first etch stop layer 201 is shown by ESL, the alumina layer 201c is shown by AlOx, the first oxygen-doped silicon carbide layer 201b is shown by ODC, the aluminum nitride layer 201a is shown by AlN, and the thicknesses of AlOx, ODC and AlN are shown as respectivelyAnd/>I.e., ESL (AlOx 50A/ODC 50A/AlN 25A), in other embodiments, the thickness of each film layer can also be varied as desired.
In the embodiment of the present invention, the material of the metal hard mask layer 205 includes TiN, and in fig. 5A, the metal hard mask layer 205 is also denoted by TiN.
A nitrogen-free anti-reflective coating 204 is also formed between the metal hard mask layer 205 and the interlayer film 203. In FIG. 5A, the nitrogen-free anti-reflective coating 204 is also denoted by NFDARC, and in FIG. 5A, the nitrogen-free anti-reflective coating 204 is also shown asIn other embodiments, the thickness of the nitrogen-free anti-reflective coating 204 can also be varied as desired.
A first oxide layer 206 is further formed on the surface of the metal hard mask layer 205. In some embodiments, the first oxide layer 206 is formed using a PECVD process and the silicon source is TEOS, so the first oxide layer 206 is TEOS oxide, and in FIG. 5A, the first oxide layer 206 is also denoted TEOS.
The interlayer film 203 includes a low dielectric constant (LK) layer. In the field of semiconductor fabrication, a low dielectric constant layer is generally referred to as a dielectric layer having a dielectric constant lower than that of silicon oxide. In some preferred embodiments, the interlayer film 203 is made of ultra low dielectric constant (ULK) material, and in fig. 5A, the interlayer film 203 is also denoted by ULK, and in fig. 5A, the thickness of the interlayer film 203 is also shown asIn other embodiments, the thickness of the interlayer film 203 can also be changed as desired. In some embodiments, the ULK can employ Black Diamond (BD), which includes silicon, oxygen, carbon, and hydrogen elements, i.e., siOCH materials.
In the embodiment of the present invention, a bottom silicon oxide layer 202 is further formed between the aluminum oxide layer 201c and the low dielectric constant layer.
The bottom silicon oxide layer 202 is formed using a PECVD process and the silicon source is TEOS. In fig. 5A, the bottom silicon oxide layer 202 is also denoted by TEOS. The thickness of the bottom silicon oxide layer 202 is also shown in FIG. 5A asIn other embodiments, the thickness of the bottom silicon oxide layer 202 can also be varied as desired.
In an embodiment of the present invention, the underlying structure includes an underlying interlayer film and an underlying metal layer, and each subsequently formed via 212 is in contact with the underlying metal layer at the bottom.
In step S202, as shown in fig. 5A, the metal hard mask layer 205 is subjected to a first patterning etching to open the trench 208 forming region.
In step S203, as shown in fig. 5B, a via hard mask layer 207 is formed and the via hard mask layer 207 is subjected to a second patterning etching to open the via 212 forming region.
In the embodiment of the present invention, the through hole hard mask layer 207 includes a second oxide layer 207a, a second oxygen-doped silicon carbide layer 207b and a third oxide layer 207c sequentially stacked.
The third oxide layer 207c serves as a cap layer.
The surface of the second oxide layer 207a is flat, and the second oxide layer 207a completely fills and covers the open area of the metal hard mask layer 205 on the surface of the metal hard mask layer 205.
In the second patterned etching, the second oxide layer 207a serves as an etching stop layer.
In some preferred embodiments, the second oxide layer 207a is formed using a Low Temperature Oxidation (LTO) process. Unlike the high temperature oxidation process, in which oxidation is performed between silicon to form an oxide layer using high temperature, the low temperature oxidation process uses decomposition and recombination of compounds at a decomposition temperature of the compounds, which is lower than a temperature required for directly thermally oxidizing silicon.
In step S204, as shown in fig. 5C, an integrated etching is performed to simultaneously form a trench 208 and a via opening 209 in the interlayer film 203, the integrated etching stopping at the surface of the aluminum oxide layer 201C, the via hard mask layer 207 being removed in the integrated etching, the surface of the aluminum oxide layer 201C at the bottom of the via opening 209 being exposed.
In fig. 4, step S204 is denoted as AIO etc.
In step S205, as shown in fig. 5D, the aluminum oxide layer 201c exposed at the bottom of the via opening 209 is removed (removed) by a first wet etching.
In fig. 5, step S205 is denoted as ALO remove. ALO represents aluminum oxide, i.e., the aluminum oxide layer 201c.
In some embodiments, the etching solution of the first wet etching uses an R2390 liquid medicine.
In step S206, as shown in fig. 5E, the first oxygen-doped silicon carbide layer 201b exposed at the bottom of the via opening 209 is removed by a first dry etching, where the metal hard mask layer 205 continues to serve as a hard mask to protect the interlayer film 203 and reduce the interlayer film 203 loss.
In fig. 5, step S206 is denoted as ODC notch. ODC represents the oxygen-doped silicon carbide layer, i.e. the first oxygen-doped silicon carbide layer 201b.
In step S207, as shown in fig. 5F, the metal hard mask layer 205 is removed by a second wet etching.
In fig. 5, step S207 is denoted as TiN remove. TiN is the metal hard mask layer 205.
In some embodiments, the etching solution of the second wet etching uses an R2360 liquid medicine.
In step S208, as shown in fig. 5G, the aluminum nitride layer 201a is removed by using a third wet etching process.
In fig. 5, step S208 is denoted as ALN remove. ALN represents aluminum nitride, i.e., the aluminum nitride layer 201a.
In some embodiments, the etching solution of the third wet etching uses R2380 liquid medicine.
In step S209, as shown in fig. 5H, a metal layer is formed to fill the trench 208 and the via opening 209, a metal line 211 is formed from the metal layer filled in the trench 208, and a via 212 is formed from the metal layer filled in the via opening 209.
The via 212 is located at the bottom of a partial region of the metal line 211.
In an embodiment of the present invention, the material of the metal layer includes copper.
And forming the metal layer by adopting a copper electroplating process, and then flattening the metal layer by adopting a chemical mechanical polishing process. In fig. 5, step S209 is denoted as Cu ECP AND CMP.
In the embodiment of the invention, the trench 208 and the via opening 209 are simultaneously formed by adopting integrated etching, the first etching stop layer 201 at the bottom of the interlayer film 203 needs to be introduced at the same time, the first etching stop layer 201 at the bottom of the via opening 209 needs to be removed after the integrated etching, and simultaneously, the metal hard mask layer 205 introduced for defining the pattern of the trench 208 needs to be removed, so that the interlayer film 203 is prevented from being worn out during the process of removing the first etching stop layer 201 exposed at the bottom of the via opening 209.
The embodiment of the invention improves the bridging short circuit problem of Via and metal at the weak point of the wafer edge in the prior art by changing the position of removing TiN by a wet method, namely, removing TiN after AIO etching in the prior art is changed into removing TiN after ODC etching (etching). Because the ODC and the Low dielectric constant (Low-K) material of the interlayer film are both oxides, the etching selection is relatively Low, and therefore, a certain Loss (Loss) amount is also generated on the Low-K material when the ODC is etched, and particularly, the Low-K material at the adjacent graph of the Via and the metal is easier to lose, so that bridging short circuit is caused. Therefore, tiN is reserved to ODC Etch, the effect of a hard mask can be further played, the Loss of Low-K is reduced, bridging short circuit between Via and adjacent metal is avoided, and the chip yield is greatly improved.
The present invention has been described in detail by way of specific examples, but these should not be construed as limiting the invention. Many variations and modifications may be made by one skilled in the art without departing from the principles of the invention, which is also considered to be within the scope of the invention.
Claims (14)
1. The dual damascene process method is characterized by comprising the following steps of:
forming a first etching stop layer, an interlayer film and a metal hard mask layer on the bottom layer structure, wherein the first etching stop layer comprises an aluminum nitride layer, a first oxygen-doped silicon carbide layer and an aluminum oxide layer which are sequentially overlapped;
performing first graphical etching on the metal hard mask layer to open a groove forming area;
Forming a through hole hard mask layer and performing second graphical etching on the through hole hard mask layer to open a through hole forming area;
Performing integrated etching to simultaneously form a groove and a through hole opening in the interlayer film, wherein the integrated etching is stopped on the surface of the aluminum oxide layer, the through hole hard mask layer is removed in the integrated etching, and the surface of the aluminum oxide layer at the bottom of the through hole opening is exposed;
Removing the aluminum oxide layer exposed at the bottom of the through hole opening by adopting first wet etching;
removing the first oxygen-doped silicon carbide layer exposed at the bottom of the through hole opening by adopting a first dry etching, wherein in the first dry etching, the metal hard mask layer is continuously used as a hard mask to protect the interlayer film and reduce the interlayer film loss;
removing the metal hard mask layer by adopting a second wet etching;
removing the aluminum nitride layer by adopting a third wet etching process;
And forming a metal layer to fill the groove and the through hole opening, wherein a metal line is formed by the metal layer filled in the groove, and a through hole is formed by the metal layer filled in the through hole opening.
2. The dual damascene process of claim 1, wherein: the material of the metal hard mask layer comprises TiN.
3. The dual damascene process of claim 2, wherein: and a nitrogen-free anti-reflection coating is also formed between the metal hard mask layer and the interlayer film.
4. The dual damascene process of claim 3 wherein: and a first oxide layer is also formed on the surface of the metal hard mask layer.
5. The dual damascene process of claim 4 wherein: the first oxide layer is formed by adopting a PECVD process and the silicon source adopts TEOS.
6. The dual damascene process of claim 1, wherein: the interlayer film includes a low dielectric constant layer.
7. The dual damascene process of claim 6 wherein: a bottom silicon oxide layer is also formed between the aluminum oxide layer and the low dielectric constant layer.
8. The dual damascene process of claim 7 wherein: the bottom silicon oxide layer is formed using a PECVD process and the silicon source is TEOS.
9. The dual damascene process of claim 1, wherein: the through hole hard mask layer comprises a second oxide layer, a second oxygen-doped silicon carbide layer and a third oxide layer which are sequentially overlapped;
The third oxide layer is used as a cap layer;
the surface of the second oxide layer is flat, and the second oxide layer completely fills and covers the opening area of the metal hard mask layer on the surface of the metal hard mask layer;
In the second patterned etching, the second oxide layer is used as an etching stop layer.
10. The dual damascene process of claim 9 wherein: the second oxide layer is formed by adopting a low-temperature oxidation process.
11. The dual damascene process of claim 1, wherein: the bottom layer structure comprises a bottom layer interlayer film and a bottom layer metal layer, and each through hole is in contact with the bottom layer metal layer at the bottom.
12. The dual damascene process of claim 1, wherein: the material of the metal layer comprises copper.
13. The dual damascene process of claim 12 wherein: and forming the metal layer by adopting a copper electroplating process, and then flattening the metal layer by adopting a chemical mechanical polishing process.
14. The dual damascene process of claim 1, wherein: the through hole is positioned at the bottom of a partial region of the metal wire.
Priority Applications (1)
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| CN202410330053.3A CN118053809A (en) | 2024-03-21 | 2024-03-21 | Dual damascene process |
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