CN118051174A

CN118051174A - High-bandwidth DDR dual inline memory module, memory system and operation method thereof

Info

Publication number: CN118051174A
Application number: CN202211461023.3A
Authority: CN
Inventors: 黄磊; 敖海; 刘炎; 贾仪彬
Original assignee: Xindong Microelectronics Technology Wuhan Co ltd
Current assignee: Xindong Microelectronics Technology Wuhan Co ltd
Priority date: 2022-11-17
Filing date: 2022-11-17
Publication date: 2024-05-17

Abstract

The invention discloses a high-bandwidth DDR dual inline memory module, a memory system and an operation method thereof. The high bandwidth DDR dual inline memory module includes a divided clock latch driver, a combined data buffer, and a plurality of DRAM chip particles, wherein: a divided clock latch driver configured to change a length of a command when the command is transmitted to the combined data buffer; a combined data buffer configured to decode according to the flag bit and length of the command; a plurality of DRAM chip particles configured to perform an access operation in response to the decoded command. According to the invention, the frequency division clock latch driver is used for setting the enabling bit in the command when sending the command to the combined data buffer, dynamically changing the length of the command, expanding the format length of the original command, adding additional information after the command, enabling the command to have more effective information, and effectively improving the efficiency of processing the command without configuring an external register.

Description

High-bandwidth DDR dual inline memory module, memory system and operation method thereof

Technical Field

The invention belongs to the technical field of memories, and particularly relates to a high-bandwidth DDR dual-in-line memory module, a memory system and an operation method thereof.

Background

The Double Data Rate (DDR) synchronous dynamic random access memory (Synchronous Dynamic Random Access Memory, SDRAM) (also known as DRAM) standard, which is currently in widespread use, is adapted for DDR4 and DDR5 memories and provides a channel that can support Dual in-line-line Memory Module (DIMM) devices, which can record Data on both the rising and falling edges of the clock.

As DRAM technology continues to evolve, the IO speed gap between DRAM and host/controller is gradually increasing. But adding more DDR channels to increase DIMM bandwidth is not an effective solution due to limited routing resources on the package, DIMM, and PCB.

The interface between the existing clock latch driver (REGISTERING CLOCK DRIVER, RCD) and the Data Buffer (DB) is a Data Buffer control bus having a fixed length command format suitable for communication between the clock latch driver and the Data Buffer without the concept of a dummy channel.

The industry has proposed a high bandwidth DIMM (High Bandwidth Dual Inline Memory Module, HBDIMM) that divides the same channel of HBDIMM into an a-side and a B-side, called Pseudo Channels (PCs), and doubles the data rate by doubling the Pseudo Channels (PCs) of the same interface between the host CPU and the RCD without increasing the DRAM speed requirements. The speed of the pseudo channel between the RCD and DRAM is half the speed of the interface between the host CPU and the RCD.

In existing HBDIMM systems, the host CPU can send a continuous command to both pseudo channels and the clock latch driver will receive the second command during processing of the previous command. However, the existing clock latch driver must determine the content of the command sent to the data buffer when the first command is received and cannot be changed later, and the processing efficiency of the command is low.

Disclosure of Invention

In order to meet the above defects or improvement demands of the prior art, the invention provides a high-bandwidth DDR dual inline memory module, which has a command format with variable length, thereby effectively improving the command processing efficiency.

To achieve the above object, according to one aspect of the present invention, there is provided a high-bandwidth DDR dual inline memory module including a divided clock latch driver, a combined data buffer, and a plurality of DRAM chip particles, wherein:

The divided clock latch driver configured to change a length of a command when the command is sent to the combined data buffer;

the combined data buffer is configured to decode according to the flag bit and the length of the command;

a plurality of the DRAM chip particles configured to perform an access operation in response to the decoded command.

In some embodiments, the divided clock latch driver is configured to set an enable flag bit in the command for converting the command from a first length to a second length, wherein the first length is less than the second length.

In some embodiments, the divided clock latch driver is configured to add additional information after the command of the first length to be converted to the second length according to an enable flag bit.

In some implementations, the combined data buffer has a command decoder to stop decoding the command when the command is of the first length; and further configured to continue decoding the command when the command is of the second length.

In some embodiments, the divided clock latch driver is configured to set a plurality of enable flags in the command for converting the command from a first length to a third length, wherein the first length is less than the third length.

In some embodiments, the divided clock latch driver is configured to add first additional information after the command of the first length to be converted to a second length according to the plurality of enable flag bits; and adding second additional information behind the command with the second length according to the plurality of enable flag bits to convert the command into the third length, wherein the second length is smaller than the third length.

According to another aspect of the present invention, there is provided a memory system comprising a CPU and the above-described high bandwidth DDR dual inline memory module.

According to yet another aspect of the present invention, there is provided a method of operating a memory system comprising a host and a high bandwidth DDR dual inline memory module, the method comprising:

The host sends a command to a frequency division clock latch driver of the high-bandwidth DDR dual inline memory module;

The frequency division clock latch driver determines whether to change the length of the command according to the received command and sends the command to a combined data buffer of the high-bandwidth DDR dual-in-line memory module;

The combined data buffer decodes according to the length of the command and performs an access operation on a plurality of DRAM chip particles of the high bandwidth DDR dual inline memory module according to the decoded command.

In some implementations, the determining whether to change the length of the command and sending to the combined data buffer of the high bandwidth DDR dual inline memory module includes:

When it is determined to change the length of the command, the divided clock latch driver sets at least one enable flag bit in the command and adds additional information after the command, converting the command from a first length to a second length, wherein the first length is less than the second length;

the divided clock latch driver sends the command of the second length to the combined data buffer;

When it is determined not to change the length of the command, the divided clock latch driver directly sends the command to the combined data buffer.

In some embodiments, the decoding according to the length of the command comprises:

When the command is of the first length, the combined data buffer stops decoding the command;

when the command is of the second length, the combined data buffer continues to decode the command.

According to still another aspect of the present invention, there is provided an electronic apparatus including: the high bandwidth DDR dual inline memory module described above;

Or the electronic device comprises:

A processor;

a memory communicatively coupled to the processor;

The memory stores instructions executable by the processor to enable the processor to perform the method described above.

According to yet another aspect of the present invention, there is provided a computer readable storage medium storing computer instructions which, when executed by the processor, implement the above-described method.

In general, the above technical solutions conceived by the present invention have the following beneficial effects compared with the prior art: the frequency division clock latch driver is used for setting at least one enabling bit in the command when sending the command to the combined data buffer, dynamically changing the length of the command, and adding at least one piece of additional information behind the original command, so that the format length of the original command is expanded, more effective information is provided, the efficiency of processing the command is effectively improved, an external register is not required to be configured, and the efficiency of processing the command is effectively improved.

Drawings

FIG. 1 is a schematic diagram of a high bandwidth DDR dual inline memory module 100 according to one embodiment of the invention;

FIG. 2 is a schematic diagram of a variable command length format according to one embodiment of the invention;

FIG. 3 is a schematic diagram of a variable command length format according to another embodiment of the present invention;

FIG. 4 is a schematic diagram of the architecture of a high bandwidth storage system according to one embodiment of the present invention;

FIG. 5 is a flow chart of a method of operation of a high bandwidth storage system according to one embodiment of the invention;

Fig. 6 is a block diagram of an electronic device according to an embodiment of the invention.

Detailed Description

The present application will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present application more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application. As will be recognized by those of skill in the pertinent art, the described embodiments may be modified in various different ways without departing from the spirit or scope of the present application. Accordingly, the drawings and description are to be regarded as illustrative in nature and not as restrictive.

Fig. 1 is a schematic diagram of a high bandwidth DDR dual inline memory module 100 according to an embodiment of the present invention. As shown in fig. 1, each high-bandwidth DDR dual inline memory module 100 is divided into two sub-channels (sub-channels) on the left and right, each sub-Channel is further divided into A B sides, and each side is called a Pseudo Channel (PC), i.e., PC0 and PC1 in fig. 1. Each dummy channel includes a plurality of DRAM chip particles (not shown in fig. 1) for performing writing and reading of data, and the like. In an embodiment of the present invention, since the frequency of DCA (e.g. 6.4 GHz) is 2 times the QCA frequency (e.g. 3.2 GHz), the names of the clock latch drivers (Register Clock Rriver, RCD) are no longer appropriate, and more specific names will be used below: the divided Clock latches the drivers (REGISTER AND DIVIDED Clock Driver, RDCD) to avoid aliasing. In addition, the names of the combined data buffers (Combined Data Buffer, CDB) will also be used hereinafter to distinguish from existing data buffers.

In an embodiment of the present invention, the high bandwidth DDR dual inline memory module 100 includes a divided clock latch driver configured to change a length of a command when the command is sent to the combined data buffer and a combined data buffer configured to decode according to a flag bit and the length of the command. The high bandwidth DDR dual inline memory module 100 also includes a plurality of DRAM chip particles (not shown in FIG. 1) configured to perform corresponding access operations in response to the combined data buffer decoded commands.

In some embodiments, there is an interface BCOM between the divided clock latch driver and the combined data buffer through which the command to be sent to the combined data buffer is sent by the divided clock latch driver.

Since the commands of two pseudo channels in the same sub-channel can be independent, this presents challenges to the interface between the divided clock latch driver and the combined data buffer, which requires handling command information including, for example, pseudo channel ID, rank ID, and burst-length (burst-length). However, the existing fixed length command formats are not very efficient in meeting the requirements, as the existing commands can only be in a fixed long command format or in a plurality of short command formats. Taking the bcom_mrr (Mode REGISTER READ, read Mode register) command in the data buffer control bus protocol as an example, the existing bcom_mrr command has two forms: long commands and short commands. In the prior art, an external register is defined to inform the data buffer of the length of the bcom_mrr command, i.e. to inform the data buffer whether the bcom_mrr command is a long command or a short command, and the data buffer performs the corresponding processing. The external register is updated whenever the command length changes, for example, when the current long command is next to the short command, or when the current short command is next to the long command. This makes the system require an additional external register and reduces the efficiency of command processing, especially when the command length changes more frequently.

In some implementations, the divided clock latch driver is configured to set an enable flag bit in the command for converting the command from a first length to a second length, wherein the first length is less than the second length.

Fig. 2 is a schematic diagram of a variable command length format according to an embodiment of the present invention. In an embodiment of the present invention, the single input command between the host and the divided clock latch driver, the command between the divided clock latch driver and the combined data buffer has the shortest length. When the host sends, for example, a continuous instruction (i.e., a back-to-back instruction), the divided clock latch driver can set an enable flag bit in the command sent to the combined data buffer, so that the length of the command can be dynamically changed, the processing efficiency of the command is effectively improved, and no external register is required to be configured, so that the design is simpler and more efficient, and the processing efficiency of the command is further improved.

In some embodiments, the divided clock latch driver is configured to add additional information after the command of the first length to be converted to the second length according to the enable flag bit. When the frequency division clock latch driver sets the enable flag bit according to a preset rule, some additional information can be added behind the original command, so that the command is changed from the original first length to a second length added with the additional information.

Specifically, a flag bit may be defined in the last command period of the short command format, and the remaining information is appended to the tail of the short format bcom_mrr command. As shown in fig. 2, the short format bcom_mrr command has only two command periods Cycle No.0 and Cycle No.1, MRR command contents are transmitted in the command period Cycle No.0, command related information LONG, RK and CW are transmitted in the command period Cycle No.1, wherein the command is represented as a short format command when LONG is 0 and as a LONG format command when LONG is 1; select rank0 when RK is 0, select rank1 when RK is 1; the DRAM space is represented when CW is 0, and the combined data buffer space is represented when CW is 1. In the embodiment of the invention, LONG is selected as the enable flag bit, and when LONG is 0, the current command is a short format command. When the command is required to be changed into a LONG format command, the frequency division clock latch driver sets LONG to 1, and at the moment, the length of the command can be expanded, and the original short format command with 2 command periods is converted into a LONG format command with 5 command periods, so that the dynamic adjustment of the command format is realized.

In the embodiment of the invention, when the original command is changed from a short format command to a long format command, other additional information can be added behind the command. Specifically, as shown in fig. 2, when the LONG of the command Cycle No.1 is set to 1 and 3 command cycles Cycle No.2 to Cycle No.4 are added to the back of the command, the command is extended from the original 2 command cycles to 5 command cycles. And adding additional information after the original command, such as information to add RSV and MRA [7:6] at the added command period Cycle No.2, MRA [5:3] at the command period Cycle No.3, and MRA [2:0] at the command period Cycle No. 4. By dynamically changing the command length and adding additional information behind the original information, one command can add more effective information according to the needs, and a plurality of short commands in a fixed format are not needed, so that the command processing efficiency is effectively improved.

In some embodiments, the combined data buffer has a command decoder for stopping decoding a received command when the command is of a first length; and further for continuing to decode the received command when the command is of the second length. When a command is received by the combined data buffer, the command is decoded by its command decoder. Specifically, in the example of a variable command length format as shown in FIG. 2, the LONG bit is a flag bit that indicates whether the command is in a short format or a LONG format. The combined data buffer determines the length of the command based on the enable flag bit in the command, if long=0, indicating that the command is a short command, and no additional information is subsequently available, then the decoding of the current command is selected to be stopped, and a new command is started to be detected. If long=1, indicating that the command is a LONG command, followed by other additional information, the command decoder in the combined data buffer chooses to continue decoding the command to obtain the complete information for the LONG format command. As shown in fig. 2, when the flag bit LONG in the command Cycle No.1 is 1, which indicates that the following command cycles Cycle No.2 to Cycle No.4 have valid information, the command decoder in the combined data buffer continues to keep decoding for the command cycles Cycle No.2 to Cycle No. 4.

Fig. 3 is a schematic diagram of a variable command length format according to another embodiment of the present invention. In some embodiments, for a continuous read command with a dummy channel ID, a rank ID, and a burst length, a read command in a variable length command format may be as shown in FIG. 3. Specifically, the first command period Cycle No.0 of bcom_rd contains the command content CMD (2' b 11) and the dummy channel selection signal PC1ST, where PC1 st=0 indicates that the first command of the continuous read command is transmitted to the first dummy channel PC0, and PC1 st=1 indicates that the first command of the continuous read command is transmitted to the second dummy channel PC1. In the second command period Cycle No.1 of bcom_rd, including the enable flag bit PC2nd_en, the burst length signal BL1ST, and the rank select signal RK1ST, PC2 nd_en=0 indicates that there is no second command, PC2 nd_en=1 indicates that there is a second command sent to another dummy channel different from the first command selected, for example, when PC1 st=0 of the first command period Cycle No.0 indicates that the first command is sent to the first dummy channel PC0, then the second command at this time is sent to the second dummy channel PC1; when the first command Cycle No.0 has pc1st=1, which means that the first command is transmitted to the second dummy channel PC1, the second command at this time is transmitted to the first dummy channel PC0. Rk1st=0 indicates that the first command in the continuous read command is sent to rank0, rk1st=1 indicates that the first command in the continuous read command is sent to rank1. Bl1st=0 indicates that the burst length of the first command in the continuous read commands is BL16, and bl1st=1 indicates that the burst length of the first command in the continuous read commands is BC8.

In the embodiment of the present invention, when PC2 nd_en=1 in the second command period Cycle No.1 of bcom_rd, it indicates that there is a second command, corresponding to an increase in the length of the current original command, and there is a third command period Cycle No.2, including RSV, RK2ND, and BL2ND signals. I.e. the third command period No.2 exists when PC2 nd_en=1, wherein rk2 nd=0 indicates that the second command is sent to rank0 and rk2 nd=1 indicates that the second command is sent to rank1. Bl2nd=0 indicates that the burst length of the second command is BL16, and bl2nd=1 indicates that the burst length of the second command is BC8. It will be appreciated that in the high bandwidth DDR dual inline memory module of embodiments of the present invention, when the host sends a continuous read command to the divided clock latch driver, the divided clock latch driver sends a second command byte to the combined data buffer, and the flag bit PC2ND EN may be changed to tell the combined data buffer that the command is a long format command or a short format command.

In some embodiments, the divided clock latch driver is configured to set a plurality of enable flag bits in a command for converting the command from a first length to a third length, wherein the first length is less than the third length. The divided clock latch driver is configured to add first additional information to the command of the first length according to the plurality of enable flag bits to be converted into the second length; and adding second additional information after the command with the second length according to the plurality of enable flag bits to convert the command with the second length into a third length, wherein the second length is smaller than the third length. Specifically, taking fig. 2 as an example, RSV in the third command period Cycle No.2 may be used as an enable flag bit, where rsv=0 indicates that no further additional information needs to be added after the original command format length has been changed, and rsv=1 indicates that after the original command format length has been changed (i.e., from the original 2 command periods to 5 command periods), and further additional information needs to be added, the command length is further increased by another enable flag bit (i.e., RSV), for example, three command periods Cycle No.5 to Cycle No.7 (not shown in the figure) continue to be added, i.e., from 5 command periods to 8 command periods to add other necessary additional information. It will be appreciated that when rsv=0, the command decoder of the combined data buffer stops decoding at command Cycle No.4 and waits for detection of a subsequent command; when rsv=1, the command decoder of the combined data buffer continues to keep decoding for the command periods No.5 to Cycle No. 7.

It is understood that the enable flag bit may be located in any command period of the command, so long as it is guaranteed that at least one enable flag bit indicates a subsequent command length format change before the command is completely finished, and a variable length format is implemented.

In some embodiments, taking fig. 3 as an example, when the host sends a plurality of continuous read commands, an enable flag bit (e.g. RSV) may be configured in a third command Cycle No.2 of the bcom_rd, and when there is a third command after the second command, the rsv=1 may be used to make the command with the original format length expanded once expand twice, and other additional information may be added after the command Cycle No.2, so that the command length may be dynamically changed according to the requirement, and the command processing efficiency is improved.

It can be understood that the specific form of the selection of the enable bit and the additional information in the command can be configured according to the actual application requirement, which is not limited by the present invention.

By adopting the high-bandwidth DDR dual-inline memory module provided by the embodiment of the invention, the frequency division clock latch driver is used for setting the enabling zone bit in the command when sending the command to the combined data buffer, dynamically changing the length of the command, expanding the format length of the original command, adding additional information after the command, enabling the command to have more effective information, and effectively improving the efficiency of processing the command without configuring an external register.

Fig. 4 is a schematic diagram of a high bandwidth memory system 300 according to an embodiment of the present invention, including a CPU 200 and a high bandwidth DDR dual inline memory module 100 as described above. It will be appreciated that fig. 4 is merely exemplary and shows some of the modules connected and signal transmission relationships, and other modules such as a Memory Controller (MC) are not shown. In some embodiments, CPU 200 acts as a host for sending instructions to high bandwidth DDR dual inline memory module 100 and data to be written to DRAM particles, and also for receiving data to be read from high bandwidth DDR dual inline memory module 100. The divided clock latch driver of the high bandwidth DDR dual inline memory module 100 is configured to determine whether to change the format length of the command based on the command issued by the host, and to add additional information after the command of the first length by configuring at least one of the commands to be a flag bit if necessary, such that the command extends from the first length to the second length, wherein the first length is less than the second length.

For a more specific implementation manner of each module of the high-bandwidth storage system, reference may be made to the description of the high-bandwidth DDR dual inline memory module of the present invention, and similar advantageous effects will be obtained, and will not be described herein.

FIG. 5 is a flow chart of a method of operating a high bandwidth storage system according to an embodiment of the present invention, which specifically includes the following steps:

Step S1: the host sends a command to the divided clock latch driver of the high bandwidth DDR dual inline memory module. In some embodiments, the host sends different commands to the divided clock latch driver of the high bandwidth DDR dual inline memory module, including commands to be sent to the combined data buffer of the high bandwidth DDR dual inline memory module, and commands to be sent to multiple dummy channels of the high bandwidth DDR dual inline memory module. Specifically, commands to be sent by the divided clock latch driver to the combined data buffer may be sent through the BCOM interface between the two.

Step S2: the divided clock latch driver determines whether to change the length of the command according to the received command and sends the command to the combined data buffer of the high-bandwidth DDR dual inline memory module. In some embodiments, when it is determined to change the length of the command, the divided clock latches at least one enable flag bit in the driver set command and adds additional information after the command, converting the command from a first length to a second length, wherein the first length is less than the second length; the divided clock latch driver sends a command of a second length to the combined data buffer. Specifically, when the command length sent to the combined data buffer needs to be changed, the frequency division clock latches the enable bit in the driver configuration command, adds additional information behind the original command, dynamically increases the format length of the original command, enables one command to have more effective information, does not need to send by using a plurality of fixed-length commands as in the prior art, and effectively improves the efficiency of command processing.

In some implementations, the divided clock latch driver sends the command directly to the combined data buffer when it is determined not to change the length of the command. Specifically, when the command length sent to the combined data buffer does not need to be changed, the divided clock latch driver directly sends the command to the combined data buffer through the BCOM interface for subsequent operations.

Step S3: the combined data buffer decodes according to the length of the command and performs an access operation to a plurality of DRAM chip particles of the high bandwidth DDR dual inline memory module according to the decoded command. In some embodiments, the combined data buffer determines the length of the command based on an enable flag bit in the command, and stops decoding the command when the command is the first length; when the command is of the second length, the combined data buffer continues to decode the command. Specifically, when the combined data buffer determines that the command is in a short format according to the enable flag bit in the command, after decoding of a short format command period is completed, decoding of the command is stopped, and waiting for detection of the enable flag bit of a subsequent command is continued to determine the command length. When the combined data buffer determines that the command is in a long format according to the enable flag bit in the command, after the decoding of the short format command period is completed, the command is continuously decoded until the decoding is completed according to the increased command period.

It will be appreciated that the method of operation of the memory system described above is equally applicable between standard clock latch drivers and data buffers of a high bandwidth memory system or a multiple merge array dual in-line memory module (Multiplexer Combined RANKS DIMM), as the invention is not limited in this regard.

By adopting the operation method of the memory system, the host sends the command to the high-bandwidth DDR dual-inline memory module, the frequency division clock latch driver sets at least one enabling zone bit in the command when sending the command to the combined data buffer, at least one piece of additional information is added behind the original command, the length of the command is dynamically changed, the format length of the original command is expanded, more effective information is provided, and the efficiency of processing the command is effectively improved.

In the embodiment of the present invention, the DRAM memory particles may be DDR4, DDR5, DDR6, LPDDR or GDDR, or may be LPDDR4, LPDDR5 or LPDDR5x, or may be DRAM memory particles of other forms, which is not limited in this invention.

Fig. 6 is a block diagram of an electronic device according to an embodiment of the application. The embodiment of the application also provides an electronic device, as shown in fig. 6, which comprises: at least one processor 701, and a memory 703 communicatively coupled to the at least one processor 701. The memory 703 stores instructions executable by the at least one processor 701. The instructions are executed by at least one processor 701. The processor 701, when executing the instructions, implements the method of operation of the storage system in the above-described embodiments. The number of memory 703 and processors 701 may be one or more. The electronic device is intended to represent various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. The electronic device may also represent various forms of mobile devices, such as personal digital processing, cellular telephones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are meant to be exemplary only, and are not meant to limit implementations of the applications described and/or claimed herein.

The electronic device may further comprise a communication interface 705 for communicating with an external device for data interactive transmission. The various devices are interconnected using different buses and may be mounted on a common motherboard or in other manners as desired. The processor 701 may process instructions executing within the electronic device, including instructions stored in or on memory to display graphical information of a graphical user interface (GRAPHICAL USER INTERFACE, GUI) on an external input/output device, such as a display device coupled to the interface. In other embodiments, multiple processors and/or multiple buses may be used, if desired, along with multiple memories and multiple memories. Also, multiple electronic devices may be connected, each providing a portion of the necessary operations (e.g., as a server array, a set of blade servers, or a multiprocessor system). The bus may be classified as an address bus, a data bus, a control bus, etc. For ease of illustration, only one thick line is shown in fig. 6, but not only one bus or one type of bus.

Alternatively, in a specific implementation, if the memory 703, the processor 701, and the communication interface 705 are integrated on a chip, the memory 703, the processor 701, and the communication interface 705 may communicate with each other through internal interfaces.

It should be appreciated that the processor may be a central Processing unit (Central Processing Unit, CPU), other general purpose processor, digital signal processor (DIGITAL SIGNAL Processing, DSP), application SPECIFIC INTEGRATED Circuit (ASIC), field programmable gate array (Field Programmable GATE ARRAY, FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware components, or the like. A general purpose processor may be a microprocessor or any conventional processor or the like. It is noted that the processor may be a processor supporting an advanced reduced instruction set machine (ADVANCED RISC MACHINES, ARM) architecture.

The present application provides a computer-readable storage medium (such as the memory 703 described above) storing computer instructions that when executed by a processor implement the methods provided in the embodiments of the present application.

Alternatively, the memory 703 may include a storage program area and a storage data area, wherein the storage program area may store an operating system, at least one application program required for a function; the storage data area may store data created according to the use of the electronic device of the operation method of the storage system, and the like. In addition, the memory 703 may include high-speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, the memory 703 may optionally include memory located remotely from the processor 701, which may be connected to the electronics of the method of operation of the storage system via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.

In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.

Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.

Any process or method description in a flowchart or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more (two or more) executable instructions for implementing specific logical functions or steps of the process. And the scope of the preferred embodiments of the present application includes additional implementations in which functions may be performed in a substantially simultaneous manner or in an opposite order from that shown or discussed, including in accordance with the functions that are involved.

Logic and/or steps represented in the flowcharts or otherwise described herein, e.g., a ordered listing of executable instructions for implementing logical functions, can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions.

It is to be understood that portions of the present application may be implemented in hardware, software, firmware, or a combination thereof. In the above-described embodiments, the various steps or methods may be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. All or part of the steps of the methods of the embodiments described above may be performed by a program that, when executed, comprises one or a combination of the steps of the method embodiments, instructs the associated hardware to perform the method.

In addition, each functional unit in the embodiments of the present application may be integrated in one processing module, or each unit may exist alone physically, or two or more units may be integrated in one module. The integrated modules may be implemented in hardware or in software functional modules. The integrated modules described above, if implemented in the form of software functional modules and sold or used as a stand-alone product, may also be stored in a computer-readable storage medium. The storage medium may be a read-only memory, a magnetic or optical disk, or the like.

The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that various changes and substitutions are possible within the scope of the present application. Therefore, the protection scope of the application is subject to the protection scope of the claims.

Claims

1. A high bandwidth DDR dual inline memory module comprising a divided clock latch driver, a combined data buffer, and a plurality of DRAM chip particles, wherein:

2. The high bandwidth DDR dual inline memory module of claim 1, wherein the divided clock latch driver is configured to set an enable flag bit in the command to transition the command from a first length to a second length, wherein the first length is less than the second length.

3. The high bandwidth DDR dual inline memory module of claim 2, wherein the divided clock latch driver is configured to add additional information after the command of the first length to transition to the second length according to an enable flag bit.

4. The high bandwidth DDR dual inline memory module of claim 2, wherein said combined data buffer has a command decoder for stopping decoding said command when said command is of said first length; and further configured to continue decoding the command when the command is of the second length.

5. The high bandwidth DDR dual inline memory module of claim 1, wherein the divided clock latch driver is configured to set a plurality of enable flag bits in the command for converting the command from a first length to a third length, wherein the first length is less than the third length.

6. The high bandwidth DDR dual inline memory module of claim 5, wherein the divided clock latch driver is configured to add first additional information after the command of the first length to be converted to a second length according to the plurality of enable flag bits; and adding second additional information behind the command with the second length according to the plurality of enable flag bits to convert the command into the third length, wherein the second length is smaller than the third length.

7. A memory system comprising a CPU and a high bandwidth DDR dual inline memory module as claimed in any one of claims 1 to 6.

8. A method of operation of a memory system comprising a host and a high bandwidth DDR dual inline memory module, the method of operation comprising:

9. The method of operation of claim 8, wherein the determining whether to change the length of the command and send to the combined data buffer of the high bandwidth DDR dual inline memory module comprises:

10. The method of operation of claim 9, wherein said decoding according to the length of the command comprises:

11. An electronic device comprising the high bandwidth DDR dual inline memory module of any one of claims 1 to 6;

Or the electronic device comprises:

A processor;

a memory communicatively coupled to the processor;

the memory stores instructions executable by the processor to enable the processor to perform the method of any one of claims 8 to 10.

12. A computer readable storage medium storing computer instructions which, when executed by a processor, implement the method of any one of claims 8 to 10.