CN118043970A - Hybrid CMOS micro LED display layout - Google Patents

Abstract

A CMOS power supply layer is described that includes staggered contact regions (alternating V _led and V _cat contact regions) on at least two long sides of a μled display region. In this way, V _led and cathode current are injected uniformly along four sides of the μled display panel. The large cathode current distribution rings on the V _led and V _cat circuits are used to distribute current along the four sides of the panel. The current distribution ring surrounds the pixel die area. An insulating region on the cathode current redistribution ring adjacent to one of the plurality of microbumps may be included.

Description

Hybrid CMOS micro LED display layout

Technical Field

Embodiments of the present disclosure generally relate to Light Emitting Diode (LED) devices. More particularly, embodiments are directed to a layout structure of CMOS driver electronics for individually controlling pixel brightness of micro LEDs.

Background

A Light Emitting Diode (LED) is a semiconductor light source that emits visible light when current flows through it. An LED combines a p-type semiconductor with an n-type semiconductor. LEDs typically use group III compound semiconductors. Group III compound semiconductors provide stable operation at higher temperatures than devices using other semiconductors. Group III compounds are typically formed on a substrate formed of sapphire or silicon carbide (SiC).

LEDs have become attractive light sources for many applications. From the point of view of road signs and traffic signals, LEDs are currently dominant in general lighting, automotive, mobile electronic devices, camera flashes, display backlighting, gardening, and hygiene applications. Typical benefits of LEDs are increased efficiency, longer lifetime, and adaptability to a wide variety of form factors, as compared to competing light sources.

A highly compact pixelated Light Emitting Diode (LED) device (e.g., micro LED array for advanced automotive forward lighting) may include a monolithic large area high power LED die mixed with CMOS driver electronics for individual control of pixel brightness. A linear drive scheme is one of the most practical solutions for such control electronics, especially for large pixel array configurations.

The difficulties associated with this system involve CMOS wiring for all pixel contacts to power supply and interconnect to integrated circuit drivers. A cost effective solution must minimize the number of metal layers used for the power plane. However, minimizing the number of metal layers for the power supply layer may compromise the performance of the layout for uniformly distributing current, resulting in undesirable current crowding effects, where excessive current density levels negatively impact heat loss and reliability associated with electromigration at the contact interface.

Accordingly, there is a need for a layout architecture that optimizes current distribution in a hybrid LED die/CMOS monolithic architecture.

Disclosure of Invention

The techniques and embodiments of the present disclosure are directed to a CMOS power plane. In one or more embodiments, the CMOS power plane includes: a cathode redistribution ring having an inner portion surrounding the perimeter of the die pixel area and an outer portion including an area common supply voltage V _led interleaved with the cathode current distribution area; and a plurality of cathode micro-bumps contacting an inner portion of the cathode redistribution ring along a perimeter of the die pixel area.

Other embodiments of the present disclosure are directed to CMOS layouts. In one or more embodiments, the CMOS layout includes: a power layer on the substrate, the power layer having a plurality of alternating V _led contact areas and cathode contact areas uniformly dispersed along at least two sides of the power layer; cathode current redistribution rings extending along four sides of the power supply layer; a plurality of cathode micro-bumps connecting each of the plurality of alternating V _led contact areas and cathode contact areas to a corresponding p-contact of the plurality of pixels; and a common cathode grid electrically connecting the plurality of pixels and the plurality of micro bumps.

Other embodiments are directed to CMOS power planes. In one or more embodiments, the CMOS power plane includes: a cathode redistribution ring having an inner portion surrounding the perimeter of the die pixel area and an outer portion including an area common supply voltage V _led interleaved with the cathode current distribution area along the first, second, third and fourth sides of the CMOS power supply layer; and a plurality of cathode micro-bumps contacting an inner portion of the cathode redistribution ring along a perimeter of the die pixel area.

Other embodiments are directed to CMOS layouts. In one or more embodiments, the CMOS layout includes: a power layer on the substrate, the power layer having a plurality of alternating V _led contact areas and cathode contact areas dispersed along a first side, a second side, a third side, and a fourth side of the power layer; a cathode current redistribution ring extending along the first, second, third and fourth sides of the power supply layer; a plurality of cathode micro-bumps connecting each of the plurality of alternating V _led contact areas and cathode contact areas to a corresponding p-contact of the plurality of pixels; and a common cathode grid electrically connecting the plurality of pixels and the plurality of cathode micro-bumps.

Other embodiments are directed to CMOS power planes. In one or more embodiments, the CMOS power plane includes: a cathode redistribution ring having an inner portion surrounding the perimeter of the die pixel area and an outer portion including an area common supply voltage V _led interleaved with the cathode current distribution area; a plurality of cathode micro-bumps contacting an inner portion of the cathode redistribution ring along a perimeter of the die pixel area; and an insulating region on the cathode redistribution ring adjacent to one of the plurality of cathode micro-bumps.

Other embodiments are directed to CMOS layouts. In one or more embodiments, the CMOS layout includes: a power layer on the substrate, the power layer having a plurality of alternating V _led contact areas and cathode contact areas uniformly dispersed along at least two sides of the power layer; cathode current redistribution rings extending along four sides of the power supply layer; a plurality of cathode micro-bumps connecting each of the plurality of alternating V _led contact areas and cathode contact areas to a corresponding p-contact of the plurality of pixels; an insulating region on the cathode current redistribution ring adjacent to one of the plurality of cathode micro-bumps; and a common cathode grid electrically connecting the plurality of pixels and the plurality of cathode micro-bumps.

Drawings

So that the manner in which the above recited features of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this disclosure and are therefore not to be considered limiting of its scope, for the disclosure may admit to other equally effective embodiments. Embodiments as described herein are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings in which like reference numerals refer to similar elements.

The patent or application document contains at least one drawing in color. Copies of color drawing(s) of this patent or patent application publication will be provided by the patent office upon request and upon payment of the necessary fee.

FIG. 1A illustrates a top view of a CMOS top layer of a CMOS power supply layer in accordance with one or more embodiments;

FIG. 1B is a cross-sectional view taken along line A of FIG. 1A in accordance with one or more embodiments;

FIG. 1C is a cross-sectional view taken along line B of FIG. 1A in accordance with one or more embodiments;

FIG. 1D illustrates a top view of a CMOS second current distribution layer of the CMOS power supply layer of FIG. 1A in accordance with one or more embodiments;

FIG. 1E illustrates a top view of a common cathode of the CMOS power supply layer of FIG. 1A in accordance with one or more embodiments;

FIG. 2A illustrates a top view of a CMOS top layer of a CMOS power supply layer in accordance with one or more embodiments;

FIG. 2B illustrates a top view of a CMOS second current distribution layer of the CMOS power supply layer of FIG. 2A in accordance with one or more embodiments;

FIG. 2C illustrates a top view of a common cathode of the CMOS power supply layer of FIG. 2A in accordance with one or more embodiments;

FIG. 3A illustrates a top view of a CMOS top layer having an insulating region of a CMOS power supply layer in accordance with one or more embodiments;

FIG. 3B is an enlarged view of region 370 of the CMOS power supply layer of FIG. 3A in accordance with one or more embodiments;

FIG. 4A is a current density diagram of a CMOS power plane in accordance with one or more embodiments;

FIG. 4B is a current density diagram of a CMOS power plane in accordance with one or more embodiments;

FIG. 5A is a current density diagram of a microbump in accordance with one or more embodiments;

FIG. 5B is a current density diagram of a microbump in accordance with one or more embodiments; and

FIG. 6 illustrates a block diagram of an example of a visualization system using a μLED array of one or more embodiments.

To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. The figures are not drawn to scale. For example, the height and width of the mesa are not drawn to scale.

Detailed Description

Before describing several exemplary embodiments of the disclosure, it is to be understood that the disclosure is not limited to the details of construction or process steps set forth in the following description. The disclosure is capable of other embodiments and of being practiced or of being carried out in various ways.

The term "substrate" as used herein, according to one or more embodiments, refers to a structure, intermediate or final, having a surface or portion of a surface, upon which a process is performed. In addition, in some embodiments, references to a substrate also refer to only a portion of the substrate unless the context clearly indicates otherwise. Furthermore, according to some embodiments, mention may be made of deposition on a substrate comprising deposition on a bare substrate, or deposition on a substrate having one or more layers, films, features, or materials deposited or formed thereon.

In one or more embodiments, "substrate" means any substrate or surface of material formed on a substrate upon which film processing occurs during a fabrication process. In an exemplary embodiment, depending on the application, the substrate surface on which the processing is performed includes materials such as: silicon, silicon oxide, silicon-on-insulator (SOI), strained silicon, amorphous silicon, doped silicon, carbon doped silicon oxide, germanium, gallium arsenide, glass, sapphire, and any other suitable material such as metals, metal nitrides, group III-nitrides (e.g., gaN, alN, inN, and other alloys), metal alloys, and other conductive materials. The substrate includes, but is not limited to, a Light Emitting Diode (LED) device. In some embodiments, the substrate is exposed to a pretreatment process to polish, etch, reduce, oxidize, hydroxylate, anneal, UV cure, electron beam cure, and/or bake the substrate surface. In addition to film processing directly on the surface of the substrate itself, in some embodiments, any of the disclosed film processing steps are also performed on an underlayer formed on the substrate, and the term "substrate surface" is intended to include such underlayer as indicated above and below. Thus, for example, where a film/layer or a portion of a film/layer has been deposited onto a substrate surface, the exposed surface of the newly deposited film/layer becomes the substrate surface.

In this disclosure, the terms "wafer" and "substrate" will be used interchangeably. Thus, as used herein, a wafer is used as a substrate for forming the LED devices described herein.

For LED deployment for high density display applications or large area medium density applications, the characteristic size of the LED unit is desirably 100 microns or less, with typical values in the range of 8 to 25 microns. Such LEDs are commonly referred to as micro LEDs (μleds). Micro LED based micro display technology is still in the early stages of commercial deployment, but for some applications it is expected to slowly replace existing display technologies such as liquid crystal on silicon (LCDoS) or organic light emitting diode on silicon (oled) displays. One of the biggest obstacles to commercializing micro LED displays is the transfer technology by which pixelated LEDs are attached to a back plate.

Embodiments described herein describe CMOS driver electronics for individually controlling pixel brightness of micro LEDs. The CMOS power layer layout of one or more embodiments uses small staggered contact areas (alternating V _led and V _cat contact areas) on at least two long sides of the micro LED display area. In the CMOS power plane layout of one or more embodiments, it is advantageous that V _led and cathode current are injected uniformly along the four sides of the panel. Additionally, one large loop on the V _led and V _cat circuits is used to distribute current along four sides of the panel.

Complementary Metal Oxide Semiconductor (CMOS), also known as complementary symmetric metal oxide semiconductor (COS-MOS), is a type of Metal Oxide Semiconductor Field Effect Transistor (MOSFET) fabrication process that uses complementary and symmetric p-type and n-type MOSFET pairs to achieve logic functions. CMOS technology is used to construct Integrated Circuit (IC) chips. CMOS refers to a specific style of digital circuit design and a series of processes for implementing the circuit on an integrated circuit (chip). CMOS circuits consume less power than logic families with resistive loads.

The CMOS power circuit layout has two functions: a positive V _led potential is applied to each CMOS driver cell and a ground potential is applied to the pixel common cathode. For this purpose, two different circuits are required: (1) V _cat circuit: to electrically connect the CMOS ground contact to the common cathode grid of the LED pixel; and (2) a V _led potential circuit: to apply a positive potential (V _led) to each CMOS driver cell.

CMOS layouts can generally be divided into layers designated for digital circuits, small signal analog circuits, and power train (power train). The latter is preferably reduced to one or two layers (especially the topmost or bottommost layer) to facilitate current distribution and interconnection with external components (e.g., LED die). In regard to the latter, a peripheral ring around the die is typically used to connect the pixel common cathode grid to the V _cat circuit. In one or more embodiments, the ring connection is as close as possible to the die area to reduce ohmic losses. The interconnect between the common cathode and the ground circuit cannot be located in the die area because the minimum area required to interconnect the two layers may not fit into the current confinement space between the pixels. The interconnection of the common cathode grid to the power supply layer is achieved by micro-bumps of a size similar to the pixel size (about 40 x 40 μm). Since the current flowing through the entire device is very high and since the length of the first micro-bump row is limited, the current density in the micro-bumps is very high, thereby increasing the risk of reliability failure of the metal interconnect. Therefore, limiting the current density in the microbumps is a critical design requirement.

Furthermore, the thickness of the CMOS power supply layer is limited by process constraints. For example, the process thickness of CMOS power lines is limited to a few microns using sputtering or electroplating. As a result, the sheet resistance of the diffusion layer will be limited and the electrical losses in the diffusion layer will be significant. To solve this problem, an additional current distribution layer connected in parallel through a via is generally used.

Traditionally, CMOS power plane layout uses one portion of the CMOS backplate for V _led potential and another portion of the backplate for V _cat potential. In a conventional CMOS power plane layout, a u-shaped cathode circuit (with potential V _cat) surrounds the V _led circuit and is in contact with the microbumps. The u-shaped cathode circuit serves as a current distribution area for the cathode circuit. A problem with this configuration is that the cathode current is injected on three sides of the panel. The current in the second current distribution layer is forced to flow towards the side edges. Since it is not wide enough, the resistance is high. This is a major problem leading to non-uniform current distribution through the common cathode micro-bumps. With this CMOS layout, current is not injected uniformly along the four sides of the die area. As a result, one or more current distribution layers connected in parallel are required to uniformly distribute the cathode current on four sides of the LED pixel area and reduce the microbump current density.

Therefore, additional layers connected in parallel are required to redistribute the current along the remaining sides of the die area. Thus, the additional layer is primarily used to distribute current rather than reduce ohmic losses. As for V _led, current is injected on only one side of the panel, resulting in a significant voltage drop between the top and bottom sides of the die area. As a result, current distribution in the die area is not uniform and current density in the microbumps is very high.

1A-1C, one or more embodiments provide a CMOS power plane layout 100 in which small staggered cathode distribution areas (alternating V _cat and V _led contact areas 102, 104) and large cathode redistribution rings 112 are used for current distribution around the four sides of the die area. With this layout, the current is evenly distributed over four sides of the die area, and the additional current distribution layers connected in parallel may be used primarily to reduce ohmic losses. As a result, ohmic power loss and current density in the microbumps are significantly reduced. Furthermore, only one type of cathode micro Bump (microBump) (micro Bump (uBump) or micro Bump (μbump)) 106 is required, which simplifies the CMOS panel fabrication process.

Those skilled in the art will appreciate that the plurality of microbumps 106 are not drawn to scale for ease of illustration and that the microbumps 106 shown are shown as being larger than they actually are. Additionally, those skilled in the art will appreciate that several rows of microbumps 106 may be used for common cathode interconnect with CMOS (not shown in the figures). In practice, the minimum size of the microbumps is limited by process constraints. In a hybrid CMOS LED display of one or more embodiments, the diameter of the anode micro-bump is smaller than the pixel size and the cathode micro-bump 106 has the same or similar dimensions as the anode micro-bump 114.

An overview of a CMOS power plane 100 with staggered regions 102, 104 and a cathode redistribution ring 112 according to the present invention is shown in fig. 1A-1E. Fig. 1B and 1C are cross-sectional views 100A and 100B, respectively, of the μled display region 100 shown in fig. 1A, taken along lines a and B. Fig. 1A is a top view 100 of a CMOS top layer. Fig. 1D is a view 150 of a CMOS second current spreading layer. Fig. 1E is a view 155 of a common cathode.

Referring to fig. 1A-1C, in one or more embodiments, the CMOS power supply layer 120 uses small staggered contact areas (alternating V _led and V _cat contact areas) on at least two long sides 108 of the μled display region 100. As used herein, "staggered" refers to the spreading and alternating of V _led and cathode 102 contact regions such that the V _led contact region is adjacent to two cathode 102 contact regions. In this way, V _led and cathode 102 currents are injected uniformly along the four sides 108, 110 of the panel.

In one or more embodiments, the large cathode redistribution ring 112 on the V _cat circuit and the common supply voltage V _led 154 on the V _led circuit are used to distribute current along the four sides 108, 110 of the panel. Note that the cathode redistribution ring 112 of one or more embodiments is a complete ring and is not a u-ring. As shown, only the top and bottom sides of the display 100 are used for current injection. In one or more embodiments, the cathode redistribution ring 112 surrounds the pixel die area, the common cathode grid 130. Note that for ease of drawing, the common cathode grid 130 in fig. 1A has been drawn such that no grid covers the cathode micro-bumps 106 so that the cathode micro-bumps 106 can be seen. Those skilled in the art will appreciate that the common cathode grid 130 may extend over the cathode micro-bumps 106, as shown in fig. 1B and 1C.

The pixel die area, common cathode grid 130, includes a plurality of pixels 116, as shown in fig. 1B and 1C. Although only two pixels 116 are shown, one skilled in the art will appreciate that there may be any number of pixels depending on the size of the pixels 116 and the size of the die. In some embodiments, there may be 86 pixels. In other embodiments, there may be 170 pixels or more. The pixels 116 may have any suitable size known to those skilled in the art. In some embodiments, the pixels 116 may be 40 μm pixels, or 30 μm pixels, or 20 μm pixels.

In one or more embodiments, the staggered regions are made of at least three contact regions (alternating V _cat and V _led contact regions). In the embodiment shown in fig. 1A, the staggered regions are made of ten cathode contacts 102 and eight V _led contact 104 regions distributed periodically along two long sides 108 of the CMOS panel 100. In one or more embodiments, the greater the number of alternating V _led and cathode 102 contact areas, the better the current distribution will be. Thus, in one or more embodiments, more than three or more than five contact areas are used. In some embodiments, there are at least ten cathode 102 contact regions and at least eight V _led 104 contact regions.

In one or more embodiments, alternating V _led 104 and cathode 102 contact areas are located on both long sides 108 of CMOS panel 100 and are not located on both short sides 110 of panel 100.

Referring to fig. 1B and 1C, an architecture with a common cathode grid 130 and CMOS panel 120 raised (micro-bumps 114) to the p or anode contacts 124 of each pixel 116 is used. One advantage of this configuration is that the CMOS layout is symmetrical and the path length between the die area and the cathode contact is the same, providing good current injection uniformity. In one or more embodiments, the drive circuit 140 is used to control the current provided to each pixel individually.

In one or more embodiments, the staggered region length may vary between hundreds of micrometers and millimeters. In one or more embodiments, the staggered areas may be symmetrical. In other embodiments, the staggered areas may be asymmetric. Each interleaved region having a different polarity is electrically isolated by a region that is a few microns wide. In one or more embodiments, a top CMOS current spreading layer for the V _cat path is used, as it simplifies the interconnection to the common cathode contact. In some embodiments, a second current distribution layer (or multiple current distribution layers) is used for the V _led path. The V _led current will reach the second current distribution layer connected to the p-contact 124 of each driver cell through the electrical vias located on the contact areas. In one or more embodiments, large cathode redistribution rings 112 around four sides of the die area are used to evenly distribute current around the die.

Referring to fig. 1D, a top view of the CMOS second current spreading layer 150 is illustrated. In one or more embodiments, the common supply voltage V _led 154 surrounds the perimeter of the V _led grid 136 and includes the V _led 104 contact area. The common supply voltage V _led 154 has an interleaved cathode current distribution region 102. In one or more embodiments, the cathode current does not flow through the cathode current distribution area 102. Thus, in some not shown embodiments, the cathode current distribution region 102 may not be present, thus expanding the common supply voltage V _led 154.

FIG. 1E illustrates a common cathode 155 in accordance with one or more embodiments. The outer region of the cathode redistribution ring 112 overlaps the cathode micro bump 106. The cathode redistribution ring 112 surrounds the common cathode grid 130. The common cathode grid 130 contacts each pixel 116 on the pixel side.

In one or more embodiments not shown, an inverted architecture in which a common anode (rather than a common cathode) and CMOS panel are bumped into the n-contact of each pixel may alternatively be used. In this case, an NMOS transistor would be used in the driver 140 instead of a PMOS transistor.

Fig. 2A-2C illustrate an alternative embodiment in which a CMOS power plane layout 200 has small staggered cathode distribution areas 202, 204 (alternating V _cat and V _led contact areas 202, 204) and large cathode redistribution rings 212 for current distribution around the four sides of the die area. With this layout, the current is evenly distributed over four sides of the die area, and the additional current distribution layers connected in parallel may be used primarily to reduce ohmic losses. As a result, ohmic power loss and current density in the microbumps are significantly reduced. Furthermore, only one type of cathode micro Bump (microBump) (micro Bump (uBump) or micro Bump (μbump)) 206 is required, which simplifies the CMOS panel fabrication process.

Fig. 2A is a view 200 of the top layer of CMOS. Fig. 2B is a view 250 of a CMOS second current spreading layer. Fig. 2C is a view 255 of a common cathode.

Referring to fig. 2A, all four sides of the panel 200 may be used to place the staggered contact areas. In one or more embodiments, free space on the short side 210 of the panel is used to place addressing circuitry, driver components, sensors (sense), etc. The staggered V _led contact areas 204 and cathode 202 contact areas are placed around the four sides 208, 210 of the panel 200.

In one or more embodiments, large cathode redistribution rings 212 on the V _led and V _cat circuits are used to distribute current along the four sides 208, 210 of the panel. Note that cathode redistribution ring 212 of one or more embodiments is a complete ring and is not a u-ring. As shown, only the top and bottom sides of the display 200 are used for current injection. In one or more embodiments, cathode redistribution ring 212 surrounds a pixel die area, common cathode grid 230. The pixel die area 230 includes a plurality of pixels (not shown).

In one or more embodiments, the staggered region is made of at least three contact regions (alternating V _cat 202 contact regions and V _led contact regions). In the embodiment shown in fig. 2A, the staggered regions are made of ten cathode contacts 202 and eight V _led contact 204 regions distributed periodically along the four sides 208, 210 of the CMOS panel 200. In one or more embodiments, the greater the number of alternating V _led 204 and cathode 202 contact areas, the better the current distribution will be. Thus, in one or more embodiments, more than three or more than five contact areas are used. In some embodiments, there are at least ten cathode 202 contact regions and at least eight V _led 204 contact regions.

In one or more embodiments, alternating V _led 204 and cathode 202 contact areas are located on the long side 208 of the CMOS panel 200 and along the two short sides 210 of the panel 200.

In one or more embodiments, the staggered region length may vary between hundreds of micrometers and millimeters. In one or more embodiments, the staggered areas may be symmetrical. In other embodiments, the staggered areas may be asymmetric. Each interleaved region having a different polarity is electrically isolated by a region that is a few microns wide. In one or more embodiments, a top CMOS current spreading layer for the V _cat path is used, as it simplifies the interconnection to the common cathode contact. In some embodiments, a second current distribution layer (or multiple current distribution layers) is used for the V _led path. The V _led current will pass through the electrical vias located on the contact areas to the second current distribution layer connected to the p-contact of each driver cell. In one or more embodiments, large cathode redistribution rings 212 around four sides of the die area are used to evenly distribute current around the die.

Referring to fig. 2B, a CMOS second current spreading layer 250 is illustrated. In one or more embodiments, common supply voltage V _led 254 surrounds the perimeter of die region 230 and includes V _led contact area. The common supply voltage V _led 254 has an interleaved cathode current distribution region 202. In one or more embodiments, the cathode current does not flow through the cathode current distribution area 202. Thus, in some not shown embodiments, the cathode current distribution region 202 may not be present, thus expanding the common supply voltage V _led 254.

Fig. 2C illustrates a common cathode 255 in accordance with one or more embodiments. The outer region of the cathode redistribution ring 212 overlaps the cathode micro bump 206. Cathode redistribution ring 212 surrounds common cathode grid 230. The common cathode grid 230 contacts each pixel on the pixel side.

Traditionally, CMOS power layer V _cat layout has had a very high current density in the outermost cathode micro-bumps. This may be due to the fact that the external contact pads mainly supply current to the outermost corner cathode micro-bumps. Over time, high current densities and temperatures can accelerate the failure mechanism of intermetallic connections. If a crack or delamination occurs in one cathode microbump, current will not flow through that microbump, and the maximum current density of adjacent microbumps will also increase in turn.

Referring to fig. 3A and 3B, in one or more embodiments, a solution to reduce the current density in the micro-bumps 306 is to include an insulating region 360 between the outer V _cat pads in the common cathode grid 330 and the outermost micro-bumps 306 x. Fig. 3B is an enlarged view of region 370 of fig. 3A.

In one or more embodiments, the direct current between the outer V _cat pads in the common cathode grid 330 and the outermost corner micro-bumps 306x may then be reduced, and the current density in the cathode micro-bumps 306 may be correspondingly reduced. In one or more embodiments, the insulating region 360 allows for a reduced risk of failure of the outermost corner microbump 306x due to high current density. The insulating region 360 does not completely block current from reaching the outermost corner microbump 306x. For this purpose, there will be a gap 345 of at least 10 μm between the insulating region 360 and the outermost corner cathode micro-bump 306x. To reduce current injection on at least two micro bumps 306, the length of the insulating region 360 will be at least 80 μm. In one or more embodiments, the insulating region 360 includes two vertical etch lines to reduce current injection from both sides.

In some embodiments, insulating region 360 includes an etched opening. In other embodiments, the insulating region 360 comprises a dielectric material. Suitable dielectric materials include, but are not limited to, silicon oxide (SiO), silicon nitride (SiN), silicon carbide (SiC), aluminum oxide (AlOx), aluminum nitride (AlN), and combinations thereof. Those skilled in the art will recognize that the use of a chemical formula such as SiO to represent silicon oxide does not imply any particular stoichiometric relationship between elements. The chemical formula merely identifies the major elements of the film.

Visualization systems (such as virtual reality systems and augmented reality systems) are becoming increasingly popular in areas such as entertainment, education, medicine, and commerce.

In a virtual reality system, a display may present a view of a scene (such as a three-dimensional scene) to a user. The user may move within the scene, such as by repositioning the user's head or by walking. The virtual reality system may detect movement of the user and change the view of the scene to interpret the movement. For example, as the user rotates the user's head, the system may present views of the scene that change in view direction to match the user's gaze. In this way, the virtual reality system may simulate the presence of a user in a three-dimensional scene. Further, the virtual reality system may receive tactile sensory input, such as from a wearable position sensor, and may optionally provide tactile feedback to the user.

In an augmented reality system, a display may incorporate elements from the user's surroundings into a view of the scene. For example, the augmented reality system may add text subtitles and/or visual elements to a view of the user's surroundings. For example, retailers may use augmented reality systems to show a user what a piece of furniture would look like in a room in the user's home by incorporating a visualization of the piece of furniture over a captured image of the user's surroundings. When a user walks in the user's room, the visualization takes into account the user's motion and changes the visualization of the furniture in a manner consistent with that motion. For example, an augmented reality system may place a virtual chair in a room. A user may stand in front of a virtual chair position in a room to view the front of the chair. The user may move within the room to an area behind the virtual chair position to view the back side of the chair. In this way, the augmented reality system may add elements to the dynamic view of the user's surroundings.

Fig. 6 illustrates a block diagram of an example of a visualization system 10 utilizing a μled array of one or more embodiments. The visualization system 10 may include a wearable housing 12, such as a headset or goggles. The housing 12 may mechanically support and house the elements described in detail below. In some examples, one or more of the elements detailed below may be included in one or more additional housings that may be separate from the wearable housing 12 and may be coupled to the wearable housing 12 wirelessly and/or via a wired connection. For example, a separate housing may reduce the weight of the wearable eyewear, such as by including batteries, radios, and other elements. The housing 12 may include one or more batteries 14 that may power any or all of the elements described in detail below. The housing 12 may include circuitry that may be electrically coupled to an external power source, such as a wall outlet, to charge the battery 14. The housing 12 may include one or more radios 16 to communicate wirelessly with a server or network via a suitable protocol, such as WiFi.

The visualization system 10 may include one or more sensors 18, such as optical sensors, audio sensors, tactile sensors, thermal sensors, gyroscopic sensors, time-of-flight sensors, triangulation-based sensors, and the like. In some examples, one or more of these sensors may sense a location, position, and/or orientation of the user. In some examples, one or more sensors 18 may generate sensor signals in response to a sensed location, position, and/or orientation. The sensor signals may include sensor data corresponding to the sensed location, position, and/or orientation. For example, the sensor data may include a depth map of the surrounding environment. In some examples, such as for an augmented reality system, one or more sensors 18 may capture real-time video images of the surrounding environment in the vicinity of the user.

Visualization system 10 may include one or more video generation processors 20. The one or more video generation processors 20 may receive scene data representing a three-dimensional scene, such as a set of position coordinates of objects in the scene or a depth map of the scene, from a server and/or a storage medium. The one or more video generation processors 20 may receive one or more sensor signals from the one or more sensors 18. In response to scene data representative of the surrounding environment and at least one sensor signal representative of a location and/or orientation of a user relative to the surrounding environment, one or more video generation processors 20 may generate at least one video signal corresponding to a view of the scene. In some examples, one or more video generation processors 20 may generate two video signals, one for each eye of the user, representing views of a scene as seen from the perspective of the left and right eyes of the user, respectively. In some examples, one or more video generation processors 20 may generate more than two video signals and combine the video signals to provide one video signal for both eyes, two video signals for both eyes, or other combinations.

Visualization system 10 may include one or more light sources 22 that may provide light to a display of visualization system 10. Suitable light sources 22 may include light emitting diodes, monolithic light emitting diodes, a plurality of light emitting diodes, an array of light emitting diodes disposed on a common substrate, a segmented light emitting diode having individually addressable and controllable (and/or grouped and/or sub-group controllable) light emitting diode elements disposed on a single substrate, an array of micro light emitting diodes (microLED), and so forth.

The light emitting diode may be a white light emitting diode. For example, a white light emitting diode may emit excitation light, such as blue or violet light. White light emitting diodes may include one or more phosphors that may absorb some or all of the excitation light, and in response may emit phosphor light (such as yellow light) having a wavelength greater than the wavelength of the excitation light.

One or more of the light sources 22 may include light emitting elements having different colors or wavelengths. For example, the light source may include a red light emitting diode that may emit red light, a green light emitting diode that may emit green light, and a blue light emitting diode that may emit blue light. The red, green, and blue light are combined in a particular ratio to produce any suitable color that is visually perceivable in the visible portion of the electromagnetic spectrum.

Visualization system 10 may include one or more modulators 24. Modulator 24 may be implemented in one of at least two configurations.

In a first configuration, modulator 24 may include circuitry that may directly modulate light source 22. For example, light source 22 may comprise an array of light emitting diodes, and modulator 24 may directly modulate the electrical power, voltage, and/or current directed to each light emitting diode in the array to form modulated light. The modulation may be performed in an analog manner and/or in a digital manner. In some examples, light source 22 may include a red light emitting diode array, a green light emitting diode array, and a blue light emitting diode array, and modulator 24 may directly modulate the red light emitting diodes, green light emitting diodes, and blue light emitting diodes to form modulated light to produce a particular image.

In a second configuration, modulator 24 may include a modulation panel, such as a liquid crystal panel. The light source 22 may produce uniform illumination or near uniform illumination to illuminate the modulation panel. The modulation panel may include pixels. Each pixel may selectively attenuate a corresponding portion of the modulation panel region in response to an electrical modulation signal to form modulated light. In some examples, modulator 24 may include multiple modulation panels that may modulate different colors of light. For example, modulator 24 may include a red modulation panel that may attenuate red light from a red light source (such as a red light emitting diode), a green modulation panel that may attenuate green light from a green light source (such as a green light emitting diode), and a blue modulation panel that may attenuate blue light from a blue light source (such as a blue light emitting diode).

In some examples of the second configuration, modulator 24 may receive uniform white light or near uniform white light from a white light source (such as a white light emitting diode). The modulation panel may include a wavelength selective filter on each pixel of the modulation panel. The panel pixels may be arranged in groups (such as three or four groups), where each group may form one pixel of a color image. For example, each group may include a panel pixel having a red filter, a panel pixel having a green filter, and a panel pixel having a blue filter. Other suitable configurations may also be used.

Visualization system 10 may include one or more modulation processors 26, which one or more modulation processors 26 may receive video signals (such as from one or more video generation processors 20) and may generate an electrically modulated signal in response. For configurations in which modulator 24 directly modulates light source 22, the electrically modulated signal may drive light source 24. For configurations in which modulator 24 comprises a modulation panel, the electrical modulation signal may drive the modulation panel.

Visualization system 10 may include one or more beam combiners 28 (also referred to as beam splitters 28) that may combine beams of different colors to form a single polychromatic beam. For configurations in which light source 22 may include a plurality of different colored light emitting diodes, visualization system 10 may include one or more wavelength-sensitive (e.g., dichroic) beam splitters 28 that may combine different colored light to form a single polychromatic light beam.

The visualization system 10 may direct the modulated light toward the eye of the viewer in one of at least two configurations. In a first configuration, visualization system 10 may function as a projector and may include suitable projection optics 30 that may project modulated light onto one or more screens 32. The screen 32 may be positioned at a suitable distance from the user's eyes. The visualization system 10 may optionally include one or more lenses 34, which one or more lenses 34 may position the virtual image of the screen 32 at a suitable distance from the eye, such as a close-focus (close-focus) distance, such as 500mm, 750mm, or another suitable distance. In some examples, visualization system 10 may include a single screen 32 such that modulated light may be directed toward both eyes of a user. In some examples, visualization system 10 may include two screens 32 such that modulated light from each screen 32 may be directed toward a respective eye of a user. In some examples, visualization system 10 may include more than two screens 32. In a second configuration, the visualization system 10 may direct modulated light directly into one or both eyes of the viewer. For example, projection optics 30 may form an image on the retina of one eye of the user, or on each of the two eyes of the user.

For some configurations of augmented reality systems, the visualization system 10 may include an at least partially transparent display such that a user may view the user's surroundings through the display. For such a configuration, the augmented reality system may generate an enhanced modulated light corresponding to the ambient environment, rather than the ambient environment itself. For example, in an example where a retailer presents a chair, the augmented reality system may direct modulated light corresponding to the chair, rather than the rest of the room, toward the screen or toward the eyes of the user.

The present disclosure will now be described with reference to the following examples. Before describing several exemplary embodiments of the disclosure, it is to be understood that the disclosure is not limited to the details of construction or process steps set forth in the following description. The disclosure is capable of other embodiments and of being practiced or of being carried out in various ways.

Example

Comparative example 1

A CMOS layout with two current distribution layers is formed. The CMOS layout has a u-shaped cathode ring. The current density of the CMOS layout is calculated. As shown in fig. 4A, the current density is non-uniform.

Example 2

A CMOS layout with eight staggered current distribution areas is formed. The current density of a CMOS layout with eight staggered current distribution areas is calculated. As shown in fig. 4B, the current density is uniform.

Table 1 shows a comparison of power loss between a comparative example 1CMOS layout with two current distribution layers and an example 2CMOS layout with staggered areas on the bottom and top panel sides and with continuous current distribution loops. In the power plane layout of one or more embodiments, ohmic losses are reduced by more than 40%. The average current density through the cathode microbumps is also much lower.

Table 1: comparison of Power loss

Example 3

A CMOS layout with eight staggered current distribution areas is formed. The layout has no insulating area between the external V _cat pads and the outermost microbump vias. The current density was measured and is shown in fig. 7A.

Example 4

A CMOS layout with eight staggered current distribution areas is formed. The layout has an insulating region between the external V _cat pad and the outermost microbump via. The current density is measured. Fig. 5A and 5B compare the current densities in the cathode micro-bumps between the layout with (example 4) and without (example 3) the insulating region between the outer V _cat contact region and the outermost corner micro-bump. The current density in the outermost corner cathode microbumps of the layout with insulating regions is reduced by more than 30%.

Examples

Various embodiments are listed below. It will be appreciated that the embodiments listed below may be combined with all aspects and other embodiments according to the scope of the invention.

Example (a). A CMOS power plane comprising: a cathode redistribution ring having an inner portion surrounding the perimeter of the die pixel area and an outer portion including a common supply voltage V _led interleaved with the cathode current distribution area; and a plurality of cathode micro-bumps contacting an inner portion of the cathode redistribution ring along a perimeter of the die pixel area.

Example (b). The CMOS power plane of embodiment (a) wherein the common supply voltage V _led and the cathode current distribution region are staggered on both sides of the die pixel region.

Example (c). The CMOS power plane of embodiments (a) through (b) wherein the common supply voltage V _led and the cathode current distribution region are interleaved on four sides of the die pixel region.

Example (d). The CMOS power plane of embodiments (a) through (c) wherein there are at least three common supply voltages V _led interleaved with at least three cathode current distribution regions.

Example (e). The CMOS power supply layer of embodiments (a) through (d) further comprising an insulating region on the cathode redistribution ring adjacent to one of the plurality of cathode micro-bumps.

Example (f). The CMOS power supply layer according to embodiments (a) to (e), wherein the insulating region comprises an etch line.

Example (g). The CMOS power supply layer according to embodiments (a) through (f), wherein the insulating region comprises a dielectric material.

Example (h). The CMOS power plane of embodiments (a) through (g) further comprising a plurality of PMOS transistors connected to the die pixel area.

Example (i). The CMOS power supply layer according to embodiments (a) through (h), wherein the plurality of cathode micro-bumps are electrically connected to a common cathode grid.

Example (j). The CMOS power plane of embodiments (a) through (i), wherein the die pixel area comprises a plurality of pixels.

Example (k). The CMOS power supply layer according to embodiments (a) through (j), wherein the insulating region has a size greater than 80 μm.

Example (l). A CMOS layout comprising: a power layer on the substrate, the power layer having a plurality of alternating V _led contact areas and cathode contact areas uniformly dispersed along at least two sides of the power layer; cathode current redistribution rings extending along four sides of the power supply layer; a plurality of cathode micro-bumps connecting each of the plurality of alternating V _led contact areas and cathode contact areas to a corresponding p-contact of the plurality of pixels; and a common cathode grid electrically connecting the plurality of pixels and the plurality of cathode micro-bumps.

Example (m). The CMOS layout of embodiment (i) wherein the V _led contact regions and the cathode contact regions are staggered on both sides.

Example (n). The CMOS layout of embodiments (i) through (m) wherein the V _led contact regions and the cathode contact regions are staggered on four sides.

Example (o). The CMOS layout of embodiments (1) through (n) wherein there are at least three V _led contact regions alternating with at least three cathode contact regions.

Example (p). The CMOS layout of embodiments (1) through (o) further comprising an insulating region on the cathode current redistribution ring adjacent to one of the plurality of cathode micro-bumps.

Example (q). The CMOS layout of embodiments (l) through (p) wherein the insulating region comprises an etch line.

Example (r). The CMOS layout of embodiments (l) through (q) wherein the insulating region comprises a dielectric material.

Example(s). The CMOS layout according to embodiments (l) through (r) further comprising a plurality of PMOS transistors connected in parallel with at least one of the plurality of pixels.

Example (t). The CMOS layout according to embodiments (1) to(s) wherein the size of the insulating region is greater than 80 μm.

Example (u). A CMOS power plane comprising: a cathode redistribution ring having an inner portion surrounding the perimeter of the die pixel area and an outer portion including an area common supply voltage V _led interleaved with the cathode current distribution area along the first, second, third and fourth sides of the CMOS power supply layer; and a plurality of cathode micro-bumps contacting an inner portion of the cathode redistribution ring along a perimeter of the die pixel area.

Example (v). The CMOS power plane of embodiment (u) wherein there are at least three common supply voltage V _led regions interleaved with at least three cathode current distribution regions.

Example (w). The CMOS power supply layer of embodiments (u) through (v) further comprising an insulating region on the cathode redistribution ring adjacent to one of the plurality of cathode micro-bumps.

Example (x). The CMOS power supply layer according to embodiments (u) through (w), wherein the insulating region comprises an etch line.

Example (y). The CMOS power supply layer according to embodiments (u) through (x), wherein the insulating region comprises a dielectric material.

Example (z). The CMOS power plane of embodiments (u) through (y) further comprising a plurality of PMOS transistors connected to the die pixel area.

Example (aa). The CMOS power supply layer according to embodiments (u) through (z), wherein the plurality of cathode micro-bumps are electrically connected to a common cathode grid.

Example (bb). The CMOS power supply layer of embodiments (u) through (aa) wherein said die pixel area comprises a plurality of pixels.

Example (cc). The CMOS power supply layer according to embodiments (u) through (bb), wherein the insulating region has a size greater than 80 μm.

Example (dd). The CMOS power supply layer according to embodiments (u) through (cc), wherein the insulating region is at least 10 μm away from one of the plurality of cathode micro-bumps.

Example (ee). A CMOS layout comprising: a power layer on the substrate, the power layer having a plurality of alternating V _led contact areas and cathode contact areas dispersed along a first side, a second side, a third side, and a fourth side of the power layer; a cathode current redistribution ring extending along the first, second, third and fourth sides of the power plane; a plurality of cathode micro-bumps connecting each of the plurality of alternating V _led contact areas and cathode contact areas to a corresponding p-contact of the plurality of pixels; and a common cathode grid electrically connecting the plurality of pixels and the plurality of cathode micro-bumps.

Example (ff). The CMOS layout according to embodiment (ee) wherein there are at least three V _led contact areas alternating with at least three cathode contact areas.

Example (gg). The CMOS layout of embodiments (ee) through (ff) further comprising an insulating region on the cathode current redistribution ring adjacent to one of the plurality of cathode micro-bumps.

Example (hh). The CMOS layout according to embodiments (ee) through (gg) wherein the insulating region comprises an etched line.

Example (ii). The CMOS layout according to embodiments (ee) through (hh) further comprising a plurality of PMOS transistors connected in parallel with at least one of the plurality of pixels.

Example (jj). The CMOS power supply layer according to embodiments (ee) to (ii), wherein the size of the insulating region is greater than 80 μm.

Example (kk). The CMOS layout of embodiments (ee) through (jj) wherein said insulating region is at least 10 μm away from one of said plurality of cathode micro-bumps.

Example (ll). The CMOS layout according to embodiments (ee) through (kk) wherein said insulating region comprises a dielectric material.

Example (mm). The CMOS layout of embodiments (ee) through (ll) wherein alternating V _led contact regions and cathode contact regions are uniformly dispersed along the first, second, third, and fourth sides of the power plane.

Example (nn). A CMOS power plane comprising: a cathode redistribution ring having an inner portion surrounding the perimeter of the die pixel area and an outer portion including an area common supply voltage V _led interleaved with the cathode current distribution area; a plurality of cathode micro-bumps contacting an inner portion of the cathode redistribution ring along a perimeter of the die pixel area; and an insulating region on the cathode redistribution ring adjacent to one of the plurality of cathode micro-bumps.

Example (oo). The CMOS power plane of embodiment (nn) wherein the common supply voltage V _led and the cathode current distribution region are interleaved on both sides of the die pixel region.

Example (pp). The CMOS power plane of embodiments (nn) through (oo) wherein the common supply voltage V _led and the cathode current distribution region are interleaved on four sides of the die pixel region.

Example (qq). The CMOS power plane of embodiments (nn) through (pp) wherein there are at least three common supply voltages V _led interleaved with at least three cathode current distribution regions.

Example (rr). The CMOS power supply layer according to embodiments (nn) through (qq), wherein the insulating region includes an etch line.

Example (ss). The CMOS power supply layer according to embodiments (nn) through (rr) wherein the insulating region comprises a dielectric material.

Example (tt). The CMOS power plane of embodiments (nn) through (ss) wherein the plurality of cathode micro-bumps are electrically connected to a common cathode grid.

Example (uu). The CMOS power plane of embodiments (nn) through (tt), wherein the die pixel area includes a plurality of pixels.

Example (v). The CMOS power supply layer according to embodiments (nn) to (uu), wherein the size of the insulating region is greater than 80 μm.

Example (ww). The CMOS power supply layer according to embodiments (nn) through (v) wherein the insulating region is at least 10 μm away from one of the plurality of cathode micro-bumps.

Example (xx). The CMOS power plane of embodiments (nn) through (ww) wherein there are eight common supply voltages V _led interleaved with ten cathode current distribution regions.

Example (yy). A CMOS layout comprising: a power layer on the substrate, the power layer having a plurality of alternating V _led contact areas and cathode contact areas uniformly dispersed along at least two sides of the power layer; cathode current redistribution rings extending along four sides of the power supply layer; a plurality of cathode micro-bumps connecting each of the plurality of alternating V _led contact areas and cathode contact areas to a corresponding p-contact of the plurality of pixels; an insulating region on the cathode current redistribution ring adjacent to one of the plurality of cathode micro-bumps; and a common cathode grid electrically connecting the plurality of pixels and the plurality of cathode micro-bumps.

Example (zz). The CMOS layout of embodiment (yy) wherein the V _led contact regions and cathode contact regions are staggered on both sides.

Example (aaa). The CMOS layout of embodiments (yy) through (zz) wherein the V _led contact regions and the cathode contact regions are staggered on four sides.

Example (bbb). The CMOS layout of embodiments (yy) through (aaa) wherein there are at least three V _led contact regions alternating with at least three cathode contact regions.

Example (ccc). The CMOS layout of embodiments (yy) through (bbb) wherein the insulating region comprises an etch line.

Example (ddd). The CMOS layout of embodiments (yy) through (ccc) wherein the insulating region comprises a dielectric material.

Example (eee). The CMOS layout of embodiments (yy) through (ddd) further comprising a plurality of PMOS transistors connected in parallel with at least one of the plurality of pixels.

Example (fff). The CMOS layout of embodiments (yy) through (eee) wherein the insulating region has a size greater than 80 μm.

Example (ggg). The CMOS layout of embodiments (yy) through (fff) wherein said insulating region is at least 10 μm away from one of said plurality of cathode micro bumps.

The use of the terms "a" and "an" and "the" and similar referents in the context of describing the materials and methods discussed herein (especially in the context of the following claims) are to be construed to cover both the singular and the plural, unless otherwise indicated herein or clearly contradicted by context. Recitation of ranges of values herein are merely intended to serve as a shorthand method of referring individually to each separate value falling within the range, unless otherwise indicated herein, and each separate value is incorporated into the specification as if it were individually recited herein. All methods described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The use of any and all examples, or exemplary language (e.g., "such as") provided herein, is intended merely to better illuminate the materials and methods and does not pose a limitation on the scope unless otherwise claimed. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the disclosed materials and methods.

Throughout this specification, references to the terms first, second, third, etc. may be used herein to describe various elements, and these elements should not be limited by these terms. These terms may be used to distinguish one element from another element.

Throughout this specification, reference to a layer, region, or substrate being "on" or extending "onto" another element means that it can be directly on or extend directly onto the other element, or intervening elements may also be present. When an element is referred to as being "directly on" or "directly extending onto" another element, there may be no intervening elements present. In addition, when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element and/or be connected or coupled to the other element via one or more intervening elements. When an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present between the element and the other element. It will be understood that these terms are intended to encompass different orientations of the element in addition to any orientation depicted in the figures.

Relative terms such as "below," "above," "upper," "lower," "horizontal" or "vertical" may be used herein to describe one element, layer or region's relationship to another element, layer or region as illustrated in the figures. It will be understood that these terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

Reference throughout this specification to "one embodiment," "certain embodiments," "one or more embodiments," or "an embodiment" means that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, appearances of the phrases such as "in one or more embodiments," "in some embodiments," "in one embodiment," or "in an embodiment" in various places throughout this specification are not necessarily referring to the same embodiment of the disclosure. The particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments.

Although the present disclosure has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made in the methods and apparatus of the present disclosure without departing from the spirit or scope of the disclosure. Accordingly, it is intended that the present disclosure include modifications and variations that are within the scope of the appended claims and their equivalents.

Claims (20)

1. A CMOS power plane comprising:

a cathode redistribution ring having an inner portion surrounding the perimeter of the die pixel area and an outer portion including a common supply voltage V _led interleaved with the cathode current distribution area; and

A plurality of cathode micro-bumps contacting an inner portion of the cathode redistribution ring along a perimeter of the die pixel area.

2. The CMOS power plane of claim 1, wherein the common supply voltage V _led and the cathode current distribution region are interleaved on both sides of the die pixel region.

3. The CMOS power plane of claim 1, wherein the common supply voltage V _led and the cathode current distribution region are interleaved on four sides of the die pixel region.

4. The CMOS power plane of claim 1, wherein there are at least three common supply voltages V _led interleaved with at least three cathode current distribution regions.

5. The CMOS power supply layer of claim 1 further comprising an insulating region on said cathode redistribution ring adjacent to one of said plurality of cathode micro-bumps.

6. The CMOS power plane of claim 5, wherein the insulating region comprises an etch line.

7. The CMOS power plane of claim 5, wherein the insulating region comprises a dielectric material.

8. The CMOS power plane of claim 1, further comprising a plurality of PMOS transistors connected to the die pixel area.

9. The CMOS power supply layer of claim 1 wherein said plurality of cathode micro-bumps are electrically connected to a common cathode grid.

10. The CMOS power plane of claim 1, wherein the die pixel area comprises a plurality of pixels.

11. The CMOS power plane of claim 5, wherein the insulating region has a dimension greater than 80 μιη.

12. A CMOS layout comprising:

A power layer on a substrate, the power layer having a plurality of alternating V _led contact areas and cathode contact areas uniformly dispersed along at least two sides of the power layer;

a cathode current redistribution ring extending along four sides of the power supply layer;

a plurality of cathode micro-bumps connecting each of the plurality of alternating V _led contact regions and the cathode contact region to a corresponding p-contact of a plurality of pixels; and

A common cathode grid electrically connecting the plurality of pixels and the plurality of cathode micro-bumps.

13. The CMOS layout of claim 12 wherein said V _led contact regions and said cathode contact regions are staggered on both sides.

14. The CMOS layout of claim 12 wherein said V _led contact regions and said cathode contact regions are staggered on four sides.

15. The CMOS layout of claim 12 wherein there are at least three V _led contact regions alternating with at least three cathode contact regions.

16. The CMOS layout of claim 12 further comprising an insulating region on said cathode current redistribution ring adjacent to one of said plurality of cathode micro-bumps.

17. The CMOS power plane of claim 16, wherein the insulating region comprises an etch line.

18. The CMOS power supply layer of claim 17 wherein said insulating region comprises a dielectric material.

19. The CMOS layout of claim 12 further comprising a plurality of PMOS transistors connected in parallel with at least one of the plurality of pixels.

20. The CMOS layout of claim 16 wherein the insulating region is greater than 80 μm in size.