CN118042818A

CN118042818A - Integrated circuit device and method of forming the same

Info

Publication number: CN118042818A
Application number: CN202410084650.2A
Authority: CN
Inventors: 林高正; 藤原英弘; 钟彦麟; 詹伟闵; 陈炎辉
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2023-01-24
Filing date: 2024-01-19
Publication date: 2024-05-14

Abstract

An Integrated Circuit (IC) device includes a memory array including a plurality of memory cells, a first word line located above the memory array and electrically coupled to at least one first memory cell of the plurality of memory cells, and a second word line located below the memory array and electrically coupled to at least one second memory cell of the plurality of memory cells. Each memory cell of the plurality of memory cells includes a Complementary Field Effect Transistor (CFET) device. Embodiments of the application also relate to a method of forming an integrated circuit device.

Description

Integrated circuit device and method of forming the same

Technical Field

Embodiments of the application relate to integrated circuit devices and methods of forming the same.

Background

An integrated circuit ("IC") device includes one or more semiconductor devices represented in an IC layout (also referred to as a "layout"). The layout is hierarchical and includes modules that perform higher-level functions according to the design specifications of the semiconductor device. Modules are typically constructed from a combination of units, each representing one or more semiconductor structures configured to perform a particular function. Cells with pre-designed layout, sometimes referred to as standard cells, are stored in a standard cell library (hereinafter "library" or "cell library" for simplicity) and can be accessed by various tools, such as Electronic Design Automation (EDA) tools, to generate, optimize, and verify the design of the IC.

In order to reduce the size of the IC device, a layer of semiconductor devices is sometimes formed or bonded over another layer of semiconductor devices. Examples include Complementary Field Effect Transistor (CFET) devices, where an upper or top semiconductor device overlies a lower or bottom semiconductor device in a stacked configuration.

Disclosure of Invention

According to an aspect of an embodiment of the present application, there is provided an integrated circuit device including: a memory array including a plurality of memory cells; a first word line over the memory array and electrically coupled to at least one first memory cell of the plurality of memory cells; and a second word line located below the memory array and electrically coupled to at least one second memory cell of the plurality of memory cells, wherein each memory cell of the plurality of memory cells comprises a complementary field effect transistor device.

According to another aspect of an embodiment of the present application, there is provided an integrated circuit device including: a memory array comprising a plurality of memory cells arranged in a plurality of columns and a plurality of rows of the memory array, wherein the plurality of rows comprises a first row and a second row, a first word line located above the memory array; and a second word line located under the memory array, wherein each memory cell in the first row and a corresponding memory cell in the second row are arranged in a same column among a plurality of columns of the memory array, and each memory cell in the first row is electrically coupled to one of the first word line and the second word line, and a corresponding memory cell in the second row is electrically coupled to the other of the first word line and the second word line.

According to yet another aspect of an embodiment of the present application, there is provided a method of forming an integrated circuit device, comprising: forming a plurality of memory cells over a front side of a substrate, the plurality of memory cells arranged in a memory array; depositing and patterning a front side redistribution structure over a front side of the substrate, the front side redistribution structure including a front side word line over the memory array and electrically coupled to at least one first memory cell of the plurality of memory cells; a backside redistribution structure is deposited and patterned on a backside of the substrate, the backside redistribution structure comprising a backside word line under the memory array and electrically coupled to at least one second memory cell of the plurality of memory cells, wherein the front side word line has a section extending over the at least one second memory cell without being electrically coupled to the at least one second memory cell, or the backside word line has a section extending under the at least one first memory cell without being electrically coupled to the at least one first memory cell.

Drawings

The various aspects of the invention are best understood from the following detailed description when read in connection with the accompanying drawings. It should be emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

1A-1C are schematic block diagrams of various memory devices according to some embodiments.

FIG. 2 is a schematic circuit diagram of a memory cell according to some embodiments.

Fig. 3A and 3B are corresponding schematic diagrams of top and bottom layers of a layout of a memory cell, and fig. 3C is a schematic diagram of a layout of a memory cell, according to some embodiments.

Fig. 4A-4D are schematic cross-sectional views of portions of a memory device according to some embodiments.

FIG. 5 is a schematic diagram of a layout of a memory cell according to some embodiments.

Fig. 6 is a schematic cross-sectional view of a portion of a memory device according to some embodiments.

Fig. 7 is a schematic cross-sectional view of a portion of a memory device according to some embodiments.

Fig. 8A is a schematic circuit diagram of a portion of a memory device, fig. 8B is an exploded schematic diagram of a corresponding portion of a layout diagram of the memory device, and fig. 8C is a simplified schematic diagram of a portion of a layout diagram of the memory device, according to some embodiments.

Fig. 9A is a schematic circuit diagram of a portion of a memory device, fig. 9B is an exploded schematic diagram of a corresponding portion of a layout diagram of the memory device, and fig. 9C is a simplified schematic diagram of a portion of a layout diagram of the memory device, according to some embodiments.

9D-9F are schematic circuit diagrams of portions of various memory devices according to some embodiments.

10A-10B are flowcharts of various methods according to some embodiments.

FIG. 11 is a block diagram of an Electronic Design Automation (EDA) system, according to some embodiments.

Fig. 12 is a block diagram of an IC device manufacturing system and an IC manufacturing flow associated therewith, in accordance with some embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific embodiments or examples of components, materials, values, steps, arrangements, etc. are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. Other components, materials, values, steps, arrangements, etc. are contemplated. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component, such that the first component and the second component may not be in direct contact. Further, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, for ease of description, spaced relationship terms such as "below …," "below …," "lower," "above …," "upper," and the like may be used herein to describe one element or component's relationship to another element or component as illustrated in the figures. In addition to the orientations shown in the drawings, the term spaced apart relationship is intended to include different orientations of the device in use or operation. The device may be otherwise positioned (rotated 90 degrees or at other orientations) and the spaced apart relationship descriptors used herein interpreted accordingly.

In some embodiments, an IC device includes a memory device having a memory array of memory cells, a first word line located above the memory array and electrically coupled to at least one first memory cell of the plurality of memory cells, and a second word line located below the memory array and electrically coupled to at least one second memory cell of the plurality of memory cells. The first and second word lines are sometimes referred to as front side and back side word lines, respectively. In at least one embodiment, by using both front side and back side word lines to access memory cells in a memory device, word line loading of the memory device can be reduced, and thus timing delays can be reduced and access speeds increased.

In some embodiments, a flying word line configuration is provided. In a flying word line configuration in accordance with at least one embodiment, the front side word line and the back side word line are electrically coupled together. One of the front side word line and the back side word line is a flyword line that flies over memory cells in a first or near end section of a memory row in the memory array without being electrically coupled to the memory cells. The flyword lines are electrically coupled to memory cells in a second or distal section of the memory row. The other of the front side word line and the back side word line is physically shorter than the fly word line and is electrically coupled to memory cells in a proximal section of the memory row. As a result, in one or more embodiments, the resistance and capacitance on the shortened word line, which does not have a portion above or below the distal section of the memory row, may be reduced. In one or more embodiments, on the other hand, the capacitance of at least the portion of the flying word line that flies over the proximal section of the memory row may be reduced.

In some embodiments, a hybrid word line configuration is provided. In a hybrid wordline configuration in accordance with at least one embodiment, the front side and back side wordlines are controlled independently of each other. Two memory rows are located between the front side word line and the back side word line. Memory cells in one of the two memory rows are electrically coupled to one of the front side word line and the back side word line, while corresponding memory cells in the other memory row are electrically coupled to the other of the back side word line and the front side word line. In one or more embodiments, any arrangement (or dichotomy) of memory cells electrically coupled to the front side word line and memory cells electrically coupled to the back side word line is possible along one of the two memory rows. As a result, in at least one embodiment, the width of the front and back side word lines across two memory rows may be increased and the resistance of the front and back side word lines reduced.

FIG. 1A is a schematic block diagram of a memory device 100A according to some embodiments. The memory device is an IC device. In at least one embodiment, the memory device is a separate IC device. In some embodiments, the memory device is included as part of a larger IC device that includes circuitry for other functions in addition to the memory device.

Memory device 100A includes a memory array 101 comprised of a plurality of memory cells MC, and a memory controller 102 coupled to control the operation of memory cells MC. In the memory array 101, memory cells MC are arranged in a plurality of columns C0-C m, where m is a natural number, and a plurality of rows R0, R1, R2, etc. The columns and rows in a memory array are sometimes referred to as memory columns and memory rows. The memory columns extend in the column direction, designated as the C-axis in fig. 1A. The memory rows extend in a row direction transverse to the column direction and are designated as the R-axis in fig. 1A. In at least one embodiment, the memory cell MC is a Static Random Access Memory (SRAM) memory cell. Other memory configurations and/or types are within the scope of the various embodiments.

Memory device 100A also includes a plurality of word lines along the rows of memory array 101 and a plurality of bit lines extending along the columns of the memory array. The word lines are generally referred to herein as WL and the bit lines are also generally referred to herein as BL. Unless otherwise indicated, both the front side word line and the back side word line are generally described or referred to as word line WL. In some embodiments, each bit line includes a pair of bit lines BL and BLB, which are described or referred to as bit line BL unless otherwise indicated. Each memory cell MC is coupled to the memory controller 102 by a corresponding word line and a corresponding bit line. The word line WL is configured to transmit an address or the like of the memory cell MC to be read from and/or written to. The word lines WL are sometimes referred to as "address lines". The bit lines BL are configured to transfer data or the like to be written to and/or read from the memory cells MC indicated by the addresses on the respective word lines. The bit line BL is sometimes referred to as a "data line". Various numbers of word lines WL and/or bit lines BL in the memory device 100A are within the scope of the various embodiments.

The memory controller 102 includes a word line driving circuit 103, a bit line multiplexer (BL MUX) 104, and a read/write circuit 105, the read/write circuit 105 being configured to perform at least one of a read operation or a write operation on one or more selected memory cells MC in the memory array 101. The word line driving circuit 103 is configured to decode a row address of one or more memory cells MC selected to be accessed in a read operation or a write operation. The word line driving circuit 103 also includes a plurality of word line drivers 130, 131, 132, etc., each coupled to one or more corresponding word lines WL as described herein. The word line driving circuit 103 is configured to supply one set of access voltages to a selected word line WL corresponding to a decoded row address and a different set of voltages (e.g., zero) to another unselected word line WL through the corresponding word line drivers 130, 131, 132, etc. Each of the bit line multiplexers 104 is coupled to one or more bit lines BL. The read/write circuit 105 is coupled to the bit line multiplexer 104 and is configured to decode a column address of the memory cell MC to be accessed in a read operation or a write operation. The read/write circuit 105 is configured to supply one set of voltages to the selected bit line BL corresponding to the selected memory cell MC to be accessed through the bit line multiplexer 104, and to supply a different set of voltages to the other unselected bit lines BL. In a read operation, one or more sense amplifiers (not shown) of the read/write circuit 105 are configured to sense data read from the accessed memory cells MC and retrieved through the corresponding bit lines BL. The memory controller 102 also includes control circuitry 106, the control circuitry 106 to control operation of the word line driver circuitry 103, the bit line multiplexer 104, the read/write circuitry 105, and/or other components in the memory controller 102. In at least one embodiment, memory controller 102 further includes one or more clock generators for providing clock signals to the various components of memory device 100A, one or more input/output (I/O) circuits for exchanging data with external devices, and/or one or more sub-controllers for controlling various operations in memory device 100A. The described memory device configurations are examples, and other memory device configurations are within the scope of the various embodiments.

In the example configuration of fig. 1A, the memory cells MC in each memory column are electrically coupled to a common bit line. For example, memory cells MC in memory columns C [0], C [ k-1], C [ k ], C [ k+1], C [ m ], where k is a natural number less than m, are electrically coupled to bit lines BL [0], BL [ k-1], BL [ k ], BL [ k+1], BL [ m ], respectively.

The memory cells MC in each memory row are electrically coupled to either the front side word line or the back side word line. As described herein, the front side word line is a word line above the memory array or at the front side of the substrate, while the back side word line is a word line below the memory array or at the back side of the substrate. In fig. 1A to 9F, the front side word line is shown by a solid line and indicated by a tag including "WL", and the back side word line is shown by a broken line and indicated by a tag including "BWL". For example, memory cells MC in memory row R [0] are electrically coupled to either front side word line WL [0] or back side word line BWL [0]. Specifically, the memory row R [0] includes a first section including memory cells MC electrically coupled to bit lines BL [0] -BL [ k-1] and front side word line WL [0], and a second section including memory cells MC electrically coupled to bit lines BL [ k+1] -BL [ m ] and back side word line BWL [0]. Similarly, memory row R [1] includes a first section including memory cells MC electrically coupled to front side word line WL [1], a second section including memory cells MC electrically coupled to back side word line BWL [1], memory row R [2] includes a first section including memory cells MC electrically coupled to front side word line WL [2] and a second section including memory cells MC electrically coupled to back side word line BWL [2 ]. In the example configuration in FIG. 1A, a first section of memory rows R [0], R [1], R [2], etc. has the same number of memory cells MC and configures a first section or first bank (bank) 111 of memory array 101, and a second section of memory rows R [0], R [1], R [2], etc. has the same number of memory cells MC and configures a second section or second bank 112 of memory array 101. Other configurations in which the first section or the second section of different memory rows have different numbers of memory cells MC are within the scope of the various embodiments. In at least one embodiment, the number of memory cells MC in the first section of the memory row is the same as the number of memory cells MC in the second section of the memory row, i.e., m=2k. Other configurations in which the number of memory cells MC in a first section of a memory row is different from the number of memory cells MC in a second section of the memory row are within the scope of the various embodiments.

Each of the memory rows R [0], R [1], R [2], etc. also includes dummy memory cells DMC between the corresponding first and second sections. Dummy memory cells DMC of memory rows R [0], R [1], R [2], etc. are electrically coupled to bit lines BL [ k ], and dummy memory columns 113 between first bank 111 and second bank 112 of memory array 101 are configured. In at least one embodiment, the dummy memory cell DMC has the same configuration as the memory cell MC; however, the data read from the dummy memory cells DMC in the read operation as described herein is ignored. In the example configuration of FIG. 1A, the dummy memory cells DMC are electrically coupled to front side word lines WL [0], WL [1], WL [2], and so on. Other configurations are within the scope of the various embodiments. For example, in at least one embodiment, the dummy memory cell DMC is electrically coupled to the backside word line BWL [0], BWL [1], BWL [2], etc. In some embodiments, at least one dummy memory cell DMC is electrically coupled to a corresponding front side word line, while at least one additional dummy memory cell DMC is electrically coupled to a respective back side word line. In some embodiments, the dummy memory cells are configured to separate shared VG vias (described below) between adjacent memory cells. The aim is to avoid the following potential situations: the edge memory cells between the first and second sections of the memory array are half-on (e.g., one pass gate is on) when the corresponding word line is accessed, which in turn will not result in a functional bit cell operation.

For each of the memory rows R [0], R [1], R [2], etc., the front side word line is electrically coupled to the back side word line and to the output of the corresponding word line driver. For example, for memory row R [0], front side word line WL [0] is electrically coupled to back side word line BWL [0] and to the output of the corresponding word line driver 130. In the example configuration in fig. 1A, the word line driver 130 includes an inverter. Other word line driver configurations are within the scope of the various embodiments. In an access operation (e.g., a read operation or a write operation), a drive signal WLB (0) corresponding to a decoded row address of one or more memory cells MC selected to be accessed in memory row R [0] is applied to an input of word line driver 130. In response to the driving signal WLB (0), the word line driver 130 is configured to apply an access voltage WL (0) corresponding to an inverted signal of the driving signal WLB (0) to the front side word line WL [0] and the back side word line BWL [0] to access the selected further memory cells MC in the memory row R [0 ]. Similarly, for memory row R [1], the corresponding word line driver 131 is configured to receive the drive signal WLB (1) and output the access voltage WL (1) to the front side word line WL [1] and the back side word line BWL [1]. For memory row R [2], the corresponding word line driver 132 is configured to receive the drive signal WLB (2) and output an access voltage WL (2) to front side word line WL [2] and back side word line BWL [2].

As shown in fig. 1A, the farther a memory cell MC in a memory row is from a corresponding word line driver, the longer the access voltage is from the word line driver to the memory cell MC. As the physical distance between memory cell MC and the corresponding word line driver increases, so does the resistance and capacitance associated with the length of the corresponding word line between memory cell MC and word line driver, which in turn increases the timing delay (RC) and potentially limits the access speed (e.g., read speed or write speed) of the memory device. In one or more embodiments, these problems are solved by a flyword line configuration that includes using both front side and back side word lines to access memory rows.

For example, the backside word line BWL [0] in FIG. 1A is a fly word line that includes a first section 115 that extends under a first section of memory row R [0] in the first bank 111 without being electrically coupled to memory cells MC in the first section. In other words, the first segment 115 of the backside word line BWL [0] is "flown" past the first segment of the memory row R [0]. The backside word line BWL [0] also includes a second segment 116 that adjoins the first segment 115. The second section 116 extends under the second section of the memory row R [0] in the second bank 112 and is electrically coupled to the memory cells MC in the second section. The front side word line WL [0] is electrically coupled to memory cells MC in the first section of memory row R [0] in the first memory bank 111. The front side word line WL [0] is physically shorter than the back side word line BWL [0] and does not extend into the second bank 112. In other words, the second segment 116 of the back side word line BWL [0] extends continuously from the first segment 115 and beyond the front side word line WL [0]. Memory cells MC in a first section of memory row R [0] are accessed by front side word line WL [0] and memory cells MC in a second section of memory row R [0] are accessed by back side word line BWL [0]. The flyline configuration described is also implemented for other memory rows. For example, for memory row R [1], back side word line BWL [1] is a fly word line and front side word line WL [1] is a shortened word line. For memory row R2, backside word line BWL 2 is the fly word line and front side word line WL 2 is the shortened word line. Other flyline configurations are within the scope of various embodiments, as described herein, for example, with respect to fig. 1B-1C.

Because the first segment 115 of the backside word line BWL [0] flies through the memory cells in the first segment without being electrically coupled thereto, at least the capacitance associated with the first segment 115 is reduced. As a result, in at least one embodiment, the word line load associated with the backside word line BWL [0] and the timing delay RC for accessing the memory cells MC in the second section are reduced, and the access speed to the memory cells MC within the second section is increased. In addition, because the front side word line WL [0] is physically shorter and does not extend into the second bank 112, the resistance and capacitance associated with the front side word line WL [0] is reduced. As a result, in at least one embodiment, the word line load associated with front side word line WL [0] is reduced, which, along with the reduced word line load associated with back side word line BWL [0], reduces the load on word line driver 130 and improves the performance and/or power consumption of memory device 100A.

In some embodiments, the described advantages are achieved without one or more of the disadvantages of other methods of accessing memory cells in a memory array using word lines only on one side of the memory array. To address the problems associated with large timing delays when accessing memory cells at the far edge of the memory array, other approaches implement word lines in multiple metal layers, which increases manufacturing costs and/or creates additional parasitic capacitance. In contrast, in one or more embodiments, the described flying word line configuration reduces timing delays by accessing the memory array via both the front side word line and the back side word line, while also reducing word line capacitance, resistance, loading, and the like. In at least one embodiment, each of the front side word lines and the back side word lines are formed in a single metal layer, as described herein, which simplifies the manufacturing process and is an improvement over other methods.

Fig. 1B, 1C are schematic block diagrams of corresponding memory devices 100B, 100C according to some embodiments. For simplicity, corresponding components in fig. 1A-1C are denoted by the same reference numerals.

In fig. 1B, memory device 100B includes a second memory array 101' (array 2) in addition to memory array 101 of the first memory array (array 1). The configuration of the second memory array 101' is similar to the first memory array 101 and is accessed through a flyword line configuration similar to that described with respect to the first memory array 101. The flying word line configuration for accessing the first memory array 101 and the second memory array 101' is schematically illustrated in fig. 1B by a pair of front side word lines WL and back side word lines BWL and a pair of front side word lines WL ' and back side word lines BWL ', respectively. The second memory array 101' includes a first bank (or near-end bank) accessed by a front-side word line WL ', a second bank (or far-end bank) accessed by a back-side word line BWL ', and a dummy memory column 113' similar to the dummy memory column 113 and arranged between the first bank and the second bank of the second memory column 101 '. The memory controller 102 of the memory device 100B includes a word line driver circuit 103 (WLDRV), a control circuit 106 (CNT), a first input/output circuit 145 (MIO 1) associated with the first memory array 101, and a second input/output circuit 145 '(MIO 2) associated with the second memory array 101'. The front side word lines and back side word lines in the memory arrays 101, 101' are electrically coupled to respective word line drivers in the word line driving circuit 103. The first input/output circuit 145 includes the bit line multiplexer 104 and the read/write circuit 105 associated with the first memory array 101. The second input/output circuit 145 'similarly includes a bit line multiplexer and read/write circuits associated with the second memory array 101'.

In fig. 1C, memory device 100C includes similar components as those described with respect to memory device 100B. In contrast to memory device 100B, which includes a flyword line on the back side (i.e., back side word lines BWL, BWL 'are flyword lines), memory device 100C includes flyword lines on the front side, i.e., front side word lines WL, WL' are flyword lines. In at least one embodiment, one or more of the advantages described herein with respect to the memory device 100A may be realized by one or more of the memory devices 100B, 100C.

The configurations described with respect to one or more of fig. 1A-1B are examples. Other configurations are within the scope of the various embodiments while achieving one or more of the described advantages. For example, in at least one embodiment, one of the memory arrays 101, 101 'includes a flyword line on the front side, while the other of the memory arrays 101 and 101' includes a flyword line on the back side. In one or more embodiments, at least one memory row is accessed by a flywordline configuration on the back side and at least one other memory row is accessed by a flywordline configuration on the front side in the same memory array.

Fig. 2 is a schematic circuit diagram of a memory cell 200 according to some embodiments. In some embodiments, memory cell 200 corresponds to one or more of one or more memory cells MC in memory devices 100A, 100B, 100C. In the example configuration in fig. 2, the memory cell 200 is an SRAM cell including six transistors (6T), and is sometimes referred to as a 6T SRAM cell. Other memory types and/or other SRAM cell configurations, such as 4T SRAM, 8T SRAM,10T SRAM, 12T SRAM, etc., are within the scope of the various embodiments.

The memory cell 200 includes a first inverter INV1, a second inverter NV2, and access transistors or transfer gates T1, T2, the first inverter INV1 including a pair of P-type transistors P1 and N-type transistors N1, and the second inverter NV2 including a pair of P-type transistors P2 and N-type transistors N2. In the example configuration in fig. 2, the transistors T1, T2 are N-type transistors. Examples of transistors include, but are not limited to, metal Oxide Semiconductor Field Effect Transistors (MOSFETs), complementary Metal Oxide Semiconductor (CMOS) transistors, P-channel metal oxide semiconductor and/or N-channel field effect transistors (PFETs/NFETs), bipolar junction transistors, high voltage transistors, high frequency transistors, finfets, planar MOS transistors with raised source/drain, nanoflake FETs, nanowire FETs, and the like. Other transistor configurations are within the scope of the various embodiments.

The inverters INV1, INV2 are cross-coupled to each other to form a latch circuit for data storage. For example, cross-coupling connection 201 electrically couples the output of first inverter INV1 (node Q) to the input of second inverter INV2, and cross-coupling connection 202 electrically couples the input of first inverter INV1 to the output of second inverter INV2 (node QB). The input of the first inverter INV1 is configured by the gates of the transistors P1 and N1, and the output Q of the first inverter INV1 is configured by the first source/drain of the electrically coupled transistors P1 and N1. The input of the second inverter INV2 is configured by the gates of the transistor P2 and the transistor N2, and the output QB of the second inverter INV1 is configured by the first source/drain of the transistor P2 and the transistor N2 electrically coupled. The second terminals of the transistors P1 and P2 are electrically coupled to the power supply VDD, and the second terminals of the transistors N1 and N2 are electrically coupled to a reference voltage, e.g., ground voltage VSS. The data bits are stored in the memory cell 200 as a voltage level at node Q, which is accessible by the memory controller via the bit line BL. Access to node Q is controlled by a transistor T1 electrically coupled between bit line BL and node Q. The data bits stored by node QB are complementary to the data bits stored by node Q, e.g., when node Q is at logic "high", node QB is at logic "low", and vice versa. Node QB may be accessed by a memory controller via bit line BLB. Access to node QB is controlled by transistor T2, which is electrically coupled between bit line BLB and node QB. The gates of transistors T1 and T2 are electrically coupled to a word line, which in one or more embodiments is a front side word line WL or a back side word line BWL.

In at least one embodiment described herein, transistor P1 and transistor N1 are configured by a first CFET device, transistor P2 and transistor N2 are configured by a second CFET device, transistor T1 is configured by a portion of a third CFET device, and transistor T2 is configured by a portion of a fourth CFET device.

Fig. 3A and 3B are corresponding schematic diagrams at a top layer 300A and a bottom layer 300B of a layout of a memory cell 300, and fig. 3C is a schematic diagram of a layout of a memory cell 300, according to some embodiments. In some embodiments, memory cell 300 corresponds to memory cell 200 and/or to one or more of memory cells MC in one or more of memory devices 100A, 100B, 100C. In some embodiments, the map of memory cells 300 is stored in a cell library and/or on a non-transitory computer readable recording medium.

In the example configuration of fig. 3A-3C, the memory cell 300 includes CFET devices, each including a top semiconductor device and a bottom semiconductor device. The top layer 300A (fig. 3A) corresponds to the top semiconductor device, while the bottom layer 300B (fig. 3B) corresponds to the bottom semiconductor device. The layout in fig. 3C is a combination of top layer 300A stacked on bottom layer 300B.

Referring to fig. 3A-3C, the memory cell 300 includes a boundary 310, the boundary 310 being the same for the top layer 300A and the bottom layer 300B. Boundary 310 includes edges 311, 312, 313, 314. Edges 311, 312 are elongated along the X-axis and edges 313, 314 are elongated along the Y-axis transverse to the X-axis. Edges 311, 312, 313, 314 are joined together to form a closed boundary 310. In the placing and routing operations described herein (also referred to as "Automatic Placement and Routing (APR)") the cells are placed in an IC layout with the cells abutting each other at respective boundaries. Boundary 310 is sometimes referred to as a "placement and routing boundary" or "pr boundary". The rectangular shape of boundary 310 is merely an example. Other boundary shapes of the various cells are within the scope of the various embodiments. Memory cell 300 is within boundary 310.

The top layer 300A includes a layout of a top semiconductor device of a first type and the bottom layer 300B includes a layout of a corresponding bottom semiconductor device of a second type different from the first type. In some embodiments, the first type is one of P-type and N-type and the second type is the other of P-type and N-type. In the example configuration of fig. 3A-3C, the top layer 300A includes N-type transistors, such as NMOS, and the bottom layer 300B includes P-type transistors, such as PMOS.

Each of the top layer 300A and the bottom layer 300B includes at least one active region. The active region is sometimes referred to as an Oxide Definition (OD) region or source/drain region and is schematically shown in the drawings with a label including an "OD". For example, the top layer 300A includes active areas OD-1, OD-2, and the bottom layer 300B includes active areas OD-3, OD-4. In the layout of fig. 3C, active regions OD-1 and OD-3 overlap or are stacked on each other along the thickness direction of the substrate as described herein, and are generally referred to as active region OD1. Similarly, the active regions OD-2 and OD-4 overlap or are stacked on each other along the thickness direction of the substrate, and are generally referred to as active regions OD2.

The active areas OD-1, OD-2, OD-3, OD-4 are located above a first side or front side of the substrate as described herein. The active regions OD-1, OD-2, OD-3, OD-4 extend along the X axis. The active regions OD-1, OD-2, OD-3, OD-4 comprise P-type dopants or N-type dopants to form one or more circuit elements or semiconductor devices. Active regions configured to form one or more PMOS devices are sometimes referred to as "PMOS active regions" and active regions configured to form one or more NMOS devices are sometimes referred to as "NMOS active regions". In the example configuration described with respect to fig. 3A-3C, active regions OD-1, OD-2 comprise NMOS active regions and OD-4 comprises PMOS active regions.

The top layer 300A further includes a plurality of gate regions G1-G4 that overlap with corresponding gate regions in the bottom layer 300B or are stacked on corresponding gate regions in the bottom layer 300B along the thickness direction of the substrate. Each of the gate regions G1-G4 in the top layer 300A is further electrically coupled to a corresponding underlying gate region in the bottom layer 300B. The gate regions in fig. 3A-3C are generally designated as gate regions G1-G4. The depicted configuration in which the gate region in the top layer 300A is electrically coupled to the underlying gate region in the bottom layer 300B is an example. In at least one embodiment, the gate region in the top layer 300A overlaps with the underlying gate region in the bottom layer 300B, but is electrically isolated from the underlying gate region in the bottom layer 300B. The gate regions G1-G4 are elongated along the Y-axis. The gate regions G1-G4 comprise a conductive material such as polysilicon, metal, or the like.

The top layer 300A also includes a plurality of top semiconductor devices configured by gate regions G1-G4 and active regions OD-1, OD-2. Specifically, the gate region G1 and the active region OD-1 configure an NMOS corresponding to the transistor N1, the gate region G2 and the active region OD-1 configure an NMOS corresponding to the transistor T1, the gate region G3 and the active region OD-2 configure an NMOS corresponding to the transistor T2, and the gate region G4 and the active region OD-2 configure an NMOS corresponding to the transistor N2.

The bottom layer 300B also includes a plurality of bottom semiconductor devices configured by gate regions G1, G4 and active regions OD-3, OD-4. Specifically, the gate region G1 and the active region OD-3 configure a PMOS corresponding to the transistor P1, and the gate region G4 and the active region OD-4 configure a PMOS corresponding to the transistor P2. The transistor N1 and the underlying transistor P1 configure a CFET device corresponding to the gate region G1, and the transistor N2 and the underlying transistor P2 configure another CFET device corresponding to the gate region G4.

Bottom layer 300B also includes regions NOD-3, NOD-4 located below active regions OD-1, OD-2, respectively, but are not configured to form PMOS. In some embodiments, the regions NOD-3, NOD-4 do not include epitaxial structures. The region NOD-3 and the active region OD-3 are disposed on opposite sides of the gate region G2 along the X-axis. Within boundary 310, active region OD-1 overlaps the combination of active region OD-3 and region NOD-3. If region NOD-3 is configured as a PMOS active region, the PMOS will be formed by gate region G2, active region OD3, and region NOD-3. Because region NOD-3 is not configured to form a PMOS, no PMOS is formed in bottom layer 300B below transistor T1 in top layer 300A. The CFET device corresponding to the gate region G2 includes NMOS (i.e., transistor T1), but does not include PMOS. Similarly, the region NOD-4 and the active region OD-4, which are not configured to form a PMOS, are arranged on opposite sides of the gate region G3 along the X-axis, and the CFET device corresponding to the gate region G3 includes an NMOS (i.e., transistor T2), but does not include a PMOS.

The memory cell 300 also includes source/drain contacts over and in electrical contact with corresponding source/drains in the active areas OD-1, OD-2, OD-3, OD-4. The source/drain contacts are sometimes referred to as metal-to-device (MD) contacts and are schematically represented in fig. 3A-3C by labels including "MD". The source/drain contacts of the top semiconductor device at the top layer 300A are sometimes referred to as MD contacts. The source/drain contacts of the bottom semiconductor device at the bottom layer 300B are sometimes referred to as BMD contacts. For simplicity, MD contacts herein refer to either top-layer MD contacts or bottom-layer BMD contacts unless specified otherwise. The MD contacts include conductive material on the corresponding source/drain in the corresponding active region to define electrical connections of one or more devices formed in the active region to other internal circuitry of the memory device, to IC devices including the memory device, or to external circuitry. MD contacts are arranged alternately with gate regions along the X-axis. At the top layer 300A in fig. 3A, each of the MD contacts MD1-MD4 is on a corresponding source/drain of one of the transistors N1, T2, N2. At the bottom layer 300B in fig. 3B, each of the BMD contacts BMD1, BMD4 is on a corresponding source/drain of one of the transistors P1, P2. MD contacts MD1, MD4 overlap BMD contacts BMD1, BMD4, respectively, but are electrically isolated from BMD contacts BMD1, BMD 4.

The memory cell 300 also includes source/drain local interconnects (MDLI). Interconnect MDLI is a conductive structure that electrically couples the MD contact with the underlying BMD contact. In the example configuration in fig. 3A-3C, each interconnect MDLI replaces a respective MD contact and BMD contact and makes physical and electrical contact with a source/drain in the top layer 300A and an underlying source/drain in the bottom layer 300B. In particular, memory cell 300 includes interconnect MDLI1 that electrically couples the common source/drain of transistor N1 and transistor T1 at top layer 300A to the underlying source/drain of transistor P1 at bottom layer 300B. Memory cell 300 also includes an interconnect MDLI2 that electrically couples the common source/drain of transistor N2 and transistor T2 at top layer 300A to the second source/drain of transistor P2 at bottom layer 300B.

The memory cell 300 also includes a bridging interconnect (BCT). Interconnect BCT is a conductive structure that electrically couples interconnect MDLI with adjacent gate regions. Specifically, the memory cell 300 includes an interconnect BCT1 electrically coupling the gate region G4 to the interconnect MDLI1, and an interconnect BCT2 electrically coupling the gate region G1 to the interconnect MDLI 2. Interconnects MDLI, BCT1 correspond to node Q, and interconnects MDLI, BCT2 correspond to node QB. In the example configuration in fig. 3A, interconnects BCT1, BCT2 are included in the top layer 300A. In some embodiments, at least one of the interconnects BCT1, BCT2 is included in the bottom layer 300B.

The top layer 300A also includes vias over and in electrical contact with the gate region and the MD contacts. The vias above and in electrical contact with the gate region and the MD contacts are sometimes referred to as through-hole-to-device (VD) vias. The via above and in electrical contact with the gate is sometimes referred to as a via-to-gate (VG) via. VD and VG vias are schematically illustrated in fig. 3A-3C, with corresponding labels including "VD" and "VG". In the example configuration of fig. 3A, the vias VG1, VG2 are on the gate regions G2, G3, respectively, and the vias VD1-VD4 are on the MD contacts MD1-MD4, respectively.

Similarly, the bottom layer 300B includes backside VD and/or VG vias that electrically contact corresponding BMD contacts and/or gate regions. The backside VD and VG vias are schematically illustrated in fig. 3A-3C, with corresponding labels including "BVD" and "BVG". In the example configuration in fig. 3B, through-holes BVD1, BVD4 are located on BMD contacts BMD1, BMD4, respectively. Exemplary materials for VD, VG, BVD, BVG vias include metals. Other configurations are within the scope of the various embodiments.

The top layer 300A also includes a plurality of metal layers and via layers arranged consecutively and alternately over VD, VG vias. The lowest metal layer immediately above and in electrical contact with the VD, VG vias is the M0 (zero metal) layer, the next metal layer immediately above the M0 layer is the M1 layer, the next metal layer immediately above the M1 layer is the M2 layer, and so on. The conductive pattern in the M0 layer is referred to as an M0 conductive pattern, the conductive pattern in the M1 layer is referred to as an M1 conductive pattern, and so on. The via layer Vn is disposed between and electrically couples the Mn layer and the mn+1 layer, where n is an integer from zero to above. For example, the via zero (V0) layer is the lowest via layer disposed between the M0 layer and the M1 layer and electrically coupling the M0 layer and the M1 layer. Other via layers are V1, V2, etc. The via in the V0 layer is referred to as a V0 via, the via in the V1 layer is referred to as a V1 via, and so on.

Similarly, the bottom layer 300B includes a plurality of backside metal layers and a plurality of backside via layers that are continuously and alternately disposed under BVD, BVG vias. The backside metal layer closest to the front side (or active areas OD-3, OD-4) is the backside M0 (BM 0) layer, the next backside metal layer is the backside M1 (BM 1) layer, and so on. The backside via layer BVn is disposed between and electrically couples the BMn layer and the bmn+1 layer, where n is an integer from zero to above. For example, the via layer BV0 is a backside via layer disposed between the BM0 layer and the BM1 layer and electrically coupling the BM0 layer and the BM1 layer. Other backside via layers are BV1, BV2, etc.

In the example configuration in fig. 3A, the top layer 300A includes M0 conductive patterns M0-1 to M0-6 corresponding to over the vias VD1, VG1, VD2, VD3, VG2, VD 4. The M0 conductive patterns M0-1, M0-6 are configured to electrically couple to one or more VSS power rails. The M0 conductive patterns M0-2, M0-5 are configured to be electrically coupled to the front side word line WL described with respect to FIG. 3C. M0 conductive patterns M0-2, M0-5 are denoted WL-1, WL-2. The M0 conductive patterns M0-3, M0-4 are configured to be electrically coupled corresponding to the bit lines BL, BLB. FIG. 3A further illustrates the use of M0 tracks 321-324 in the top layer 300A. The M0 track 321 is configured for VSS and word lines, and an M0 conductive pattern M0-1 for VSS and an M0 conductive pattern M0-2 for word line WL are arranged along the M0 track 321. The M0 track 322 is configured for the bit line BL, and M0 conductive patterns M0-3 for the bit line BL are arranged along the M0 track 322. The M0 track 323 is configured for another bit line BLB, and M0 conductive patterns M0-4 for the bit line BLB are arranged along the M0 track 323. The M0 track 324 is configured for VSS and word lines, and M0 conductive patterns M0-6 for VSS and M0 conductive patterns M0-5 for word lines WL are arranged along the M0 track 324.

In the example configuration in fig. 3B, the bottom layer 300B includes BM0 conductive patterns BM0-1, BM0-4 corresponding to the via BVD1, BVD 4. The BM0 conductive patterns BM0-1, BM0-4 are configured to be electrically coupled to one or more VDD power rails. Fig. 3B further illustrates the use of BM0 tracks 332, 333 in the bottom layer 300B. The BM0 tracks 332, 333 are configured for VDD, and BM0 conductive patterns BM0-1, BM0-4 for VDD are arranged along the BM0 tracks 332, 333 accordingly.

In the example configuration in fig. 3A-3C, the edge 311 of the boundary 310 follows the M0 track 324 and coincides with the center line of the M0 conductive patterns M0-5, M0-6. Edge 312 of boundary 310 follows M0 track 321 and coincides with the centerline of M0 conductive patterns M0-1, M0-2. Edge 313 of boundary 310 coincides with the centerlines of MD contacts MD1, MD3 and BMD contact BMD 1. Edge 314 of boundary 310 coincides with the center line of MD contacts MD2, MD4 and BMD contacting BMD 4.

In fig. 3C, the memory cell 300 includes a front side word line WL configured in the M1 layer in addition to the various components described with respect to fig. 3A, 3B. The front side word line WL includes an M1 conductive pattern that extends continuously along the Y-axis over the entire height of the memory cell 300. For simplicity, the portion of the front side word line WL above the memory cell 300 is not shown. Although not shown in fig. 3C, the front side word line WL further extends continuously over other memory cells (to abut each other with the memory cell 300 or the memory cell 300) placed along the Y-axis. In the example configuration in fig. 3C, the Y-axis corresponds to the R-axis described with respect to fig. 1A-1C.

The memory cell 300 also includes two V0 vias (not shown) over the M0 conductive patterns M0-2, M0, respectively, to electrically couple the front side word line WL to the M0 conductive patterns M0-2, M0-5, then to the vias VG1, VG2, and then to the gate regions G2, G3 of the access transistors T1, T2. In at least one embodiment, the access transistors T1, T2 are turned on in response to an access voltage applied to the front side word line WL and allow access to data stored in the memory cell 300. Memory cell 300 is an example of a memory cell that is electrically coupled to and accessible through a front side word line. Examples of memory cells electrically coupled to and accessible through the backside word line are described with respect to fig. 5-6. In at least one embodiment, one or more of the advantages described herein may be realized by a memory device including one or more memory cells 300.

Fig. 4A-4D are schematic cross-sectional views of portions of a memory device 400 according to some embodiments. The portion of the memory device 400 in fig. 4A-4D corresponds to the memory cell 300. The views in fig. 4A and 4B correspond to the X-axis cross-sectional views taken along the lines A-A 'and B-B' in fig. 3C. The views in fig. 4C and 4D correspond to the Y-axis cross-sectional views taken along the lines C-C 'and D-D' in fig. 3C. For simplicity, corresponding components in fig. 3A-3C and 4A-4D are denoted by the same reference numerals.

As shown in fig. 4A, the memory device 400 includes a substrate 440, the substrate 440 having a front side 441 and a back side 442 opposite the front side 441 in a thickness direction of the substrate 440. In at least one embodiment, front side 441 is referred to as the "first side", "upper side", or "device side", and back side 442 is referred to as the "second side" or "lower side". The thickness direction of the substrate 440 is also the thickness direction of the memory device 400 and is designated as the Z-axis in fig. 4A-4D. In some embodiments, substrate 440 comprises a semiconductor material, such as silicon, silicon germanium (SiGe), gallium arsenide, or other suitable semiconductor material. In some embodiments, the substrate 440 includes a dielectric material, such as silicon nitride, silicon oxide, ceramic, glass, or other suitable material. In some embodiments, substrate 440 comprises a multi-layer structure. In some embodiments, the substrate 440 is omitted or includes an insulating layer that replaces the original semiconductor body used during fabrication. The substrate 440 is omitted from fig. 4B-4D for simplicity.

The memory device 400 also includes CFET devices 451-454 on the front side 441 of the substrate 440. The CFET devices 451-454 correspond to gate regions G1-G4. The CFET devices 451, 452 are shown in fig. 4A, and the CFET devices 453, 454 are shown in fig. 4B. The CFET device 451 includes a transistor N1 as a top semiconductor device over a transistor P1 as a bottom semiconductor device, and the CFET device 454 includes a transistor N2 as a top semiconductor device over a transistor P2 as a bottom semiconductor device. In the CFET device 452, the transistor T1 is a top semiconductor device and, as described herein, a bottom semiconductor device is not formed since the region NOD-3 is not configured to form a PMOS. Similarly, in CFET device 453, transistor T2 is a top semiconductor device and, as described herein, a bottom semiconductor device is not formed because region NOD-2 is not configured to form a PMOS. The top semiconductor devices (i.e., transistors N1, N2, T1, T2) are examples of semiconductor devices in the upper layer of the memory device 400, while the bottom semiconductor devices (i.e., transistors P1, P2) are examples of semiconductor devices in the lower layer of the memory device 400.

Each top semiconductor device or bottom semiconductor device includes a channel disposed in a respective active region. In the example configuration in fig. 4A, the channel of the transistor N1 includes a semiconductor material such as Si in the corresponding active region OD-1, and is configured as a plurality of N-type nanoplates 461, the plurality of N-type nanoplates 461 being stacked on each other and spaced apart in the thickness direction. Similarly, the channel of the transistor P1 includes a semiconductor material such as Si in the corresponding active region OD-3, and is configured as a plurality of P-type nano-sheets 462, the plurality of P-type nano-sheets 462 being stacked and spaced apart from each other in the thickness direction. The channel materials and nanoplatelets described are examples. Other channel materials and/or channel types (such as nanowires, finfets, planes, etc.) are also within the scope of the various embodiments.

Each top semiconductor device or bottom semiconductor device further comprises a gate corresponding to one of the gate regions G1-G4. For simplicity, gates in memory device 400 are denoted by the same reference numerals G1-G4 for corresponding gate regions in memory cell 300. In some embodiments, the gates G1-G4 are metal gates. Other gate materials, such as polysilicon, are within the scope of the various embodiments. In the example configuration of fig. 4A-4B, the gates G1-G4 are full ring gates extending around the respective channels. In some embodiments, the gate material of gates G1-G4 replaces sacrificial material, such as SiGe, in the corresponding active region during the fabrication process.

In the example configuration of fig. 4A, 4B, the gate of the top semiconductor device in a CFET device is electrically coupled to the gate of the underlying bottom semiconductor device of the same CFET device through a local interconnect. For example, in CFET device 451, the gate of transistor N1 is electrically coupled to the gate of transistor P1 through local interconnect 463. In some embodiments, the local interconnect 463 is formed as an integral part of the gate G1 surrounding the nanoplates 461, 462. Because the gate of transistor N1 is electrically coupled to the gate of transistor P1, the gates of transistors N1, P1 are commonly referred to by the same reference number G1. In at least one embodiment, the CFET device comprises an isolated gate configuration in which the gate of the top semiconductor device is not electrically coupled to the gate of the underlying bottom semiconductor device through a local interconnect, i.e., a local interconnect similar to local interconnect 463 is omitted in the isolated gate configuration.

Each top semiconductor device or bottom semiconductor device further includes a gate dielectric (not shown) between the respective gate and the channel. For example, in transistor N1, a gate dielectric is between gate G1 and nanoplatelets 461 and extends around each nanoplatelet 461. Example materials for the gate dielectric include high-k dielectric materials and the like.

Each top semiconductor device or bottom semiconductor device further includes a source/drain in the corresponding active region. For example, transistor N1 and transistor T1 share a common source/drain 464 in active region OD-1, and transistor P1 includes a source/drain 465 in active region OD-3. In some embodiments, the source/drain includes an epitaxial structure coupled to adjacent nanoplates. For example, source/drain 464 is coupled to nanoplatelets 461, and source/drain 465 is coupled to nanoplatelets 462. In some embodiments, the source/drain is grown by an epitaxial process.

The memory device 400 also includes interconnects MDLI, MDLI as described with respect to fig. 3A-3C. In the exemplary configuration in fig. 4A, interconnect MDLI1 extends around source/drain 464, 465 and is electrically coupled to source/drain 464, 464. Interconnect MDLI2 is similarly configured as shown in fig. 4B. Exemplary materials for interconnect MDLI include metals.

As shown in fig. 4A-4B, the memory device 400 also includes various MD contacts, VD vias, VG vias, and BMD contacts, BVD vias, BVG vias on the front side, as described with respect to fig. 3A-3C. The memory device 400 also includes a front side redistribution structure 466 and a back side redistribution structure 467. The front side redistribution structure 466 is on the front side, over VD, VG vias, and includes various metal layers M0, M1, etc., as well as via layers V0, V1, etc., as described herein. The backside redistribution structure 467 is on the backside, underneath the BVD, BVG via and includes various backside metal layers BM0, BM1, etc., as well as backside via layers BV0, BV1, etc., as described herein. In the example configuration in fig. 4A, via BVD1 extends through substrate 440 from backside 442 to front side 441 to make physical and electrical contact with BMD contact BMD 1. BM0 conductive pattern BM0-1 is on the backside 442 of substrate 440 and is in physical and electrical contact with via BVD 1. Although not shown in fig. 4A, BVG vias extend through the substrate 440 in a similar manner and electrically couple the gate on the front side with the BM0 conductive pattern on the back side. Various metal layers and via layers in the front and back redistribution structures 466 and 467 are omitted for simplicity.

As shown in fig. 4C, the memory device 400 includes interconnects BCT1, BCT2 corresponding to over interconnects MDLI1, MDLI2. As shown in fig. 4D, interconnect BCT2 is also over gate G1. Accordingly, interconnect BCT2 electrically couples gate G1 to interconnect MDLI2. Similarly (although not shown), interconnect BCT1 electrically couples gate G4 to interconnect MDLI1.

Although not shown in fig. 4D, the memory device 400 includes V0 vias that electrically couple the M0 conductive patterns M0-5 to the front side word lines WL in the overlying M1 layer. In at least one embodiment, one or more of the advantages described herein may be realized by the memory device 400.

Fig. 5 is a schematic diagram of a layout of a memory cell 500 according to some embodiments. In some embodiments, memory cell 500 corresponds to one or more of memory cell 200 and/or one or more of memory cells MC in memory devices 100A, 100B, 100C. In some embodiments, the map of memory cells 500 is stored in a cell library and/or on a non-transitory computer readable recording medium. Fig. 5 is similar to fig. 3C. For simplicity, components in memory cell 500 that correspond to components in memory cell 300 are indicated by the same reference numbers as memory cell 300 or by an increase of 200 in the reference numbers of memory cell 300.

Memory cell 500 is an example of a memory cell electrically coupled to and accessible through a backside word line. This is in contrast to memory cell 300, which memory cell 300 is an example of a memory cell that is electrically coupled to and accessible through a front side word line. In contrast to memory cell 300, memory cell 500 includes vias BVG1, BVG2 and BM0 conductive patterns BM0-2, BM0-5 instead of vias VG1, VG2 and M0 conductive patterns M0-2, M0-5. The M0 track 521 in the memory cell 500 differs from the corresponding M0 track 321 in that the M0 track 521 is not configured for a word line. In contrast, the memory cell 500 includes a BM0 track 531 configured for a backside word line, and a BM0 conductive pattern BM0-2 (designated BWL-1) is disposed along the BM0 track 531. Furthermore, M0 track 524 in memory cell 500 differs from corresponding M0 track 324 in that M0 track 524 is not configured for a word line. Instead, the memory cell 500 includes a BM0 track 534 configured for a backside word line, and BM0 conductive patterns BM0-5 (designated BWL-2) are disposed along the BM0 track 534.

The memory cell 500 also includes a backside word line BWL disposed in the BM1 layer. The backside word line BWL includes a BM1 conductive pattern that extends continuously along the Y-axis over the entire height of the memory cell 500. For simplicity, portions of the backside word line BWL under memory cell 500 are not shown. Although not shown in fig. 5, the backside word line BWL further extends continuously over other memory cells (to abut each other with the memory cell 500 or the memory cell 500) placed along the Y-axis. In the example configuration in fig. 5, the Y-axis corresponds to the R-axis described with respect to fig. 1A-1C.

The memory cell 500 also includes two BV0 vias (not shown) over the corresponding BM0 conductive patterns BM0-2, BM0-5 to electrically couple the backside word line BWL to the BM0 conductive patterns BM0-2, BM0-5, then to the vias BVG, BVG2, and then to the gate regions G2, G3 of the access transistors T1, T2. In at least one embodiment, the access transistors T1, T2 are turned on and allow access to data stored in the memory cell 500 in response to an access voltage applied to the backside word line BWL. In at least one embodiment, one or more of the advantages described herein may be realized by a memory device including one or more memory cells 500.

Fig. 6 is a schematic cross-sectional view of a portion of a memory device 600 according to some embodiments. The portion of the memory device 600 in fig. 6 corresponds to the memory cell 500. The view in fig. 6 is similar to the view in fig. 4D and corresponds to a Y-axis cross-sectional view taken along line D-D' in fig. 5. For simplicity, corresponding parts in fig. 5 and 6 are denoted by the same reference numerals.

As shown in fig. 6, BM0 conductive patterns BM0-5 are electrically coupled to the gate electrode G3 through the via BVG 2. The via BVG2 extends through a substrate (not shown) corresponding to the substrate 440. Although not shown in fig. 6, the memory device 600 includes BV0 vias that electrically couple the BM0 conductive patterns BM0-5 to backside word lines BWL in the underlying BM1 layer. The cross-sectional view of the memory device 600 along lines A-A ', B-B ', C-C ' in fig. 5 is correspondingly similar to the view in fig. 4A-4C, except that the front side word line WL in the M1 layer in fig. 4A-4C is replaced by the back side word line BWL in the BM1 layer. In at least one embodiment, one or more of the advantages described herein may be realized by the memory device 600.

Fig. 7 is a schematic cross-sectional view of a portion of a memory device 700 according to some embodiments. In some embodiments, portions of memory device 700 in FIG. 7 correspond to portions of one or more of memory devices 100A-100C.

Specifically, the memory device 700 includes a memory row 701 and a corresponding word line driver 703, the word line driver 703 being electrically coupled to memory cells MC in the memory row 701 through a back side word line 710 and a front side word line 720. In some embodiments, memory row 701 corresponds to one or more of memory rows R [0], R [1], R [2], etc., word line driver 703 corresponds to one or more of word line drivers 130, 131, 132, etc., backside word line 710 corresponds to one or more of backside word lines BWL [0], BWL [1], BWL [2], etc., and frontside word line 720 corresponds to one or more of frontside word lines WL [0], WL [1], WL [2], etc. Fig. 7 is a combined view of an X-axis cross-sectional view and a Y-axis cross-sectional view. The X-axis cross-sectional view is to the right of line 704 and shows memory row 701 and corresponding word lines 710, 720. The Y-axis cross-sectional view is to the left of line 704 and shows word line driver 703.

In the example configuration in fig. 7, the word line driver 703 includes a plurality of CFET devices coupled in a configuration referred to as a multi-finger driver. In such a configuration, each finger corresponds to one gate. For example, two gates 705, 706 are shown in fig. 7 and correspond to two fingers of the word line driver 703. The number of gates/fingers and/or CFET devices in the word line driver 703 is not limited to a particular number and is determined in one or more embodiments based on the expected drive strength of the word line driver, which in turn depends on other factors including the word line load associated with the memory row 701. The CFET device including gates 705, 706 is configured as an inverter. Gates 705, 706 are electrically coupled together to receive a drive signal WLB, which in one or more embodiments corresponds to one or more of drive signals WLB (0), WLB (1), WLB (2), etc. The word line driver 703 is configured to output an access voltage (not numbered) at MDLI interconnect 708 in response to a drive signal WLB, the MDLI interconnect 708 being located at the last inverter and configuring the output of the word line driver 703. MDLI interconnect 708 is electrically coupled to backside word line 710 by connection 711 including BVD via, BM0 conductive pattern, and BV0 via. MDLI interconnect 708 is also electrically coupled to front side word line 720 by a connection 721 that includes VD vias, M0 conductive patterns, and V0 vias.

The memory row 701 includes memory cells 740 in a first section and electrically coupled to the front side word line 720, memory cells 760 in a second section and electrically coupled to the back side word line 710, and dummy memory cells 750 between the first section and the second section. In some embodiments, one or more of memory cells 740 correspond to portions of memory cell 300 and/or memory device 400 described with respect to fig. 4A-4D, while front side word line 720 corresponds to front side word line WL described with respect to fig. 3C and 4A-4D. In some embodiments, one or more of memory cells 760 correspond to portions of memory cell 500 and/or memory device 600 described with respect to fig. 5-6, while backside word line 710 corresponds to backside word line BWL described with respect to fig. 5-6.

The backside word line 710 includes a first section 715 and a second section 716 continuous with the first section 715. In some embodiments, the first section 715 and the second section 716 correspond to the first section 115 and the second section 116 of the backside word line described with reference to fig. 1A. The first section 715 extends below the memory cells 740 and is parallel to the front side word line 720 without being electrically coupled to the memory cells 740. In some embodiments, the layout of each of the memory cells 740 is as shown in FIG. 3C, where a backside word line BWL is added in the BM1 layer as described with respect to FIG. 5, but the backside word line BWL is not electrically coupled to the gates G1-G4. In other words, the first section 715 flies through the memory cells 740. The second section 716 extends continuously from the first section 715 and beyond the front side word line 720. The front side word line 720 is a shortened word line in the memory device 700.

The backside word line 710 described is an example of a backside word line formed in a single metal layer, i.e., both the first section 715 and the second section 716 are in the same metal layer, e.g., in the BM1 layer. Fig. 7 further illustrates an alternative configuration of backside word lines formed in multiple metal layers. In an alternative configuration, the backside word line 710' includes a first section 715' in the BM3 layer and a second section 716 in the BM1 layer, the second section 716 being closer to the memory row 701 or a memory array comprising the memory row 701 than the first section 715' of the BM3 layer. The first section 715' is electrically coupled to MDLI interconnect 708 by connection 711 and another connection 712 including BM1 conductive pattern, BV1 via, BM2 conductive pattern, and BV2 via. The first section 715 is also electrically coupled to the second section 716 by a connection 713 including BV1 vias, BM2 conductive patterns, and BV2 vias.

Compared to the backside word line 710, the backside word line 710 'includes a first section 715' in the BM3 layer, the first section 715 'being farther from the memory row 701 than the first section 715, and in one or more embodiments, the first section 715' has a wider metal width than the first section 715. As a result, in at least one embodiment, the backside word line 710' in multiple metal layers exhibits lower resistance and capacitance than the backside word line 710 in a single metal layer, and further improves performance and/or power consumption. In at least one embodiment, one or more of the advantages described herein may be realized by a memory device 700 having a backside word line 710 or backside word line 710'.

The memory device 700 described with respect to fig. 7 includes a back side word line 710 or back side word line 710' as a fly word line on the back side. Other configurations having a flyer line on the front side are within the scope of the various embodiments. Further, in one or more embodiments, the flylines on the front side may be configured in a single metal layer (e.g., M1 layer) or multiple metal layers (e.g., M1 layer and M3 layer). In at least one embodiment, one or more of the advantages described herein may be realized by a memory device including a flyword line on a front side.

Fig. 8A is a schematic circuit diagram of a portion of a memory device 800A, fig. 8B is an exploded schematic diagram of a corresponding portion of a layout diagram 800B of the memory device 800, and fig. 8C is a simplified schematic diagram of a portion of the layout diagram 800B, according to some embodiments.

In the example configuration in fig. 8A, memory device 800A includes components corresponding to those of memory device 700 and are denoted by the same reference numerals as the corresponding components of memory device 700. Memory device 800A includes a portion 801, which portion 801 includes memory cells 740 electrically coupled to front side word lines WL, dummy memory cells 750, and memory cells 760 electrically coupled to back side word lines BWL as flyword lines. Layout diagrams of the portion 801 are described with respect to fig. 8B, 8C.

In fig. 8B, a layout diagram 800B of a memory device 800A includes a portion corresponding to the portion 801 in fig. 8A, shown in an exploded view. Layout 800B includes memory cells 840, 850, 860 corresponding to memory cells 740, 750, 760 in fig. 8A. Memory cell 840 has the same layout as memory cell 300. Memory cell 850 has a layout of memory cell 300 'with memory cell 300' being a version of memory cell 300 flipped across the Y-axis. Memory cell 860 has the same layout as memory cell 500. In some embodiments, the layout 800B is generated by loading one or more cells from a cell library and placing the loaded cells in abutment along the X-axis and/or the Y-axis. In some embodiments, the layout 800B is generated in part of an Automatic Placement and Routing (APR) method. In some embodiments, one or more operations of the APR method are performed by an APR system, such as the systems included in the EDA systems described herein. In some embodiments, one or more operations of the APR method are performed by a processor, such as the processor of the EDA system described herein.

For example, in an APR operation, edge 842 of memory cell 840 is placed adjacent to edge 851 of memory cell 850 and edge 852 of memory cell 850 is placed adjacent to edge 861 of memory cell 860 while edges 843, 844 of memory cell 840 are aligned with edges 853, 854 of memory cell 850 and edges 863, 864 of memory cell 860. As a result, the M0 conductive patterns 845, 846 of memory cell 840 merge with the M0 conductive patterns 855, 856 of memory cell 850, respectively, and the M0 conductive pattern 857 of memory cell 850 merges with the M0 conductive pattern 867 of memory cell 860. The M0 conductive pattern 858 of the memory cell 850 overlaps the BM0 conductive pattern 868 of the memory cell 860.

In fig. 8C, a simplified schematic diagram of a portion of a layout 800B obtained after sequentially adjoining memory cells 840, 850, 860 along the Y-axis is shown. For simplicity, the boundaries of the memory cells 840, 850, 860 and the M0 or BM0 conductive patterns for coupling to the front side and back side word lines are shown in fig. 8C, while other components of the memory cells 840, 850, 860 are omitted.

In layout 800B, the front side word line WL extends over the memory cell 840 along the Y-axis and is electrically coupled to the M0 conductive patterns 848, 845 through corresponding V0 vias (not shown). The front side word line WL does not extend beyond the memory cell 860. The back side word line BWL overlaps the front side word line WL along the Z-axis and extends below the memory cells 840, 850, 860 along the Y-axis. The backside word line BWL is not electrically coupled to the memory cell 840. The backside word line BWL is electrically coupled to the BM0 conductive patterns 865, 868 through corresponding BV0 vias (not shown). In the example configuration in fig. 8C, the width of the front side word line WL and the back side word line BWL along the X-axis approximates the cell width of the memory cells 840, 850, 860 along the X-axis. In at least one embodiment, one or more of the advantages described herein may be realized by the memory device 800A and/or the IC device corresponding to the layout 800B.

Fig. 9A is a schematic circuit diagram of a portion of a memory device 900A, fig. 9B is an exploded schematic diagram of a corresponding portion of a layout diagram 900B of the memory device 900A, and fig. 9C is a simplified schematic diagram of the portion of the layout diagram 900B, according to some embodiments.

Although not shown in fig. 9A, the memory device 900A includes a memory array, a plurality of word lines, a plurality of bit lines, and a controller including a word line driver, as described with respect to fig. 1A-1C. In the portion shown in FIG. 9A, memory device 900A includes memory rows R [ j ], R [ j+1] of the memory array, front side word line WL [ j ] and back side word line BWL [ j+1] of the plurality of word lines, and word line drivers DRV [ j ], DRV [ j+1] of the word line drivers of the memory controller, where j is a natural number less than m. The front side word line WL [ j ] is electrically coupled to the output of word line driver DRV [ j ], and the back side word line BWL [ j+1] is electrically coupled to the output of word line driver DRV [ j+1 ]. As a result, the front side word line WL [ j ] and the back side word line BWL [ j+1] are independently controlled by the corresponding word line drivers DRV [ j ], DRV [ j+1 ]. One of the front side word line WL [ j ] and the back side word line BWL [ j+1] is an even word line, and the other of the front side word line WL [ j ] and the back side word line BWL [ j+1] is an odd word line. In some embodiments, repeating the portion of memory device 900A shown in fig. 9A in the column direction (i.e., the C-axis) results in a hybrid word line configuration with even front side word lines and odd back side word lines, or with odd front side word lines and even back side word lines.

Each memory cell MC in memory row R j and memory cell MC in a corresponding or adjacent memory row R j +1 are arranged in the same memory column of the plurality of memory columns in the memory array of memory device 900A. For example, memory row R [ j ] includes memory cells 910-913, and memory row R [ j+1] includes memory cells 920-923. Adjacent or corresponding memory cells 910, 920 belong to a first memory column and are coupled to the same bit line BL (not shown) or the same pair of bit lines BL, BLB (not shown). Similarly, the corresponding memory cell 911, 921 belongs to the second memory column, the corresponding memory cell 912, 922 belongs to the third memory column, and so on.

Each memory cell MC in memory row R [ j ] is electrically coupled to one of front side word line WL [ j ] and back side word line BWL [ j+1], while the corresponding memory cell MC in memory row R [ j+1] is electrically coupled to the other of front side word line WL [ j ] and back side word line BWL [ j+1]. In the example configuration in FIG. 9A, all memory cells 910-913 in memory row R [ j ] and the like are coupled to front side word line WL [ j ], and all corresponding memory cells 920-923 in memory row R [ j+1] and the like are coupled to back side word line BWL [ j+1].

In some embodiments, at least one memory cell in a memory row may be coupled to a front side word line, while at least one other memory cell in the same memory row is coupled to a back side word line. For example, in at least one example embodiment, memory cells 910 in memory row R [ j ] are electrically coupled to backside word line BWL [ j+1], while other memory cells 911-913 in memory row R [ j ] are electrically coupled to front side word line WL [ j ]. In such an example embodiment, the corresponding memory cells 920 in memory row R [ j+1] are electrically coupled to the front side word line WL [ j ], while the other corresponding memory cells 921-923 in memory row R [ j+1] are electrically coupled to the back side word line BWL [ j+1]. In some embodiments, there is no restriction or constraint on which memory cell in a memory row will be coupled to a front side word line and which additional memory cell in the same memory row will be coupled to a back side word line. For example, any memory cell in memory row R [ j ] may be electrically coupled to either of front side word line WL [ j ] and back side word line BWL [ j+1], provided that the corresponding memory cell in memory row R [ i+1] is electrically coupled to the other of front side word line WL [ j ] and back side word line BWL [ j+1]. In one or more embodiments, any arrangement (or dichotomy) of memory cells electrically coupled to front side word lines and memory cells electrically coupled to back side word lines along a memory row is possible. Other example embodiments in which memory cells in a memory row are coupled to a front side word line and a back side word line are described with respect to fig. 9D-9F. A layout of a portion 901 including memory cells 911, 912, 921, 922 in fig. 9A described with respect to fig. 9B, 9C.

In fig. 9B, a layout diagram 900B of a memory device 900A includes a portion corresponding to a portion 901 in fig. 9A, which is shown in an exploded view. In layout 900B, memory cell 911 has the same layout as memory cell 300', memory cell 912 has the same layout as memory element 300, memory cell 921 has the same layout as memory cell 500, and memory cell 922 is the layout of memory cell 500', memory cell 500' being the flipped version of memory cell 500 across the Y-axis. In some embodiments, the map 900B is generated by an APR operation as described herein. For example, in an APR operation, the facing edges of memory cells 911, 912, 921, 922 are placed in abutment, as indicated schematically by double-ended arrow 930. As a result, the M0 conductive patterns 931 of the memory cells 911, 912, 921, 922 are merged into a common M0 conductive pattern for VSS, the M0 conductive patterns 934 of the memory cells 911, 912 are merged into a common M0 conductive pattern for the front side word line, and the BM0 conductive patterns 935 of the memory cells 921, 922 are merged into a common BM0 conductive pattern for the back side word line.

In fig. 9C, a simplified schematic diagram of a portion of a layout 900B obtained after adjoining memory cells 911, 912, 921, 922 is shown. For simplicity, the boundaries of the memory cells 911, 912, 921, 922 and their M0 or BM0 conductive patterns for coupling to the front side and back side word lines are shown in fig. 9C, while other components of the memory cells 911, 912, 921, 922 are omitted.

In layout 900B, the front side word line WL [ j ] extends along the Y-axis along the length of memory rows R [ j ], R [ j+1] and overlaps with the memory cells of memory rows R [ j ], R [ j+1 ]. Likewise, the backside word line BWL [ j+1] extends along the Y-axis along the length of memory rows R [ j ], R [ j+1] and overlaps with memory cells of memory rows R [ j ], R [ j+1 ]. For simplicity, the backside word line BWL [ j+1] is indicated schematically in FIG. 9C and is not shown entirely. The front side word line WL [ j ] is electrically coupled to the underlying memory cells through V0 vias (not shown) and corresponding M0 conductive patterns 932, 934, 936. The backside word line BWL [ j+1] is electrically coupled to the overlying memory cells through BV0 vias (not shown) and corresponding BM0 conductive patterns 933, 935, 937.

The back side word line BWL [ j+1] overlaps the front side word line WL [ j ] along the Y-axis by more than the length of the memory rows R [ j ], R [ j+1], and has substantially the same width as the front side word line WL [ j ] along the X-axis. In the example configuration in FIG. 9C, the width of the front side word line WL [ j ] and the back side word line BWL [ j+1] along the X axis is greater than the cell width of each memory cell 911, 912, 921, 922 along the X axis and is approximately twice the cell width. In some embodiments, the width of the front side word line WL [ j ] and the back side word line BWL [ j+1] are approximately twice the width of the front side word line and the back side word line described with respect to fig. 8C. With such a wider width, in one or more embodiments, the resistance of the front side word line WL [ j ] and the back side word line BWL [ j+1] may be reduced, word line loading may be reduced, and performance and/or power consumption may be improved without the area penalty associated with, for example, a dummy memory cell. In at least one embodiment, one or more of the advantages described herein may be realized by the memory device 900A and/or the IC device corresponding to the layout 900B.

9D-9F are schematic circuit diagrams of various portions of memory devices 900D-900F according to some embodiments. In some embodiments, one or more of memory devices 900D-900F correspond to one or more of memory devices 100A-100C and 900A. For simplicity, corresponding parts in fig. 9A and 9D-9F are denoted by the same reference numerals.

In FIGS. 9D-9E, memory cells 910-917, etc., of memory row R [ j ] include a plurality of first memory cells electrically coupled to front side word line WL [ j ], and a plurality of second memory cells electrically coupled to back side word line BWL [ j+1 ]. The memory cells 920-927, etc., of the memory row R [ j+1] include a plurality of third memory cells corresponding to the first memory cell in the memory row R [ j ] and electrically coupled to the backside word line BWL [ j+1], and a plurality of fourth memory cells corresponding to the second memory cell in the memory row R [ j ] and electrically coupled to the front side word line WL [ j ].

For example, in memory device 900D in FIG. 9D, memory row R [ j ] includes first memory cells 910, 912, 914, 916, etc. electrically coupled to front side word line WL [ j ], and second memory cells 911, 913, 915, 917, etc. electrically coupled to back side word line BWL [ j+1 ]. The memory row R [ j+1] includes third memory cells 920, 922, 924, 926, etc. electrically coupled to the backside word line BWL [ j+1], and fourth memory cells 921, 923, 925, 927, etc. electrically coupled to the front side word line WL [ j ]. The first memory units 910, 912, 914, 916, etc. are arranged in a plurality of first memory unit groups, each having one first memory unit, and the second memory units 911, 913, 915, 917, etc. are arranged in a plurality of second memory unit groups, each having one second memory unit. The first memory cell group and the second memory cell group are alternately arranged along the memory row R [ j ]. As a result, the first memory cells 910, 912, 914, 916, etc. are alternately arranged with the second memory cells 911, 913, 915, 917, etc. along the memory row R [ j ]. The third memory cells 920, 922, 924, 926, etc. and the fourth memory cells 921, 923, 925, 927, etc. in the memory row R [ j+1] are grouped and/or arranged in a similar manner. In some embodiments, the layout of memory device 900D is similar to layout 900B, except that along each of memory rows R [ j ], R [ j+1], M0 conductive patterns for front side word line WL [ j ] are alternately arranged with BM0 conductive patterns for back side word line BWL [ j+1 ].

For another example, in memory device 900E in FIG. 9E, memory row R [ j ] includes first memory cells 910, 911, 914, 915, etc. electrically coupled to front side word line WL [ j ], and second memory cells 912, 913, 916, 917, etc. electrically coupled to back side word line BWL [ j+1 ]. The memory row R [ j+1] includes third memory cells 920, 921, 924, 925, etc. electrically coupled to the backside word line BWL [ j+1], and fourth memory cells 922, 923, 926, 927, etc. electrically coupled to the front side word line WL [ j ]. The first memory units 910, 911, 914, 915, etc. are arranged in a plurality of first memory unit groups, each having two first memory units, e.g., a memory unit group of the memory units 910, 911, and another memory unit group of the memory units 914, 915, etc. The second memory units 912, 913, 916, 917, etc. are arranged in a plurality of second memory unit groups, each having two second memory units, for example, a memory unit group of the memory units 912, 913, and another memory unit group of the memory units 916, 917, etc. The first memory cell group and the second memory cell group are alternately arranged along the memory row R [ j ]. The third memory cells 920, 921, 924, 925, etc. and the fourth memory cells 922, 923, 926, 927, etc. in the memory row R [ j+1] are grouped and/or arranged in a similar manner.

The memory devices 900D, 900E are examples of the first memory cell group and the second memory cell group having the same number of memory cells, i.e., the first memory cells electrically coupled to the front side word line WL [ j ] and the second memory cells electrically coupled to the back side word line BWL [ j+1] are arranged at fixed intervals and/or in a repeating pattern along the memory row R [ j ]. However, as described herein, in one or more embodiments, any arrangement (or dichotomy) of memory cells electrically coupled to the front side word line and memory cells electrically coupled to the back side word line is possible. For example, in some embodiments, a first group of memory cells includes a plurality of memory cells that are different from another first group of memory cells and/or different from a second group of memory cells.

In fig. 9F, the memory device 900F is an example in which first memory cells 910, 912, 916, 917, etc. electrically coupled to the front side word line WL [ j ], and second memory cells 911, 913, 914, 915, etc. electrically coupled to the back side word line BWL [ j+1], are arranged in a random manner along the memory row R [ j ] without a repeating pattern. In at least one embodiment, one or more of the advantages described herein may be realized by one or more of the memory devices 900D-900F.

Fig. 10A is a flow chart of a method 1000A of manufacturing an IC device according to some embodiments. In some embodiments, method 1000A may be used to fabricate one or more memory devices as described herein.

At operation 1005, a plurality of CFET devices are formed over a front side of a substrate, the CFET devices configuring a plurality of memory cells arranged in a memory array. For example, various CFET devices are formed over front side 441 of substrate 440 to configure memory cells as described with respect to fig. 4A-4D.

Referring to fig. 4A-4D, an exemplary fabrication process begins with a substrate 440. In some embodiments, the substrate 440 is a silicon-on-insulator (SOI) substrate having a semiconductor body and an insulating layer on the semiconductor body. Other substrate configurations are within the scope of the various embodiments.

Alternating layers of a first semiconductor material and a second semiconductor material different from the first semiconductor material are sequentially deposited over the front side 441 of the substrate 440. In some embodiments, the first semiconductor material comprises silicon and the second semiconductor material comprises SiGe. As a result, alternating SiGe/Si/SiGe/Si layers are stacked on the front side 441 of the substrate 440. In some embodiments, alternating layers of SiGe/Si/SiGe/Si are formed by an epitaxial process. Other materials and/or fabrication processes for alternating layers of different first and second semiconductor materials are within the scope of the various embodiments.

In some embodiments, a dummy gate structure (not shown) is formed over the alternating layers of SiGe/Si/SiGe/Si, serving as a mask for subsequent patterning and subsequent formation of metal gates. In one example, each dummy gate structure includes various dummy layers, such as a dummy gate electrode (e.g., polysilicon), a hard mask layer (e.g., siN, siCN, siO, etc.). The dummy gate structure is formed by a deposition process, a photolithography process, an etching process, a combination thereof, and the like. The alternating layers SiGe/Si/SiGe/Si are patterned by using the dummy gate structure as a mask.

Next, various semiconductor devices are manufactured. In at least one embodiment, isolation regions are formed in the trenches to separate and electrically isolate the active regions of the devices to be fabricated. In some embodiments, one or more dielectric materials, such as SiO and/or SiN, are deposited, for example, by Chemical Vapor Deposition (CVD), plasma Enhanced CVD (PECVD), atomic Layer Deposition (ALD), physical vapor deposition, thermal oxidation, or the like. Subsequently, the dielectric material is recessed, for example by etching and/or Chemical Mechanical Polishing (CMP), to form isolation regions.

In some embodiments, the SiGe at the exposed edge of the alternating layers SiGe/Si/SiGe/Si is selectively removed by an etching process. In some embodiments, the selective removal of SiGe includes an oxidation process followed by a selective etch.

In some embodiments, source/drain features similar to source/drains 464, 465 are epitaxially grown as an epitaxial structure. The source/drain features are grown in contact with the exposed edges of the Si layer. Example epitaxial processes include, but are not limited to, CVD deposition, ultra high vacuum CVD (UHV-CVD), low Pressure CVD (LPCVD), plasma Enhanced CVD (PECVD), selective Epitaxial Growth (SEG), and the like.

In some embodiments, a metal gate replacement process is performed to replace the dummy gate structure with a metal gate structure. In some embodiments, the dummy gate structure is removed by one or more etching processes, such as wet etching, dry etching, and the like. The SiGe layer is selectively removed by a selective oxidation/etching process. The Si layer remains and the nanoplates 461, 462 for the top and bottom semiconductor devices are configured. The metal gate structure is formed to wrap around the nanoplates 461, 462. In some embodiments, each metal gate structure includes a gate dielectric surrounding the nanoplates 461, 462, and a metal gate, such as gate G1, over the gate dielectric to obtain corresponding top and bottom semiconductor devices, such as transistors N1, P1. Example materials for the gate dielectric include high-k dielectric materials such as HfO₂、HfSiO、HfSiO₄、HfSiN、HfLaO、HfTaO、Hf-TiO、Hf ZrO、Hf/AlOx、ZrO、ZrO₂、ZrSiO₂、AlO、AlSiO、Al₂O₃、TiO、TiO₂、LaO、LaSiO、Ta₂O₃、Ta₂O₅、Y₂O₃、SrTiO₃、BaZrO、BaTiO₃(BTO)、(Ba,Sr)TiO₃(BST)、Si₃N₄、 hafnium oxide-aluminum oxide (HfO ₂-Al₂O₃) alloy, and the like. In some embodiments, the gate dielectric is deposited by CVD, PVD, ALD or the like. In some embodiments, each metal gate comprises one or more metals, such as Al, cu, W, ti, ta, tiN, taN, niSi, coSi, and is formed by, for example, CVD, ALD, PVD, electroplating, chemical oxidation, thermal oxidation, or the like.

One or more interconnects MDLI, MD contact structures, VD vias, VG vias are formed, for example, by etching and metal deposition operations.

At operation 1010, deposition and patterning operations are performed to form a front-side redistribution structure on a front side of a substrate. The front side redistribution structure includes a front side word line over the memory array and electrically coupled to at least one memory cell of the plurality of memory cells. For example, a front side redistribution structure 466 is formed over the front side 441 of the substrate 440. The front side redistribution structure 466 includes a front side word line WL, e.g., in the M1 layer, over the memory array and electrically coupled to at least one memory cell of the plurality of memory cells, as described herein, e.g., with respect to one or more of fig. 1A-1C, 7.

At operation 1015, deposition and patterning operations are performed to form a backside redistribution structure on the backside of the substrate. The backside redistribution structure includes a backside word line located under the memory array and electrically coupled to at least one other memory cell of the plurality of memory cells. For example, after the front side redistribution structure 466 is formed, the IC device being fabricated is flipped upside down and temporarily bonded to the carrier. Wafer thinning is performed from the backside 442 (now facing upward) to remove portions of the substrate 440. In some embodiments, the wafer thinning process includes a polishing operation, a grinding operation (e.g., chemical Mechanical Polishing (CMP)), and the like. In at least one embodiment, the original substrate used to form the CFET device is completely removed and a new substrate, such as an insulating substrate, is formed over the CFET device. A backside redistribution structure 467 is formed on the backside 442 of the substrate 440 by deposition and patterning operations. The backside redistribution structure 467 includes backside word lines BWL, e.g., in the BM1 layer, under the memory array and electrically coupled to at least one further memory cell of the plurality of memory cells, as described herein, e.g., with respect to one or more of fig. 1A-1C, fig. 7.

In some embodiments, one or more IC devices fabricated by method 1000A may realize one or more of the advantages described herein. Although the described fabrication process includes forming a nanoplatelet device in one or more embodiments, other types of devices, such as nanowires, finfets, planes, etc., are also within the scope of the various embodiments. The described manufacturing process and/or sequence of operations are examples. Other manufacturing processes and/or sequences of operations are within the scope of the various embodiments.

FIG. 10B is a flowchart of a method 1000B of operating a memory device, according to some embodiments. In some embodiments, method 1000B may be used to operate one or more memory devices as described herein, for example, with respect to one or more of fig. 1A-1C, fig. 2, fig. 7.

At operation 1030, an access voltage is applied to the memory cells in the row through a first word line above the row and a second word line below the row. The first word line is electrically coupled to a first memory cell of the memory cells in the row, and the second word line is electrically connected to a second memory cell of the memory cells in the row. For example, as described with respect to FIG. 1A, the controller 102 controls the word line driving circuit 103 to apply (e.g., through the word line driver 130) an access voltage WL (0) to the memory cells MC in the memory row R [0] through the front side word line WL [0] above the memory array 101 and the back side word line BWL [0] below the memory array 101. The front side word line WL [0] is electrically coupled to the first memory cells of the first bank 111 in memory row R [0] and the back side word line BWL [0] is electrically coupled to the second memory cells of the second bank 112 in memory row R [0 ].

At operation 1035, data is read from the first memory cell and the second memory cell while ignoring data read from dummy memory cells in the row and between the first memory cell and the second memory cell. For example, as described with respect to fig. 1A, the controller 102 controls the bit line multiplexer 104 and/or the read/write circuit 105 to read data from the first memory cells of the first bank 111 and from the second memory cells of the second bank 112 through the respective bit lines BL. In such a read operation, as described with respect to FIG. 1A, data read from the dummy memory cells DMC in the memory row R [0] and between the first memory cells of the first bank 111 and the second memory cells of the second bank 112 are ignored. In some embodiments, performance and/or power consumption may be improved by using front side and back side word lines to access memory cells in memory array 101, as described herein.

The described methods include example operations, but are not necessarily required to be performed in the order shown. Operations may be added, replaced, sequenced, and/or eliminated as appropriate in accordance with the spirit and scope of embodiments of the present disclosure. Embodiments combining different features and/or different embodiments are within the scope of some embodiments of the present disclosure and will be apparent to those of skill in the art upon reading some embodiments of the present disclosure.

In some embodiments, at least one of the methods discussed above is performed in whole or in part by at least one EDA system. In some embodiments, the EDA system may be used as part of a design room of an IC manufacturing system discussed below.

FIG. 11 is a block diagram of an Electronic Design Automation (EDA) system 1100, according to some embodiments.

In some embodiments, the EDA system 1100 includes an APR system. In accordance with one or more embodiments, the methods of designing a layout described herein represent that the wiring arrangement is practicable, e.g., using the EDA system 1100 in accordance with some embodiments.

In some embodiments, the EDA system 1100 is a general-purpose computing device that includes a hardware processor 1102 and a non-transitory computer-readable storage medium 1104. The storage medium 1104 is encoded with (i.e., stores) computer program code 1106 (i.e., a set of executable instructions). Execution of code 1106 represents (at least in part) an EDA tool by hardware processor 1102 that implements part or all of the methods discussed herein with respect to one or more embodiments (hereafter referred to as processes and/or methods).

The processor 1102 is electrically coupled to a computer-readable storage medium 1104 via bus 1108. The processor 1102 is also electrically coupled to an I/O interface 1110 via bus 1108. A network interface 1112 is also electrically connected to the processor 1102 via bus 1108. The network interface 1112 is connected to the network 1114 so that the processor 1102 and the computer-readable storage medium 1104 can be connected to external elements via the network 1114. The processor 1102 is configured to execute computer program code 1106 encoded in the computer-readable storage medium 1104 to make the system 1100 available for performing part or all of the processes and/or methods. In one or more embodiments, the processor 1102 is a Central Processing Unit (CPU), multiprocessor, distributed processing system, application Specific Integrated Circuit (ASIC), and/or suitable processing unit.

In one or more embodiments, the computer-readable storage medium 1104 is an electronic, magnetic, optical, electromagnetic, infrared, and/or semiconductor system (or apparatus or device). For example, computer-readable storage media 1104 includes semiconductor or solid state memory, magnetic tape, removable computer diskette, random Access Memory (RAM), read-only memory (ROM), rigid magnetic disk and/or optical disk. In one or more embodiments using optical disks, computer-readable storage media 1104 includes a compact disk read-only memory (CD-ROM), compact disk read/write (CD-R/W), and/or Digital Video Disk (DVD).

In one or more embodiments, the storage medium 1104 stores computer program code 1106, the computer program code 1106 being configured to make the system 1100 (where such execution represents (at least part of) an EDA tool) available to perform part or all of the processes and/or methods. In one or more embodiments, the storage medium 1104 also stores some or all of the information that facilitates the execution of the processes and/or methods. In one or more embodiments, the storage medium 1104 stores a library 1107 of standard cells, including such standard cells disclosed herein.

The EDA system 1100 includes an I/O interface 1110. The I/O interface 1110 is coupled to external circuitry. In one or more embodiments, the I/O interface 1110 includes a keyboard, a keypad, a mouse, a track ball, a track pad, a touch screen, and/or cursor direction keys for communicating information and commands to the processor 1102.

The EDA system 1100 also includes a network interface 1112 coupled to the processor 1102. The network interface 1112 allows the EDA system 1100 to communicate with a network 1114, with one or more other computer systems connected to the network 1114. Network interface 1112 includes wireless network interfaces such as bluetooth, WIFI, WIMAX, GPRS, or WCDMA; or a wired network interface such as ethernet, USB, or IEEE-1364. In one or more embodiments, some or all of the processes and/or methods are implemented in two or more systems 1100.

System 1100 is configured to receive information via I/O interface 1110. The information received through I/O interface 1110 includes one or more of instructions, data, design rules, libraries of standard cells, and/or other parameters for processing by processor 1102. Information is transferred to processor 1102 through bus 1108. EDA system 1100 is configured to receive information related to a UI through I/O interface 1110. Information is stored in computer-readable medium 1104 as a User Interface (UI) 1142.

In some embodiments, some or all of the processes and/or methods are implemented as stand-alone software applications executed by a processor. In some embodiments, part or all of the process and/or method is implemented as a software application that is part of an additional software application. In some embodiments, part or all of the process and/or method is implemented as a plug-in to a software application. In some embodiments, at least one of the processes and/or methods is implemented as a software application as part of an EDA tool. In some embodiments, part or all of the processes and/or methods are implemented as software applications used by the EDA system 1100. In some embodiments, a layout including standard cells uses, for exampleIs generated by a tool or another suitable layout generation tool,/>Commercially available from CADENCE DESIGN SYSTEMS.

In some embodiments, these processes are implemented as functions of a program stored in a non-transitory computer-readable recording medium. Examples of the non-transitory computer readable recording medium include, but are not limited to, external/removable and/or internal/built-in storage or memory units, such as one or more of optical disks (e.g., DVD), magnetic disks (e.g., hard disk), semiconductor memories (e.g., ROM, RAM, memory card), and the like.

Fig. 12 is a block diagram of an Integrated Circuit (IC) manufacturing system 1200 and an IC manufacturing flow associated therewith, in accordance with some embodiments. In some embodiments, at least one of the following is manufactured using the manufacturing system 1200 based on the layout: (A) One or more semiconductor masks or (B) at least one component in a layer of a semiconductor integrated circuit.

In fig. 12, IC fabrication system 1200 includes entities such as design chamber 1220, mask chamber 1230, and IC manufacturer/manufacturer ("fab") 1250 that interact in the design, development, and manufacturing cycles and/or services associated with the fabrication of IC device 1260. The entities in system 1200 are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and/or wireless communication channels. Each entity interacts with and provides services to and/or receives services from one or more other entities. In some embodiments, two or more of design chamber 1220, mask chamber 1230, and IC fabrication facility 1250 are owned by a single larger company. In some embodiments, two or more of design chamber 1220, mask chamber 1230, and IC fabrication facility 1250 coexist in a common facility and use common resources.

Design room (or design team) 1220 generates an IC design layout 1222. The IC design layout 1222 includes various geometric patterns designed for the IC device 1260. The geometric pattern corresponds to the pattern of metal, oxide, or semiconductor layers that make up the various components of the IC device 1260 to be fabricated. The various layers are combined to form various IC components. For example, portions of the IC design layout 1222 include various IC components, such as active regions, gate electrodes, source and drain electrodes, metal lines or vias for interlayer interconnects, and openings for bond pads, formed in a semiconductor substrate (e.g., a silicon wafer) and in various material layers disposed on the semiconductor substrate. Design company 1220 implements the appropriate design program to form IC design layout 1222. The design process includes one or more of logical design, physical design, or placement and routing operations. The IC design layout 1222 is presented in one or more data files with information of the geometric pattern. For example, the IC design layout 1222 may be represented in a GDSII file format or a DFII file format.

Mask chamber 1230 includes data preparation 1232 and mask fabrication 1244. Mask chamber 1230 uses IC design layout 1222 to fabricate one or more masks 1245, mask 1245 being used to fabricate the various layers of IC device 1260 according to IC design layout table 1222. Mask chamber 1230 performs mask data preparation 1232 in which the IC design layout 1222 is translated into a representative data file ("RDF"). Mask data preparation 1232 provides RDF to mask fabrication 1244. Mask fabrication 1244 includes a mask writer. The mask writer converts RDF into an image on a substrate such as a mask (reticle) 1245 or a semiconductor wafer 1253. Mask data preparation 1232 manipulates design layout 1222 to meet the specific characteristics of the mask writer and/or requirements of IC fabrication facility 1250. In fig. 12, mask data preparation 1232 and mask fabrication 1244 are illustrated as separate elements. In some embodiments, mask data preparation 1232 and mask fabrication 1244 may be collectively referred to as mask data preparation.

In some embodiments, the mask data preparation 1232 includes Optical Proximity Correction (OPC) that uses lithographic enhancement techniques to compensate for image errors, such as may be caused by diffraction, interference, other process effects, and the like. OPC adjusts the IC design layout 1222. In some embodiments, mask data preparation 1232 includes further Resolution Enhancement Techniques (RET), such as off-axis illumination, sub-resolution assist features, phase shift masks, other suitable techniques, or the like, or combinations thereof. In some embodiments, reverse photolithography (ILT) is also used, which treats OPC as a reverse imaging problem.

In some embodiments, mask data preparation 1232 includes a Mask Rules Checker (MRC) that checks IC design layout 1222 that has been processed in OPC using a set of mask creation rules that contain certain geometric and/or connection constraints to ensure sufficient margin to account for variability of semiconductor manufacturing processes, etc. In some embodiments, the MRC modifies the IC design layout 1222 to compensate for limitations during mask fabrication 1244, which may undo some of the modifications performed by the OPC to satisfy the mask creation rules.

In some embodiments, mask data preparation 1232 includes a lithographic process inspection (LPC) that simulates the processing to be performed by IC fabrication factory 1250 to fabricate IC device 1260. The LPC simulates this process based on the IC design layout 1222 to create a device that simulates manufacturing, such as IC device 1260. The processing parameters in the LPC simulation may include parameters associated with various processes of the IC manufacturing cycle, parameters associated with tools used to manufacture the IC, and/or other aspects of the manufacturing process. The LPC accounts for various factors such as aerial image contrast, depth of focus ("DOF"), mask error enhancement factor ("MEEF"), other suitable factors, and the like, or combinations thereof. In some embodiments, after the simulated fabricated device is created by the LPC, OPC and/or MRC are repeated to further refine the IC design layout 1222 if the simulated device is not sufficiently close in shape to meet the design rules.

It should be appreciated that the above description of the mask data preparation 1232 has been simplified for clarity. In some embodiments, data preparation 1232 includes additional features, such as Logic Operations (LOPs), to modify IC design layout 1222 according to manufacturing rules. Further, the processing applied to the IC design layout 1222 during the data preparation 1232 may be performed in a variety of different orders.

After mask data preparation 1232 and during mask fabrication 1244, a mask 1245 or set of masks 1245 is fabricated based on the modified IC design layout 1222. In some embodiments, mask fabrication 1244 includes performing one or more photolithographic exposures based on the IC design layout 1222. In some embodiments, a pattern is formed on a mask (photomask or reticle) 1245 using an electron beam (e-beam) or multiple e-beam mechanism based on the modified IC design layout 1222. Mask 1245 may be formed using a variety of techniques. In some embodiments, the mask 1245 is formed using binary techniques. In some embodiments, the mask pattern includes opaque regions and transparent regions. A radiation beam, such as an Ultraviolet (UV) beam, used to expose a layer of image sensitive material (e.g., photoresist) that has been coated on a wafer is blocked by the opaque regions and transmitted through the transparent regions. In one example, the binary mask version of mask 1245 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in opaque regions of the binary mask. In another example, a mask 1245 is formed using a phase shift technique. In a Phase Shift Mask (PSM) version of mask 1245, various features in the pattern formed on the phase shift mask are configured with appropriate phase differences to enhance resolution and imaging quality. In various examples, the phase shift mask may be an attenuated PSM or an alternating PSM. The mask produced by mask fabrication 1244 is used in various processes. Such a mask may be used, for example, in an ion implantation process to form various doped regions in semiconductor wafer 1253, an etching process to form various etched regions in semiconductor wafer 1253, and/or in other suitable processes.

IC fabrication facility 1250 is an IC fabrication business that includes one or more fabrication facilities for fabricating a variety of different IC products. In some embodiments, IC fabrication facility 1250 is a semiconductor foundry. For example, there may be fabrication facilities for front end of line (FEOL) fabrication of multiple IC products, while a second fabrication facility may provide back end of line (BEOL) fabrication for interconnection and packaging of IC products, and a third fabrication facility may provide other services for foundry.

IC fab 1250 includes a fabrication tool 1252 configured to perform various fabrication operations on semiconductor wafer 1253 such that IC devices 1260 are fabricated in accordance with a mask (e.g., mask 1245). In various embodiments, the fabrication tool 1252 includes one or more of a wafer stepper, an ion implanter, a photoresist coater, a process chamber (e.g., a CVD chamber or an LPCVD furnace), a CMP system, a plasma etching system, a wafer cleaning system, or other fabrication equipment capable of performing one or more suitable fabrication processes herein.

IC fabrication facility 1250 uses mask 1245, which is fabricated by mask chamber 1230, to fabricate IC device 1260. Thus, IC fabrication facility 1250 uses IC design layout 1222, at least indirectly, to fabricate IC device 1260. In some embodiments, semiconductor wafer 1253 is fabricated by IC fabrication facility 1250 using mask 1245 to form IC device 1260. In some embodiments, IC fabrication includes performing one or more lithographic exposures based at least indirectly on the IC design layout 1222. Semiconductor wafer 1253 includes a silicon substrate or other suitable substrate having a layer of material formed thereon. Semiconductor wafer 1253 also includes one or more of various doped regions, dielectric features, multilevel interconnects, and the like (formed in subsequent fabrication steps).

In some embodiments, an Integrated Circuit (IC) device includes: a memory array including a plurality of memory cells; a first word line over the memory array and electrically coupled to at least one first memory cell of the plurality of memory cells; and a second word line located below the memory array and electrically coupled to at least one second memory cell of the plurality of memory cells, wherein each memory cell of the plurality of memory cells comprises a Complementary Field Effect Transistor (CFET) device.

In some embodiments, each memory cell of the plurality of memory cells comprises a Static Random Access Memory (SRAM) cell.

In some embodiments, the IC device further comprises: a word line driver has an output electrically coupled to both the first word line and the second word line.

In some embodiments, the first word line is electrically coupled to the second word line.

In some embodiments, the first word line has a section that extends over the at least one second memory cell without being electrically coupled to the at least one second memory cell, or the second word line has a section that extends under the at least one first memory cell without being electrically coupled to the at least one first memory cell.

In some embodiments, the first word line includes: a first section extending parallel to the second word line and over the at least one second memory cell without being electrically coupled to the at least one second memory cell, and a second section extending further from the first section beyond the second word line and being electrically coupled to the at least one first memory cell, or the second word line comprising: a first section extending parallel to the first word line and located below the at least one first memory cell without being electrically coupled to the at least one first memory cell, and a second section extending from the first section beyond the first word line and being electrically coupled to the at least one second memory cell.

In some embodiments, the first section of the first word line is located in a first metal layer and the second section of the first word line is located in a second metal layer closer to the memory array than the first metal layer; or the first section of the second word line is located in a first metal layer and the second section of the second word line is located in a second metal layer closer to the memory array than the first metal layer.

In some embodiments, the first and second sections of the first word line are both located in the same metal layer, or the first and second sections of the second word line are both located in the same metal layer.

In some embodiments, the at least one first memory cell and the at least one second memory cell are arranged in a same row of memory cells in the memory array, and the row further includes dummy memory cells located between the at least one first memory cell and the at least one second memory cell.

In some embodiments, the memory array includes a plurality of rows and a plurality of columns, the plurality of memory cells are arranged in the plurality of rows and the plurality of columns, the plurality of rows includes a first row and a second row, each of the first word line and the second word line overlaps with a memory cell in the first row and the second row, at least one first memory cell includes a plurality of first memory cells, at least one second memory cell includes a plurality of second memory cells, and each first memory cell of the plurality of first memory cells and a corresponding second memory cell of the plurality of second memory cells are arranged in a same column of the plurality of columns of the memory array.

In some embodiments, an Integrated Circuit (IC) device includes: a memory array comprising a plurality of memory cells arranged in a plurality of columns and a plurality of rows of the memory array, wherein the plurality of rows comprises a first row and a second row, a first word line located above the memory array; and a second word line located under the memory array, wherein each memory cell in the first row and a corresponding memory cell in the second row are arranged in a same column among a plurality of columns of the memory array, and each memory cell in the first row is electrically coupled to one of the first word line and the second word line, and a corresponding memory cell in the second row is electrically coupled to the other of the first word line and the second word line.

In some embodiments, each memory cell of the plurality of memory cells includes a Complementary Field Effect Transistor (CFET) device.

In some embodiments, all memory cells in the first row are electrically coupled to a first word line and all memory cells in the second row are electrically coupled to a second word line.

In some embodiments, the first row comprises: a first memory cell electrically coupled to the first word line, and a second memory cell electrically coupled to the second word line, and the second row comprises: a third memory cell corresponding to the first memory cell and electrically coupled to the second word line, and a fourth memory cell corresponding to the second memory cell and electrically coupled to the first word line.

In some embodiments, the first memory cells are arranged in a plurality of first memory cell groups, the second memory cells are arranged in a plurality of second memory cell groups, and the plurality of first memory cell groups and the plurality of second memory cell groups are alternately arranged along the first row.

In some embodiments, each of the plurality of first memory cell groups includes the same number of first memory cells and each of the plurality of second memory cell groups includes the same number of second memory cells.

In some embodiments, the number of first memory cells of at least one of the plurality of first memory cell groups includes a different number than at least one other of the plurality of first memory cell groups.

In a method of forming an integrated circuit device according to some embodiments, a plurality of memory cells are formed over a front side of a substrate. A plurality of memory cells are arranged in a memory array. A front side redistribution structure is deposited and patterned over the front side of the substrate. The front side redistribution structure includes a front side word line over the memory array and electrically coupled to at least one first memory cell among the plurality of memory cells. A backside redistribution structure is deposited and patterned on the backside of the substrate. The backside redistribution structure includes a backside word line under the memory array and electrically coupled to at least one second memory cell among the plurality of memory cells. The front side word line has a section that extends over the at least one second memory cell without being electrically coupled to the at least one second memory cell, or the back side word line has a section that extends under the at least one first memory cell without being electrically coupled to the at least one first memory cell.

In some embodiments, the method further comprises: the front side word line is electrically coupled to the back side word line.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments described herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. An integrated circuit device, comprising:

a memory array including a plurality of memory cells;

A first word line located above the memory array and electrically coupled to at least one first memory cell of the plurality of memory cells; and

A second word line located below the memory array and electrically coupled to at least one second memory cell among the plurality of memory cells,

Wherein each memory cell of the plurality of memory cells comprises a complementary field effect transistor device.

2. The integrated circuit device of claim 1, wherein

Each memory cell of the plurality of memory cells includes a static random access memory cell.

3. The integrated circuit device of claim 1, further comprising:

a word line driver has an output electrically coupled to both the first word line and the second word line.

4. The integrated circuit device of claim 1, wherein

The first word line is electrically coupled to the second word line.

5. The integrated circuit device of claim 4, wherein

The first word line has a section extending over the at least one second memory cell without being electrically coupled to the at least one second memory cell, or

The second word line has a section extending below the at least one first memory cell without being electrically coupled to the at least one first memory cell.

6. The integrated circuit device of claim 4, wherein

The first word line includes:

A first section extending parallel to the second word line and located above the at least one second memory cell without being electrically coupled to the at least one second memory cell, and

A second section extending from the first section further beyond the second word line and electrically coupled to the at least one first memory cell, or

The second word line includes:

a first section extending parallel to the first word line and located below the at least one first memory cell without being electrically coupled to the at least one first memory cell, an

A second section extends from the first section beyond the first word line and is electrically coupled to the at least one second memory cell.

7. The integrated circuit device of claim 6, wherein

The first section of the first word line is located in a first metal layer and the second section of the first word line is located in a second metal layer closer to the memory array than the first metal layer; or alternatively

The first section of the second word line is located in a first metal layer and the second section of the second word line is located in a second metal layer closer to the memory array than the first metal layer.

8. An integrated circuit device, comprising:

A memory array comprising a plurality of memory cells arranged in a plurality of columns and a plurality of rows of the memory array, wherein the plurality of rows comprises a first row and a second row,

A first word line over the memory array; and

A second word line, located below the memory array,

Wherein the method comprises the steps of

Each memory cell in the first row and a corresponding memory cell in the second row are arranged in the same column among the plurality of columns of the memory array, and

Each memory cell in the first row is electrically coupled to one of the first word line and the second word line, and the corresponding memory cell in the second row is electrically coupled to the other of the first word line and the second word line.

9. The integrated circuit device of claim 8, wherein

The first row includes:

A first memory cell electrically coupled to the first word line, an

A second memory cell electrically coupled to the second word line, an

The second row includes:

a third memory cell corresponding to the first memory cell and electrically coupled to the second word line, an

A fourth memory cell corresponds to the second memory cell and is electrically coupled to the first word line.

10. A method of forming an integrated circuit device, comprising:

forming a plurality of memory cells over a front side of a substrate, the plurality of memory cells arranged in a memory array;

Depositing and patterning a front side redistribution structure over a front side of the substrate, the front side redistribution structure comprising a front side word line over the memory array and electrically coupled to at least one first memory cell of the plurality of memory cells;

A backside redistribution structure is deposited and patterned on a backside of the substrate, the backside redistribution structure comprising a backside word line under the memory array and electrically coupled to at least one second memory cell of the plurality of memory cells,

Wherein the method comprises the steps of

The front side word line has a section extending over the at least one second memory cell without being electrically coupled to the at least one second memory cell, or

The backside word line has a section extending below the at least one first memory cell without being electrically coupled to the at least one first memory cell.