CN118041510A - High-speed pseudorandom sequence generator construction method based on FPGA and degenerated chaotic system - Google Patents
High-speed pseudorandom sequence generator construction method based on FPGA and degenerated chaotic system Download PDFInfo
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Abstract
A construction method of a high-speed pseudorandom sequence generator based on FPGA and a non-degenerate chaotic system relates to the field of cryptography and secret communication. The method solves the problem that most chaotic systems only pay attention to the performance of pseudo-random sequences at present, but neglect the hardware resource consumption and the throughput of the sequences. The method comprises the following steps: s1: the method comprises the steps of representing an initial value by adopting a fixed point number in an FPGA, wherein the length of the initial value is set to be 40 bits wide; s2: obtaining a coefficient matrix, and constructing a non-degenerated chaotic system according to the coefficient matrix; s3: generating a chaotic sequence of each dimension according to the non-degenerate chaotic system; s4: cutting off the chaotic sequences of each dimension and combining the sequence into a new sequence according to the sequence; s5: quantizing the sequences combined in the step S4 to generate a binary sequence; s6: and (5) repeating the steps S2 to S5 to construct non-degenerate chaotic pseudorandom sequence generators with different dimensions. The invention is applied to the field of network security.
Description
Technical Field
The invention relates to the field of cryptography and secret communication, in particular to a method for constructing a high-speed pseudorandom sequence generator based on an FPGA and a non-degenerate chaotic system.
Background
In recent years, along with the wide use of networks in various fields, the information security is threatened while convenience is provided for people, and the property and reputation of individuals are extremely easy to damage. The pseudo-random sequence can verify the consistency of data, ensure the randomness of encryption and play a key role in guaranteeing the information security. The initial pseudo-random sequence is often generated by a linear feedback shift register, but the structure is simple and easy to crack. The subsequent occurrence of chaos, its unique sensitivity and unpredictable nature, makes the generation of pseudo-random sequences novel. Most chaotic systems at present only pay attention to the performance of pseudo-random sequences, and neglect the consumption of hardware resources and the throughput of sequences.
Disclosure of Invention
Aiming at the problem that most chaotic systems only pay attention to the performance of pseudo random sequences and neglect hardware resource consumption and throughput of sequences, the invention provides a high-speed pseudo random sequence generator construction method based on an FPGA and a non-degenerate chaotic system, which comprises the following steps:
s1: the method comprises the steps of representing an initial value by adopting a fixed point number in an FPGA, wherein the length of the initial value is set to be 40 bits wide;
s2: obtaining a coefficient matrix, and constructing a non-degenerated chaotic system according to the coefficient matrix;
S3: generating a chaotic sequence of each dimension according to the non-degenerate chaotic system;
s4: cutting off the chaotic sequences of each dimension and combining the sequence into a new sequence according to the sequence;
s5: quantizing the sequences combined in the step S4 to generate a binary sequence;
S6: and (5) repeating the steps S2 to S5 to construct non-degenerate chaotic pseudorandom sequence generators with different dimensions.
Further, a preferred mode is also proposed, wherein in the step S1, the 40-bit width has no sign bit and no integer bit.
Further, a preferred mode is also proposed, and the step S2 includes:
Obtaining an n-dimensional constant coefficient matrix A:
Constructing a non-degenerated chaotic system according to an n-dimensional constant coefficient matrix A:
Wherein x (i) is a one-dimensional vector (x 1(i),x2(i),x3(i),...,xn(i))T∈Rn×1, F is a mapping of a state x (i) to another state x (i+1), x 1 (i+1) to x n (i+1) are state variables, x 1(1),x2(1),...xn (1) is an initial value of the non-degenerate chaotic system, N is a selected system dimension, a (n,n) is a system parameter, and N is a modulus coefficient.
Further, a preferred mode is also proposed, wherein the modulus N is 1.
Further, a preferred mode is also proposed, and the step S3 includes:
Storing the initial value (x 1(0),x2(0),...xn(0))T in 40-bit wide registers (x1_a, x2_a, kxn_a) respectively to participate in the calculation;
respectively left-shifting and adding (x1_a, x2_a, kxn_a) in the non-degenerate chaotic system;
The mode N in the non-degenerated chaotic system is selected to be 1, and the added value is modulo 1;
when the calculation result is smaller than 1, the modular operation is completed by the combination logic through truncation;
when the calculation result is greater than 1, the modulus result is subtracted from 1;
The generated state value is assigned to a new register (x1_n, x2_n, kxn_n) with a bit width of 40, and a new round of calculation is performed.
Further, a preferred mode is also proposed, and the step S4 includes:
cutting off N outputs in the generated state values respectively and combining the N outputs into a new sequence in sequence, wherein the new sequence is represented by Y:
Wherein i is the iteration round number, and n is the system dimension;
each truncation gives the upper 30 bits of the N outputs of (x1_n, x2_n, kxn_n) of 40 bits wide to Y (i), respectively, with the final bit width of Y (i) being len=30n-1.
Further, a preferred mode is also proposed, and the step S5 includes:
The quantization mode divides the sequence into three parts according to bit values, namely an upper Y (i) [ Len-1:len/2], a lower Y (i) [ Len/2-1:1] and a 0 th Y (i) [0];
Each bit is obtained by exclusive-or operation of the other two bits of the same sequence, and the bit value depends on the length of the sequence;
and (3) creating a register B, and assigning the quantized output of the Y (i) sequence to the register B, wherein the length of the register B is Len.
Based on the same inventive concept, the invention also provides a computer device, comprising a memory and a processor, wherein the memory stores a computer program, and when the processor runs the computer program stored in the memory, the processor executes a high-speed pseudo-random sequence generator construction method based on the FPGA and the nondegenerate chaotic system.
Based on the same inventive concept, the invention also provides a computer readable storage medium for storing a computer program, wherein the computer program executes a high-speed pseudo-random sequence generator construction method based on the FPGA and the non-degenerate chaotic system.
The invention has the advantages that:
the invention designs a high-speed pseudorandom sequence generator construction method based on an FPGA and a non-degenerate chaotic system, wherein the pseudorandom sequence generator adopts the non-degenerate chaotic system with simple structure but complex chaotic behavior, and the designed system has adjustable dimension, has at most positive Lis index and can generate pseudorandom sequences with stronger randomness. Aiming at the condition that the hardware implementation of the current pseudo-random sequence generator is complex, the invention has the advantages of less hardware resources, easy implementation of FPGA hardware and suitability for environments with limited resources. The quantitative design strengthens the complexity of the sequence, ensures the throughput of the sequence, and leads the pseudo-random sequence generator designed by the invention to take advantage in testing and data communication. Because of excellent initial value sensitivity of the chaotic system, different initial values can generate different pseudo-random sequences for encryption and other operations, and the chaotic system has better universality.
Hardware resource consumption is related to system engineering and implementation methods. The prior chaotic pseudorandom sequence generator design mostly has the problem of high resource occupancy rate, and compared with fixed point numbers, the FPGA needs to consume more calculation resources for the processing of floating point numbers, so the fixed point numbers are adopted to represent initial values, and the use of hardware resources can be reduced. Fixed point processing is generally more efficient than floating point processing. By acquiring the coefficient matrix, a non-degenerate chaotic system is constructed. The nature of such systems can increase randomness and security because degeneracy tends to make the system more vulnerable to attack. The non-degeneracy chaotic pseudorandom sequence generator with different dimensions is constructed, which means that the chaotic sequence with multiple dimensions can be generated at the same time, and the diversity and complexity of the sequence are enhanced. And cutting, combining and quantizing the generated chaotic sequence, and finally generating a binary sequence. Such processing makes the generated sequence more suitable for specific applications, such as binary sequences often required in encryption algorithms.
The invention is applied to the field of network security.
Drawings
FIG. 1 is a flow chart of a method for constructing a high-speed pseudorandom sequence generator based on an FPGA and a non-degenerate chaotic system according to an embodiment;
Fig. 2 is a flowchart of a chaotic pseudorandom sequence quantization according to a seventh embodiment;
FIG. 3 is a phase diagram of a three-dimensional non-degenerate chaotic system according to an eleventh embodiment;
FIG. 4 is a three-dimensional non-degenerate chaotic pseudorandom sequence quantization flow chart according to an eleventh embodiment;
FIG. 5 is a three-dimensional non-degenerate chaotic pseudorandom sequence generator Resource Utilization diagram according to an eleventh embodiment, wherein Resource is an internal hardware Resource of an FPGA, utilization is a number of resources used when implementing the pseudorandom sequence generator, available is a number of resources provided by an FPGA chip, utlization% is a design Resource occupancy, LUT is a lookup table, FF is a register, IO is a port, and BUFG is a global clock buffer;
FIG. 6 is a pseudo-random sequence waveform diagram for an initial value of (0.1,0.2,0.3) according to the eleventh embodiment;
FIG. 7 is a pseudo random sequence waveform diagram for the initial value (0.1,0.3,0.4) of the eleventh embodiment;
FIG. 8 is a sixteen-way plot of the pseudorandom sequence at an initial value of (0.1,0.3,0.4) described in embodiment eleven.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments.
Embodiment one, this embodiment will be described with reference to fig. 1. The embodiment of the method for constructing the high-speed pseudorandom sequence generator based on the FPGA and the nondegenerate chaotic system comprises the following steps:
s1: the method comprises the steps of representing an initial value by adopting a fixed point number in an FPGA, wherein the length of the initial value is set to be 40 bits wide;
s2: obtaining a coefficient matrix, and constructing a non-degenerated chaotic system according to the coefficient matrix;
S3: generating a chaotic sequence of each dimension according to the non-degenerate chaotic system;
s4: cutting off the chaotic sequences of each dimension and combining the sequence into a new sequence according to the sequence;
s5: quantizing the sequences combined in the step S4 to generate a binary sequence;
S6: and (5) repeating the steps S2 to S5 to construct non-degenerate chaotic pseudorandom sequence generators with different dimensions.
Hardware resource consumption is related to system equations and implementation methods. The prior chaotic pseudorandom sequence generator design mostly has the problem of high resource occupancy rate, and compared with fixed point numbers, the FPGA needs to consume more calculation resources for the processing of floating point numbers, so the fixed point numbers are adopted to represent initial values, and the use of hardware resources can be reduced. Fixed point processing is generally more efficient than floating point processing. By acquiring the coefficient matrix, a non-degenerate chaotic system is constructed. The nature of such systems can increase randomness and security because degeneracy tends to make the system more vulnerable to attack. The non-degeneracy chaotic pseudorandom sequence generator with different dimensions is constructed, which means that the chaotic sequence with multiple dimensions can be generated at the same time, and the diversity and complexity of the sequence are enhanced. And cutting, combining and quantizing the generated chaotic sequence, and finally generating a binary sequence. Such processing makes the generated sequence more suitable for specific applications, such as binary sequences often required in encryption algorithms.
The initial values are represented in this embodiment using a fixed point number 40 bits wide, which helps to handle more efficiently on an FPGA. Fixed-point representation is generally more suitable for hardware implementations than floating-point. And obtaining a coefficient matrix, and constructing the non-degenerated chaotic system according to the matrix. The dynamic behavior of the chaotic system is embodied by the operation of the matrix. The chaotic sequences of all dimensions are truncated and then combined into a new sequence in sequence, and the processing is helpful for enhancing the randomness of the chaotic sequence. The combined sequence is quantized and a final binary sequence is generated, which helps to convert the output of the chaotic sequence into a more easily processed form.
Generally, the method aims at improving randomness and safety, simultaneously considering the use efficiency of hardware resources and adapting to different application requirements.
In the second embodiment, the method for constructing a high-speed pseudorandom sequence generator based on an FPGA and a non-degenerate chaotic system according to the first embodiment is further limited, and in the step S1, 40 bits of width do not have sign bits and integer digits.
In the embodiment, the sign bit and the integer bit are removed, so that hardware resources can be saved, and resources can be more efficiently utilized particularly in a resource-limited environment such as an FPGA. The method has the advantages of eliminating sign bits and integer bits, simplifying design and implementation processes, reducing complexity, reducing possible errors and fault points and improving design reliability.
In this embodiment, the sign bit and the integer displacement in the 40-bit width are divided, so that the representation range of the chaotic sequence is more compact, and only the bit for representing the decimal part is reserved. The fixed point representation is still used, but only the fractional part is of interest, and the integer and sign parts are not considered. The method is mainly used for realizing a more efficient chaotic sequence generator under the condition of limited hardware resources, and further improving the performance and resource utilization rate of the FPGA system. The elimination of sign bits and integer bits simplifies the design process, reduces the complexity of implementation, and makes the design easier to understand, verify and maintain. By saving resources and simplifying the design, more resources can be used for calculation and optimization of the chaotic sequence, thereby improving the performance and output quality of the sequence generator.
In the third embodiment, the method for constructing a high-speed pseudorandom sequence generator based on an FPGA and a non-degenerate chaotic system according to the second embodiment is further defined, and the step S2 includes:
Obtaining an n-dimensional constant coefficient matrix A:
Constructing a non-degenerated chaotic system according to an n-dimensional constant coefficient matrix A:
Wherein x (i) is a one-dimensional vector (x 1(i),x2(i),x3(i),...,xn(i))T∈Rn×1, F is a mapping of a state x (i) to another state x (i+1), x 1 (i+1) to x n (i+1) are state variables, x 1(1),x2(1),...xn (1) is an initial value of the non-degenerate chaotic system, N is a selected system dimension, a (n,n) is a system parameter, and N is a modulus coefficient.
According to the embodiment, the n-dimensional constant coefficient matrix is introduced, so that chaotic systems with different characteristics can be flexibly constructed according to specific requirements, and the applicability and flexibility of the system are improved. Through careful design of the n-dimensional constant coefficient matrix, randomness of the chaotic system can be enhanced, and a more complex and high-quality pseudo-random sequence can be generated.
The n-dimensional constant coefficient matrix is a key parameter, and defines transition relations among states, so that the evolution track and the property of the chaotic system are influenced. And constructing a non-degeneracy chaotic system according to the n-dimensional constant coefficient matrix, and generating a complex chaotic sequence through evolution of a state variable. Specifically, let the iterative equation of the non-degenerate chaotic system of N dimension be:
x(i+1)＝F[x(i)]modN (1)
Where x (i) is a one-dimensional vector (x 1(i),x2(i),x3(i),...,xn(i))T∈Rn×1, F is a mapping of state x (i) to another state x (i+1), which can be expanded to F [ x (i) ]=a·x (i), N is a modulus coefficient, and a is an N-dimensional constant coefficient block matrix, expressed as follows:
Wherein, matrix A 1 is an n-2 dimension diagonal matrix, two matrices A 2 and A 3,A2 of the secondary diagonal are (n-2) x 2 dimension matrix, A 3 is 0 matrix, A 4 is two dimension matrix, the general form of the above matrix is:
thus, the specific structure of the n-dimensional constant coefficient matrix a is expressed as:
In addition, it is required that the diagonal element a (i,i) of A 1, 1.ltoreq.i.ltoreq.n, are each larger than 1 or smaller than-1, and the elements in A 4 satisfy the following two formulas.
a(n-1,n-1)＝a(n,n),a(n,n-1)＝a(n-1,n) (7)
Then, according to equation (1), the general form of the nondegenerate chaotic system can be expressed as:
wherein x 1 (i+1) is a state variable, when i is 0, x 1(1),x2(1),...xn (1) is an initial value of the non-degenerate chaotic system, N is a selected system dimension, and a modulus coefficient N is 1. The non-degenerated chaotic system means that the positive Liriot index of the system reaches the maximum number possible, the more positive Liriot indexes, the more complex the chaotic behavior of the system, (9) the non-quadratic term and the above term exist in the formula, the Jacobian matrix is the constant coefficient matrix A, the Liriot index of the N-dimensional chaotic system is known to depend on the coefficient variable matrix A according to the relation between the characteristic values and the Liriot indexes, when the absolute values of all the characteristic values of the A are larger than 1, the Liriot index is larger than 0, and the larger the absolute values of the characteristic values of the A are, and the larger the Liriot index is.
As can be seen from the rules of the block matrixes A 1 and A 4, the Lis index of the chaotic system designed by the embodiment is larger than 0, so that the randomness of the pseudo-random sequence generated by the system is stronger, and the confidentiality of data is enhanced in information transmission.
The fourth embodiment is further limited to the method for constructing a high-speed pseudorandom sequence generator based on an FPGA and a non-degenerate chaotic system according to the third embodiment, where the modulus N is 1.
In this embodiment, the modulus N is set to 1 to ensure that the constructed system is a chaotic system, the chaotic system is a transformation of stretching and folding, the stretching also means divergence, and the li index can show the motion characteristics of the chaotic system, and the positive and negative values and the magnitude of the value in a certain direction indicate the average divergence or convergence speed of adjacent tracks in the attractor along the direction for a long time. Therefore, having a positive li index is often used as a basis for chaos. However, the positive Lis index of the chaotic system means that the chaotic attractor is unstable locally, the positive Lis index of the chaotic system can be guaranteed to be the maximum on the basis of the previous design, the system track can be diffused to infinity due to the stretching of one taste, the system track is limited on the global range, the system is subjected to the modular processing,
In the embodiment, N is selected to be 1, so that the whole system track is repeatedly stretched and folded in a bounded area, and non-degenerate chaotic motion is generated.
In a fifth embodiment, the present embodiment is further defined by a method for constructing a high-speed pseudo-random sequence generator based on an FPGA and a non-degenerate chaotic system according to the second embodiment, where the step S3 includes:
Storing the initial value (x 1(0),x2(0),...xn(0))T in 40-bit wide registers (x1_a, x2_a, kxn_a) respectively to participate in the calculation;
respectively left-shifting and adding (x1_a, x2_a, kxn_a) in the non-degenerate chaotic system;
The mode N in the non-degenerated chaotic system is selected to be 1, and the added value is modulo 1;
when the calculation result is smaller than 1, the modular operation is completed by the combination logic through truncation;
when the calculation result is greater than 1, the modulus result is subtracted from 1;
The generated state value is assigned to a new register (x1_n, x2_n, kxn_n) with a bit width of 40, and a new round of calculation is performed.
This embodiment will be described with reference to the second embodiment. In practical applications, each round of iteration takes part in calculation by storing initial values (x 1(0),x2(0),...xn(0))T) in 40-bit wide registers (x1_a, x2_a, kxn_a) respectively, the product of system coefficients and one term in equation (9) is implemented by left shift, that is, a (1,1) in a (1,1)x1 (i) is replaced by power sum of 2, so a (1,1) is formed by powers of several terms 2, the register x1_a is left shifted several times and the number of left shifted bits each time is power of that term.
In a sixth embodiment, the present embodiment is further defined by a method for constructing a high-speed pseudo-random sequence generator based on an FPGA and a non-degenerate chaotic system according to the fourth embodiment, and the step S4 includes:
cutting off N outputs in the generated state values respectively and combining the N outputs into a new sequence in sequence, wherein the new sequence is represented by Y:
Wherein i is the iteration round number, and n is the system dimension;
each truncation gives the upper 30 bits of the N outputs of (x1_n, x2_n, kxn_n) of 40 bits wide to Y (i), respectively, with the final bit width of Y (i) being len=30n-1.
According to the embodiment, N outputs are truncated and combined into a new sequence Y in sequence, so that the randomness and complexity of the sequence can be increased, and the quality of the pseudo-random sequence is improved. By cutting off the output in the combination process, the correlation between the sequences can be reduced, the independence of the sequences is improved, and the method is more suitable for the fields of encryption, communication and the like.
Specifically, the high 30 bits of each output are used as a part of the new sequence Y, partial information in the chaotic sequence is reserved through the truncation operation, and meanwhile, the partial information is discarded, so that the sequence randomness is increased. The N cut outputs are sequentially combined into a new sequence Y, so that the sequence and the continuity are ensured, and the method is more easily applied to scenes needing continuous randomness. The embodiment improves the quality and randomness of the chaotic sequence, so that the chaotic sequence is more suitable for various applications with higher randomness requirements, such as the fields of cryptography, communication and the like. By increasing the randomness and complexity of the sequence, the safety of the sequence is improved, so that the sequence is more difficult to crack or predict, and the safety of communication and data transmission is enhanced.
The seventh embodiment is further defined that the method for constructing a high-speed pseudo-random sequence generator based on an FPGA and a non-degenerate chaotic system according to the first embodiment, wherein the step S5 includes:
The quantization mode divides the sequence into three parts according to bit values, namely an upper Y (i) [ Len-1:len/2], a lower Y (i) [ Len/2-1:1] and a 0 th Y (i) [0];
Each bit is obtained by exclusive-or operation of the other two bits of the same sequence, and the bit value depends on the length of the sequence;
and (3) creating a register B, and assigning the quantized output of the Y (i) sequence to the register B, wherein the length of the register B is Len.
According to the embodiment, the sequence is divided into the high bit, the low bit and the 0 th bit according to the bit values, each bit is obtained by performing exclusive OR operation on the other two bits, so that the complexity and the randomness of the chaotic sequence can be increased, and the sequence quality is improved. By combining and outputting the quantized three parts to B, the output efficiency can be improved, making the sequence generation more efficient.
In the embodiment, the sequence is divided into a high position, a low position and a 0 th position according to the bit value, and the diversity and the randomness of the sequence are increased through different combination forms of the three parts. The value of each bit is obtained by exclusive-or operation of the other two bits, and the specific bit value depends on the length of the sequence, so that each bit can be ensured to be influenced by the first two bits, and the complexity of the sequence is increased.
The specific quantization flow is as follows: the combined sequence Y (i) is divided into 3 parts and respectively carries out different quantization essence to weaken the correlation between sequence bits, Y (i) has the length of Len, thus the sequence Y (i) is divided into three parts, each bit of high-order B (i) [ Len-1:Len/2] is obtained by carrying out exclusive OR operation on low-order 1 bits and low-order Len/2 of corresponding Y (i), each bit of low-order B (i) [ Len/2-1:1] is obtained by carrying out exclusive OR operation on low-order 1 bits and high-order Len/2 of corresponding Y (i), and 0-order B (i) [0] is obtained by carrying out exclusive OR operation on fixed Y (i) [ Len-1] and Y (i) [ Len/2 ].
An eighth embodiment is a system for constructing a non-degenerate chaotic pseudorandom sequence generator based on an FPGA according to the eighth embodiment, the system comprising:
The initialization unit is used for representing an initial value by adopting the fixed point number in the FPGA, and the length of the initial value is set to be 40 bits wide;
the non-degenerate chaotic system construction unit is used for acquiring a coefficient matrix and constructing a non-degenerate chaotic system according to the coefficient matrix;
the chaotic sequence generation unit is used for generating a chaotic sequence of each dimension according to the non-degenerate chaotic system;
the cutting unit is used for cutting the chaotic sequence of each dimension and combining the sequence into a new sequence according to the sequence;
The quantization unit is used for carrying out quantization according to the combined sequences to generate a binary sequence;
The acquisition unit of the pseudo-random sequence generator is used for repeating the non-degenerate chaotic system construction unit to the quantization unit to construct the non-degenerate chaotic pseudo-random sequence generator with different dimensions.
A computer device according to a ninth embodiment includes a memory and a processor, where the memory stores a computer program, and when the processor runs the computer program stored in the memory, the processor executes a method for constructing a high-speed pseudo-random sequence generator based on an FPGA and a non-degenerate chaotic system as in any one of the first to seventh embodiments.
The tenth embodiment is a computer readable storage medium according to the first embodiment, which is configured to store a computer program, where the computer program executes the method for constructing a high-speed pseudorandom sequence generator based on an FPGA and a non-degenerate chaotic system according to any one of the first to seventh embodiments.
Embodiment eleven, this embodiment will be described with reference to fig. 3 to 8. The present embodiment provides a specific example of the method for constructing a high-speed pseudorandom sequence generator based on an FPGA and a non-degenerate chaotic system according to the first embodiment, and is also used for explaining the second to seventh embodiments, specifically:
The non-degeneracy chaotic system with the dimension of 3 is selected to construct a pseudo-random sequence generator, so that only one 2-dimensional A 4, 1-dimensional A 1 and A 2 are needed, and proper parameters, a (1,1) >1, are selected according to rules, The matrix a may be:
The Lien index of the system can be increased by selecting larger system parameters, so that the chaotic system with more complex characteristics is obtained. The system equation constructed from a is as follows:
Calculating eigenvalues of a for jacobian matrix a of (2) shows that 3 li indexes of the chaotic system are le1=5.2575, le2=3.6636 and le3= 3.3673, respectively. The initial value is set to (x 1(0),x2(0),x3(0))T＝(0.1,0.2,0.3)T, which can be expressed by fixed point numbers:
The phase diagram of the chaotic system is shown in fig. 3, and the tracks are uniformly distributed in the whole phase space, so that the chaotic system is proved to have better unpredictability and initial value sensitivity.
Substituting the initial values into the system, and storing the initial values in registers x1_a, x2_a and x3_a respectively to participate in calculation, wherein 192 in formula (2) can be expressed as 192=2 6+27, 40 can be expressed as 40=2 3+25, 5 is expressed as 5=2 0+22, and 34 is expressed as 34=2 1+25.
Therefore, x1_n= (x1_a < < 6) + (x1_a < < 7) + (x3_a < < 3) + (x3_a < < 5), x2_n is the same as x3_n, and < < indicates left shift, and the left shift is adopted to replace multiplication, so that ip core call to the FPGA is reduced, and the utilization rate of hardware resources is improved.
The chaos sequence generated after iteration is (x1_n, x2_n, x3_n), because the initial value is positive, the result generated after the left phase shift addition calculation in the previous step is still positive, the module is taken for judgment, when the output is smaller than 1, the module operation is completed by the combination logic through cutting, and when the output is larger than 1, the module result is subtracted from 1. And reassigned to (x1_n, x2_n, x3_n).
Further, the three sequence output results are first assigned to (x1_a, x2_a, x3_a) as the initial value of the next round for calculation. The three sequence outputs are truncated and stored in register x4 with a bit width of 90, letting x4[29:0] =x1_a [39:10], x4[59:30] =x2_a [39:10], x4[89:60] =x3_a [39:10]. Then, the sequence x4 is input into the quantization process in fig. 4 for quantization, and is divided into three parts, namely, a high bit [89:45], a low bit [44:1] and 0 bit, a register x5 is newly built, and the three calculated parts are stored into the register x5 according to the bits, so that the sequence output by the x5 is a pseudo-random sequence.
The Artix-7 series xc7a100tfgg484-2 chip of Xilinx company is selected to realize the proposed pseudo-random sequence generator, and FIG. 5 is a resource diagram occupied by the design of the pseudo-random sequence generator after comprehensive compiling and executing, and the figure shows that the design consumes less hardware resources and can be better suitable for small-sized equipment.
Fig. 6 is a simulation diagram of a pseudo-random sequence generated by changing an initial value (x 1(0),x2(0),x3(0))T＝(0.1,0.3,0.4)T, fig. 7 is a simulation diagram of a pseudo-random sequence generated by changing, it can be seen that even if the initial value of x 1 (0) is unchanged, the iteration is still completely different under the influence of x 2 (0) and x 3 (0), which shows that the system has better initial value sensitivity and can generate a high-quality pseudo-random sequence generator, and as can be seen from fig. 8, the pseudo-random sequence generator based on the 3-dimensional non-degenerate chaotic system can generate a 90-bit pseudo-random sequence in one period of 10ns, the calculated throughput is as high as 9Gbit/s, and the high-speed pseudo-random sequence generator is the preferred choice in the fields of communication, encryption and the like.
Table 1 shows (x 1(0),x2(0),x3(0))T＝(0.1,0.3,0.4)T NIST SP800-22 test results, wherein 5 test strips represent the average value, 100 groups of 10 6 samples were selected, the significance level α=0.01, and the data was considered random only when the P value was greater than 0.01.
TABLE 1NIST SP 800-22 test results
| Test item | p value | Pass rate of |
| Frequency detection | 0.236810 | 1.00 |
| Intra-block frequency detection | 0.935716 | 1.00 |
| Cumulative sum | 0.534272 | 0.99 |
| Run length verification | 0.455937 | 0.99 |
| Intra block longest run verification | 0.955835 | 1.00 |
While the preferred embodiments of the present disclosure have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the disclosure.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present disclosure without departing from the spirit or scope of the disclosure. Thus, the present disclosure is intended to include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
It will be appreciated by those skilled in the art that embodiments of the present disclosure may be provided as a method, system, or computer program product. Accordingly, the present disclosure may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present disclosure may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein. The present disclosure is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the disclosure. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks. These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks. These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
Finally, it should be noted that: the above embodiments are only for illustrating the technical aspects of the present disclosure and not for limiting the scope thereof, and although the present disclosure has been described in detail with reference to the above embodiments, it should be understood by those of ordinary skill in the art that: various alterations, modifications, and equivalents may be suggested to the specific embodiments of the invention, which would occur to persons skilled in the art upon reading the disclosure, are intended to be within the scope of the appended claims.
Claims (9)
1. The method for constructing the high-speed pseudo-random sequence generator based on the FPGA and the nondegenerate chaotic system is characterized by comprising the following steps of:
s1: the method comprises the steps of representing an initial value by adopting a fixed point number in an FPGA, wherein the length of the initial value is set to be 40 bits wide;
s2: obtaining a coefficient matrix, and constructing a non-degenerated chaotic system according to the coefficient matrix;
S3: generating a chaotic sequence of each dimension according to the non-degenerate chaotic system;
s4: cutting off the chaotic sequences of each dimension and combining the sequence into a new sequence according to the sequence;
s5: quantizing the sequences combined in the step S4 to generate a binary sequence;
S6: and (5) repeating the steps S2 to S5 to construct non-degenerate chaotic pseudorandom sequence generators with different dimensions.
2. The method for constructing the high-speed pseudorandom sequence generator based on the FPGA and the nondegenerate chaotic system according to claim 1, wherein in the step S1, no sign bit and no integer bit exist in 40 bits of width.
3. The method for constructing the high-speed pseudo-random sequence generator based on the FPGA and the nondegenerate chaotic system according to claim 2, wherein the step S2 comprises the following steps:
Obtaining an n-dimensional constant coefficient matrix A:
Constructing a non-degenerated chaotic system according to an n-dimensional constant coefficient matrix A:
Wherein x (i) is a one-dimensional vector (x 1(i),x2(i),x3(i),...,xn(i))T∈Rn×1, F is a mapping of a state x (i) to another state x (i+1), x 1 (i+1) to x n (i+1) are state variables, x 1(1),x2(1),...xn (1) is an initial value of the non-degenerate chaotic system, N is a selected system dimension, a (n,n) is a system parameter, and N is a modulus coefficient.
4. The method for constructing a high-speed pseudorandom sequence generator based on an FPGA and a nondegenerate chaotic system according to claim 3, wherein the modulus N is 1.
5. The method for constructing the high-speed pseudo-random sequence generator based on the FPGA and the nondegenerate chaotic system according to claim 2, wherein the step S3 comprises the following steps:
Storing the initial value (x 1(0),x2(0),...xn(0))T in 40-bit wide registers (x1_a, x2_a, kxn_a) respectively to participate in the calculation;
respectively left-shifting and adding (x1_a, x2_a, kxn_a) in the non-degenerate chaotic system;
The mode N in the non-degenerated chaotic system is selected to be 1, and the added value is modulo 1;
when the calculation result is smaller than 1, the modular operation is completed by the combination logic through truncation;
when the calculation result is greater than 1, the modulus result is subtracted from 1;
The generated state value is assigned to a new register (x1_n, x2_n, kxn_n) with a bit width of 40, and a new round of calculation is performed.
6. The method for constructing a high-speed pseudorandom sequence generator based on FPGA and nondegenerate chaotic system according to claim 4, wherein the step S4 comprises:
cutting off N outputs in the generated state values respectively and combining the N outputs into a new sequence in sequence, wherein the new sequence is represented by Y:
Wherein i is the iteration round number, and n is the system dimension;
each truncation gives the upper 30 bits of the N outputs of (x1_n, x2_n, kxn_n) of 40 bits wide to Y (i), respectively, with the final bit width of Y (i) being len=30n-1.
7. The method for constructing the high-speed pseudorandom sequence generator based on the FPGA and the nondegenerate chaotic system according to claim 1, wherein the step S5 comprises the following steps:
The quantization mode divides the sequence into three parts according to bit values, namely an upper Y (i) [ Len-1:len/2], a lower Y (i) [ Len/2-1:1] and a 0 th Y (i) [0];
Each bit is obtained by exclusive-or operation of the other two bits of the same sequence, and the bit value depends on the length of the sequence;
and (3) creating a register B, and assigning the quantized output of the Y (i) sequence to the register B, wherein the length of the register B is Len.
8. A computer device comprising a memory and a processor, the memory having a computer program stored therein, the processor performing a method of constructing a high-speed pseudorandom sequence generator based on an FPGA and a non-degenerate chaotic system as in any of claims 1-7 when the processor runs the computer program stored in the memory.
9. A computer-readable storage medium storing a computer program for executing a method of constructing a high-speed pseudo-random sequence generator based on an FPGA and a non-degenerate chaotic system as set forth in any one of claims 1 to 7.
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