CN118041504A - Communication method of four-wire system synchronous serial port based on RS422 level standard - Google Patents

Abstract

The invention discloses a communication method of a four-wire system synchronous serial port based on an RS422 level standard, which comprises the following steps: both communication parties simultaneously comprise independent sending channels and receiving channels; splitting each single byte of effective data to be transmitted, performing error correction coding by adopting Hamming codes, respectively assembling, and attaching a low-level start bit and a high-level stop bit to form transmission information; the receiving channels at each end of the two communication parties detect and receive the level information of each bit by utilizing the rising edge or the falling edge of the clock transmitted by the opposite party in a shift register mode, and the bit information is received and shift operation is finished at the same time; and finally restoring 1 byte of effective data. The invention has the advantages of simple principle, simple and convenient realization, realization of active transmission at two ends, reduction of error rate and the like.

Description

Communication method of four-wire system synchronous serial port based on RS422 level standard

Technical Field

The invention mainly relates to the technical field of communication in navigation, in particular to a four-wire synchronous serial port communication method based on an RS422 level standard.

Background

The conventional MIMU/GNSS integrated navigation system can output position, speed and attitude information, and the components of the integrated navigation system generally comprise a MIMU micro inertial measurement unit, a GNSS satellite navigation receiver, an integrated navigation algorithm board card and the like. The integrated navigation and control system can be further formed by adding a control interface and a control algorithm to the integrated navigation system. The navigation and control integrated system faces larger data throughput in the aspect of real-time data recording and storage, and a transmission baud rate of 10-20Mbps is needed to ensure that all original data and intermediate state data are recorded without frame loss as far as possible. That is, the navigation and control integrated system faces a large data throughput pressure in terms of real-time data recording and storage, and a transmission baud rate of 10-20Mbps is required to ensure that all original data and intermediate state data are recorded without frame loss as much as possible, so that the problem of post analysis is facilitated.

For data recording, the data is unidirectional, i.e. sent from the master (navigation and control integrated system) to the slave (recorder). However, for the image tracking module, both the master terminal transmits the gesture data information to the slave terminal and the slave terminal (the image tracking module) transmits the image information to the master terminal (the navigation and control integrated system), so that a bidirectional active transmission mechanism is required.

For the transmission baud rate of 20Mbps, the technical problem to be solved is that the common asynchronous serial port IP core can be simply transformed into the synchronous serial port IP core based on the FPGA platform to realize the bidirectional active transmission mechanism.

For such high baud rates, the asynchronous serial port mode with a highest baud rate of 921600bps is generally incapable; the reason for this is: the receiving end generally needs to internally provide a clock with 16 times of baud rate to detect level information, and when the baud rate reaches 20Mbps, the clock with 16 times of baud rate is 320MHz, which is difficult to realize 320MHz design on some common FPGA platforms (especially domestic FPGA platforms).

The synchronous serial port is a high-speed communication solution based on a serial port mode, and the synchronous of a receiving clock and a transmitting clock is ensured by transmitting clock information to a receiving end at the same time. The synchronous serial ports generally have modes of SPI, I2C, SSI, BISS-C and the like, and one common characteristic is that only a master end transmits a unidirectional clock to an external slave end, so that one problem is that: the slave device cannot actively transmit data to the master device.

The reason why the slave device cannot actively transmit data to the master device from a technical point of view is: only the unidirectional clock, rather than the bidirectional clock, sent by the master to the external slave. In order to realize that the master end actively transmits data to the slave end and the slave end actively transmits data to the master end, a bidirectional clock is needed, namely, the clock transmitted by the master end is transmitted to the slave end and the clock transmitted by the slave end is transmitted to the master end.

At present, conventional standard interfaces such as SPI, I2C, SSI, BISS-C and the like are characterized by only having unidirectional clocks and not bidirectional clocks. The network communication has a bidirectional clock internally, such as interfaces MII, GMII between PHY and MAC have a bidirectional clock, but the signals output by the PHY through the transformer have no bidirectional clock. For example, chinese patent application No.: 200610114711.7 technical scheme: the 'anti-interference device when the RS485 character-oriented synchronous serial communication bus is idle' and the technical scheme of China patent application number 201210330464. X 'the communication method of the synchronous serial communication interface and the synchronous serial communication interface' only have 1-path clock signals.

In combination with the above analysis, it can be seen that some of the technical shortcomings existing in the prior art are:

1. for the universal synchronous serial ports SPI and I2C without the bidirectional clock, if the function of actively transmitting a large amount of data by the slave end is to be realized only by the master end, CPU resources of the master end are occupied.

2. Compared with the common serial port technology, the network mode or LVDS mode transmission is realized on a domestic FPGA platform, and a certain hardware or software complexity is increased.

3. The transmission efficiency without error correction coding is high, but for data with a baud rate of 20Mbps to be reliably transmitted over a distance of about 3 meters at present, the error rate has to be considered, because the highest transmission baud rate of a typical RS422 driving chip is only 10Mbps. The only few domestic RS422 drive chips with 20Mbps baud rate are required to transmit as close as possible. In general, if it is desired to transmit a low error rate transmission over a distance of about 3 meters based on a homemade RS422 driver chip with a 20Mbps baud rate, error correction coding becomes necessary. If there is no error correction coding, there may be a certain bit error rate.

Disclosure of Invention

The technical problem to be solved by the invention is as follows: aiming at the technical problems existing in the prior art, the invention provides the four-wire synchronous serial port communication method based on the RS422 level standard, which has the advantages of simple principle, simple and convenient realization, and capability of realizing active transmission at two ends and reducing error rate.

In order to solve the technical problems, the invention adopts the following technical scheme:

a four-wire synchronous serial port communication method based on RS422 level standard, comprising:

Both communication parties simultaneously comprise a sending channel and a receiving channel; the transmitting channel and the receiving channel are two independent channels, and the transmitting channel at each end of the two communication parties has synchronous clock output, namely a transmitting clock;

Data processing and sending: splitting each single byte of effective data to be transmitted, performing error correction coding by adopting Hamming codes, respectively assembling by the error correction coding, adding a low-level start bit and a high-level stop bit, and finally forming transmission information;

Data receiving and extracting: the receiving channels at each end of the two communication parties detect and receive the level information of each bit by utilizing the rising edge or the falling edge of the clock transmitted by the opposite party in a shift register mode, and the bit information is received and shift operation is finished at the same time; the receiving channels at each end of the two communication parties extract 1bit initial bit according to the clock signal of the sending channel of the sending end of the opposite party, continuously receive the transmission information through the shift register, recover the effective data through the Hamming code error correction decoding circuit after extracting the information, and finally recover the effective data of 1 byte.

As a further improvement of the process of the invention: when the data is processed and transmitted, each single byte of effective data to be transmitted is split into high 4bit effective data and low 4bit effective data, then error correction coding is carried out by respectively adopting Hamming codes, and the two 7 bits, including high 7bit and low 7bit, are respectively assembled by the error correction coding, and the total is 14 bits.

As a further improvement of the process of the invention: and adding a 1bit low level start bit before 14 bits, adding a 1bit high level stop bit after 14 bits, and finally forming 16bit transmission information.

As a further improvement of the process of the invention: and when the data is received and extracted, the high 7bit information and the low 7bit information are extracted respectively, the high 4bit effective data and the low 4bit effective data are recovered through a Hamming code error correction decoding circuit, and finally the 1 byte effective data are recovered.

As a further improvement of the process of the invention: the data lines of the transmitting channel and the receiving channel of each end of the two communication parties and the RS422 level conversion chip are 4-wire system: a transmitting clock, transmitting data, receiving clock, receiving data; the external interface after the RS422 level conversion is 4 pairs and 8 lines of differential: transmit clock+, transmit clock-, transmit data+, transmit data-, receive clock+, receive clock-, receive data-.

As a further improvement of the process of the invention: the sending clock of the sending channel and the sending data of each end of the two communication parties need to be synchronously generated by a clock with twice frequency; wherein: taking a clock with twice frequency as a reference, and obtaining a 'transmitting clock' signal of a 4-wire system through frequency division by 2; and taking a clock with twice frequency as a reference, and carrying out shift output on a 16-bit shift register to be transmitted every two clock cycles to obtain the 4-wire system data transmission signal.

As a further improvement of the process of the invention: the information bit in the idle state is high level, and the synchronous clock (transmission clock) is always present in the idle state.

As a further improvement of the process of the invention: the single byte valid data is error correction coded and the start bit and stop bit are packed into 16bit transmission information, wherein the sequence from LSB to MSB is as follows: 1bit start bit, low 7bit information, high 7bit information, and 1bit high level stop bit; the low 7bit information is in the sequence from LSB to MSB: lp0, lp1, d0, lp2, d1, d2, d3; the high 7bit information is in the sequence from LSB to MSB: hp0, hp1, d4, hp2, d5, d6, d7.

As a further improvement of the process of the invention: the data receiving and extracting process comprises the following steps:

If the level turning moment of the 4-wire transmission data signal generated by the transmission channel corresponds to the rising edge of the 4-wire transmission clock signal, the receiving channel detects and receives bit data level information by utilizing the clock falling edge transmitted by the opposite side in a shift register mode, and receives the bit information and completes shift operation at the same time;

If the level turning moment of the 4-wire transmission data signal generated by the transmission channel corresponds to the falling edge of the 4-wire transmission clock signal, the receiving channel detects and receives bit data level information by utilizing the clock rising edge transmitted by the opposite side in a shift register mode, receives bit information and completes shift operation.

As a further improvement of the process of the invention: in the process of receiving and extracting data, a receiving channel at each end of two communication parties extracts a 1bit starting bit according to a clock signal of a sending channel of the other party, and the method comprises the following steps:

the receiving channel monitors 1bit low level after continuous 16bit high level, bit of the low level is the initial bit, and the first byte synchronization among frames is completed;

The receiving channel normally receives 16 clock period information bits and then is a low-level initial bit of 16-bit transmission information corresponding to effective data of the next byte, wherein the low-level initial bit is the initial bit of the next 16-bit transmission information, and different bytes in the frame are synchronized;

Different byte synchronization distinguishing conditions in the frame are the turning of the starting bit from the high level to the low level; the high level is 1bit, and the two 16bit transmission information corresponding to the two bytes of effective data can be continuously transmitted; or the high level is a plurality of bits, and the specification that the information bit in the idle state is high level when the information can be discontinuously transmitted corresponding to the two times of 16-bit transmission information corresponding to the two-byte effective data is provided.

Compared with the prior art, the invention has the advantages that:

1. The communication method of the four-wire system synchronous serial port based on the RS422 level standard has the advantages of simple principle, simple and convenient realization, realization of active transmission at two ends, reduction of error rate and convenient data recovery; the method of the invention is based on 4-wire system communication +RS422 level standard, adopts (7, 4) Hamming code to realize 1bit error correction coding, and adds 1bit start bit and 1bit stop bit to form 8bit effective data corresponding to 16bit transmission information, and adopts 2 times frequency, namely 40MHz clock signal to simultaneously generate synchronous clock and data bit information.

2. According to the communication method of the four-wire system synchronous serial port based on the RS422 level standard, the sending channel and the receiving channel are two independent channels and are provided with synchronous clocks, so that no division of a master end and a slave end exists, and both communication parties A or B can actively send data through the respective sending channels. The hardware of the receiving end automatically completes data receiving and then stores the data into the FIFO, so that CPU resources of the receiving end are not occupied. In contrast, if the SPI single clock master receives the data of the slave, the CPU resource of the master is always required to be occupied.

3. The communication method of the four-wire system synchronous serial port based on the RS422 level standard adopts 1bit (7, 4) Hamming code error correction coding and decoding, and can further reduce the transmission error rate. The single byte effective data is split into 2 high 4bit and low 4bit with equal length, and error correction coding bits are added respectively for transmission, so that the receiving end is convenient to recover and assemble. In contrast, if (15, 11) hamming codes are used, although the transmission efficiency is improved, the trouble of data recovery and assembly is increased, because 11 bits and 8 bits of a single byte do not form a multiple relationship, whereas 4 bits and 8 bits of a single byte in the (7, 4) hamming code scheme can form a multiple relationship. And a 1bit low level start bit scheme is adopted, so that the detection synchronization of a receiving end to the start time of a data frame is facilitated. And a 1bit high level stop bit scheme is adopted, so that detection synchronization between continuous effective bytes in a data frame is facilitated. The single byte valid data bit 8 bits corresponds to 16 bits of information bits. The synchronization between the continuous effective bytes refers to the 1bit high level stop bit of the 16bit information bit corresponding to the last byte and the 1bit low level start bit of the 16bit information bit corresponding to the byte, namely the transmission process of the continuous two-byte effective data must have the level turning process from the stop bit high level to the start bit low level, or the transmission process of the discontinuous two-byte effective data must have the level turning process from the idle bit high level to the start bit low level.

4. According to the communication method of the four-wire system synchronous serial port based on the RS422 level standard, the information bit in the idle state is high level, and the clock in the idle state always exists, so that the detection synchronization of the initial bit of the receiving end can be facilitated. The reason is that the always present clock facilitates level information detection of the idle bits. In contrast, if no clock signal is present at idle time, the state of the clock signal needs to be detected, which increases the complexity of detection to a certain extent.

5. According to the communication method of the four-wire system synchronous serial port based on the RS422 level standard, the frequency of a 2-time transmission clock, namely, the frequency of a 40MHz frequency clock signal is adopted in a transmitting end to obtain a 20MHz frequency clock signal transmission clock; on the other hand, the 16bit transmission information is shifted and sent out every two clock cycles under the triggering of the 40MHz frequency clock signal. By such a design, the output information bit level change is aligned with the clock edge (rising edge or falling edge), and at the receiving end, the received information bit and the received clock arrive completely at the same time, i.e. are synchronous, as long as the external transmission line is equal in length and the cable delay is equal. In contrast, if the processing scheme of 2 times of frequency is not adopted, but the transmitting end directly outputs the information bit by adopting the transmitting clock, a relatively lagging time relationship exists in principle, namely, the change of the information bit is advanced by the change of the instant. The information bit is detected at the receiving end by means of a further roll-over delay (falling edge or rising edge) of the clock, the detection instant is not exactly the middle instant of the information bit, but an instant after the delay is added at the middle instant. This additional delay time is the delay required for the flip-flop inside the transmitting-side shift register to flip-flop under the triggering of the transmitting clock.

6. The communication method of the four-wire system synchronous serial port based on the RS422 level standard can realize the purpose of low bit error rate synchronous serial transmission at a length distance of about 3 meters aiming at a domestic RS422 driving chip with 20Mbps baud rate transmission capability and a domestic FPGA platform by slightly improving the existing asynchronous serial port IP core.

Drawings

Fig. 1 is a schematic diagram of connection relationship between internal channels and level interface portions of two communication parties and two communication parties in a specific application example of the method of the present invention.

Fig. 2 is a schematic diagram of the internal structure of the transmitting channel and the receiving channel of the two communication parties in the embodiment of the present invention.

Fig. 3 is a schematic diagram of a transmission clock sent by a transmitting end and a transmission data timing chart in a specific application example, where a transmission data change time corresponds to a rising edge of the transmission clock.

Fig. 4 is a schematic diagram of a transmission clock sent by a transmitting end and a transmission data timing chart in a specific application example, where a transmission data change time corresponds to a falling edge of the transmission clock.

Detailed Description

The invention will be described in further detail with reference to the drawings and the specific examples.

The invention aims to solve the technical problem of realizing synchronous serial port technology which can actively transmit data from a master end to a slave end and from the slave end to the master end. Further, high-speed transmission with low error rate is realized based on the mature RS422 standard and by using an RS422 level driving chip of 20 Mbps.

As shown in fig. 1 to 4, the communication method of the four-wire synchronous serial port based on the RS422 level standard of the present invention includes:

Both communication parties simultaneously comprise a sending channel and a receiving channel; the transmitting channel and the receiving channel are two independent channels, and the transmitting channel at each end of the two communication parties has synchronous clock output, namely a transmitting clock;

Splitting each single byte effective data to be transmitted into high 4bit effective data and low 4bit effective data, then respectively adopting Hamming codes to perform error correction coding, and respectively assembling into two 7 bits (namely high 7bit and low 7 bit) through error correction coding, wherein the total is 14 bits;

Adding a 1bit low level start bit before 14 bits, adding a 1bit high level stop bit after 14 bits, and finally forming 16bit transmission information;

The receiving channels at each end of the two communication parties detect and receive each bit level information by using the rising edge (or the falling edge) of the clock transmitted by the opposite party in a shift register mode, and the bit information is received and shift operation is finished at the same time;

The receiving channels at each end of the two communication parties extract 1bit initial bit according to the clock signal of the sending channel of the sending end of the opposite party, then the 16bit transmission information is continuously received through the shift register, the high 7bit information and the low 7bit information are respectively extracted, the high 4bit effective data and the low 4bit effective data are recovered through the Hamming code error correction decoding circuit, and finally the 1 byte effective data are restored.

In a specific application example, the data lines of the transmitting channel and the receiving channel of each end of the two communication parties and the RS422 level conversion chip are 4-wire system: a transmitting clock, transmitting data, receiving clock, receiving data; the external interface after the RS422 level conversion is 4 pairs and 8 lines of differential: transmit clock+, transmit clock-, transmit data+, transmit data-, receive clock+, receive clock-, receive data-.

In a specific application example, the information bit in the idle state is at a high level, and a synchronous clock (transmission clock) exists in the idle state.

In a specific application example, the invention adopts (7, 4) Hamming codes to carry out error correction coding, wherein effective data has 4 bits, check bits 3 bits and information bits are 7 bits in total; the order of MSB on the left LSB on the right is as follows: (d 3, d2, d1, p2, d0, p1, p 0), wherein d0 to d3 are valid data bits (data), and p0 to p2 bits are parity bits (parity); the p0 to p2 check bits are generated in a (7, 4) hamming manner.

In a specific application example, the single byte effective data is error correction coded and the start bit and the stop bit are packed into 16bit transmission information, wherein the sequence from LSB to MSB is as follows: 1bit start bit (low level), low 7bit information, high 7bit information, 1bit high level stop bit; the low 7bit information is in the sequence from LSB to MSB: (lp 0, lp1, d0, lp2, d1, d2, d 3); the high 7bit information is in the sequence from LSB to MSB: (hp 0, hp1, d4, hp2, d5, d6, d 7).

In a specific application example, because the data lines of the transmitting channel and the receiving channel of each end of the two parties and the RS422 level conversion chip are 4-wire system, the transmitting clock of the transmitting channel of each end of the two parties and the transmitting data need to be generated synchronously with a clock with twice the frequency. Wherein: taking a clock with double frequency as a reference, and obtaining a 'transmitting clock' signal of the 4-wire system through frequency division by 2; and taking a clock with twice frequency as a reference, and carrying out shift output on a 16-bit shift register to be transmitted every two clock cycles to obtain the 4-wire system data transmission signal.

In a specific application example, a receiving channel at each end of two communication parties detects and receives bit level information by using a clock rising edge (or a falling edge) transmitted by the other party in a shift register mode, and receives the bit information and simultaneously completes shift operation, wherein:

(1) If the level turning moment of the 4-wire transmission data signal generated by the transmission channel corresponds to the rising edge of the 4-wire transmission clock signal, the receiving channel detects and receives bit data level information by utilizing the clock falling edge transmitted by the opposite side in a shift register mode, receives the bit information and completes shift operation.

(2) If the level turning moment of the 4-wire transmission data signal generated by the transmission channel corresponds to the falling edge of the 4-wire transmission clock signal, the receiving channel detects and receives bit data level information by utilizing the clock rising edge transmitted by the opposite side in a shift register mode, receives bit information and completes shift operation.

In a specific application example, the single byte valid data is error correction coded and the start bit and stop bit are packed into 16bit transmission information, wherein:

(1) Two times of 16-bit transmission information corresponding to two adjacent bytes of effective data can be continuously transmitted, and as a result, only 1-bit high-level stop bits exist between the two times of 16-bit transmission information;

(2) Two times of 16-bit transmission information corresponding to two adjacent bytes of effective data can be discontinuously transmitted, and as a result, a plurality of 1-bit high levels exist between the two times of 16-bit transmission information.

In a specific application example, a receiving channel at each end of two communication parties extracts a 1bit start bit according to a clock signal of a sending channel of the other party, wherein:

(1) The receiving channel monitors 1bit low level after continuous 16bit high level, bit of the low level is the initial bit, and the first byte synchronization between frames is completed.

(2) The receiving channel normally receives 16 clock period information bits and then is a low level start bit of 16bit transmission information corresponding to effective data of the next byte, and the low level start bit is a start bit of the next 16bit transmission information, so that different bytes in the frame are synchronized.

(3) The synchronous distinguishing condition of different bytes in the frame is the inversion of the start bit from high level to low level. The high level may be 1bit, which corresponds to the "continuous transmission of the information of 16 bits twice corresponding to the two-byte valid data", the high level may be a plurality of bits, which corresponds to the provision that the information bit of the idle state is the high level "when the information of 16 bits twice corresponding to the two-byte valid data can be discontinuously transmitted".

From the above, the key innovation of the above scheme of the present invention in specific application is that:

One frame of effective data consists of a plurality of bytes of effective data, wherein the single byte of effective data is changed into 14bit information after error correction coding, and is changed into 16bit transmission information after adding 1bit start bit and 1bit stop bit.

The sending and receiving are two independent channels, which respectively comprise 1-channel clock and 1-channel data channel, and respectively comprise a sending clock, sending data, a receiving clock and receiving data, and occupy 4I/O ports in total, namely 4 lines.

The level specification adopts the RS422 standard, and logic signals of 'transmitting clock', 'transmitting data', 'receiving clock', 'receiving data' are respectively changed into after passing through the RS422 driving chip: transmit clock+, transmit clock-, transmit data+, transmit data-, receive clock+, receive clock-, receive data+, receive data-.

Both transmission and reception are based on the same timing specification as follows: the information bit is at a high level when idle, the sending clock always exists, and 1bit of information is transmitted in each clock cycle. The data start bit is 1bit low level, then 7bit information bits are transmitted twice consecutively, wherein the low 7bit information is before, the high 7bit information is after, and the 7bit information bits are in the sequence of LSM before MSB, and the data stop bit is 1bit high level. The transmission of valid data in a single byte requires 16 bits of information, corresponding to 16 clock cycles, see fig. 3 and 4.

The level change of the information bit corresponding to the data of the transmitting end is aligned with the edge of the transmitting clock. Specifically, the method comprises two aspects: on one hand, clock signals with the frequency of 2 times of the transmission clock are adopted to divide the frequency to obtain clock signals with the transmission clock which are output outwards, and the clock signals correspond to the frequency-division-2 trigger circuit in figure 2; on the other hand, the 16bit information is shifted and sent out every two clock cycles under the triggering of the clock signal with the frequency of 2 times of the "sending clock", which corresponds to the "16bit shift register" circuit in fig. 2.

Receiving bit synchronization: if the level inversion time of the 4-wire transmission data signal generated by the transmission channel corresponds to the rising edge of the 4-wire transmission clock signal and corresponds to fig. 3, the reception channel detects and receives bit data level information by using the clock falling edge transmitted by the opposite side in a shift register mode, receives the bit information and completes shift operation, and ensures that the falling edge detection time is positioned at the middle time of the duration of the information bit and corresponds to the synchronous circuit of fig. 2.

If the level inversion time of the 4-wire transmission data signal generated by the transmission channel corresponds to the falling edge of the 4-wire transmission clock signal and corresponds to fig. 4, the reception channel detects and receives bit data level information by using the clock rising edge transmitted by the opposite side in a shift register mode, receives the bit information and completes shift operation, and ensures that the rising edge detection time is positioned at the middle time of the duration of the information bit and corresponds to the synchronous circuit of fig. 2.

Receiving byte synchronization: and monitoring a 1bit low level after the continuous 16bit high level, wherein the bit of the low level is the start bit, and the first byte synchronization between frames is completed. And normally receiving a low-level start bit of 16-bit transmission information corresponding to effective data of the next byte after 16 clock cycles, wherein the low-level start bit is the first start bit of the next 16-bit transmission information, and different byte synchronization in a frame is completed. The synchronous distinguishing condition of different bytes in the frame is the inversion of the start bit from high level to low level. The high level may be 1bit, which corresponds to the "two times 16bit transmission information corresponding to the two bytes of valid data may be continuously transmitted", the high level may be a plurality of bits, which corresponds to the "when two times 16bit transmission information corresponding to the two bytes of valid data may be discontinuously transmitted," the information bit in the idle state is in the high level "and corresponds to the" synchronization circuit "of fig. 2.

Receiving error correction: the receiving end detects and receives bit level information by using the rising edge (or the falling edge) of the clock transmitted by the opposite side. After receiving the 7bit information transmitted once, the original 4bit effective data is recovered and restored by the (7, 4) Hamming code error correction decoding circuit. After receiving 4bit effective data twice successively, the data is assembled into 8bit single byte effective data, corresponding to the (7, 4) Hamming code error correction decoding circuit of figure 2.

After the technical scheme of the invention is adopted, the detailed working process of the invention is as follows in combination with a specific application:

1. a sending end working flow;

(1) And splitting high 4bit effective data and low 4bit effective data aiming at each byte.

(2) And (7, 4) Hamming code error correction coding with 1bit error correction capability is carried out on the split low 4bit effective data (d 3, d2, d1, d 0) to obtain 3bit error correction codes (lp 2, lp1, lp 0).

(3) Assembling the low 4bit effective data (d 3, d2, d1, d 0) with the 3bit error correcting codes (lp 2, lp1, lp 0) obtained in the step (2), so as to obtain low 7bit information codes under the (7, 4) hamming code rule, wherein the low 7bit information codes are arranged as follows according to the sequence from MSB to LSB: (d 3, d2, d1, lp2, d0, lp1, lp 0).

(4) And carrying out 1bit (7, 4) Hamming code error correction coding on the split high 4bit (d 7, d6, d5, d 4) to obtain 3bit error correction codes (hp 2, hp1, hp 0).

(5) Assembling the high 4bit effective data (d 7, d6, d5, d 4) with the 3bit error correcting codes (hp 2, hp1, hp 0) obtained in the step (4), and obtaining high 7bit information codes under the (7, 4) hamming code rule, wherein the high 7bit information codes are arranged according to the sequence from MSB to LSB: (d 7, d6, d5, hp2, d4, hp1, hp 0).

(6) Encoding the low 7bit information obtained in the step (3) by using the 1bit low level information start bit '0', encoding the high 7bit information obtained in the step (5), and assembling the 1bit high level stop bit '1' into a 16bit shift register to obtain a 16bit information bit sequence arranged from Low (LSB) to high (MSB): (0, lp0, lp1, d0, lp2, d1, d2, d3, hp0, hp1, d4, hp2, d5, d6, d7, 1).

The 16bit information bit sequence is as follows: (0, lp0, lp1, d0, lp2, d1, d2, d3, hp0, hp1, d4, hp2, d5, d6, d7, 1) are sequentially sent out to the ports through the shift registers in order from Low (LSB) to high (MSB). Specifically, "0" is sent out first, followed by lp0, d7 followed by the last bit "1".

1. A receiving end workflow;

(1) The receiving end detects and receives bit data level information by utilizing the rising edge (or the falling edge) of the clock transmitted by the opposite side in a shift register mode, receives the bit information and simultaneously completes shift operation.

(2) And extracting a start bit corresponding to the 16-bit transmission information. Comprising two aspects: on the one hand, the starting bit corresponding to the valid data of the first byte between frames is: monitoring a 1bit low level after continuous 16bit high level, wherein a bit of the low level is a start bit, and finishing first byte synchronization between frames; on the other hand, the starting bit corresponding to each byte of valid data in the frame is: and normally receiving a low-level start bit of 16-bit transmission information corresponding to effective data of the next byte after 16 clock cycles, wherein the low-level start bit is the start bit of the next 16-bit transmission information, and different bytes in the frame are synchronized.

The synchronous distinguishing condition of different bytes in the frame is the inversion of the start bit from high level to low level. The high level may be 1bit, which corresponds to the "continuous transmission of the information of 16 bits twice corresponding to the two-byte valid data", the high level may be a plurality of bits, which corresponds to the provision that the information bit of the idle state is the high level "when the information of 16 bits twice corresponding to the two-byte valid data can be discontinuously transmitted".

(3) And continuously receiving 16-bit transmission information in a shift register mode.

(4) And after the 16bit transmission information is received, the low 7bit coding information and the high 7bit coding information are extracted at the same time.

(5) The (7, 4) Hamming code error correction circuit is used for carrying out 1bit error correction on the low 7bit coding information and the high 7bit coding information at the same time, and respectively restoring high 4bit and low 4bit effective data.

(6) And assembling the high 4bit and low 4bit effective data obtained through the 1bit error correction and reduction processing into the 8bit single byte effective data.

(7) And storing the assembled single-byte effective data into the FIFO.

(8) And generating an interrupt indication signal by a contracted interrupt triggering mode for triggering the interrupt by the CPU.

Specifically, in one example, the transmitting end may select to divide the frequency of the "transmitting clock" by 2 times, that is, the 40MHz frequency clock signal to obtain the 20MHz frequency clock signal "transmitting clock"; on the other hand, the 16bit transmission information is shifted and sent out every two clock cycles under the triggering of the 40MHz frequency clock signal.

The RS422 level conversion interface chip can select GB490H-GEC, and can realize data transmission with the length of 3 meters and 20 Mbps. Five twisted pairs are adopted for differential signal transmission between a transmitting end and a receiving end of two communication parties.

And the transmission clock and the transmission data timing diagram sent by the transmission end correspond to the rising edge of the transmission clock at the time of the change of the transmission data.

Specifically, in another example, the transmitting end divides the frequency of the "transmitting clock" by 2 times, that is, the 40MHz frequency clock signal to obtain a 20MHz frequency clock signal "transmitting clock"; on the other hand, the 16bit transmission information is shifted and sent out every two clock cycles under the triggering of the 40MHz frequency clock signal.

The RS422 level conversion interface chip adopts SIT65HVD75, and can realize data transmission with the length of 3 meters and 20 Mbps. Five twisted pairs are adopted for differential signal transmission between a transmitting end and a receiving end of two communication parties.

And the transmission clock and the transmission data timing diagram sent by the transmission end correspond to the falling edge of the transmission clock at the time of the change of the transmission data.

The above is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above examples, and all technical solutions belonging to the concept of the present invention belong to the protection scope of the present invention. It should be noted that modifications and adaptations to the invention without departing from the principles thereof are intended to be within the scope of the invention as set forth in the following claims.

Claims (10)

1. A four-wire system synchronous serial port communication method based on an RS422 level standard, comprising:

Both communication parties simultaneously comprise a sending channel and a receiving channel; the transmitting channel and the receiving channel are two independent channels, and the transmitting channel at each end of the two communication parties has synchronous clock output, namely a transmitting clock;

Data processing and sending: splitting each single byte of effective data to be transmitted, performing error correction coding by adopting Hamming codes, respectively assembling by the error correction coding, adding a low-level start bit and a high-level stop bit, and finally forming transmission information;

Data receiving and extracting: the receiving channels at each end of the two communication parties detect and receive the level information of each bit by utilizing the rising edge or the falling edge of the clock transmitted by the opposite party in a shift register mode, and the bit information is received and shift operation is finished at the same time; the receiving channels at each end of the two communication parties extract 1bit initial bit according to the clock signal of the sending channel of the sending end of the opposite party, continuously receive the transmission information through the shift register, recover the effective data through the Hamming code error correction decoding circuit after extracting the information, and finally recover the effective data of 1 byte.

2. The communication method of four-wire system synchronous serial port based on RS422 level standard according to claim 1, wherein when the data is processed and transmitted, each single byte of effective data to be transmitted is split into high 4bit effective data and low 4bit effective data, then error correction coding is performed by respectively adopting hamming codes, and two 7 bits including high 7bit and low 7bit and 14bit are assembled by respectively performing error correction coding.

3. The method for four-wire synchronous serial port communication based on the RS422 level standard according to claim 2, wherein a 1bit low level start bit is added before 14 bits, a 1bit high level stop bit is added after 14 bits, and finally 16bit transmission information is formed.

4. The method for four-wire system synchronous serial port based on RS422 level standard according to claim 3, wherein when receiving and extracting the data, the high 7bit information and the low 7bit information are extracted respectively, the high 4bit valid data and the low 4bit valid data are recovered by a hamming code error correction decoding circuit, and finally 1 byte valid data are recovered.

5. The method for four-wire system synchronous serial port communication based on RS422 level standard according to any one of claims 1 to 4, wherein the data lines of the transmitting channel and the receiving channel of each end of the two parties of communication and the RS422 level conversion chip are 4-wire system: a transmitting clock, transmitting data, receiving clock, receiving data; the external interface after the RS422 level conversion is 4 pairs and 8 lines of differential: transmit clock+, transmit clock-, transmit data+, transmit data-, receive clock+, receive clock-, receive data-.

6. The method for four-wire synchronous serial port communication based on RS422 level standard according to claim 5, wherein the transmission clock of the transmission channel of each end of the two parties of communication and the transmission data need to be generated synchronously with a clock of twice the frequency; wherein: taking a clock with twice frequency as a reference, and obtaining a 'transmitting clock' signal of a 4-wire system through frequency division by 2; and taking a clock with twice frequency as a reference, and carrying out shift output on a 16-bit shift register to be transmitted every two clock cycles to obtain the 4-wire system data transmission signal.

7. The method for four-wire synchronous serial port communication based on the RS422 level standard according to any one of claims 2 to 4, wherein the information bit in the idle state is high, and the synchronous clock is always present in the idle state.

8. The method for four-wire synchronous serial port communication based on RS422 level standard according to any one of claims 2 to 4, wherein the single byte valid data is error correction coded and the start bit and stop bit are packed into 16bit transmission information, wherein the sequence from LSB to MSB is: 1bit start bit, low 7bit information, high 7bit information, and 1bit high level stop bit; the low 7bit information is in the sequence from LSB to MSB: lp0, lp1, d0, lp2, d1, d2, d3; the high 7bit information is in the sequence from LSB to MSB: hp0, hp1, d4, hp2, d5, d6, d7.

9. The method for four-wire synchronous serial port communication based on RS422 level standard according to any one of claims 1 to 4, wherein the data receiving and extracting process includes:

If the level turning moment of the 4-wire transmission data signal generated by the transmission channel corresponds to the rising edge of the 4-wire transmission clock signal, the receiving channel detects and receives bit data level information by utilizing the clock falling edge transmitted by the opposite side in a shift register mode, and receives the bit information and completes shift operation at the same time;

If the level turning moment of the 4-wire transmission data signal generated by the transmission channel corresponds to the falling edge of the 4-wire transmission clock signal, the receiving channel detects and receives bit data level information by utilizing the clock rising edge transmitted by the opposite side in a shift register mode, receives bit information and completes shift operation.

10. The method for four-wire system synchronous serial port based on RS422 level standard according to any one of claims 1 to 4, wherein in the data receiving and extracting process, the receiving channel at each end of the two parties of communication extracts a 1bit start bit according to the clock signal of the sending channel of the other party, comprising:

the receiving channel monitors 1bit low level after continuous 16bit high level, bit of the low level is the initial bit, and the first byte synchronization among frames is completed;

The receiving channel normally receives 16 clock period information bits and then is a low-level initial bit of 16-bit transmission information corresponding to effective data of the next byte, wherein the low-level initial bit is the initial bit of the next 16-bit transmission information, and different bytes in the frame are synchronized;

Different byte synchronization distinguishing conditions in the frame are the turning of the starting bit from the high level to the low level; the high level is 1bit, and the two 16bit transmission information corresponding to the two bytes of effective data can be continuously transmitted; or the high level is a plurality of bits, and the specification that the information bit in the idle state is high level when the information can be discontinuously transmitted corresponding to the two times of 16-bit transmission information corresponding to the two-byte effective data is provided.