CN118039686A - High electron mobility transistor and manufacturing method thereof - Google Patents

High electron mobility transistor and manufacturing method thereof Download PDF

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Publication number
CN118039686A
CN118039686A CN202410094540.4A CN202410094540A CN118039686A CN 118039686 A CN118039686 A CN 118039686A CN 202410094540 A CN202410094540 A CN 202410094540A CN 118039686 A CN118039686 A CN 118039686A
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China
Prior art keywords
type semiconductor
layer
semiconductor layer
hemt
electron mobility
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苏柏文
张明华
吕水烟
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United Microelectronics Corp
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United Microelectronics Corp
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Priority to CN202410094540.4A priority Critical patent/CN118039686A/en
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    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
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    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7789—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface the two-dimensional charge carrier gas being at least partially not parallel to a main surface of the semiconductor body

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Abstract

The invention discloses a high electron mobility transistor and a manufacturing method thereof, wherein the manufacturing method mainly comprises the steps of firstly forming a patterned mask on a substrate, then removing the substrate by using the patterned mask to form a plurality of raised parts and a damaged layer on the raised parts, then removing the damaged layer, forming a barrier layer on the raised parts, forming a P-type semiconductor layer on the barrier layer, and then forming a source electrode and a drain electrode on two sides of the P-type semiconductor layer.

Description

High electron mobility transistor and manufacturing method thereof
The application relates to a Chinese patent application (application number: 202010081655.1, application date: 2020, 02, 06, title: high electron mobility transistor and manufacturing method thereof).
Technical Field
The invention relates to a high electron mobility transistor and a manufacturing method thereof.
Background
Gallium nitride-based materials based high electron mobility transistors have numerous advantages in terms of electrical, mechanical, and chemical properties, such as wide band gap, high breakdown voltage, high electron mobility, large elastic modulus (elastic modulus), high voltage and piezoresistive coefficient (high piezoelectric and piezoresistive coefficients), and chemical inertness. The above advantages make gallium nitride based materials useful in the fabrication of devices for applications such as high brightness light emitting diodes, power switching devices, regulators, battery protectors, panel display drivers, communication devices, etc.
Disclosure of Invention
An embodiment of the invention discloses a method for manufacturing a high electron mobility transistor, which mainly comprises the steps of firstly forming a patterned mask on a substrate, then removing the substrate by using the patterned mask to form a plurality of raised parts and a damaged layer on the raised parts, then removing the damaged layer, forming a barrier layer on the raised parts, forming a P-type semiconductor layer on the barrier layer, and then forming a source electrode and a drain electrode on two sides of the P-type semiconductor layer.
In another embodiment of the present invention, a high electron mobility transistor is disclosed, which mainly comprises a plurality of bumps extending on a substrate along a first direction, a P-type semiconductor layer extending on the substrate along a second direction, a barrier layer disposed between the substrate and the P-type semiconductor layer, and a source electrode and a drain electrode disposed on both sides of the P-type semiconductor layer.
Drawings
FIGS. 1-7 are schematic diagrams illustrating a method of fabricating a HEMT according to an embodiment of the invention;
Fig. 8 is a schematic perspective view of a hemt according to an embodiment of the invention.
Description of the main reference signs
12 Substrate
14 Buffer layer
16 Patterning mask
18 Opening(s)
20 Bump portion
22 Groove
24 Damaged layer
26 Barrier layer
28P-type semiconductor layer
30 Patterning mask
32 Protective layer
34 Gate electrode
36 Source electrode
38 Drain electrode
40 Grid structure
Detailed Description
Referring to fig. 1, fig. 1 is a schematic diagram illustrating a method for fabricating a high electron mobility transistor according to an embodiment of the present invention, wherein the top half of fig. 1 is a top view of the high electron mobility transistor according to the present invention, the top half of fig. 1 is a schematic diagram illustrating a cross section of the middle half along a tangent line AA ', and the bottom half of fig. 1 is a schematic diagram illustrating a cross section of the middle half along a tangent line BB'. As shown in fig. 1, a substrate 12, such as a substrate made of silicon, silicon carbide or aluminum oxide (or sapphire), is provided, wherein the substrate 12 may be a single-layer substrate, a multi-layer substrate, a gradient substrate, or a combination thereof. The substrate 12 may further comprise a silicon-on-insulator (SOI) substrate according to other embodiments of the present invention.
A buffer layer 14 is then formed on the substrate 12. In one embodiment, buffer layer 14 comprises a III-V semiconductor, such as gallium nitride, which may have a thickness between 0.5 microns and 10 microns. In one embodiment, buffer layer 14 may be formed on substrate 12 using a Molecular Beam Epitaxy (MBE) process, a metal organic vapor deposition (metal organic chemical vapor deposition, MOCVD) process, a chemical vapor deposition (chemical vapor deposition, CVD) process, a hydride vapor phase epitaxy (hydride vapor phase epitaxy, HVPE) process, or a combination thereof. A patterned mask 16 is then formed over the buffer layer 14, wherein the patterned mask 16 has a plurality of openings 18 exposing portions of the surface of the buffer layer 14. In this embodiment, the patterned mask 16 may be composed of a patterned photoresist or a dielectric material such as silicon nitride.
With continued reference to fig. 2, fig. 2 is a schematic diagram illustrating a method for fabricating a high electron mobility transistor according to fig. 1, wherein the top half of fig. 2 is a top view of the high electron mobility transistor according to the present invention, the top half of fig. 2 is a schematic diagram illustrating a cross section of the top half along a tangent line CC ', and the bottom half of fig. 2 is a schematic diagram illustrating a cross section of the top half along a tangent line DD'. As shown in fig. 2, the patterned mask 16 is used to remove a portion of the buffer layer 14 to form a plurality of ridges 20 or ridge-like structures and a plurality of grooves 22 between the ridges 20, wherein the ridges 20 and the grooves 22 extend along a first direction on the substrate 12. According to an embodiment of the present invention, the step of removing a portion of the buffer layer 14 by using the patterned mask 16 to form the bump 20 and the recess 22 may be performed by using a dry etching process or a wet etching process according to the material of the patterned mask 16. For example, if patterned mask 16 is comprised of a patterned photoresist, a dry etching process, such as an oxygen plasma process, may be used to remove portions of buffer layer 14 to form ridges 20 and grooves 22. In addition, if patterned mask 16 is comprised of a dielectric material such as silicon nitride, a wet etch process may be used to remove portions of buffer layer 14 to form ridge 20 and recess 22 using an etch recipe such as phosphoric acid, and such variations are within the scope of the present invention.
It should be noted that whether the dry etching process or the wet etching process is used to form the ridge-like bump 20 on the substrate 12 or the buffer layer 14, the etching formulation used is preferably used to damage a portion of the surface of the buffer layer 14 during the etching process and to form a damaged layer (DAMAGED LAYER) 24 on the surface of the bump 20 or more specifically on the surface of the bump 20 in the recess 22 at the same time as the bump 20 is formed. In accordance with an embodiment of the present invention, the material of the damaged layer 24 is preferably dependent on the material used for the buffer layer 14 itself, for example, if the buffer layer 14 of this embodiment is composed of gallium nitride, the damaged layer 24 preferably comprises gallium nitride or more specifically gallium nitride with carbon bonds. It should be noted that, since the high electron mobility transistor device is fabricated in this embodiment, the dimensions of the ridges 20 and the grooves 22 formed at this stage include dimensions of width and depth which are much larger than those of the fin structure in the conventional fin structure field effect transistor device. For example, in the present embodiment, the width of the grooves 22 and/or the ridges 20 is preferably greater than 180 nm or more preferably between 180 nm and 600 nm, and the depth of the grooves 22 and/or the ridges 20 is also preferably greater than 180 nm or more preferably between 180 nm and 600 nm.
With continued reference to fig. 3, fig. 3 is a schematic diagram illustrating a method for fabricating a high electron mobility transistor according to fig. 2, wherein the top half of fig. 3 is a top view of the high electron mobility transistor according to the present invention, the top half of fig. 3 is a schematic diagram illustrating a cross section of the top half along a tangent line EE ', and the bottom half of fig. 3 is a schematic diagram illustrating a cross section of the top half along a tangent line FF'. As shown in fig. 3, the patterned mask 16 is removed, and a cleaning process is performed to remove all of the damaged layer 24 and expose the buffer layer 14 in the recess 22. In this embodiment, the cleaning solution used in the cleaning process may include, but is not limited to, hydrochloric acid (HCl) and/or ammonium sulfide ((NH 4)2 S).
With continued reference to fig. 4, fig. 4 is a schematic diagram illustrating a method for fabricating a hemt according to fig. 3, wherein the top half of fig. 4 is a top view of the hemt according to the present invention, the top half of fig. 4 is a schematic cross-sectional view of the middle half along a tangent line GG ', and the bottom half of fig. 4 is a schematic cross-sectional view of the middle half along a tangent line HH'. As shown in fig. 4, a barrier layer 26 is then formed over the bump 20. In this embodiment, the barrier layer preferably comprises a III-V semiconductor such as aluminum gallium nitride (Al xGa1-x N), where 0< x <1 ". As in the case of the buffer layer 14, the barrier layer 26 may be formed on the surface of the bump 20 and in the recess 22 but not filling the recess 22 by a Molecular Beam Epitaxy (MBE), a metal organic vapor deposition (metal organic chemical vapor deposition, MOCVD), a chemical vapor deposition (chemical vapor deposition, CVD), a hydride vapor phase epitaxy (hydride vapor phase epitaxy, HVPE), or a combination thereof.
With continued reference to fig. 5, fig. 5 is a schematic diagram illustrating a method for fabricating a high electron mobility transistor according to fig. 4, wherein the top half of fig. 5 is a top view of the high electron mobility transistor according to the present invention, the top half of fig. 5 is a schematic diagram illustrating a cross section of the top half along a tangent II ', and the bottom half of fig. 5 is a schematic diagram illustrating a cross section of the top half along a tangent JJ'. As shown in fig. 5, a P-type semiconductor layer 28 is formed to cover the surface of the barrier layer 26 and fill the recess 22, and then a patterned mask 30, such as a patterned photoresist, is formed on the P-type semiconductor layer 28, wherein the patterned mask 30 preferably extends along a direction perpendicular to the bump 20 and both sides of the patterned mask 30 preferably expose the P-type semiconductor layer 28.
In one embodiment, the P-type semiconductor layer 28 preferably comprises P-type gallium nitride, and the P-type semiconductor layer 28 may be formed on the surface of the barrier layer 26 by a Molecular Beam Epitaxy (MBE) process, a metal organic vapor deposition (metal organic chemical vapor deposition, MOCVD) process, a chemical vapor deposition (chemical vapor deposition, CVD) process, a hydride vapor phase epitaxy (hydride vapor phase epitaxy, HVPE) process, or a combination thereof.
With continued reference to fig. 6, fig. 6 is a schematic diagram illustrating a method for fabricating a high electron mobility transistor according to the present invention, wherein the top half of fig. 6 is a schematic diagram illustrating a cross section of the top half of fig. 6 along a tangent KK ', and the bottom half of fig. 6 is a schematic diagram illustrating a cross section of the bottom half along a tangent LL'. As shown in fig. 6, a pattern transfer process is then performed, for example, using the patterned mask 30 as a mask to remove the P-type semiconductor layer 28 on both sides, thereby transferring the pattern of the patterned mask 30 onto the P-type semiconductor layer 28 to form a patterned P-type semiconductor layer 28 and removing the patterned mask 30, wherein the patterned P-type semiconductor layer 28 and the patterned mask 30 preferably extend on the bump 20 along a direction generally perpendicular to the bump 20.
With continued reference to fig. 7-8, fig. 7 is a schematic diagram illustrating a method for fabricating a high electron mobility transistor according to fig. 6, in which the first half of fig. 7 is a top view of the high electron mobility transistor according to the present invention, the second half of fig. 7 is a schematic diagram illustrating a cross section of the second half along a tangent line MM ', the third half of fig. 7 is a schematic diagram illustrating a cross section of the second half along a tangent line NN', and fig. 8 is a schematic diagram illustrating a three-dimensional structure of the high electron mobility transistor according to fig. 7. As shown in fig. 7, a passivation layer 32 is formed on the barrier layer 26 and the P-type semiconductor layer 28, and then a gate electrode 34 is formed on the P-type semiconductor layer 28 and the source electrode 36 and the drain electrode 38 are formed on both sides of the gate electrode 34, wherein the P-type semiconductor layer 28 and the gate electrode 34 together form a gate structure 40.
In this embodiment, a photolithography and etching process is performed to remove a portion of the passivation layer 32 on the P-type semiconductor layer 28 to form a recess (not shown), form a gate electrode 34 in the recess, remove a portion of the passivation layer 32 and a portion of the barrier layer 26 on both sides of the P-type semiconductor layer 28 to form two recesses, and form a source electrode 36 and a drain electrode 38 on both sides of the gate electrode 34 respectively. It should be noted that the source electrode 36 and the drain electrode 38 formed in this embodiment are preferably slot-shaped electrodes, so that the source electrode 36 and the drain electrode 38 preferably extend along the same direction as the P-type semiconductor layer 28 or the gate electrode 34 from the top view in the center of fig. 7 and the three-dimensional structure of fig. 8, and the bottom thereof is preferably electrically connected to and contacts the plurality of underlying bumps 20, and the protection layer 32 surrounds the P-type semiconductor layer 28 and the source electrode 36 and the drain electrode 38.
It should be noted that, although the bottoms of the source electrode 36 and the drain electrode 38 are in direct contact with the bump 20 or the buffer layer 14 in the present embodiment, but not limited thereto, the portion of the barrier layer 26 directly under the source electrode 36 and the drain electrode 38 is not removed when the patterned passivation layer 32 is used to form the source electrode 36 and the drain electrode 38, so that the bottoms of the source electrode 36 and the drain electrode 38 are in direct contact with the barrier layer 26, and the variation is also included in the scope of the present invention. In addition, in order to more clearly show the elements of the gate structure 40, the source electrode 36, and the drain electrode 38, the protection layer 32 surrounding the gate structure 40, the source electrode 36, and the drain electrode 38 and filling the recess 22 between the bump 20 is preferably omitted in the three-dimensional structure disclosed in fig. 8.
In the present embodiment, the gate electrode 34, the source electrode 36 and the drain electrode 38 are preferably formed of metal, wherein the gate electrode 34 is preferably formed of a Schottky metal and the source electrode 36 and the drain electrode 38 are preferably formed of an ohmic contact metal. In accordance with an embodiment of the present invention, the gate electrode 34, the source electrode 36, and the drain electrode 38 may each comprise gold, silver, platinum, titanium, aluminum, tungsten, palladium, or a combination thereof. In some embodiments, the conductive material may be formed in the recesses using an electroplating process, a sputtering process, a resistive heating vapor deposition process, an electron beam vapor deposition process, a physical vapor deposition (physical vapor deposition, PVD) process, a chemical vapor deposition process (chemical vapor deposition, CVD) process, or a combination thereof, and then the electrode material is patterned using one or more etches to form the gate electrode 34, the source electrode 36, and the drain electrode 38. Thus, the fabrication of a high electron mobility transistor according to an embodiment of the present invention is completed.
Generally, the current on-state current (Ion) is achieved by increasing the overall width of the gate electrode, which in turn means that the overall area of the device is increased, resulting in increased cost. In order to overcome the defect, the invention mainly utilizes a patterning mask to match with lithography and etching to form a plurality of ridge-shaped raised parts on a buffer layer and even a substrate formed by gallium nitride, and then sequentially forms a P-type semiconductor layer which spans the raised parts and is used as a grid structure, a source electrode and a drain electrode on two sides of the P-type semiconductor layer. The hemt according to the present invention can obtain a larger effective gate width (EFFECTIVE GATE WIDTH) as shown in the middle upper view angle of fig. 7, which extends in a direction perpendicular to the bump 20, thereby providing a higher on-current. In addition, in view of the fact that the buffer layer or the substrate formed by removing part of the gallium nitride is easy to form a damaged layer on the side wall of the ridge-shaped ridge portion to affect the device performance, another embodiment of the invention can select to perform an additional cleaning manufacturing process to remove all the damaged layer before forming the P-type semiconductor layer or the barrier layer, thereby ensuring that the high electron mobility transistor is finished in a stable electrical performance.
The foregoing description is only of the preferred embodiments of the invention, and all changes and modifications that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

Claims (10)

1. A high electron mobility transistor comprising:
The buffer layer is arranged on the substrate;
A plurality of raised portions extending along a first direction on the buffer layer;
a plurality of grooves extending between the plurality of ridges along the first direction;
A P-type semiconductor layer extending over the plurality of bumps along a second direction and inserted into the plurality of grooves; and
And the source electrode and the drain electrode are adjacent to two sides of the P-type semiconductor layer, extend along the second direction and are positioned right above the plurality of raised parts.
2. The hemt of claim 1, further comprising a gate electrode disposed on said P-type semiconductor layer.
3. The hemt of claim 2, wherein said gate electrode comprises a metal.
4. The hemt of claim 1, wherein the buffer layer comprises gallium nitride.
5. The hemt of claim 1, wherein said P-type semiconductor layer comprises P-type gallium nitride.
6. The hemt of claim 1, further comprising a barrier layer disposed between said buffer layer and said P-type semiconductor layer.
7. The hemt of claim 6 wherein the barrier layer comprises Al xGa1-x N.
8. The hemt of claim 1, wherein said source electrode comprises a socket electrode.
9. The hemt of claim 1, wherein said drain electrode comprises a socket electrode.
10. The hemt of claim 1, wherein the first direction is orthogonal to the second direction.
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