CN118039658A

CN118039658A - Semiconductor structure, manufacturing method thereof and image sensor

Info

Publication number: CN118039658A
Application number: CN202410125301.0A
Authority: CN
Inventors: 张莉玮; 奚鹏程; 范春晖; 张维; 赵庆贺
Original assignee: Hefei Haitu Microelectronics Co ltd
Current assignee: Hefei Haitu Microelectronics Co ltd
Priority date: 2024-01-29
Filing date: 2024-01-29
Publication date: 2024-05-14

Abstract

The invention provides a semiconductor structure, a manufacturing method thereof and an image sensor, wherein the semiconductor structure comprises the following components: a substrate structure; the first doped region is arranged in the substrate structure, a first PN junction is formed at the joint of the first doped region and the substrate structure, the first doped region comprises a plurality of doped branches, the doped branches are distributed in an array along the surface of the substrate structure, and in each doped branch, the ion doping concentration is gradually decreased from the center to the edge; and the second doped region is arranged in the first doped region, and is connected with the first doped region and forms a second PN junction. The invention provides a semiconductor structure, a manufacturing method thereof and an image sensor, which can improve the full well capacity of the semiconductor structure, thereby improving the imaging quality of the image sensor.

Description

Semiconductor structure, manufacturing method thereof and image sensor

Technical Field

The present invention relates to the field of image sensing technologies, and in particular, to a semiconductor structure, a manufacturing method thereof, and an image sensor.

Background

With the advancement of technology and society, image sensors have been demanded to have high pixels, high full well charge capacity, high dynamic, high sensitivity, night vision, and the like. The full well capacity refers to the limit of the number of electrons which can be collected and contained by the pixel, and is one of important performance criteria of the pixel. The full well capacity directly determines the maximum signal-to-noise ratio of the image sensor and is highly correlated with sensitivity, dynamic range, noise and optical response.

While the process nodes of the image sensor are gradually reduced, the area for storing charges is compressed while the pixels are miniaturized, and the full well capacity is greatly affected. Low full well capacity can reduce the dynamic range, signal to noise ratio of the pixel, and can also reduce the range of light detectable by the pixel, severely affecting imaging quality.

Disclosure of Invention

The invention aims to provide a semiconductor structure, a manufacturing method thereof and an image sensor, which can improve the full well capacity of the semiconductor structure, thereby improving the imaging quality of the image sensor.

In order to solve the technical problems, the invention is realized by the following technical scheme:

The invention provides a semiconductor structure, comprising:

A substrate structure;

The first doped region is arranged in the substrate structure, a first PN junction is formed at the joint of the first doped region and the substrate structure, the first doped region comprises a plurality of doped subsections, the doped subsections are distributed in an array along the surface of the substrate structure, and the ion doping concentration in each doped subsection decreases from the center to the edge; and

The second doped region is arranged in the first doped region, and is connected with the first doped region and forms a second PN junction.

In an embodiment of the present invention, the semiconductor structure includes a third doped region disposed in the substrate structure, wherein the doping ions of the third doped region and the first doped region are the same.

In an embodiment of the present invention, the semiconductor structure includes a transmission gate disposed on the substrate structure, wherein one side of the transmission gate extends onto the second doped region, and the other side of the transmission gate extends onto the third doped region.

The invention provides a manufacturing method of a semiconductor structure, which at least comprises the following technical steps:

providing a substrate structure;

implanting first ions into the substrate structure to form a plurality of doping subsections, wherein the doping subsections are distributed in an array along the surface of the substrate structure;

Annealing the substrate structure, wherein after annealing, a plurality of doping subsections are connected and form a first doping region, and a first PN junction is formed at the connection part of the first doping region and the substrate structure, wherein the ion doping concentration in each doping subsection decreases from the center to the edge; and

And implanting second ions into the first doped region to form a second doped region, wherein the second doped region is connected with the first doped region and forms a second PN junction.

In an embodiment of the present invention, the step of forming the doping section includes:

Simulating and verifying a simulated photomask pattern and simulated doping parameters of a photoelectric reaction area, and obtaining a process photomask pattern and process doping parameters of the photoelectric reaction area;

Forming a photoresist layer on the substrate structure, and patterning the photoresist layer to form the process photomask pattern;

And implanting first ions into the substrate structure according to the process doping parameters to form a plurality of doping subsections.

In an embodiment of the present invention, the step of obtaining the process mask pattern and the process doping parameter of the photoelectric reaction region includes:

presetting the area of the photoelectric reaction area and a simulated photomask pattern, wherein the simulated photomask pattern is paved in the photoelectric reaction area;

Presetting a simulated doping parameter of a photoelectric reaction region, obtaining a simulated doping region according to the simulated photomask pattern and the simulated doping parameter, and simulating a diffusion distribution pattern of the simulated doping region after multiple times of heat treatment;

And simulating the simulated full well capacity of the simulated doped region after heat treatment until the simulated full well capacity is larger than a preset capacity threshold, and taking the simulated photomask pattern as the process photomask pattern and the process doping parameter.

In an embodiment of the present invention, when the simulated full well capacity is smaller than the preset capacity threshold, the simulated photomask pattern and the simulated doping parameter are adjusted, wherein the adjustment parameters of the simulated photomask pattern include a pattern shape, a pattern area, an adjacent pattern spacing distance and a pattern number, and the adjustment parameters of the simulated doping parameter include an ion doping concentration.

In an embodiment of the present invention, the simulated photomask pattern includes a plurality of shielding patterns, and a gap distance is provided between adjacent shielding patterns, wherein the gap distance is smaller than an ion diffusion distance of the simulated doped region.

In an embodiment of the present invention, the simulated photomask pattern includes a reserved pattern, the reserved pattern is disposed between adjacent shielding patterns, and a sum of areas of the reserved pattern and the shielding pattern is equal to an area of the photoelectric reaction region.

The invention provides an image sensor, which comprises a plurality of pixel units, wherein the pixel units are distributed in an array and form a pixel array, and the pixel units comprise:

a semiconductor structure as in any above, wherein the semiconductor structure comprises a substrate structure and a first doped region; and

The working transistors are arranged on the substrate structure and are electrically connected with the first doped region.

As described above, the present invention provides a semiconductor structure, a method of manufacturing the same, and an image sensor capable of maintaining the full well capacity of a photo-electric reaction region unchanged while reducing the size of Cheng Guanjian, thereby improving the imaging quality of the image sensor. The semiconductor structure, the manufacturing method thereof and the image sensor provided by the invention have the advantages that the edge effect of the photoelectric reaction area is also obviously reduced, the potential change steepness of the edge of the photoelectric reaction area is improved, and then the full-well capacitance is improved. The semiconductor structure, the manufacturing method thereof and the image sensor can reduce the influence of process errors, ensure that the full well capacity reaches a preset threshold value and have higher process yield.

Of course, it is not necessary for any one product to practice the invention to achieve all of the advantages set forth above at the same time.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic circuit diagram of an image sensor according to an embodiment of the invention.

Fig. 2 is a schematic circuit distribution diagram of a pixel unit in an image sensor.

Fig. 3 is a schematic cross-sectional structure of a pixel unit in an image sensor.

Fig. 4 is a schematic top view of a pixel unit in the image sensor.

Fig. 5 is a schematic diagram showing the potential distribution of the photo-reaction region in the image sensor.

FIG. 6 is a flowchart of a process mask pattern acquisition method according to an embodiment of the invention.

FIG. 7 is a schematic diagram of an exemplary mask pattern in accordance with one embodiment of the present invention.

FIG. 8 is a schematic diagram of an exemplary mask pattern in accordance with one embodiment of the present invention.

FIG. 9 is a schematic diagram of an exemplary mask pattern according to one embodiment of the present invention.

FIG. 10 is a schematic diagram of an exemplary mask pattern according to one embodiment of the present invention.

FIG. 11 is a schematic cross-sectional view of a simulated doped region in accordance with an embodiment of the present invention.

FIG. 12 is a schematic cross-sectional view of a simulated photo-electric reaction zone in accordance with an embodiment of the invention.

FIG. 13 is a schematic diagram showing potential distribution of an analog photoelectric reaction region according to an embodiment of the present invention.

Fig. 14 is a schematic view of a semiconductor structure implanted with dopant ions according to an embodiment of the invention.

Fig. 15 is a circuit distribution diagram of a pixel unit according to an embodiment of the invention.

In the figure: 100. an image sensor; 110. a pixel unit; 111. a photoelectric reaction region; 1111. a substrate; 1112. an epitaxial layer; 1113. a first doped region; 1114. a second doped region; 1115. a third doped region; 1116. a transmission gate; 112. an operating transistor; 113. a column output bus; 114. a row driving circuit; 115. a column readout circuit; 200.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

Image sensor chips for large-scale commercial use include two broad categories, charge coupled devices (Charged Coupled Device, CCDs) and Complementary Metal Oxide Semiconductor (CMOS) image sensor chips. The image sensor provided by the invention is a CMOS image sensor. Compared with a CCD sensor, the CMOS image sensor has the characteristics of low power consumption, low cost, good compatibility with a CMOS process and the like, is not only applied to the field of consumer electronics, such as miniature digital cameras, mobile phone cameras, video cameras and digital single lens reflex, but also is widely applied to the fields of automobile electronics, monitoring, biotechnology, medicine and the like. Referring to fig. 1 and 2, the image sensor 100 includes a plurality of pixel units 110, wherein the pixel units 110 include a photo-reactive region 111 and a plurality of operating transistors 112. The photo-electric reaction area 111 is a photosensitive element, and can convert the optical signal of the incident light into an electric signal. The operation transistor 112 is connected to the photo reaction region 111 to receive the electric signal converted by the photo reaction region 111. Wherein the operating transistor 112 is a MOS transistor. In this embodiment, the operation transistor 112 may include a Reset (RX) transistor, a source follower (Source Follower, SF), and a Row Select (RS) transistor. The pixel cell 110 is divided into a multi-T pixel structure according to the number of the operating transistors 112 in the single pixel cell 110. In this embodiment, the pixel unit 110 is, for example, a 4T pixel structure. The invention is not limited to the type of operating transistor 112.

Referring to fig. 1 and 2, in an embodiment of the invention, the pixel unit 110 includes a substrate 1111, an epitaxial layer 1112, and a plurality of photoelectric doped regions. Wherein the substrate 1111 is, for example, a silicon base material forming the photo-electric reaction region 111. Epitaxial layer 1112 is a silicon layer grown on substrate 1111. The base material of the substrate 1111 is, for example, a semiconductor substrate material such as silicon (Si), silicon carbide (SiC), sapphire (Al ₂O₃), gallium arsenide (GaAs), lithium aluminate (LiAlO ₂), or the like, and a silicon layer is formed over the base material. In this embodiment, P-type ions are doped in the substrate 1111 and the epitaxial layer 1112. The photo-electrically doped region is formed in epitaxial layer 1112. In this embodiment, the photoelectric doped region includes a first doped region 1113 and a second doped region 1114. The first doped region 1113 is buried in the epitaxial layer 1112, and the doped ions of the first doped region 1113 are N-type ions, so that a first PN junction is formed at the junction between the first doped region 1113 and the epitaxial layer 1112. The second doped region 1114 is disposed on the surface of the epitaxial layer 1112. Wherein the dopant ions of the first doped region 1113 and the second doped region 1114 are acceptor impurities and donor impurities with respect to each other. In this embodiment, the doped ions of the first doped region 1113 are N-type ions, and the doped ions of the second doped region 1114 are P-type ions. The second doped region 1114 is disposed on the first doped region 1113, and the second doped region 1114 contacts the first doped region 1113 to form a second PN junction. In the image sensor, a photoelectric reaction occurs in the first doping region 1113. The silicon surface typically has defects, interface states, or damage that can lead to the generation of noise signals, such as dark current. The second doped region 1114 can isolate these noise signals, so that the noise influence cannot freely move to the first doped region and affect the photo-generated charge signal, thereby improving the stability of the photo-electric charge signal.

Referring to fig. 2, in an embodiment of the invention, the pixel unit 110 includes a transmission transistor TG. Wherein the pixel transistor TG includes a third doped region 1115 and a transfer gate 1116. In this embodiment, the third doped region 1115 is disposed in the epitaxial layer 1112 and is located on the surface layer of the epitaxial layer 1112. The third doped region 1115 is disposed on one side of the second doped region 1114, and the doping ions of the third doped region 1115 and the first doped region 1114 are N-type donor impurities. The transfer gate 1116 may be a polysilicon layer or a metal gate, the transfer gate 1116 is disposed on the epitaxial layer 1112, and one side of the transfer gate 1116 extends onto the second doped region 1114, and the other side of the transfer gate 1116 extends onto the third doped region 1115, thereby forming a channel between the second doped region 1114 and the third doped region 1115. Wherein the transfer gate 1116 connects the second doped region 1114 and the third doped region 1115, thereby forming a transfer transistor TG. When a voltage is applied to the transfer gate 1116, the channel is turned on, the transfer transistor TG is turned on, and a current flows between the second doped region 1114 and the third doped region 1115. When light enters the pixel unit 110, the photo-reaction region 111 generates photo-generated charges due to the incident light and accumulates in the photo-reaction region 111, and when the transfer transistor TG is turned on, the charges are conducted out through the transfer transistor TG. In this embodiment, the third doped region 1115 is a charge storage node, and when photo-generated charges are exported, the photo-generated charges are stored in the third doped region 1115.

Referring to fig. 1 and 2, in an embodiment of the invention, the pixel unit 110 includes a reset transistor RST, a source follower SF, and a gate SEL. The reset transistor RST, the source follower tube SF and the gate tube SEL are MOS tubes, and the invention is not limited to the MOS tubes being PMOS tubes or NMOS tubes. One end of the reset transistor RST is connected to the transmission transistor TG, and the other end of the reset transistor RST is grounded. One end of the source follower SF is connected to the high potential end VDD Pixel, the other end is connected to the gate tube SEL, and the driving end of the source follower SF is electrically connected to the charge storage node. One end of the gate tube SEL is connected to the source follower tube SF, and the other end of the gate tube SEL is connected to the column output bus 113. The image sensor 100 includes a column output bus 113, a row driving circuit 114, and a column readout circuit 115. In the image sensor 100, a plurality of pixel units 110 are distributed in an array in a row direction and a column direction, thereby forming a row circuit and a column circuit. Wherein a plurality of pixel units 110 located in the same row are connected to the same row driving circuit 114. In this embodiment, the row drive circuit 114 sends a drive signal to the drive electrode of the operating transistor 112. Wherein the driving signal is a level signal for controlling the on or off of the operation transistor 112. In the present embodiment, the row driving circuit 114 may transmit a transfer signal, a reset signal, and a gate signal to the pixel unit 110 to control on or off of the transfer transistor TG, the reset transistor RST, and the gate pipe SEL, respectively. Wherein a plurality of pixel units 110 of the same column are connected to the same column output bus 113. In the present embodiment, the plurality of column output buses 113 are electrically connected to the column readout circuit 115. Column readout circuitry 115 may select column output bus 113 to be read out. In this embodiment, the gate of the source follower SF is connected to the charge storage node. The source follower SF always operates in a conductive state when the pixel unit 110 operates normally. The first doped region 1113 generates a photo-generated charge signal upon contact with incident light. When the stored charge of the charge storage node changes with the photo-generated charge signal, the voltage signal at the drain terminal of the source follower SF changes synchronously, wherein the voltage signal is related to the photo-generated charge signal. Specifically, in the source follower tube SF, the change amplitude of the voltage signal is correlated with the change amplitude of the photo-generated charge signal. When the charge of the pixel unit 110 is to be read out, the gate SEL is turned on, and the amount of the photo-generated charge is output from the column readout bus 113 as a voltage signal. The reset transistor RST is turned on and photo-generated charge stored in the charge storage node is conducted out through the high potential terminal vdd_pixel, thereby clearing the third doped region 1115.

As shown in fig. 2 to 5, as the process node of the image sensor 100 decreases, the cross-sectional area of the photo-reactive region 111 also decreases, so that the number of electrons that can be accommodated in the photo-reactive region 111 decreases in the same technology. The invention also provides a manufacturing method of the semiconductor structure, which can be applied to a process node of 40nm and below, and ensures that the full well capacity of the photoelectric reaction region 111 is unchanged. The semiconductor structure provided by the invention comprises a photoelectric reaction region 111. With the same image sensor 100, the depth of the photo-reactive regions 111 is equal among the plurality of process nodes, and the width and cross-sectional area of the photo-reactive regions 111 decrease as the process nodes decrease. In the semiconductor structure provided by the invention, the aspect ratio of the photoelectric reaction region 111 is less than 1:1 and greater than or equal to 1:2. As shown in fig. 3, the width of the photo-reaction region 111 is b, and the depth of the photo-reaction region 111 is D. Wherein fig. 3 is a cross-sectional view of the photo-electric reaction zone 111 and fig. 4 is a top view of the photo-electric reaction zone 111. Fig. 5 is a schematic diagram of the potential variation in the XX' direction. In a manufacturing method of forming a semiconductor structure, the photoelectric reaction region 111 is formed by implanting dopant ions into the epitaxial layer 1112. The edge concentration of the photoelectric reaction region 111 is graded by diffusion, so that the potential variation trend from the photoelectric reaction region 111 to the epitaxial layer 1112 is slowed down. As the process node decreases, the width b of the photo-reactive region 111 decreases, and thus the edge effect of the semiconductor structure becomes more pronounced, resulting in an excessively small full well capacity of the photo-reactive region 111. As shown in fig. 5, the cross-sectional potential of the photoreaction region 111 exhibits a V-shape, which results in extremely low application rate per unit area of the photoreaction region 111, and a reduction in the number of electrons that can be accommodated, and thus a reduction in the full-well capacity.

Referring to fig. 2 to 6, the present invention provides a method for manufacturing a semiconductor structure. In a method of fabricating a semiconductor structure, a substrate 1111 is provided first, and then an epitaxial layer 1112 is grown on the substrate 1111. A photoresist layer is then formed over the epitaxial layer 1112. The invention provides a manufacturing method of a semiconductor structure, which comprises the step of obtaining a process photomask pattern. Wherein the step of obtaining the process mask pattern includes steps S10 to S60.

Step S10, planning the area of the photoelectric reaction region 111.

Step S20, presetting the simulated mask pattern of the photo-electric reaction area 111.

Step S30, presetting doping parameters of the photoelectric reaction region 111, and simulating a forming pattern of the photoelectric reaction region 111 and a potential distribution diagram of the photoelectric reaction region 111 according to the photomask pattern of the photoelectric reaction region 111.

Step S40, determining whether the full well capacity of the photoelectric reaction region 111 is greater than or equal to the capacity threshold.

In step S50, when the full well capacity of the photoelectric reaction region 111 is greater than or equal to the capacity threshold, the doping parameters of the simulation photomask pattern and the photoelectric reaction region 111 are adjusted.

In step S60, when the full well capacity of the photo-electric reaction region 111 is smaller than the capacity threshold, the photo-simulation mask pattern is used as the process mask pattern of the photo-electric reaction region 111.

Referring to fig. 2 and fig. 6 to fig. 12, in step S10, the area of the photo-electric reaction region 111 is planned. As shown in fig. 7, the width b and the length of the photo-reaction region 111 are preset according to a top view of the semiconductor structure. Wherein the side of the photo-electric reaction area 111 is a linear side or an arc side. Specifically, the area of the photoelectric reaction region 111 is planned according to the area of the epitaxial layer 1112 and according to the pixel array structure and the device structure to be formed on the epitaxial layer 1112. In step S20, a dummy mask pattern of the photo-electric reaction region 111 is first preset, and a mask pattern 200 for forming the dummy mask pattern is obtained according to the dummy mask pattern. Wherein fig. 7 is a reticle pattern 200 of photo-reactive zone 111. Wherein the area of the mask pattern 200 is equal to or larger than the area of the photo-electric reaction region 111. In this embodiment, the area of the mask pattern 200 is equal to the area of the photo-reactive region 111 so as to align the mask pattern 200, the photoresist layer, and the region where the photo-reactive region 111 is to be formed. In this embodiment, the reticle pattern 200 is located on the photoresist layer. Reticle pattern 200 includes a blocking pattern 210 and a reserved pattern 220. Wherein the shielding pattern 210 is made of opaque material, and the reserved pattern 220 is made of transparent material. When the photoresist layer is exposed, the chemical properties of the region of the photoresist layer blocked by the blocking pattern 210 are unchanged, and the chemical properties of the region of the photoresist layer blocked by the reserved pattern 220 are changed, thereby transferring the pattern of the mask pattern 200 onto the photoresist layer. Then, the photoresist layer is developed to remove a portion of the photoresist layer blocked by the reserved pattern 220, thereby obtaining a simulated photomask pattern.

Referring to fig. 2 and fig. 6 to fig. 8, in an embodiment of the invention, the patterns of the simulated photomask pattern and the reticle pattern 300 are the same. Wherein there are a plurality of shielding patterns 210 in the area of the photo reaction area 111. Wherein the reserved pattern 220 is a gap pattern between adjacent barrier patterns 210. Where reserved pattern 220 has a width D. As shown in fig. 7 and 8, the number of shielding patterns 210 in the photoreaction region 111 is not limited. In step S30, in order to ensure that the edge of the design pattern is completely etched in the production process, optical proximity correction (Optical Proximity Correction, OPC) is applied to the mask pattern before photolithography, so that the target pattern formed on the wafer by the mask pattern is highly fitted with the designed layout pattern. Taking model-based optical proximity effect correction as an example, an optical model and a photoresist chemical reaction model are used to simulate a simulated mask pattern after exposure, and a simulated mask pattern after exposure formed on a photoresist layer by etching. The edges of the reticle pattern 200 are continuously adjusted by comparing the error between the simulated reticle pattern and the post-exposure reticle pattern, so that the error between the simulated reticle pattern and the post-exposure reticle pattern reaches a preset threshold. The pattern of the simulated photomask pattern is a preset pattern, and specifically is a design pattern of the mask pattern 200. The post-exposure mask pattern is a mask pattern obtained by performing a simulated exposure of the photoresist layer through the mask pattern 200.

Referring to fig. 2 and fig. 6 to fig. 10, in an embodiment of the invention, the shielding pattern 210 is a regular pattern, and the shielding pattern 210 is laid in the area of the planned area of the photoelectric reaction region 111. The sides of the shielding pattern 210 may be straight sides or arc sides. In this embodiment, a preset distance D is set between adjacent shielding patterns 210. Wherein the preset distance D is the pattern width of the reserved pattern 220. The present invention does not limit the shape of the reserved pattern 220. As shown in FIG. 7, in an embodiment of the present invention, the cross section of the shielding patterns 210 is rectangular, and a plurality of shielding patterns 210 are distributed in an array. The cross section of the reserved pattern 220 is a grid-like structure. Wherein the plurality of occlusion patterns 210 are equal. The present invention does not limit the side length of the shielding pattern 210 nor the size of the preset distance D. As shown in fig. 8, the plurality of occlusion patterns 210 are equal. Keeping the preset distance D unchanged, the side length of the shielding patterns 210 decreases, and the number of shielding patterns 210 increases. In another embodiment of the present invention, as shown in fig. 9, the cross section of the shielding pattern 210 is in a shape of a Chinese character 'hui', and the cross section of the reserved pattern 220 is in a shape of a Chinese character 'hui' or a rectangle. In yet another embodiment of the present invention, as shown in fig. 10, the shielding patterns 210 are rectangular, and the plurality of shielding patterns 210 are not equal.

Referring to fig. 2 and fig. 6 to fig. 12, in step S30, doping parameters of the photo-electric reaction region 111 are preset, wherein the doping parameters include ion doping concentration, ion implantation energy, ion implantation angle, and the like. The doping parameters used for the simulated doping are preset, wherein the ion doping concentration increases as the process node decreases. Specifically, the increase in ion doping concentration is related to the number of dimensions of the process node decrease, and a specific value of the increase in ion doping concentration can be adjusted through experiments. Wherein the distribution pattern of the photo-reactive region 111 is simulated based on the dopant diffusion model. In step S30, a preset doping parameter is input to the doping diffusion model, and the number of heat treatments to be undergone to form the semiconductor structure is obtained. First, the distribution pattern of the simulated doped region 300 is simulated according to the doping parameters and the simulated mask pattern. The dummy doped region 300 is a doped region formed by implanting doping ions into the epitaxial layer 1112, and there are a plurality of dummy doped regions 300. Wherein the plurality of dummy doped regions 300 are not in contact, and in particular, in the dummy pattern of the photo-reactive region 111, there is a gap 400 between adjacent dummy doped regions 300.

Referring to fig. 2 and fig. 6 to fig. 13, in step S30, the heat treatment type and the heat treatment parameters for forming the image sensor 100 are obtained, and the diffusion structure formed by heat treatment of the dopant ions is simulated by a dopant diffusion model. As shown in fig. 11 and 12, after the dummy doped regions 300 are diffused, adjacent dummy doped regions 300 are connected. In the simulated doped region 300, the edge dopant ion concentration is lower than the center dopant ion concentration. In which the dopant ions are diffused to fill the gap 400, thereby forming the simulated photo-reaction region 111. The potential profile of the photo-electric reaction zone 111 is simulated based on the simulated dopant ion concentrations of the regions in the photo-electric reaction zone 111. The potential distribution of the photoreaction zone 111 in the present invention is shown in fig. 13. As shown in fig. 13 and 5, in the same area, the potential change of the edge region of the photoelectric reaction region 111 is steeper, and the potential stability of the middle region of the photoelectric reaction region 111 is better and the duration range is wider. As shown in fig. 13, after the diffusion of the dummy doping regions 300, the area potential at which the two dummy doping regions 300 are in contact fluctuates, and the potential is lower in the middle area of the dummy doping regions 300. The photoelectric reaction region 111 provided by the invention can accommodate more electrons, and is beneficial to improving the capacity of the full trap.

Referring to fig. 2 and fig. 6 to fig. 13, in step S40, it is determined whether the simulated full well capacity of the photoelectric reaction region 111 is greater than or equal to the capacity threshold. Wherein the capacity threshold is a preset full well capacity of the image sensor 100. If the simulated full well capacity is smaller than the preset full well capacity, step S50 is performed. In step S50, doping parameters of the mask pattern and the photo-electric reaction region are adjusted. Wherein the step of adjusting the mask pattern includes adjusting the area of the dummy doped regions, the shape of the dummy doped regions, the number of the dummy doped regions, the spacing between adjacent dummy doped regions, and the like. The step of adjusting the doping parameter includes adjusting a doping ion concentration. After the adjustment, the process returns to step S30, and the simulated photo-electric reaction region 111 is again performed. And step S60 is executed until the simulated full well capacity is greater than or equal to the preset full well capacity. In step S60, the mask pattern is outputted as a process mask pattern of the photo-electric reaction region 111. Wherein the process mask pattern may be used as a process mask for forming the photo-reactive region 111. In step S60, when the simulated full well capacity is equal to or greater than the preset full well capacity, the doping parameter at this time is recorded as the ion implantation process parameter of the photoelectric reaction region 111.

Referring to fig. 2, 6-10, and 14 and 15, in a method for manufacturing a semiconductor structure, a photoresist layer is patterned according to a process mask pattern after the process mask pattern and after doping parameters are obtained. Next, doping ions are implanted into the epitaxial layer 1112 to form a plurality of doped regions 500 to be diffused, as shown in fig. 14. Then, doping ions are respectively implanted into the epitaxial layer 1112 to form a second doped region 1114 and a third doped region 1115. The ion implantation sequence of forming the third doped region 1115 and the second doped region 1114 is not limited in the present invention. A transfer gate 1116 is then formed on the epitaxial layer 1112, wherein one side of the transfer gate 1116 is connected to the second doped region 1114 and the other side is connected to the third doped region 1115. Deep Trench Isolation (DTI) structures are then formed in the epitaxial layer 1112, and device structure structures for the operating transistor 112 are formed in the epitaxial layer 1112. Contact pillars and metal wiring structures are then formed, forming image sensor 100. After forming the to-be-diffused doped region 500 and during forming the image sensor 100, the semiconductor structure undergoes a plurality of heat treatment processes, for example, an annealing process, and the dopant ions in the to-be-diffused doped region 500 are diffused to the outside, thereby forming the first doped region 1113. Wherein the diffused first doped region 1113 comprises a plurality of doped segments 600. In each doping section 600, the concentration of dopant ions decreases from the center to the edge.

The invention provides a semiconductor structure, a manufacturing method thereof and an image sensor. The plurality of pixel units are distributed in an array, so that a pixel array is formed. Wherein the pixel cell comprises a semiconductor structure and a plurality of operating transistors. The semiconductor structure comprises a substrate structure, a first doped region and a second doped region. The first doped region is arranged in the substrate structure, and comprises a plurality of doped branches, wherein the doped branches are distributed in an array along the surface of the substrate structure, and after annealing, the doped branches are connected, and the ion doping concentration in the doped branches decreases from the center to the edge. The second doped region is arranged in the first doped region, and is connected with the first doped region to form a photoelectric reaction region. The invention provides a semiconductor structure, a manufacturing method thereof and an image sensor, which can improve the full well capacity of the semiconductor structure, thereby improving the imaging quality of the image sensor.

The embodiments of the invention disclosed above are intended only to help illustrate the invention. The examples are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best understand and utilize the invention. The invention is limited only by the claims and the full scope and equivalents thereof.

Claims

1. A semiconductor structure, comprising:

A substrate structure;

2. The semiconductor structure of claim 1, comprising a third doped region disposed in the substrate structure, wherein the third doped region and the first doped region have the same doping ions.

3. The semiconductor structure of claim 2, comprising a transfer gate disposed on the substrate structure, wherein one side of the transfer gate extends onto the second doped region and the other side of the transfer gate extends onto the third doped region.

4. A method for manufacturing a semiconductor structure, comprising at least the following technical steps:

providing a substrate structure;

5. The method of claim 4, wherein forming the doping section comprises:

6. The method of claim 5, wherein the step of obtaining the process mask pattern and the process doping parameters of the photo-reactive region comprises:

7. The method of claim 6, wherein the simulated mask pattern and the simulated doping parameter are adjusted when the simulated full well capacity is less than the predetermined capacity threshold, wherein the simulated mask pattern adjustment parameter comprises a pattern shape, a pattern area, a distance between adjacent patterns, and a pattern number, and the simulated doping parameter adjustment parameter comprises an ion doping concentration.

8. The method of claim 5, wherein the dummy mask pattern includes a plurality of mask patterns, and a gap distance is provided between adjacent mask patterns, wherein the gap distance is smaller than an ion diffusion distance of the dummy doping region.

9. The method according to claim 8, wherein the dummy mask pattern includes a predetermined pattern, the predetermined pattern is disposed between adjacent shielding patterns, and a sum of areas of the predetermined pattern and the shielding patterns is equal to an area of the photo-electric reaction region.

10. An image sensor comprising a plurality of pixel cells, wherein the plurality of pixel cells are distributed in an array and form a pixel array, wherein the pixel cells comprise:

a semiconductor structure as claimed in any one of claims 1 to 3, wherein the semiconductor structure comprises a substrate structure and a first doped region; and