CN118039484A

CN118039484A - Stacked device structure, forming method thereof and method for forming gate stack

Info

Publication number: CN118039484A
Application number: CN202410076634.9A
Authority: CN
Inventors: 林政明; 温伟源; 廖思雅
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2023-01-24
Filing date: 2024-01-18
Publication date: 2024-05-14

Abstract

Embodiments herein disclose dipole engineering techniques for devices of stacked device structures. An exemplary method for forming a gate stack of a transistor (e.g., a top transistor) of a transistor stack includes: forming a high-k dielectric layer; forming a p-dipole dopant source over the high-k dielectric layer; performing a thermal drive-in process to drive the p-dipole dopant from the p-dipole dopant source into the high-k dielectric layer; and forming at least one conductive gate layer over the high-k dielectric layer after removing the p-dipole dopant source layer. The drive-in temperature of the thermal drive-in process is less than 600 ℃ (e.g., about 300 ℃ to about 500 ℃). The p-dipole dopant may be titanium. The method may further include adjusting the thermal drive-in process parameters to provide a gate dielectric having a p-dipole dopant profile with a peak located at + -0.5 nm of the high-k/interfacial interface. Embodiments of the application also relate to stacked device structures, methods of forming the same, and methods of forming gate stacks.

Description

Stacked device structure, forming method thereof and method for forming gate stack

Technical Field

Embodiments of the application relate to stacked device structures, methods of forming the same, and methods of forming gate stacks.

Background

The electronics industry has experienced an increasing demand for smaller and faster electronic devices that are capable of supporting more increasingly complex and sophisticated functions at the same time. To meet these needs, there is a continuing trend in the Integrated Circuit (IC) industry to manufacture low cost, high performance, and low power ICs. To date, these goals have been largely achieved by reducing the IC size (e.g., minimum IC component size), thereby improving production efficiency and reducing associated costs. But such scaling also increases the complexity of the IC fabrication process. Thus, achieving continued advances in IC devices and their performance requires similar advances in IC fabrication processes and techniques.

One area of advancement involves providing ICs with transistors having multiple threshold voltages (Vt), which can improve the performance of some of the transistors of the IC while reducing the power consumption of other transistors of the IC. Providing multiple threshold voltages is challenging for multi-gate devices, such as fin field effect transistors, all-gate transistors including nanowires and/or nanoplates, and other types of multi-gate devices, because the multi-gate devices become very small, which leaves minimal room for using different work function metals to adjust their threshold voltages. While dipole engineering can provide multi-gate devices with multiple threshold voltages while minimizing and/or eliminating the need to use different work function metals, dipole engineering techniques present challenges in implementing device stacks to achieve further scaling. Thus, while existing threshold voltage adjustment techniques have generally been adequate for their intended purposes, they have not been entirely satisfactory in all respects.

Disclosure of Invention

Some embodiments of the present application provide a method for forming a gate stack of a transistor, wherein the transistor forms part of the transistor stack, the method comprising: forming a high-k dielectric layer; forming a p-dipole dopant source over the high-k dielectric layer; performing a thermal drive-in process that drives p-dipole dopants from the p-dipole dopant source into the high-k dielectric layer, wherein a drive-in temperature of the thermal drive-in process is less than 600 ℃; and forming at least one conductive gate layer over the high-k dielectric layer after removing the p-dipole dopant source layer.

Other embodiments of the present application provide a method of forming a stacked device structure, comprising: forming a first transistor of the transistor stack; bonding the first transistor of the transistor stack to a precursor for fabricating a second transistor of the transistor stack; and forming the second transistor over the first transistor, wherein forming the second transistor comprises processing the precursor, forming a gate stack of the second transistor, wherein the gate stack comprises a gate dielectric and a gate electrode, and performing a dipole engineering process, wherein the dipole engineering process comprises: forming a p-dipole dopant source layer over the gate dielectric, performing a thermal drive-in process that drives p-dipole dopant from the p-dipole dopant source layer into the gate dielectric, wherein a drive-in temperature of the thermal drive-in process is less than 600 ℃, and removing the p-dipole dopant source layer.

Still further embodiments of the present application provide a stacked device structure comprising: a transistor stack having a first transistor disposed over a second transistor, wherein the first transistor has a first gate stack and the second transistor has a second gate stack; wherein each of the first gate stack and the second gate stack includes an interfacial layer, a high-k dielectric layer disposed over the interfacial layer, and at least one conductive gate layer disposed over the high-k dielectric layer; and wherein an interface region of the interface layer of the high-k dielectric layer and the first gate stack comprises a p-dipole dopant, wherein the p-dipole dopant is titanium.

Drawings

The disclosure is best understood from the following detailed description when read in connection with the accompanying drawing figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1 is a partial cross-sectional view of a portion or an entirety of a stacked device structure in accordance with aspects of the present disclosure.

Fig. 2 is a flow chart of a method for fabricating a gate stack of a device of stacked device structure (such as the gate stack of the device of stacked device structure of fig. 1) in accordance with aspects of the present disclosure.

Fig. 3A-11A and 3B-11B are various views of a device (such as a transistor) of a stacked device structure at various stages of manufacture, partially or entirely, in connection with the method of fig. 2, in accordance with various aspects of the present disclosure.

Fig. 12 illustrates an exemplary dipole dopant profile of a gate dielectric of a device of a stacked device structure (such as a device after dipole engineering in connection with fig. 7A-9A and 7B-9B) in accordance with aspects of the present disclosure.

Fig. 13 is a flow chart of a method for fabricating a stacked device structure, such as the stacked device structure of fig. 1, in accordance with aspects of the present disclosure.

Fig. 14A-14L are partial cross-sectional views of a portion or an entirety of a stacked device structure at various stages of fabrication, such as those associated with the method of fig. 13, in accordance with various aspects of the present disclosure.

Detailed Description

The present disclosure relates generally to Integrated Circuit (IC) devices, and more particularly to IC devices having stacked device structures, such as transistor stacks having n-type transistors and p-type transistors (i.e., complementary Field Effect Transistors (CFETs)).

The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the present disclosure. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component, such that the first component and the second component may not be in direct contact. Further, spatially relative terms such as "lower," "upper," "horizontal," "vertical," "above …," "above …," "below …," "below …," "upward," "downward," "top," "bottom," and the like, and derivatives thereof (e.g., "horizontally," "downwardly," "upwardly," etc.) are used to facilitate understanding of the relationship of one component of the disclosure to another. Spatially relative terms are intended to encompass different orientations of the device comprising the component. The present disclosure may also repeat reference numerals and/or characters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, when values or ranges of values are described using "about," "approximately," etc., the term is intended to encompass values within a reasonable range that take into account variations inherently present during manufacture, as understood by one of ordinary skill in the art. For example, a value or range of values encompasses a reasonable range including the recited value, such as within +/-10% of the recited value, based on known manufacturing tolerances associated with manufacturing components having characteristics associated with the value. For example, a material layer having a thickness of "about 5nm" may cover a size range from 4.5nm to 5.5nm, with a manufacturing tolerance of +/-10% associated with depositing the material layer as known to one of ordinary skill in the art. Further, such language is intended to capture properties and/or characteristics within manufacturing process tolerances when device components are described as having "substantially" properties and/or characteristics, taking into account any differences inherent in the manufacturing process. For example, a "substantially vertical" or "substantially horizontal" component is intended to capture components that are approximately vertical and horizontal, but not mathematically or entirely vertical and horizontal, within a given tolerance of a manufacturing process used to manufacture such components.

Stacked transistor structures, such as Complementary Field Effect Transistors (CFETs), may provide further density reduction for advanced IC technology nodes, particularly as IC technology nodes evolve to 3nm (N3) and below. Fig. 1 is a partial cross-sectional view of a portion or an entirety of a stacked device structure 10 in accordance with aspects of the present disclosure. Stacked device structure 10 includes device 12A, device 12B, substrate 14, and insulating layer 16. Device 12B is vertically stacked over device 12A, insulating layer 16 is disposed between device 12B and device 12A and separates device 12B from device 12A, and device 12A is disposed over substrate 14. In the depicted embodiment, devices 12A and 12B are stacked back-to-front. For example, the back side of device 12B is attached and/or bonded to the front side of device 12A by insulating layer 16, insulating layer 16 comprising insulating layer 16A and insulating layer 16B. In some embodiments, insulating layer 16A is formed on the front side of device 12A, insulating layer 16B is formed on the back side of device 12B, and insulating layer 16B is attached to insulating layer 16A. For clarity, fig. 1 has been simplified to better understand the inventive concepts of the present disclosure. Additional components may be added to stacked device structure 10, and in other embodiments of stacked device structure 10, some of the components described below may be replaced, modified, or eliminated.

In fig. 1, devices 12A and 12B include at least one electrically functional device, such as transistor 18A and transistor 18B, respectively. Thus, stacked device structure 10 includes a transistor stack having a top transistor (e.g., transistor 18B) and a bottom transistor (e.g., transistor 18A) separated and isolated by insulating layer 16. In some embodiments, transistors 18A and 18B are transistors of opposite conductivity types. For example, transistor 18A is an n-type transistor and transistor 18B is a p-type transistor, and vice versa. In such an embodiment, transistor 18A and transistor 18B form a CFET. In some embodiments, transistors 18A and 18B are transistors of the same conductivity type. For example, the transistors 18A and 18B are both n-type transistors or p-type transistors.

Device 12A includes various features and/or components such as semiconductor layer 20A, internal spacers 24A, epitaxial source/drains 25A, and gate structure 30A. Each gate structure 30A may include a gate stack having a gate dielectric 32A and a gate electrode 34A. Gate dielectric 32A may include an interfacial layer 36A and a gate dielectric layer 38A (e.g., a high-k dielectric layer). The gate stack may also include a hard mask layer 42A. Each gate structure 30A may also include gate spacers 40A disposed along sidewalls of the gate stack. Device 12A also includes dielectric layers such as inter-layer dielectric (ILD) layers and Contact Etch Stop Layers (CESL) 45A and source/drain contacts 50A.

Device 12B includes various features and/or components such as semiconductor layer 20B, internal spacers 24B, epitaxial source/drains 25B, and gate structure 30B. Each gate structure 30B may include a gate stack having a gate dielectric 32B and a gate electrode 34B. Gate dielectric 32B may include an interfacial layer 36B and a gate dielectric layer 38B (e.g., a high-k dielectric layer). The gate stack may also include a hard mask layer 42B. Each gate structure 30B may also include gate spacers 40B disposed along sidewalls of the gate stack. Device 12B also includes dielectric layers such as ILD layers and/or CESL 45B and source/drain contacts 50B disposed on epitaxial source/drain 25B.

In the depicted embodiment, transistor 18A is a full-gate-all-around (GAA) transistor. For example, the transistor 18A has two channels provided by respective semiconductor layers 20A (hereinafter referred to as channel layers 20A), the semiconductor layers 20A floating above the substrate 14 and extending between respective source/drains (e.g., epitaxial source/drains 25A). The transistor 18A also has a corresponding gate structure 30A disposed over its channel layer 20A and between its epitaxial source/drain 25A, with an internal spacer 24A disposed between the gate stack of its gate structure 30A and its epitaxial source/drain 25A. In a gate lateral direction (e.g., in the X-Z plane), such as depicted, the gate stack of gate structure 30A is located above top channel layer 20A, between channel layers 20A, and between bottom channel layer 20A and the mesa of substrate 14. The gate stack of the gate structure 30A wraps around the channel layer 20A along the gate longitudinal direction (e.g., in the Y-Z plane). During operation of the GAA transistor, current may flow through the channel layer 20A and between the epitaxial source/drains 25A.

In the depicted embodiment, transistor 18B is also a GAA transistor. For example, the transistor 18B has two channels provided by respective semiconductor layers 20B (hereinafter referred to as channel layers 20B), the semiconductor layers 20B floating above the substrate 14 and extending between respective source/drains (e.g., epitaxial source/drains 25B). Transistor 18B also has a corresponding gate structure 30B disposed over its channel layer 20B and between its epitaxial source/drain 25B, with an internal spacer 24B disposed between the gate stack of its gate structure 30B and its epitaxial source/drain 25B. In a gate lateral direction (e.g., in the X-Z plane), such as depicted, the gate stack of gate structure 30B is located above top channel layer 20B, between channel layers 20B, and between bottom channel layer 20B and insulating layer 16. The gate stack of gate structure 30B wraps around channel layer 20B along the gate longitudinal direction (e.g., in the Y-Z plane). During operation of the GAA transistor, current may flow through the channel layer 20B and between the epitaxial source/drains 25B.

Transistors of the stacked transistor structure, such as stacked device structure 10, may be fabricated separately, monolithically, or sequentially. When manufactured separately, the top and bottom transistors may be manufactured separately and then the top transistor is bonded/attached to the bottom transistor. When monolithically fabricated, the top and bottom transistors are fabricated from the initial device precursor. For example, a first set of semiconductor layers may be bonded/attached to a second set of semiconductor layers and then processed to form top and bottom transistors, respectively. When manufactured in sequence, the first set of semiconductor layers may be processed to form the bottom transistor, and then the second set of semiconductor layers are attached/bonded to the bottom transistor and processed to form the top transistor (i.e., the top transistor is manufactured on the bottom transistor). In both monolithic and sequential fabrication schemes, the bottom transistor may be subjected to the high temperatures used to fabricate the top transistor. For example, when dipole engineering is used (e.g., by incorporating dipole dopants into its gate stack) to adjust the threshold voltage of the top transistor, a temperature of at least 600 ℃ is required to drive aluminum-based dopants (p-dipole dopants) into the high-k dielectric layer of the gate stack of the top transistor. Such high temperatures may reduce the electrical performance and/or reliability of the bottom transistor. For example, temperatures exceeding 600 ℃ may undesirably modify the doping profile of the bottom transistor, thereby undesirably altering its threshold voltage and/or drive current (I _on).

To address these challenges, the present disclosure provides p-dipole dopants that can be driven into an adjacent layer (such as a gate dielectric layer) at low temperatures, and thus provide low temperature threshold voltage adjustment of the transistor. Exemplary p-dipole dopants disclosed herein include titanium (Ti) having a corresponding drive-in temperature of less than 600 ℃, such as a drive-in temperature of about 300 ℃ to about 500 ℃. The proposed p-dipole dopants are particularly advantageous for stacked device structures, such as CFETs, because they can provide multiple threshold voltage adjustments of the top device of the stacked device structure with minimal impact on the electrical and/or structural characteristics of the already fabricated bottom device of the stacked device structure. In addition, the electrical and/or structural characteristics of the top device may be improved by minimizing its exposure to high temperatures (such as those exceeding 600 ℃). Furthermore, in some embodiments, by incorporating the disclosed p-dipole materials, multiple threshold voltages can be flexibly provided for both p-type and n-type transistors, even with the same work function metal. This may avoid the need to pattern work function metals, making the disclosed low temperature dipole engineering process well suited for nano-sized transistors, such as FinFET and GAA transistors. Details of an improved gate stack for stacking transistors in a transistor structure and methods of making and/or designing the same are described in the following pages. Different embodiments may have different advantages, and no particular advantage is required for any embodiment.

Fig. 2 is a flow chart of a method 100 for fabricating a gate stack of a transistor in a stacked transistor structure, such as a top transistor of the stacked transistor structure, in accordance with various aspects of the present disclosure. Fig. 3A-11A and 3B-11B are various views of a transistor (such as transistor 18B of stacked transistor structure 10 of fig. 1) at various stages of fabrication, either partially or entirely, associated with method 100 of fig. 2, in accordance with various aspects of the present disclosure. The cross-sectional views of fig. 3A to 11A and 3B to 11B are taken (cut) along the gate lateral direction (e.g., x-direction) and the gate longitudinal direction (e.g., y-direction), respectively, and thus, the cross-sectional views may be referred to as an x-cut view and a y-cut view, respectively. Fig. 12 illustrates an exemplary dipole dopant profile of a gate dielectric of a transistor (such as transistor 18B) after dipole engineering in connection with fig. 7A-9A and 7B-9B, in accordance with aspects of the present disclosure. For ease of description and understanding, fig. 2, 3A-11A, 3B-11B, and 12 are discussed herein simultaneously. For clarity, fig. 2, 3A-11A, 3B-11B, and 12 have been simplified to better understand the inventive concepts of the present disclosure. Additional steps may be provided before, during, and after the method 100, and some of the steps described may be moved, replaced, or eliminated for additional embodiments of the method 100. Additional components may be added in the transistor 18B of fig. 3A-11A and 3B-11B, and some components described below may be replaced, modified, or eliminated in other embodiments of the transistor 18B of fig. 3A-11A and 3B-11B.

Turning to fig. 2, 3A, and 3B, the method 100 includes forming a gate structure over a channel layer in block 105. The gate structure includes a dummy gate and a gate spacer. This may include receiving and/or forming device precursors including substrate (wafer) 202, channel layer 210 (depicted as having mesas 202' (i.e., patterned protruding portions of substrate 202), semiconductor layer 215 and semiconductor layer 220), isolation feature 222, internal spacers 24B, epitaxial source/drain 25B, gate structure 30B (depicted as having dummy gate 230 and gate spacer 40B), and dielectric layer 250. The channel layer 210 is located in the channel region C and the epitaxial source/drain 25B is located in the source/drain region S/D. Mesa 202' of semiconductor layer 220 and channel layer 210 extends in the x-direction between epitaxial source/drain 25B, and internal spacer 24B is located between semiconductor layer 215 and epitaxial source/drain 25B. The gate structure 30B is disposed over the channel layer 210 and between the epitaxial source/drain 25B. In the X-Z plane, the gate structure 30B is located on top of the channel layer 210. In the Y-Z plane, the gate structure 30B is located on the top and sides of the channel layer 210. For example, the gate structure 30B wraps around the channel layer 210 in the Y-Z plane.

The substrate 202 includes: elemental semiconductors such as silicon and/or germanium; a compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, indium antimonide, or a combination thereof; an alloy semiconductor such as SiGe, gaAsP, alInAs, alGaAs, gaInAs, gaInP, gaInAsP or a combination thereof; or a combination thereof. In the depicted embodiment, the substrate 202 is a silicon substrate. In some embodiments, the substrate 202 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. The substrate 202 (and mesa 202') may include various doped regions, such as p-type doped regions (e.g., p-wells), n-type doped regions (e.g., n-wells), or a combination thereof. The n-doped region includes an n-type dopant such as phosphorus, arsenic, other n-type dopants, or combinations thereof. The p-type doped region includes a p-type dopant such as boron, indium, other p-type dopants, or combinations thereof. In some embodiments, the doped region includes a combination of p-type dopants and n-type dopants. The doped regions may be formed directly on and/or in the substrate 202, for example, providing a p-well structure, an n-well structure, a double-well structure, a raised structure, other suitable structures, or combinations thereof. In some embodiments, the substrate 202, mesa 202', and the semiconductor layer thereabove include an n-well (such as in the case where transistor 18B is a p-type transistor) or a p-well (such as in the case where transistor 18B is an n-type transistor).

The channel layer 210 extends in the x-direction, having a length in the x-direction, a width in the y-direction, and a height in the z-direction. Semiconductor layer 215 and semiconductor layer 220 are vertically stacked (e.g., in the z-direction) from the top surface of substrate 202 in an alternating and/or alternating configuration. The composition of semiconductor layer 215 is different from the composition of semiconductor layer 220 to achieve etch selectivity and/or different oxidation rates during subsequent processing. Semiconductor layer 215 and semiconductor layer 220 comprise different materials, atomic percentages of components, weight percentages of components, thicknesses, or combinations thereof to achieve a desired etch selectivity during an etching process, such as performing an etching process to form a floating channel layer in channel region C. For example, semiconductor layer 215 comprises silicon germanium, semiconductor layer 220 comprises silicon, and the silicon etch rate of semiconductor layer 220 is different from the silicon germanium etch rate of semiconductor layer 215 for a given etchant. In some embodiments, semiconductor layer 215 and semiconductor layer 220 comprise the same material but different atomic percentages of the components to achieve etch selectivity. For example, semiconductor layer 215 and semiconductor layer 220 include silicon germanium having different silicon atomic percentages and/or different germanium atomic percentages. The present disclosure contemplates semiconductor layer 215 and semiconductor layer 220 comprising any combination of semiconductor materials that provide a desired etch selectivity, a desired oxidation rate differential, a desired performance characteristic (e.g., a material that maximizes current flow), or a combination thereof, including any semiconductor materials disclosed herein.

The isolation feature 222 electrically isolates the active device regions and/or the inactive device regions of the device from each other. For example, isolation feature 222 separates and electrically isolates the active region of transistor 18B (e.g., channel layer 210 and/or its epitaxial source/drain 25B) from other device regions and/or devices. The isolation feature 222 comprises silicon oxide, silicon nitride, silicon oxynitride, other suitable isolation materials (including, for example, silicon, oxygen, nitrogen, carbon, other suitable isolation components, etc.), or combinations thereof. The spacer member 222 may have a multi-layered structure. For example, isolation feature 222 includes a bulk dielectric (e.g., an oxide layer) over a dielectric liner (including, for example, silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbonitride, or a combination thereof). In another example, the isolation feature 222 includes a dielectric layer over a doped liner, such as a borosilicate glass (BSG) liner and/or a phosphosilicate glass (PSG) liner. The dimensions and/or characteristics of the isolation feature 222 are configured to provide Shallow Trench Isolation (STI) structures, deep Trench Isolation (DTI) structures, local oxidation of silicon (LOCOS) structures, other suitable isolation structures, or combinations thereof. In the depicted embodiment, the isolation feature 222 may be an STI.

The inner spacer 24B is disposed under the gate spacer 40B and along the sidewalls of the semiconductor layer 215. The internal spacers 24B are disposed between the semiconductor layer 215 and the epitaxial source/drain electrodes 25B and separate the semiconductor layer 215 and the epitaxial source/drain electrodes 25B. The inner spacers 24B are further disposed between adjacent semiconductor layers 220 and between the bottommost semiconductor layer 220 and the mesa 202'. The inner spacer 24B comprises a dielectric material comprising silicon, oxygen, carbon, nitrogen, other suitable components, or combinations thereof, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbonitride, and the like. In some embodiments, the inner spacer 24B comprises a low-k dielectric material. In some embodiments, dopants (e.g., p-type dopants, n-type dopants, or combinations thereof) are introduced into the dielectric material, and the inner spacers 24B comprise a doped dielectric material.

The epitaxial source/drain 25B comprises a semiconductor material and may be doped with n-type dopants and/or p-type dopants. When forming part of a p-type transistor, such as in the depicted embodiment, the epitaxial source/drain 25B may comprise silicon germanium or germanium doped with boron, other p-type dopants, or a combination thereof. When forming part of an n-type transistor, the epitaxial source/drain 25B may comprise silicon doped with carbon, phosphorus, arsenic, other n-type dopants, or combinations thereof. The epitaxial source/drain 25B may comprise more than one semiconductor layer, wherein the semiconductor layers comprise the same or different materials and/or the same or different dopant concentrations. The epitaxial source/drain 25B may include materials and/or dopants that achieve the desired tensile and/or compressive stress in the channel region C. In some embodiments, doped regions, such as heavily doped source/drain (HDD) regions, lightly doped source/drain (LDD) regions, other doped regions, or combinations thereof, are provided in epitaxial source/drain 25B. In some embodiments, doped regions, such as LDD regions, may extend into channel region C. As used herein, source/drain regions, epitaxial source/drains, epitaxial source/drain features, etc. may refer to sources of transistors and/or devices, drains of transistors and/or devices, or sources and/or drains of a plurality of devices (e.g., including transistor 18B and/or device 12B).

The dummy gate 230 extends longitudinally in a direction different from (e.g., orthogonal to) the longitudinal direction of the channel layer 210. For example, the dummy gate 230 longitudinally extends in the y-direction, having a length in the y-direction, a width in the x-direction, and a height in the z-direction. In the X-Z plane, dummy gate 230 is disposed on top of channel layer 210. In the Y-Z plane, dummy gate 230 is disposed over the top and sidewalls of channel layer 210 such that dummy gate 230 wraps around channel layer 210. Dummy gate 230 may include a dummy gate electrode and a dummy gate dielectric. The dummy gate electrode comprises a suitable dummy gate material and the dummy gate dielectric comprises a suitable dielectric material. For example, the dummy gate electrode comprises polysilicon (i.e., a poly gate), and the dummy gate dielectric comprises silicon oxide (i.e., a dummy oxide). Dummy gate 230 may include additional layers such as a hard mask layer, a capping layer, an interface layer, a diffusion layer, a barrier layer, other suitable layers, or combinations thereof.

Gate spacer 40B is adjacent to the sidewalls of dummy gate 230 and along the sidewalls of dummy gate 230. Gate spacer 40B may include a seal spacer, an offset spacer, a sacrificial spacer, a dummy spacer, a main spacer, other suitable spacers, or a combination thereof. The gate spacer 40B may have a single-layer structure or a multi-layer structure. The gate spacer 40B comprises a dielectric material that may include silicon, oxygen, carbon, nitrogen, other suitable components, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, and the like). For example, the gate spacer 40B may include silicon, oxygen, nitrogen, carbon, and hydrogen (i.e., the gate spacer 40B is SiONCH layers).

A dielectric layer 250 is disposed over the substrate 202, the isolation feature 222, the epitaxial source/drains 25B, and the gate structure 30B. The dielectric layer 250 may have a multi-layer structure such as ILD layer 252 over CESL 45B. ILD layer 252 comprises a dielectric material comprising, for example, silicon oxide, carbon doped silicon oxide, silicon nitride, silicon oxynitride, tetraethyl orthosilicate (TEOS) formed oxide, BSG, PSG, borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), silicon nitride oxide, or silicon oxynitride,(Applied materials of santa clara, california), xerogels, aerogels, amorphous fluorocarbons, parylenes, benzocyclobutenyl (BCB) dielectric materials, siLK (dow chemical company of midland, michigan), polyimides, other suitable dielectric materials, or combinations thereof. In some embodiments, ILD layer 252 comprises a dielectric material having a dielectric constant less than that of silicon dioxide (e.g., k < 3.9). In some embodiments, ILD layer 252 comprises a dielectric material having a dielectric constant of less than about 2.5 (i.e., an extremely low k dielectric material), such as porous silicon oxide, silicon carbide, carbon doped oxide (e.g., siCOH based material (having, for example, si-CH ₃ bonds)), or a combination thereof, each of which is tuned/configured to have a dielectric constant of less than about 2.5. CESL 45B includes a dielectric material that is different from the dielectric material of ILD layer 252. For example, where ILD layer 252 comprises a low-k dielectric material (e.g., porous silicon oxide), CESL 45B may comprise silicon and nitrogen, such as silicon nitride, silicon carbonitride, or silicon oxynitride.

In some embodiments, the device precursor is received before and/or after the dielectric layer 250 is formed. Forming the dielectric layer 250 may include depositing a dielectric material over the substrate 202, the isolation features 222, the epitaxial source/drains 25B, and the gate structure 30B, and performing a planarization process, such as Chemical Mechanical Polishing (CMP), on the dielectric material. The planarization process removes any dielectric material from over gate structure 30B. The dummy gate 230 may serve as a planarization stop layer, and a planarization process may be performed until the dummy gate 230 is reached. The planarization process may planarize the top surface of the dielectric layer 250 and the top surface of the gate structure 30B. In some embodiments, the dielectric layer 250 is a device-level dielectric layer of a multilayer interconnect (MLI) component that electrically connects devices (e.g., transistors, resistors, capacitors, inductors, etc.), components of devices (e.g., gates and/or source/drains), devices within the MLI component, components of the MLI component, or combinations thereof, such that the devices and/or components may operate as specified by design requirements.

Turning to fig. 2, 4A, and 4B, the method 100 includes removing the dummy gate 230 to form a gate opening 255 exposing the channel layer 210 in block 110. The gate opening 255 has sidewalls formed by the gate spacer 40B and a bottom formed by the channel layer 210 and/or the isolation feature 222. In some embodiments, the etching process selectively removes dummy gate 230 relative to gate spacer 40B, dielectric layer 250, or a combination thereof. For example, the etching process substantially removes dummy gate 230, but does not remove or substantially does not remove gate spacer 40B, isolation feature 222, dielectric layer 250, and the like. In some embodiments, an etchant is selected for the etching process that etches the polysilicon (i.e., dummy gate 230) at a higher rate than the dielectric material (i.e., gate spacer 40B, dielectric layer 250, etc.) (i.e., the etchant has a high etch selectivity relative to the polysilicon). The etching process is a dry etch, a wet etch, other suitable etches, or a combination thereof. In some embodiments, a patterned masking layer (etch mask) covers and protects dielectric layer 250 and/or gate spacers 40B, but exposes dummy gate 230 during the etching process.

Turning to fig. 2, 5A, and 5B, the method 100 may include performing a channel release process in block 115. For example, the semiconductor layer 215 exposed by the gate opening 255 is selectively removed to form an air gap 260 between the semiconductor layers 220 and the mesa 202', thereby floating the semiconductor layers 220 in the channel region C. In the depicted embodiment, two floating semiconductor layers 220 are vertically stacked in the z-direction and provide two channels through which current can flow between the epitaxial source/drain 25B. Accordingly, the floating semiconductor layer 220 is hereinafter referred to as a channel layer 20B. In embodiments where stacked device structure 10 is formed from a FinFET, planar transistor, or other type of transistor, such as where transistor 18B may be a FinFET, the channel release process may be omitted from method 100.

In some embodiments, the channel release process includes an etching process that selectively etches the semiconductor layer 215 with minimal etching to the absence of etching of the semiconductor layer 220, the mesa 202', the gate spacer 40B, the inner spacer 24B, the isolation feature 222, the dielectric layer 250, or a combination thereof. In some embodiments, an etchant is selected for the etching process that etches silicon germanium (i.e., semiconductor layer 215) at a higher rate than silicon (i.e., semiconductor layer 220) and dielectric material (i.e., gate spacers 40B, internal spacers 24B, isolation feature 222, dielectric layer 250, etc.) (i.e., the etchant has a high etch selectivity relative to silicon germanium). The etching process is a dry etch, a wet etch, other suitable etching process, or a combination thereof. In some embodiments, the oxidation process converts the semiconductor layer 215 into semiconductor oxide features (e.g., silicon germanium oxide) before the etching process is performed, and then the etching process removes the semiconductor oxide features. In some embodiments, during and/or after removing semiconductor layer 215, an etching process is performed to modify the profile of semiconductor layer 220 to achieve a target size and/or target shape for channel layer 20B, such as a cylindrical channel layer (e.g., nanowires), a rectangular channel layer (e.g., nanorods), a sheet-shaped channel layer (e.g., nanoplatelets), and so forth.

Turning to fig. 2, 6A-11A, and 6B-11B, the method 100 includes forming a gate stack in the gate opening 255 in block 120. The gate stack includes a gate dielectric 32B (e.g., at least one dielectric gate layer, such as a high-k dielectric layer) and a gate electrode 34B (e.g., at least one conductive gate layer, such as a work function layer and/or a bulk metal layer). The gate stack fills the gate opening 255 and, in the depicted embodiment, fills the air gap 260 (see fig. 11A and 11B). For example, a gate stack is disposed between the channel layer 20B and the mesa 202'. In the X-Z plane (fig. 11A), gate stacks are disposed between gate spacers 40B and between inner spacers 24B. In the Y-Z plane (fig. 11B), the gate stack at least partially surrounds (e.g., encloses) the channel layer 20B. The gate stack may include many other layers such as capping layers, interfacial layers, diffusion layers, barrier layers, hard mask layers, or combinations thereof. The gate stack and gate spacers 40B are collectively referred to as gate structure 30B.

Referring to fig. 2, 6A, and 6B, the method 100 includes forming a gate dielectric 32B in the gate opening 255 and over the channel layer 20B in block 125. In the depicted embodiment, gate dielectric 32B includes an interfacial layer 36B 'and a gate dielectric layer 38B'. The interfacial layer 36B ' partially fills the gate opening 255 (including the air gap 260) and is formed on the semiconductor surface such that the interfacial layer 36B ' is located between the channel layer 20B and the gate dielectric layer 38B ' and between the mesa 202' and the gate dielectric layer 38B '. In the X-Z plane, interface layer 36B 'covers the top surface of channel layer 20B, the bottom surface of channel layer 20B, and the top surface of mesa 202'. In the Y-Z plane, interfacial layer 36B 'surrounds channel layer 20B and covers the top surface of mesa 202'. The interface layer 36B' is formed by thermal oxidation, chemical oxidation, atomic Layer Deposition (ALD), chemical Vapor Deposition (CVD), other suitable processes, or combinations thereof.

The interface layer 36B' includes a dielectric material such as SiO ₂、SiGeO_x, hfSiO, siON, other dielectric material, or combinations thereof. In some embodiments, the interface layer 36B' is a group IV-based oxide layer, which generally refers to an oxide based material of group IV (i.e., a material that includes at least one group IV element such as Si, ge, C, etc.). In some embodiments, the interface layer 36B' is a group III-V based oxide layer, which generally refers to an oxide of a group III-V based material (i.e., a material including at least one group III element (such as Al, ga, in, B, etc.) and at least one group V element (such as N, P, as, sb, etc.). The thickness of interface layer 36B 'is less than the thickness of gate dielectric layer 38B'. In some embodiments, the thickness of the interface layer 36B' is about 0.5nm to about 2nm. In the depicted embodiment, the interface layer 36B' has a substantially uniform thickness.

Gate dielectric layer 38B 'partially fills gate opening 255 (including air gap 260) and is formed over interface layer 36B', gate spacers 40B, inner spacers 24B, isolation feature 222, and dielectric layer 250. In the X-Z plane, gate dielectric layer 38B' has a u-shaped profile in the top portion of gate opening 255. In the Y-Z plane, gate dielectric layer 38B' surrounds channel layer 20B. The gate dielectric layer 38B' has a substantially uniform thickness. In some embodiments, the gate dielectric layer 38B' has a thickness of about 1nm to about 5nm. The gate dielectric layer 38B' is formed by ALD, CVD, physical Vapor Deposition (PVD), an oxide-based deposition process, other suitable process, or combinations thereof.

The gate dielectric layer 38B' comprises a high-k dielectric material, which generally refers to a dielectric material having a dielectric constant greater than that of silicon dioxide (k≡3.9), such as HfO₂、HfSiO、HfSiO₄、HfSiON、HfLaO、HfTaO、HfTiO、HfZrO、HfAlO_x、ZrO、ZrO₂、ZrSiO₂、AlO、AlSiO、Al₂O₃、TiO、TiO₂、LaO、LaSiO、LaO₃、La₂O₃、Ta₂O₃、Ta₂O₅、Y₂O₃、SrTiO₃、BaZrO、BaTiO₃(BTO)、(Ba、Sr)TiO₃(BST)、Si₃N₄、HfO₂-Al₂O₃、 other high-k dielectric materials or combinations thereof. For example, the gate dielectric layer 38B' is a hafnium-based oxide (e.g., hfO ₂) layer or a zirconium-based oxide (e.g., zrO ₂) layer. In some embodiments, the gate dielectric layer 38B' has a multi-layer structure.

Referring to fig. 2, 7A-9A, and 7B-9B, dipole engineering is performed after forming gate dielectric 32B to modulate the threshold voltage of transistor 18B. For example, the processes associated with blocks 130, 135, and 140 of method 100 may form a dipole in gate dielectric 32B that shifts the threshold voltage of transistor 18B. Dipoles may be formed at the interface of gate dielectric layer 38B 'and interface layer 36B' (i.e., at the high-k/interfacial interface of the gate stack) and the processing parameters associated with blocks 130, 135, and 140 of method 100 may be adjusted to achieve a desired threshold voltage shift in transistor 18B and/or to achieve a desired threshold voltage characteristic of transistor 18B. In the depicted embodiment, p-dipole dopants are incorporated into gate dielectric 32B to change (e.g., decrease) the threshold voltage of transistor 18B, with transistor 18B configured as a p-type transistor. As described below, the disclosed dipole engineering technique is a low temperature, threshold voltage adjustment process that is particularly advantageous when fabricating stacked transistor structures.

Referring to fig. 2, 7A, and 7B, the method 100 includes forming a dipole dopant source 265 over the gate dielectric 32B in block 130. A dipole dopant source layer 265 is formed on the gate dielectric layer 38B' and partially fills the gate opening 255 (including the air gap 260). In the X-Z plane, the dipole dopant source layer 265 overlies the gate dielectric layer 38B' and has a u-shaped profile in the top portion of the gate opening 255. In the Y-Z plane, the dipole dopant source layer 265 overlies the gate dielectric layer 38B' and surrounds the channel layer 20B. In some embodiments, the dipole dopant source 265 fills the air gaps 260. The dipole dopant source 265 is formed by ALD, CVD, other suitable processes, or combinations thereof.

The dipole dopant source 265 is a dielectric layer comprising a p-dipole dopant that can be driven into the gate dielectric 32B to change the threshold voltage of the transistor 18B. For example, the dipole dopant source 265 includes a p-dipole dopant (e.g., metal) and oxygen, nitrogen, carbon, or a combination thereof (e.g., non-metal). As noted above, when the stacked transistor structure is fabricated using a sequential fabrication scheme, the bottom transistor (e.g., transistor 18A) is subjected to a process for fabricating the top transistor (e.g., transistor 18B), including its thermal process. Challenges arise when using high temperatures to fabricate the top transistor. For example, when an aluminum oxide layer (e.g., an AlO layer) is implemented as a p-dipole dopant source layer for threshold voltage adjustment, aluminum is a p-dipole dopant and a thermal drive-in temperature of at least 600 ℃ (e.g., 700 ℃) is typically required to drive (diffuse) the aluminum into the underlying gate dielectric and provide the desired threshold voltage modulation. But such high temperatures (i.e., greater than 600 ℃) may adversely affect the electrical performance and/or reliability of the bottom transistor, for example, by undesirably modifying the doping profile of the bottom transistor, thereby undesirably altering its threshold voltage and/or drive current (I _on). Thus, the electrical performance and/or reliability of the bottom transistor is reduced due to the top transistor fabrication.

The present dipole engineering technique overcomes such challenges by incorporating p-dipole dopants into the dipole dopant source 265, which can be driven into the gate dielectric at low temperatures while providing high voltage threshold tunability. For example, the dipole dopant source 265 comprises an oxide, nitride, carbide, or combination thereof of a p-dipole dopant that may be driven/diffused into the gate dielectric 32B using a drive-in temperature of less than 600 ℃. In some embodiments, the p-dipole dopant is titanium and the dipole dopant source 265 comprises titanium and oxygen, nitrogen, carbon, or a combination thereof. For example, the dipole dopant source layer 265 may be a titanium oxide layer, a titanium nitride layer, or a titanium carbide layer. Incorporating titanium into gate dielectric 32B may provide a larger threshold voltage adjustment window, and thus a larger threshold voltage increase, at low temperatures than incorporating aluminum into gate dielectric 32B. For example, a titanium oxide layer provides a larger threshold voltage increase than an aluminum oxide layer, and thus titanium is particularly useful as a p-dipole dopant for low temperature threshold voltage adjustment. Such differences in threshold voltage modulation may occur when compared to aluminum because the incorporation of titanium into gate dielectric 32B may provide a high-k/interfacial interface having a dipole moment that is greater than the dipole moment of the high-k/interfacial interface into which aluminum and/or other factors are incorporated.

In some embodiments, the dipole dopant source 265 includes a p-dipole dopant that can be driven into the gate dielectric 32B at a temperature below 600 ℃ to increase the threshold voltage of the transistor 18B (e.g., a p-type transistor). In some embodiments, to ensure minimal impact on other device components and/or devices (e.g., bottom transistors), p-dipole dopants that diffuse into gate dielectric 32B with a thermal drive-in temperature of less than about 500 ℃ (such as about 300 ℃ to about 500 ℃) may be used for threshold voltage modification, such as titanium. In some embodiments, the dipole dopant source 265 is an oxide of titanium (e.g., a TiO layer) that can diffuse into the gate dielectric 32B with a thermal drive-in temperature of about 300 ℃ to about 500 ℃. In embodiments where transistor 18B is configured as an n-type transistor, low temperature driving of the disclosed p-dipole dopant into gate dielectric 32B may reduce the threshold voltage of transistor 18B. The present disclosure also contemplates other p-dipole dopants other than titanium, so long as such p-dipole dopants can be driven into gate dielectric 32B at a temperature below 600 ℃.

The dipole dopant source 265 has a substantially uniform thickness. In some embodiments, the thickness of the dipole dopant source 265 is about 0.3nm to about 1.5nm. If the dipole dopant source 265 is too thin (such as less than 0.3 nm), it may unevenly cover the gate dielectric 32B, which may affect the uniformity of the dipole engineering of the gate dielectric 32B and/or the uniformity of the threshold voltage adjustment of the transistor 18B (i.e., uneven threshold voltage adjustment may occur). If the dipole dopant source 265 is too thick (such as greater than 1.5 nm), it may be difficult to remove and thus undesirably remain in the gate stack. For example, if too thick, a residue of the dipole dopant source 265 may remain between the channel layers 20B such that the air gaps 260 remain partially filled by the dipole dopant source 265. This may affect subsequent fabrication, for example, by leaving insufficient space for gate electrodes (such as work function metal and/or bulk metal layers) to fill gate openings 255 and/or to cause transistor 18B to have different electrical characteristics (e.g., different threshold voltages) than intended. Further, the composition and thickness of the dipole dopant source 265 may be designed based on a desired threshold voltage adjustment amount. For example, thicker dipole dopant source 265 may provide greater threshold voltage variation (e.g., greater threshold voltage reduction) in transistor 18B. In some embodiments, using the disclosed p-dipole dopant materials (such as TiO) and the disclosed thicknesses, the threshold voltage of transistor 18B may be adjusted down (when configured as a p-type transistor) or up (when configured as an n-type transistor) from about 30mV to about 180mV. In some embodiments, the dipole dopant source layer 265 has a multi-layer structure in which the composition and thickness of each layer may be designed to achieve a desired threshold voltage adjustment.

Referring to fig. 2, 8A and 8B, the method 100 includes performing a thermal drive-in process 270 in block 135, the thermal drive-in process 270 driving (diffusing) dopants from the dipole dopant source 265 into the gate dielectric 32B. For example, the thermal drive-in process 270 drives p-dipole dopants from the dipole dopant source layer 265 into the gate dielectric 32B, such as into the gate dielectric layer 38B 'and/or the interface layer 36B'. The drive-in temperature of the thermal drive-in process 270 is less than 600 ℃, such as about 300 ℃ to about 500 ℃. The thermal drive-in process 270 may be an annealing process such as Rapid Thermal Annealing (RTA), millisecond annealing (MSA), microsecond annealing (SA), microwave annealing, laser annealing, spike annealing, soaking annealing, furnace annealing, other suitable annealing processes, or combinations thereof. In some embodiments, the thermal drive-in process 270 is performed in an inert gas environment, including, for example, argon (Ar), helium (He), nitrogen (N ₂), other inert gases, or combinations thereof. For example, the thermal drive-in process 270 may be an annealing process performed in an environment of N ₂, ar, he, or mixtures thereof at a temperature of about 300 ℃ to about 500 ℃ for about 10 seconds to about 180 seconds. The disclosed thermal drive-in temperature ensures that the thermal drive-in process 270 does not adversely affect the existing structures and components of transistor 18B and/or the stacked transistor structure to which transistor 18B belongs, such as transistor 18A, and is also sufficient to cause the p-dipole dopant to migrate (or diffuse) into gate dielectric 32B.

After the thermal drive-in process 270, the gate dielectric layer 38B ' becomes the gate dielectric layer 38B (i.e., doped gate dielectric layer) as the p-dipole dopant is driven into the gate dielectric layer 38B ' and/or the interfacial layer 36B ', as depicted in fig. 9A and 9B. For example, gate dielectric layer 38B is a high-k dielectric layer including titanium, such as a hafnium-based oxide (e.g., hfO ₂) layer or a zirconium-based oxide (e.g., zrO ₂) layer. In some embodiments, the p-dipole dopant also diffuses into the interface layer 36B ', such that the interface layer 36B' becomes the interface layer 36B (i.e., a doped interface layer), as depicted in fig. 9A and 9B. For example, interface layer 36B may be a dielectric layer further comprising titanium, such as a group IV-based oxide (e.g., siO ₂) layer or a group III-V-based oxide layer. In some embodiments, gate dielectric layer 38B and/or interface layer 36B are substantially free of aluminum (i.e., no aluminum is included in gate dielectric 32B).

Referring to fig. 2, 9A, and 9B, the method 100 includes removing the dipole dopant source 265 in block 140. By removing the dipole dopant source 265, the disclosed low temperature dipole engineering process provides bulk-free threshold voltage adjustment. In other words, the low temperature dipole engineering process may modulate the threshold voltage of transistor 18B by driving p-dipole dopants into gate dielectric 32B, but the material layers used for such threshold voltage modulation do not remain and therefore do not consume any volume of the final gate stack, thereby maximizing the size of gate opening 255 and/or air gap 260 for subsequent gate electrode formation. In some embodiments, the etching process selectively removes the dipole dopant source 265 relative to the gate dielectric layer 38B. For example, the etching process substantially removes the dipole dopant source 265, but does not remove or substantially does not remove the gate dielectric layer 38B. In some embodiments, an etchant is selected for the etching process that etches the dipole dopant source layer 265 (e.g., a TiO layer or another dielectric layer comprising titanium) at a higher rate than the gate dielectric layer 38B (e.g., a HfO ₂ layer, a ZrO ₂ layer, or another high-k dielectric material comprising titanium). The etching process is a dry etch, a wet etch, other suitable etches, or a combination thereof.

As shown in the enlarged view of the portion of gate dielectric 32 corresponding to block region 272 in fig. 9B, p-dipole dopant 275 diffuses into the interior portion of gate dielectric layer 38B (i.e., toward and/or near interface layer 36B). In the depicted embodiment, the p-dipole dopants 275 are distributed in the gate dielectric layer 38B and the interface layer 36B along an interface IF between the gate dielectric layer 38B and the interface layer 36B (i.e., along a high-k/interfacial interface). Thus, gate dielectric 32B has a doped interface region DIFR that includes portions of gate dielectric layer 38B and portions of interface layer 36B. In some embodiments, the thickness of the doped interface region DIFR (i.e., where the p-dipole dopant is distributed in the gate dielectric 32B) is aboutTo/>If the thickness is too small (such as less than about/>)) Any voltage threshold modification provided by the p-dipole dopant (i.e., the threshold voltage adjustment effect of the p-dipole dopant) of transistor 18B may be negligible and/or too weak. If the thickness is too great (such as greater than about) The threshold voltage adjustment effect of the p-dipole dopant may be too strong and produce undesirable side effects such as reduced mobility in the channel layer 20B.

The thickness of the gate dielectric layer 38B 'is designed such that the p-dipole dopant can effectively penetrate the gate dielectric layer 38B' to the high-k/interfacial interface IF. Further, the composition and/or thickness of the dipole dopant source 265, the composition and/or thickness of the gate dielectric layer 38B', and the parameters of the thermal drive-in process 270 (e.g., drive-in temperature, time, ambient, pressure, etc.) may be configured to provide a doped interface region DIFR having a desired dipole dopant profile along the thickness T (fig. 12) of the gate dielectric 32B. Turning to fig. 12, the doped interface region DIFR has a bell-shaped dipole dopant profile a extending from a depth d1 in the gate dielectric 32B (located in the gate dielectric layer 38B) to a depth d3 in the gate dielectric 32B (located in the interface layer 36B) and crossing the high-k/interfacial interface IF at a depth d2. For example, the concentration of the p-dipole dopant increases from the dopant concentration c1 at the depth d1 to the dopant concentration c2 at the depth d2 (this is the peak, maximum dopant concentration), and then decreases from the dopant concentration c2 at the depth d2 to the dopant concentration c1 at the depth d3. The peak of the dipole dopant profile a of the doped interface region DIFR is therefore located at the high-k/interfacial interface IF and corresponds to the location in the gate dielectric 32B having the highest dipole dopant concentration. In such an example, the p-dipole dopants are uniformly distributed in the gate dielectric layer 38B and the interface layer 36B. In some embodiments, the dopant concentration at depth d1 and the dopant concentration at depth d3 are different.

To maximize the threshold voltage tuning effect of the p-dipole dopant, the dipole dopant profile of the doped interface region DIFR peaks at + -0.5nm at the high-k/interfacial interface IF. In other words, in the depicted embodiment, the peak of the dipole dopant profile is located at a depth d2+ -0.5nm, and the location of the peak of the dipole dopant profile may be between a first depth and a second depth, wherein the difference between the first depth and the second depth is about 1nm (i.e., the location of the peak of the dipole dopant profile may be along a depth range (Δd) less than about 1 nm.) for example, the dopant interface region DIFR may have a bell-shaped dipole dopant profile B similar to the dipole dopant profile A except that it is shallower in the gate dielectric 32B than the dipole dopant profile A such that the peak of the dipole dopant profile B is located at a depth d2-0.5nm in the gate dielectric 38B. In such an example, the p-dipole dopant is primarily distributed in the gate dielectric 38B. In another example, the dopant interface region DIFR may have a bell-shaped dopant profile C similar to the dipole dopant profile A except that it is deeper in the gate dielectric 32B than the dipole dopant profile A such that the peak C is not located at a substantial threshold at a depth d2-0.5nm or any such that the dipole dopant profile is substantially deeper than the interface threshold is provided.

Referring to fig. 2, 10A, 10B, 11A, and 11B, in block 145 of method 100, a gate electrode 34B is formed over gate dielectric 32B. The gate electrode 34B fills the remainder of the gate opening 255 and the gate electrode 34B includes at least one conductive gate layer. The conductive gate layer includes a conductive material, such as Al, cu, ti, ta, W, mo, co, taN, niSi, coSi, tiN, WN, tiAl, tiAlN, taCN, taC, taSiN, other conductive materials, or a combination thereof.

Referring to fig. 10A and 10B, in some embodiments, forming the gate electrode 34B may include: depositing a work function layer 280 over the gate dielectric 32B; depositing a barrier layer 282 over the work function layer 280; and a bulk (fill) layer 284 is deposited over the barrier layer 282. The work function layer 280 partially fills the gate opening 255, the blocking layer 282 partially fills the gate opening 255, and the bulk layer 284 fills the remainder of the gate opening 255. In fig. 10B, the work function layer 280 fills the remainder of the air gap 260. In some embodiments, the work function layer 280 and the barrier layer 282 and/or bulk layer 284 fill the remainder of the air gap 260. The work function layer 280 and the barrier layer 282 have a substantially uniform thickness. In some embodiments, each layer of gate electrode 34B (here, work function layer 280, barrier layer 282, and bulk layer 284) has a thickness of about 0.5nm to about 5 nm. Work function layer 280, barrier layer 282, and bulk layer 284 may be formed by ALD, PVD, CVD, high-density plasma CVD (HDPCVD), metal-organic CVD (MOCVD), remote Plasma CVD (RPCVD), plasma Enhanced CVD (PECVD), low Pressure CVD (LPCVD), atomic Layer CVD (ALCVD), atmospheric Pressure CVD (APCVD), other suitable processes, or combinations thereof.

The work function layer 280 is a conductive layer tuned to have a desired work function (such as an n-type work function or a p-type work function), depending on the type of transistor 18B. For example, work function layer 280 may include an n-type work function material in the case where transistor 18B is configured as an n-type transistor, and work function layer 280 may include a p-type work function material in the case where transistor 18B is configured as a p-type transistor. In some embodiments, the work function layer 280 includes Ti、Al、Ag、Mn、Zr、TiC、TiAl、TiAlC、TiAlSiC、TaC、TaCN、TaSiN、TiSiN、TiN、TaN、Ru、Mo、WN、WCN、ZrSi₂、MoSi₂、TaSi₂、NiSi₂、TaAl、TaAlC、TaSiAlC、TiAlN、 other suitable work function metals and/or alloys thereof or combinations thereof. In some embodiments, the work function layer 280 is free of aluminum.

Bulk layer 284 comprises a suitable conductive material such as Al, W, cu, ti, ta, tiN, taN, polysilicon, other suitable metals, and/or alloys thereof, or combinations thereof. For example, bulk layer 284 is a tungsten layer formed by PVD or CVD. In some embodiments, a barrier (blocking) layer 282 is optionally formed (e.g., by ALD) over the work function layer 280 prior to forming the bulk layer 284 such that the barrier layer 282 is disposed between the bulk layer 284 and the work function layer 280. In some embodiments, the barrier layer 282 includes a material that prevents or eliminates diffusion and/or reaction of components between adjacent layers and/or promotes adhesion between adjacent layers, such as between the work function layer 280 and the bulk layer 284. In some embodiments, the barrier layer 282 includes a metal and nitrogen, such as titanium nitride, tantalum nitride, tungsten nitride (e.g., W ₂ N), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), other suitable metal nitrides, or combinations thereof.

Referring to fig. 11A and 11B, a planarization process is performed to remove excess gate material, such as those disposed over dielectric layer 250. For example, a Chemical Mechanical Polishing (CMP) process is performed that removes portions of the bulk layer 284, the barrier layer 282, the work function layer 280, and the gate dielectric layer 38B disposed over the dielectric layer 250. A CMP process is performed until the top surface of dielectric layer 250 is reached (exposed). In some embodiments, the CMP process is continued and the thickness of the dielectric layer 250 is reduced, and correspondingly the height of the gate structure 30B is reduced. In the depicted embodiment, after the CMP process, the top of the gate structure 30B is substantially level with the top of the dielectric layer 250, and the remaining portion of the gate material that fills the gate opening 255 forms a gate stack of the gate structure 30B. As noted above, the gate stack includes gate dielectric 32B (e.g., interface layer 36B and gate dielectric layer 38B) and gate electrode 34B (e.g., bulk layer 284, barrier layer 282, and work function layer 280). Because gate dielectric layer 38B is a high-k dielectric layer, the gate stack may be referred to as a high-k/metal gate. In some embodiments, the process may further include etching back the gate electrode 34B and/or the gate dielectric 32B (i.e., the gate dielectric layer 38B thereof) and forming a hard mask, such as hard mask 42B, of the gate stack over the etched back gate electrode 34B and/or gate dielectric 32B.

As described herein, transistor 18B is fabricated as a GAA transistor (i.e., a transistor having a gate surrounding at least one floating channel (e.g., nanowire, nanoplate, nanorod, etc.), wherein the at least one floating channel extends between a source/drain). The GAA transistor may be a p-type GAA transistor or an n-type GAA transistor. In the depicted embodiment, the transistor 18B is a p-type GAA transistor that includes a channel (e.g., channel layer 20B), source/drain (e.g., epitaxial source/drain 25B), and gate (e.g., a gate stack including gate dielectric 32B and gate electrode 34B). The gate engages a channel extending between the source/drain and during operation, current may flow between the source/drain (e.g., between the source and drain, and vice versa). In the depicted embodiment, the gate is located on top and bottom of the channel in the X-Z plane, and the gate surrounds the channel in the Y-Z plane (e.g., the gate stack is disposed on top, bottom, and sidewalls of the channel layer 20B).

In some embodiments, transistor 18B is fabricated as a FinFET. In such embodiments, the gate stack partially surrounds and/or wraps around the channel. For example, the channel is a portion of the semiconductor fin extending from the substrate 202, the gate stack is located on top of the semiconductor fin in the X-Z plane, and the gate stack wraps around the semiconductor fin in the Y-Z plane (i.e., the gate stack is disposed on top and sidewalls of the semiconductor fin). In such an embodiment, gate dielectric 32B, dipole dopant source 265, and gate electrode 34B are formed over the top and sidewalls of the semiconductor fin.

In some embodiments, transistor 18B is fabricated as a planar transistor. In such embodiments, the gate stack is disposed on one side (e.g., the top surface) of the channel. For example, the channel is part of a semiconductor substrate, and the gate stack is disposed on the top surface of the semiconductor substrate in the X-Z plane and the Y-Z plane. In such an embodiment, gate dielectric 32B, dipole dopant source 265 and gate electrode 34B are formed over the top of the channel region of the semiconductor substrate.

In some embodiments, fabrication of transistor 18B may also include forming individual contacts that may facilitate its operation. For example, one or more dielectric layers similar to dielectric layer 250 may be formed over gate structure 30B and dielectric layer 250. Contacts may then be formed in dielectric layer 250 and/or a dielectric layer disposed over dielectric layer 250. For example, contacts are formed that are physically and/or electrically coupled to the gate stack of gate structure 30B (e.g., gate electrode 34B thereof) and at least one epitaxial source/drain 25B of transistor 18B, respectively. For example, source/drain contacts 50B are formed in dielectric layer 250, and source/drain contacts 50B are disposed on epitaxial source/drain 25B. The contacts comprise a conductive material, such as a metal. The metal includes aluminum, aluminum alloys (such as aluminum/silicon/copper alloys), copper alloys, titanium nitride, tantalum nitride, tungsten, polysilicon, metal silicides, other suitable metals, or combinations thereof. The metal silicide may include nickel silicide, cobalt silicide, tungsten silicide, tantalum silicide, titanium silicide, platinum silicide, erbium silicide, palladium silicide, or combinations thereof. In some embodiments, the dielectric layer and contacts disposed over the dielectric layer 250 (e.g., gate contacts and/or source/drain contacts extending through and/or disposed over the dielectric layer 250) are portions of the MLI feature disposed over the substrate 202.

Fig. 13 is a flow chart of a method 300 for fabricating a stacked device structure, such as stacked device structure 10 of fig. 1, in accordance with aspects of the present disclosure. Fig. 14A-14L are partial cross-sectional views of a portion or an entirety of stacked device structure 10 at various stages of fabrication, such as those associated with method 300, in accordance with various aspects of the present disclosure. In the depicted embodiment, a sequential fabrication scheme (such as a sequential CFET process) is implemented to form stacked device structure 10. For ease of description and understanding, fig. 13 and fig. 14A to 14L are discussed herein simultaneously. Fig. 13 and 14A to 14L have been simplified for clarity to better understand the inventive concepts of the present disclosure. Additional steps may be provided before, during, and after method 300, and some of the steps described may be moved, replaced, or eliminated for additional embodiments of method 300. Additional components may be added to stacked device structure 10, and in other embodiments of stacked device structure 10, some of the components described below may be replaced, modified, or eliminated.

Referring to fig. 13 and 14A-14E, method 300 includes forming a first device of a stacked device structure, such as device 12A of stacked device structure 10, in block 305. In fig. 14A, fabricating device 12A includes depositing semiconductor layer stack 410 '(including semiconductor layer 415 and semiconductor layer 420) over substrate 14, and patterning semiconductor layer stack 410' and optional substrate 14 to form semiconductor fin 412 extending from substrate 14. Semiconductor fin 412 may include patterned portions of semiconductor layer stack 410 '(i.e., semiconductor layer 415 and semiconductor layer 420) and patterned portions of substrate 14 (i.e., mesa 14'). Substrate 14, semiconductor layer 415, and semiconductor layer 420 may be similar to substrate 202, semiconductor layer 215, and semiconductor layer 220, respectively. For example, substrate 14 may be a silicon substrate, semiconductor layer 415 may be a silicon germanium layer, and semiconductor layer 420 may be a silicon layer. In some embodiments, semiconductor layers 415 and 420 are alternately epitaxially grown over substrate 14. In some embodiments, the semiconductor layer stack 410' is patterned using a photolithography process and an etching process. In some embodiments, semiconductor fin 412 is formed by a fin fabrication process. In some embodiments, isolation features are formed over the substrate 14 adjacent to the semiconductor fins 412. The isolation feature may be similar to isolation feature 222. In some embodiments, the isolation feature may be formed by depositing an insulating material over the substrate 14 (e.g., by CVD) and etching back the insulating material such that at least the semiconductor layer stack 410' of the semiconductor fin 412 extends from the isolation feature.

In fig. 14B, manufacturing device 12A may include: forming a gate structure 30A over the channel region of the semiconductor fin 412; forming source/drain recesses 440 in the source/drain regions of the semiconductor fin 412; and forming the inner spacers 24A. In some embodiments, forming gate structure 30A includes: forming at least one dummy gate layer (e.g., a dummy oxide layer, a poly gate layer, and a hard mask layer) over the semiconductor fin 412 and the substrate 14; patterning the at least one dummy gate layer to form a dummy gate 430; and gate spacers 40A are formed along sidewalls of the dummy gate 430. Dummy gate 430 and gate spacer 40A may be similar to dummy gate 230 and gate spacer 40B, respectively. In some embodiments, forming the source/drain recesses 440 may include performing an etching process that selectively removes the semiconductor layer 415 and the semiconductor layer 420 relative to the gate structure 30A, such that the remaining portion of the semiconductor fin 412 forms the channel layer 410 in the channel region. In some embodiments, forming the inner spacer 24A includes: laterally etching the semiconductor layer 415 to form gaps between the semiconductor layers 420 and the mesa 14'; and filling the gap with a dielectric material (e.g., depositing and etching a dielectric layer). The inner spacer 24A may be similar to the inner spacer 24B.

In fig. 14C and 14D, the fabrication of device 12A may further include: forming epitaxial source/drains 25A in source/drain recesses 440 (fig. 14C); and forming a dielectric layer 450 (including CESL 45A and ILD layer 452) over the epitaxial source/drain 25A and gate structure 30A (fig. 14D). The epitaxial source/drain 25A may be similar to the epitaxial source/drain 25B. For example, epitaxial source/drain 25A comprises epitaxial material that is tailored and selected based on the type of device and/or transistor being fabricated. In some embodiments, where transistor 18A is configured as an n-type transistor and transistor 18B is configured as a p-type transistor, epitaxial source/drain 25A may comprise silicon doped with carbon, phosphorus, arsenic, other n-type dopants, or combinations thereof, and epitaxial source/drain 25B may comprise silicon germanium or germanium doped with boron and/or other p-type dopants. Dielectric layer 450, ILD layer 452, and CESL 45A may be similar to dielectric layer 250, ILD layer 252, and CESL 45B, respectively. In some embodiments, forming dielectric layer 450 includes: depositing CESL 45A over epitaxial source/drain 25A and gate structure 30A; and depositing ILD layer 452 over CESL 45A. A planarization process, such as CMP, may be applied to remove dielectric layer 450 from over gate structure 30A.

In fig. 14E, the fabrication of device 12A may also include performing a gate replacement process (i.e., replacing dummy gate 430 with a gate stack including gate dielectric 32A and gate electrode 34A) and performing a channel release process to provide channel layer 20A. In some embodiments, the gate replacement process includes: removing the dummy gate 430 to form a gate opening in the gate structure 30A; depositing a gate dielectric layer partially filling the gate opening; depositing a gate electrode layer filling the remaining portion of the gate opening; and performing a planarization process to remove portions of the gate dielectric layer that are over dielectric layer 450 and/or portions of the gate electrode layer that are over dielectric layer 450. In some embodiments, dipole engineering is performed on the gate dielectric layer. In some embodiments, a channel release process is performed prior to depositing the gate dielectric layer. The channel release process may include: semiconductor layer 415 is selectively removed to float semiconductor layer 420 over substrate 14 to provide channel layer 20A; and gaps are formed in the gate openings between the channel layers 20A and the mesa 14'. The gate dielectric layer and/or the gate electrode layer may fill the gap such that the gate dielectric layer and/or the gate electrode layer may be formed around the channel layer 20A. The gate replacement process and/or the channel release process may be similar to the gate replacement process and/or the channel release process described above. For example, the processes described with reference to fig. 2 (e.g., in blocks 110-145 of method 100), fig. 4A-11A, and fig. 4B-11B may be implemented to form the gate stack (i.e., gate dielectric 32A and gate electrode 34B) and channel layer 20A of gate structure 30A as described in fig. 14E.

Gate dielectric 32A and gate electrode 34A may be similar to gate dielectric 32B and gate electrode 34B, respectively. For example, gate dielectric 32A includes at least one gate dielectric layer (e.g., interface layer 36A and gate dielectric layer 38A), and gate electrode 34A includes at least one conductive layer. In some embodiments, interface layer 36A is a group IV-based oxide layer or a group III-V-based oxide layer, such as a silicon oxide layer. In some embodiments, gate dielectric layer 38A is a high-k dielectric layer, such as a hafnium-based oxide (HfO ₂) layer or a zirconium-based oxide (ZrO ₂) layer. Similar to gate dielectric 32B, during the gate replacement process, dipole engineering is performed on gate dielectric 32A such that gate dielectric 32A also includes an n-dipole dopant, a p-dipole dopant, or a combination thereof. In some embodiments, gate electrodes 34A each include a work function layer, a barrier layer, and a bulk layer, or a combination thereof, which may be similar to work function layer 280, barrier layer 282, and bulk layer 284, respectively. In some embodiments, the gate structure 30A further includes a hard mask 42A, such as a self-aligned capping (SAC) layer. The hard mask 42A may comprise a dielectric material, such as silicon nitride.

Fabrication of device 12A may also include forming interconnects for device 12A, such as gate contacts and/or source/drain contacts 50A. In some embodiments, forming the source/drain contacts 50A includes: forming source/drain contact openings in dielectric layer 450 exposing epitaxial source/drain 25A; and forming at least one conductive layer (e.g., metal) in the source/drain contact openings. In some embodiments, the source/drain contact openings are formed by forming a patterned mask layer (e.g., an etch mask) over the dielectric layer 450 and etching the exposed portions of the dielectric layer 450. In some embodiments, forming at least one conductive layer in the source/drain contact opening includes: forming a metal silicide layer over the epitaxial source/drain electrodes 25A; depositing a barrier/liner layer partially filling the source/drain contact openings; depositing a metal layer over the barrier/liner layer filling the remaining portions of the source/drain contact openings; and a planarization process is performed to remove portions of the barrier/liner layer and/or the metal layer disposed over the top of the dielectric layer 450 and/or the gate structure 30A. Thus, the source/drain contacts may include a metal silicide layer, a barrier/liner layer, and a bulk metal layer, with the barrier/liner layer being located between the bulk metal layer and the dielectric layer 450 (e.g., CESL 45A) and the bulk metal layer and the metal silicide layer. In some embodiments, one or more insulating layers may be formed and processed in the source/drain contact openings to form contact spacers, such as dielectric layers and/or air gaps, along sidewalls of conductive portions (e.g., barrier layers and/or bulk metal layers) of the source/drain contacts 50A.

Referring to fig. 13, 14F, and 14G, method 300 includes attaching and/or bonding a first device of a stacked device structure (such as device 12A of stacked device structure 10) and a precursor for manufacturing a second device of a stacked device structure (such as a precursor for manufacturing device 12B of stacked device structure 10) in block 310. In the depicted embodiment, the precursor for fabricating device 12B includes a semiconductor layer stack 210' disposed over a substrate 460. The semiconductor layer stack 210' includes a semiconductor layer 215 and a semiconductor layer 220. Bottom semiconductor layer 215 may form the front side of device 12B and top semiconductor layer 215 may form the back side of device 12B. In some embodiments, semiconductor layer 215 and semiconductor layer 220 are alternately epitaxially grown over substrate 460. In some embodiments, the substrate 460 is a semiconductor substrate, such as a silicon substrate. In some embodiments, the substrate 460 is a carrier substrate comprising silicon, soda lime glass, fused silica, calcium fluoride, other suitable carrier substrate materials, or combinations thereof.

In fig. 14F and 14G, the front side of device 12A is bonded and/or attached to the back side of device 12B by insulating layer 16 (also referred to as a bonding layer). In some embodiments, device 12A is bonded to the precursor using a dielectric-to-dielectric bond. For example, the joining includes: forming an insulating layer 16A (i.e., a first dielectric layer) over the front side of the device 12A (fig. 14F); forming an insulating layer 16B (i.e., a second dielectric layer) over the back side of the device 12B (fig. 14F); the precursor is flipped over and placed over device 12A so that insulating layer 16B contacts insulating layer 16A (fig. 14G); and an annealing process or other suitable process is performed to achieve bonding of insulating layer 16A and insulating layer 16B. In some embodiments, insulating layer 16 is an oxide layer that attaches device 12A to a precursor for fabricating device 12B. In some embodiments, the dielectric-to-dielectric bonding process is an oxide-to-oxide bonding process that includes bonding an oxide layer formed on device 12A with an oxide layer formed on a precursor of device 12B. In some embodiments, the thickness of the insulating (bonding) layer 16 is about 10nm to about 100 μm.

After bonding, a thinning process and/or a lift-off process may be performed to remove the substrate 460 from the front side of the device 12B. For example, a planarization process such as CMP or an etching process may be performed to remove the substrate 460. The top semiconductor layer 215 may serve as a CMP stop layer and/or an etch stop layer when the substrate 460 is removed. Thereafter, the top semiconductor layer 215 may be removed from the semiconductor layer stack 210', for example, by an etching process. Removing top semiconductor layer 215 provides device 12B with top semiconductor layer 220, which will provide a top channel for device 12B as described herein. Other methods and/or techniques for removing the substrate 460 and/or the top semiconductor layer 215 are contemplated.

Referring to fig. 13 and 14H-14L, method 300 includes forming a second device of stacked device structure, such as device 12B of stacked device structure 10, in block 315. Forming device 12B includes processing the precursor (e.g., semiconductor layer stack 210') and performing a low temperature dipole engineering process, as described herein. In fig. 14H, the fabrication of device 12B includes patterning semiconductor layer stack 210' to form semiconductor fin 462 extending from insulating layer 16. Semiconductor fin 462 may include patterned portions of semiconductor layer stack 210' (i.e., semiconductor layer 215 and semiconductor layer 220). In some embodiments, the insulating layer 16 is also patterned such that the semiconductor fin 462 is disposed on a patterned portion (i.e., an insulating mesa) of the insulating layer 16. In some embodiments, the semiconductor layer stack 210' is patterned using a photolithography process and an etching process. In some embodiments, the semiconductor fin 462 is formed by a fin fabrication process. In some embodiments, isolation features, such as isolation feature 222, are formed over insulating layer 16 adjacent semiconductor fin 462.

In fig. 14H and 14I, fabricating the device 12B may further include: forming a gate structure 30B over the channel region of the semiconductor fin 462; forming source/drain recesses 470 in the source/drain regions of the semiconductor fin 462; and forming the inner spacers 24B. In some embodiments, forming gate structure 30B includes: forming at least one dummy gate layer (e.g., a dummy oxide layer, a polysilicon gate layer, and a hard mask layer) over the semiconductor fin 462 and the insulating layer 16; patterning at least one dummy gate layer to form a dummy gate 230; and gate spacers 40B are formed along sidewalls of the dummy gate 230. In some embodiments, forming the source/drain recesses 470 may include performing an etching process that selectively removes the semiconductor layer 215 and the semiconductor layer 220 relative to the gate structure 30B, such that the remaining portion of the semiconductor fin 462 forms the channel layer 210 in the channel region. In some embodiments, forming the inner spacer 24B includes: laterally etching the semiconductor layer 215 to form gaps between the semiconductor layer 220 and the insulating layer 16 (e.g., an insulating mesa thereof); and filling the gap with a dielectric material (e.g., depositing and etching a dielectric layer). In some embodiments, the processing described with reference to fig. 2 (e.g., in block 105 of method 100), fig. 3A and 3B may be implemented to form gate structure 30B (including dummy gate 230 and gate spacer 40B), channel layer 210, and inner spacer 24B as depicted in fig. 14H and 14I.

In fig. 14J, the fabrication of device 12B may further include: forming epitaxial source/drain 25B in source/drain recess 470; and forming a dielectric layer 250 (including CESL 45B and ILD layer 252) over epitaxial source/drain 25B and gate structure 30B. As noted above, epitaxial source/drain 25B comprises epitaxial material that is tailored and selected based on the type of device and/or transistor being fabricated. Here, where transistor 18B is configured as a p-type transistor, epitaxial source/drain 25B may comprise silicon germanium or germanium doped with boron and/or other p-type dopants. In some embodiments, the dielectric layer 250 is formed as described above with reference to fig. 2 (e.g., in block 105 of method 100), fig. 3A, and fig. 3B. A planarization process such as CMP may be applied to remove the dielectric layer 250 from over the gate structure 30B (fig. 14K).

In fig. 14K and 14L, the fabrication of device 12B may further include: a gate replacement process is performed (i.e., dummy gate 230 is replaced with a gate stack including gate dielectric 32B and gate electrode 34B) (fig. 14K); a channel release process is performed to provide a channel layer 20B (fig. 14K); and interconnects forming device 12B, such as gate contacts and/or source/drain contacts 50B (e.g., fig. 14L). Because device 12B is fabricated on device 12A, the processes performed to form transistor 18B (such as its gate stack) may adversely affect the characteristics and/or reliability of device 12A, such as described above. For example, a high temperature process may undesirably alter the doping profile of transistor 18A, which may undesirably alter its threshold voltage and/or reduce the structural integrity of transistor 18A, which may undesirably reduce its reliability. To minimize and/or eliminate such adverse effects, the gate stack and channel layer 20B of transistor 18B (top transistor) are formed as described above with reference to fig. 2 (e.g., in blocks 110-145 of method 100), fig. 4A-11A, and fig. 4B-11B. For example, the manufacturing may include: removing dummy gate 230 to form a gate opening in gate structure 30B (fig. 4A and 4B); performing a channel release process (fig. 5A and 5B); depositing a gate dielectric layer (e.g., interfacial layer 36B 'and gate dielectric layer 38B') that partially fills the gate opening (fig. 6A and 6B); performing a low temperature dipole engineering process on the gate dielectric layer (fig. 7A-9A and fig. 7B-9B); depositing a gate electrode layer (e.g., work function layer 280, barrier layer 282, and/or bulk layer 284) that fills the remainder of the gate opening (fig. 10A and 10B); and performing a planarization process to remove portions of the gate dielectric layer over dielectric layer 250 and/or portions of the gate electrode layer over dielectric layer 250 (fig. 11A and 11B). The channel release process may include: selectively removing the semiconductor layer 215, thereby floating the semiconductor layer 220 over the insulating layer 16 to provide the channel layer 20B; and gaps are formed in the gate openings between the channel layers 20B and the insulating layer 16 (or mesas thereof). The gate dielectric layer and/or the gate electrode layer may fill the gap and thus be formed around the channel layer 20B. Source/drain contacts 50B may then be formed similarly as described for source/drain contacts 50A.

The gate stack of transistor 18A may be configured the same as or different from the gate stack of transistor 18B. In the depicted embodiment, because transistor 18A is configured as an n-type transistor and transistor 18B is configured as a p-type transistor, gate dielectric 32A and gate dielectric 32B comprise different dipole dopant conductivity types. For example, gate dielectric 32A includes an n-dipole dopant (e.g., lanthanum), while gate dielectric 32B includes a p-dipole dopant (e.g., titanium) driven into it at a temperature below 600 ℃. Further, in such examples, gate electrode 34A and gate electrode 34B may comprise different work function materials. For example, gate electrode 34A may include an n-type work function material, while gate electrode 34B may include a p-type work function material. In some embodiments, gate dielectric 32A and gate dielectric 32B comprise different dipole dopant conductivity types, and gate electrode 34A and gate electrode 34B comprise the same conductive material (e.g., the same work function material).

In some embodiments, where both transistor 18A and transistor 18B are configured as p-type transistors, gate dielectric 32A and gate dielectric 32B include the same dipole dopant conductivity type (i.e., p-dipole dopant). Because transistor 18A is the bottom transistor of stacked device structure 10, and is therefore fabricated first, fabrication of transistor 18A does not affect devices that have been fabricated, and process temperatures, such as thermal drive-in temperatures, may be relaxed. For example, in some embodiments, gate dielectric 32A includes a p-dipole dopant (e.g., aluminum) that may be driven into it at a temperature greater than about 600 ℃, while gate dielectric 32B includes a p-dipole dopant (e.g., titanium) driven into it at a temperature less than 600 ℃. In some embodiments, gate dielectric 32A and gate dielectric 32B include the same p-dipole dopant (e.g., titanium) driven into them at a temperature below 600 ℃.

In some embodiments, where transistor 18A is configured as a p-type transistor and transistor 18B is configured as an n-type transistor, gate dielectric 32A and gate dielectric 32B comprise different dipole dopant conductivity types. Because transistor 18A is the bottom transistor of stacked device structure 10, and is therefore fabricated first, fabrication of transistor 18A does not affect devices that have been fabricated, and process temperatures, such as thermal drive-in temperatures, may be relaxed. For example, in some embodiments, gate dielectric 32A includes a p-dipole dopant (e.g., aluminum) that may be driven into it at a temperature greater than about 600 ℃, while gate dielectric 32B includes an n-dipole dopant. In some embodiments, the n-dipole dopant may be driven into the gate dielectric 32B at a temperature below 600 ℃ (e.g., strontium, erbium, magnesium, or a combination thereof). In some embodiments, gate dielectric 32A includes a p-dipole dopant (e.g., titanium) driven into it at a temperature below 600 ℃.

Devices and/or structures described herein, such as stacked device structure 10, device 12A, device 12B, transistor 18A, and transistor 18B, etc., may be included in a microprocessor, memory, other IC device, or a combination thereof. In some embodiments, the stacked device structures described herein are part of an IC chip, a system on a chip (SoC), or part thereof, that includes various passive and active microelectronic devices, such as resistors, capacitors, inductors, diodes, p-type FETs (PFETs), n-type FETs (NFETs), metal Oxide Semiconductor FETs (MOSFETs), complementary Metal Oxide Semiconductor (CMOS) transistors, bipolar Junction Transistors (BJTs), laterally Diffused MOS (LDMOS) transistors, high voltage transistors, high frequency transistors, other components, or combinations thereof.

The present disclosure provides many different embodiments. Methods of gate stack (e.g., high-k/metal gate) fabrication are described herein that implement low temperature dipole engineering and provide a number of advantages, particularly for stacked device structures. The gate stacks disclosed herein may be implemented in a variety of device types. For example, the gate stacks described herein are suitable for planar Field Effect Transistors (FETs), multi-gate transistors (such as finfets, GAA transistors, omega gate (Ω gate) devices, pi gate (pi gate) devices, or combinations thereof), as well as strained semiconductor devices, silicon-on-insulator (SOI) devices, partially depleted SOI devices, fully depleted SOI devices, other devices, or combinations thereof. The present disclosure also contemplates other semiconductor devices, such as capacitors, that one of ordinary skill may recognize as having the benefit of the material layer stacks and dipole engineering techniques described herein.

An exemplary method for forming a gate stack of a transistor stack includes: forming a high-k dielectric layer; forming a p-dipole dopant source over the high-k dielectric layer; performing a thermal drive-in process to drive the p-dipole dopant from the p-dipole dopant source into the high-k dielectric layer; and forming at least one conductive gate layer over the high-k dielectric layer after removing the p-dipole dopant source layer. The driving temperature of the thermal driving process is less than 600 ℃. In some embodiments, the drive-in temperature of the thermal drive-in process is about 300 ℃ to about 500 ℃. In some embodiments, the method further comprises: an interfacial layer is formed prior to forming the high-k dielectric layer, wherein the interfacial layer and the high-k dielectric layer form a gate dielectric of the gate stack. In some embodiments, the method further comprises: parameters of the thermal drive-in process are adjusted to provide a gate dielectric having a desired p-dipole dopant profile along the thickness of the gate dielectric. The peak of the desired p-dipole dopant profile is located at 0.5nm at the interface between the high-k dielectric layer and the interfacial layer, and the peak of the desired p-dipole dopant profile corresponds to the location in the gate dielectric having the greatest p-dipole dopant concentration.

In some embodiments, the p-dipole dopant is titanium. In some embodiments, the p-dipole dopant source layer comprises titanium and oxygen, nitrogen, carbon, or combinations thereof. In some embodiments, the p-dipole dopant source layer is a titanium oxide layer and the high-k dielectric layer is a zirconium-based oxide layer or a hafnium-based oxide layer.

Another exemplary method includes: forming a first transistor of the transistor stack; bonding a first transistor of the transistor stack to a precursor for fabricating a second transistor of the transistor stack; and forming a second transistor over the first transistor. Forming the second transistor includes processing the precursor, forming a gate stack of the second transistor, and performing a dipole engineering process. The gate stack includes a gate dielectric and a gate electrode. The dipole engineering process comprises the following steps: forming a p-dipole dopant source layer over the gate dielectric; performing a thermal drive-in process that drives the p-dipole dopant from the p-dipole dopant source into the gate dielectric; and removing the p-dipole dopant source layer. The driving temperature of the thermal driving process is less than 600 ℃. In some embodiments, the gate electrode is formed after the p-dipole dopant source layer is removed.

In some embodiments, the dipole engineering process is a first dipole engineering process, the thermal drive-in process is a first thermal drive-in process, the drive-in temperature is a first drive-in temperature, the gate dielectric is a first gate dielectric, the gate electrode is a first gate electrode, the gate stack is a first gate stack, the p-dipole dopant source layer is a first p-dipole dopant source layer, and the p-dipole dopant is a first p-dipole dopant. In such embodiments, forming the first transistor may include forming a second gate stack and performing a second dipole engineering process. The second gate stack includes a second gate dielectric and a second gate electrode. In some embodiments, the second dipole engineering process comprises: forming a second p-dipole dopant source over a second gate dielectric of a second gate stack of the first transistor; performing a second thermal drive-in process that drives a second p-dipole dopant from the second p-dipole dopant source into the second gate dielectric; and removing the second p-dipole dopant source layer. In some embodiments, the second gate electrode is formed after removing the second p-dipole dopant source layer.

In some embodiments, the second drive-in temperature of the second thermal drive-in process is less than 600 ℃. In such an embodiment, the first p-dipole dopant may be the same as the second p-dipole dopant, and the first p-dipole dopant and the second p-dipole dopant may be titanium. In some embodiments, the first n-dipole dopant may be different from the second n-dipole dopant, and the first n-dipole dopant is titanium.

In some embodiments, the second drive-in temperature of the second thermal drive-in process is at least 600 ℃. In such an embodiment, the first p-dipole dopant is different from the second p-dipole dopant, the first p-dipole dopant may be titanium, and the second p-dipole dopant may be aluminum.

In some embodiments, the second dipole engineering process comprises: forming an n-dipole dopant source over a second gate dielectric of a second gate stack of the first transistor; performing a second thermal drive-in process that drives n-dipole dopants from the n-dipole dopant source into the second gate dielectric; and removing the n-dipole dopant source layer. In such embodiments, the p-dipole dopant may be titanium, the second drive-in temperature of the second thermal drive-in process is less than about 600 ℃, and the n-dipole dopant may be strontium, erbium, magnesium, or a combination thereof. In other such embodiments, the p-dipole dopant may be titanium, the second drive-in temperature of the second thermal drive-in process is at least 600 ℃, and the n-dipole dopant may be lanthanum.

An example stacked device structure includes a transistor stack having a first transistor disposed over a second transistor. The first transistor has a first gate stack and the second transistor has a second gate stack. The first gate stack and the second gate stack each include an interfacial layer, a high-k dielectric layer disposed over the interfacial layer, and at least one conductive gate layer disposed over the high-k dielectric layer. The interface region of the interface layer of the high-k dielectric layer and the first gate stack includes a p-dipole dopant. The p-dipole dopant may be titanium. In some embodiments, the first transistor is a p-type transistor and the second transistor is an n-type transistor.

In some embodiments, the p-dipole dopant is a first p-dipole dopant, the interface region is a first interface region, and the second interface region of the interface layer of the high-k dielectric layer and the second gate stack comprises a second p-dipole dopant. The second p-dipole dopant may be the same as or different from the first p-dipole dopant. In some embodiments, the interface region is a first interface region and the second interface region of the interface layer of the high-k dielectric layer and the second gate stack comprises an n-dipole dopant.

In some embodiments, the interface region of the high-k dielectric layer and the interfacial layer of the first gate stack includes a portion of the high-k dielectric layer of the first gate stack, a portion of the interfacial layer of the first gate stack, and an interface between the high-k dielectric layer and the interfacial layer of the first gate stack. The peak of the dipole dopant distribution of the p-dipole dopant in the interface region is located at the interface + -0.5 nm. The peak of the dipole dopant profile corresponds to the location in the interface region having the greatest p-dipole dopant concentration.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the various aspects of the disclosure. Those skilled in the art will appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method for forming a gate stack of a transistor, wherein the transistor forms part of a transistor stack, the method comprising:

Forming a high-k dielectric layer;

forming a p-dipole dopant source over the high-k dielectric layer;

performing a thermal drive-in process that drives p-dipole dopants from the p-dipole dopant source into the high-k dielectric layer, wherein a drive-in temperature of the thermal drive-in process is less than 600 ℃; and

After removing the p-dipole dopant source, at least one conductive gate layer is formed over the high-k dielectric layer.

2. The method of claim 1, wherein the drive-in temperature of the thermal drive-in process is about 300 ℃ to about 500 ℃.

3. The method of claim 1, wherein the p-dipole dopant is titanium.

4. The method of claim 1, wherein the p-dipole dopant source comprises titanium and oxygen, nitrogen, carbon, or a combination thereof.

5. The method according to claim 1, wherein:

The p-dipole dopant source layer is a titanium oxide layer; and

The high-k dielectric layer is a zirconium-based oxide layer.

6. The method according to claim 1, wherein:

The p-dipole dopant source layer is a titanium oxide layer; and

The high-k dielectric layer is a hafnium-based oxide layer.

7. The method of claim 1, further comprising: an interfacial layer is formed prior to forming the high-k dielectric layer, wherein the interfacial layer and the high-k dielectric layer form a gate dielectric of the gate stack.

8. The method of claim 7, further comprising: parameters of the thermal drive-in process are adjusted to provide the gate dielectric with a desired p-dipole dopant profile along a thickness of the gate dielectric, wherein a peak of the desired p-dipole dopant profile is located at 0.5nm of an interface between the high-k dielectric layer and the interfacial layer, and wherein the peak of the desired p-dipole dopant profile corresponds to a location in the gate dielectric having a maximum p-dipole dopant concentration.

9. A method of forming a stacked device structure, comprising:

forming a first transistor of the transistor stack;

Bonding the first transistor of the transistor stack to a precursor for fabricating a second transistor of the transistor stack; and

Forming the second transistor over the first transistor, wherein forming the second transistor comprises processing the precursor, forming a gate stack of the second transistor, wherein the gate stack comprises a gate dielectric and a gate electrode, and performing a dipole engineering process, wherein the dipole engineering process comprises:

a p-dipole dopant source is formed over the gate dielectric,

Performing a thermal drive-in process that drives p-dipole dopants from the p-dipole dopant source into the gate dielectric, wherein a drive-in temperature of the thermal drive-in process is less than 600 ℃, and

The p-dipole dopant source layer is removed.

10. A stacked device structure, comprising:

A transistor stack having a first transistor disposed over a second transistor, wherein the first transistor has a first gate stack and the second transistor has a second gate stack;

Wherein each of the first gate stack and the second gate stack includes an interfacial layer, a high-k dielectric layer disposed over the interfacial layer, and at least one conductive gate layer disposed over the high-k dielectric layer; and

Wherein an interface region of the interface layer of the high-k dielectric layer and the first gate stack comprises a p-dipole dopant, wherein the p-dipole dopant is titanium.