CN118039324A - Center tap on-chip transformer with low alternating current impedance - Google Patents
Center tap on-chip transformer with low alternating current impedance Download PDFInfo
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- CN118039324A CN118039324A CN202310798000.XA CN202310798000A CN118039324A CN 118039324 A CN118039324 A CN 118039324A CN 202310798000 A CN202310798000 A CN 202310798000A CN 118039324 A CN118039324 A CN 118039324A
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Abstract
The invention provides a center tap on-chip transformer with low alternating current impedance, which comprises a center tap, a primary coil and a secondary coil; the secondary coil and the primary coil are arranged at intervals through a medium layer; the center tap is electrically connected with the primary coil and comprises a power line, a capacitor unit and a ground line; the power line is electrically connected with one end of the capacitor unit, and the ground line is electrically connected with the other end of the capacitor unit. The on-chip transformer with the low alternating current impedance reduces the impedance of a center tap, reduces parasitic inductance generated by a power line and improves the performance of the transformer.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a center tap on-chip transformer with low alternating current impedance.
Background
On-chip integrated transformers with center taps are commonly used in the design of millimeter wave circuits, such as power amplifiers, low noise amplifiers, mixers, frequency multipliers, and other circuit modules. The transformer is commonly used for realizing the functions of impedance matching, single-end-differential conversion and the like; the center tap is introduced into the transformer winding and can be used as a power supply to provide a low resistance path for common mode current or to provide a dc bias for the transistor.
In prior art solutions, the power supply and bias are often connected to the transformer from outside the transformer through a long length of center tap wiring to power or bias the circuit module. The center tap routing scheme introduces a large parasitic inductance, which causes a large impedance Z to be seen at the center tap of the transformer at a specific frequency point, which is a non-ideal factor for millimeter wave circuit design and affects the performance of the transformer.
Disclosure of Invention
The invention aims to provide a center tap on-chip transformer with low alternating current impedance, which reduces the impedance of a center tap, reduces parasitic inductance generated by a power line and improves the performance of the transformer.
To achieve the above object, in a first aspect, the present invention provides a center-tapped on-chip transformer having a low ac impedance, including a center tap, a primary coil, and a secondary coil;
the secondary coil and the primary coil are arranged at intervals through a medium layer;
The center tap is electrically connected with the primary coil and comprises a power line, a capacitor unit and a ground line; wherein,
The power line is electrically connected with one end of the capacitor unit, and the ground line is electrically connected with the other end of the capacitor unit.
In some embodiments, the center tap comprises M metal layers arranged in sequence;
a dielectric layer is arranged between each two metal layers, and a via hole is arranged on each metal layer;
the metal layers from the first layer to the M-2 layer are connected through an electric connecting wire to form a MOM capacitor;
the power line is routed through the M layer of the metal layer and is electrically connected with one end of the MOM capacitor through the corresponding via hole, and the ground line is routed through the M-1 layer of the metal layer and is electrically connected with the other end of the MOM capacitor through the corresponding other via hole.
In some embodiments, both ends of the center tap are provided with electrical outlets.
In some embodiments, one end of the center tap is provided with an electrical outlet, and the other end of the center tap is electrically connected to a capacitor.
In some embodiments, further comprising a substrate;
The center tapped on-chip transformer with low ac impedance is disposed on the substrate.
The center tap on-chip transformer with low alternating current impedance has the following beneficial effects:
1. the parasitic inductance of the power supply line is reduced.
2. The impedance at the center tap is reduced.
Drawings
FIG. 1 is a schematic diagram of a prior art on-chip transformer and center tap configuration;
FIG. 2 is a schematic diagram of an equivalent parasitic inductance of a prior art center tap;
FIG. 3 is a plot of |Z VDD |, |IP3| versus frequency;
FIG. 4 is a schematic diagram of the effect of a common mode signal of a prior art center tap on a differential signal;
FIG. 5 is a schematic diagram of a prior art single-side-powered unbalanced-track transformer;
FIG. 6 is a schematic diagram of a center-tapped on-chip transformer with low AC impedance according to an embodiment of the present invention;
FIG. 7 is a structural side view of a center tap with low AC impedance according to an embodiment of the present invention;
FIG. 8 is a schematic diagram of power and ground return path magnetic field cancellation;
FIG. 9 is an equivalent circuit diagram of a center tap of an embodiment provided by the present invention;
FIG. 10 is a schematic diagram of a single-side-powered center-tapped on-chip transformer with low AC impedance according to an embodiment of the present invention;
FIG. 11 is a schematic diagram of a center-tapped on-chip transformer with low AC impedance according to yet another embodiment of the present invention;
FIG. 12 is a schematic diagram of a single-side-powered center-tapped on-chip transformer with low AC impedance according to yet another embodiment of the present invention;
Fig. 13 is a graph comparing impedance modulus values at low frequencies for Z VDD of the prior art transformer and Z VDD of the on-chip transformer of the present application.
Reference numerals:
A center tap 1, a primary coil 2, a secondary coil 3, a capacitor 4, a capacitor unit 10, a first layer of the metal layer 11, a sixth layer of the metal layer 12, a seventh layer of the metal layer 13, an eighth layer of the metal layer 14, a power supply line 20, and a ground line 30.
Detailed Description
This application may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the application to those skilled in the art. In the drawings, the size of layers and regions, as well as the relative sizes, may be exaggerated for clarity. Like numbers refer to like elements throughout. It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.
Spatially relative terms, such as "under," "below," "beneath," "under," "above," "over," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.
Referring to fig. 1, the power supply and bias of a conventional transformer is often routed from outside the transformer through a long length of center tap 1 to a primary winding 2 on the transformer to power or bias the circuit module.
Referring to fig. 2, a conventional routing manner of the center tap 1 introduces a large parasitic inductance, which makes a large impedance Z VDD seen at the center tap 1 of the transformer at a specific frequency point, and brings about the following adverse effects:
1. Non-linearities are introduced: when the center tap 1 of the transformer is connected to the power supply through a long wire, the seen power supply impedance Z VDD affects the third-order intermodulation point (3rd order Intercept Point,IP3) of the circuit. As shown in fig. 3, the modulus of Z VDD is a curve varying with frequency, and at a low frequency point, the parasitic inductance of the power trace and the decoupling capacitance in the circuit resonate in parallel, so as to generate an impedance peak, and the frequency point is used as the frequency interval Δf to perform a double-tone test, so that the IP3 of the circuit is significantly deteriorated. Also, as the impedance mode value at the resonance point increases, the distortion of IP3 becomes more serious. Therefore, a solution is needed to reduce the impedance modulus at the resonance point to improve the IP3 performance of the designed circuit at any Δf. Likewise, when biased at center tap 1, a low resistance node is also required, otherwise additional nonlinearity is introduced.
2. Transformer common mode rejection capability decreases: since a large impedance Z VDD is seen at the center tap 1, this results in the presence of a common mode signal at the common mode point. As shown in fig. 4, external common mode interference may be superimposed on the differential signal of the differential circuit, resulting in an unbalanced amplitude and interference to the useful signal.
3. The impedance of the two sides of the center tap 1 with single-side power supply is unbalanced: when the chip area is limited or the electric leading-out terminal (PAD) resource is limited, the mode of simultaneously connecting the PAD at the two sides of the center tap 1 brings additional expense, and a structure of connecting the PAD at one side is often adopted at the moment. As shown in fig. 5, due to the asymmetry of the structure of the PAD connected to the single side, the central tap 1 wiring on one side of the PAD and the transformer coil have higher electromagnetic coupling, so that the impedance on two sides of the tap is unbalanced, and interference is formed on the differential signal.
4. Additional influence of parasitic inductance on circuit design: the wiring of the transformer center tap 1 is equivalent to a section of large parasitic inductance, and belongs to non-ideal factors for millimeter wave circuit design. For example, in millimeter wave and even higher frequency circuits, this extra parasitic inductance is likely to affect the peak efficiency and saturated output power of the power amplifier.
Referring to fig. 6, in order to solve the above technical problems, an embodiment of the present invention provides an on-chip transformer having a center tap 1 with low ac impedance, the on-chip transformer having the center tap 1 with low ac impedance including the center tap 1, a primary coil 2, and a secondary coil 3.
In particular, the center-tapped on-chip transformer with low ac impedance is provided on a substrate (not shown).
The substrate is a semiconductor substrate, and the semiconductor substrate can be a silicon substrate, a germanium substrate, a silicon-on-insulator substrate, a silicon carbide substrate, a germanium-silicon substrate, a gallium nitride substrate or a glass substrate.
The medium layer is arranged on the primary coil 2, and the secondary coil 3 is arranged on the medium layer, so that the secondary coil 3 and the primary coil 2 are arranged at intervals through the medium layer.
The dielectric layer is generally capable of withstanding the maximum electric field across it. In one embodiment of the present invention, the dielectric layer is made of silicon oxide.
In other embodiments of the application, other insulating polymers and oxides (e.g., insulating materials commonly used in integrated circuit fabrication) may also be used.
The center tap 1 is electrically connected with the primary coil 2, and the center tap 1 includes a power line 20, a capacitance unit 10, and a ground line 30. The power line 20 is electrically connected to one end of the capacitor unit 10, and the ground line 30 is electrically connected to the other end of the capacitor unit 10.
In some embodiments, the center tap 1 includes M metal layers sequentially stacked. Each of the metal layers has a dielectric layer therebetween, which may be formed of an oxide material. And each metal layer is provided with a via hole. The first metal layer 11 to the M-2 layer are connected by an electrical connection line to form a Metal Oxide Metal (MOM) capacitor, i.e. the capacitor unit 10. The power line 20 is routed through the M-th layer of the metal layer and is electrically connected to one end of the MOM capacitor through the corresponding via hole, and the ground line 30 is routed through the M-1-th layer of the metal layer and is electrically connected to the other end of the MOM capacitor through the corresponding other via hole.
Referring to fig. 7, for example, when M is equal to 8, the power line 20 may be routed through the eighth layer of the metal layer 14, and the ground line 30 may be routed through the seventh layer of the metal layer 13. At this time, each of the metal layers 11 to 12 may form the MOM capacitor through an electrical connection line passing through a corresponding via hole.
The via hole formed in the seventh metal layer 13 is defined as a seventh via hole, and the via hole formed in the sixth metal layer 12 is defined as a sixth via hole. The power line 20 may be electrically connected to one end of the MOM capacitor through the seventh via hole and the sixth via hole, and the ground line 30 may be electrically connected to the other end of the MOM capacitor through the sixth via hole, so as to achieve coupling between the power line 20 and the ground line 30 through the MOM capacitor.
In some embodiments, the ground line 30 is laid under the power line 20, and the capacitor unit 10 is introduced between the power line 20 and the ground line 30, so that the power supply impedance can be reduced.
Referring to fig. 8, it can be understood that a layer of the ground wire 30 is laid near the power wire 20, so as to form a current return path, and the power wire 20 and the ground wire 30 have opposite current directions, and perform a function of eliminating a magnetic field, so that parasitic inductance of the power wire 20 can be significantly reduced.
As shown in fig. 9, the equivalent model of the capacitive unit 10 is similar to the transmission line lumped parameter model,But unlike the transmission line, the capacitance in each of the capacitance units 10 is additionally introduced, and a small impedance can be seen from the center tap 1 by adding a large MOM capacitance.
As shown in fig. 10, in some embodiments, one end of the center leg is provided with an electrical outlet (PAD) and the other end of the center leg is electrically connected to a capacitor 4. For such a single-side power supply unbalanced wiring, the central shaft head can be adopted, the central tap 1 does not need to place PADs at two ends of the transformer to keep impedance balance, and the impedance of two sides can be very low, similar to AC ground, by adding a small capacitor 4 at the unbalanced side. Thus, PAD resources are saved, chip area is reduced, and common mode impedance seen by the center tap 1 is still low.
Referring to fig. 11, in some embodiments, for an on-chip transformer with a center tap 1 with low ac impedance and PAD on both sides, a ground line 30 may be laid directly on the outside of the power line 20 at the center tap in parallel, and then a MOM capacitor may be connected between the power line 20 and the ground line 30.
Referring to fig. 12, in some embodiments, also, for an on-chip transformer with a center tap 1 of low ac impedance supplied by a single-side PAD, a capacitor 4 is connected on the other side, and then a ground 30 may be laid directly under the running of the power line 20 at the center tap, or a ground 30 may be laid in parallel on the outside of the center tap, and a MOM capacitor may be connected between the power line 20 and the ground 30.
It should be noted that in this embodiment, MOM capacitors are used, and in fact, various types of capacitors may be used or mixed to be used as alternatives, such as MOS capacitors, varactor capacitors, MIM capacitors, etc., so that the capacitance density is higher, and the impedance of the center tap 1 may be further reduced.
Referring to fig. 13, in the scheme that the power supply is directly connected to the center tap 1, the maximum value of the impedance modulus of Z VDD at low frequency is about 10ohm, and after the scheme provided by the application is optimized, the peak value of Z VDD at about 50MHz is about 2ohm, the impedance modulus is obviously reduced, and the linearity is obviously improved.
While embodiments of the present invention have been described in detail hereinabove, it will be apparent to those skilled in the art that various modifications and variations can be made to these embodiments. It is to be understood that such modifications and variations are within the scope and spirit of the present invention as set forth in the following claims. Moreover, the invention described herein is capable of other embodiments and of being practiced or of being carried out in various ways.
Claims (6)
1. A center-tapped on-chip transformer with low ac impedance, comprising a center tap, a primary coil and a secondary coil;
the secondary coil and the primary coil are arranged at intervals through a medium layer;
The center tap is electrically connected with the primary coil and comprises a power line, a capacitor unit and a ground line; wherein,
The power line is electrically connected with one end of the capacitor unit, and the ground line is electrically connected with the other end of the capacitor unit.
2. The on-chip transformer of claim 1, wherein the center tap comprises M metal layers stacked in sequence;
a dielectric layer is arranged between each two metal layers, and a via hole is arranged on each metal layer;
the metal layers from the first layer to the M-2 layer are connected through an electric connecting wire to form a MOM capacitor;
the power line is routed through the M layer of the metal layer and is electrically connected with one end of the MOM capacitor through the corresponding via hole, and the ground line is routed through the M-1 layer of the metal layer and is electrically connected with the other end of the MOM capacitor through the corresponding other via hole.
3. The on-chip transformer of claim 2, wherein both ends of the center tap are provided with electrical outlets.
4. The on-chip transformer of claim 2, wherein one end of the center tap is provided with an electrical outlet, and the other end of the center tap is electrically connected to a capacitor.
5. The on-chip transformer according to claim 1, wherein the power line and the ground line are arranged side by side in parallel, and the capacitance unit is located between the power line and the ground line and electrically connected to the power line and the ground line.
6. The on-chip transformer of claim 1, further comprising a substrate;
The center tapped on-chip transformer with low ac impedance is disposed on the substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310798000.XA CN118039324A (en) | 2023-06-30 | 2023-06-30 | Center tap on-chip transformer with low alternating current impedance |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310798000.XA CN118039324A (en) | 2023-06-30 | 2023-06-30 | Center tap on-chip transformer with low alternating current impedance |
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| Publication Number | Publication Date |
|---|---|
| CN118039324A true CN118039324A (en) | 2024-05-14 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310798000.XA Pending CN118039324A (en) | 2023-06-30 | 2023-06-30 | Center tap on-chip transformer with low alternating current impedance |
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- 2023-06-30 CN CN202310798000.XA patent/CN118039324A/en active Pending
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