CN118034610B

CN118034610B - Key data processing method applied to memory, device and equipment

Info

Publication number: CN118034610B
Application number: CN202410405275.7A
Authority: CN
Inventors: 潘学功; 罗鹏; 陈强; 马博
Original assignee: Open Security Research Inc
Current assignee: Open Security Research Inc
Filing date: 2024-04-07
Publication date: 2024-07-02
Anticipated expiration: 2044-04-07

Abstract

The application provides a key data processing method applied to a memory, the memory, a device and equipment, and belongs to the technical field of data management. The method comprises the following steps: performing space pre-division processing on a storage space of a memory according to pre-stored data to obtain a plurality of data Identification (ID) ranges and a plurality of data storage areas, and determining a data type-storage area mapping relation; when the data updating/writing instruction of the instruction to be operated is detected, ID allocation processing is carried out according to the data to be processed and the mapping relation between the data type and the storage area, so that an ID to be written, an address range to be stored, a data area to be stored and a data item deleting space are obtained; determining a standby space; and when the length of the standby space is detected to be greater than the length of the data to be processed, writing the data to be processed into the standby space according to a preset data format, and generating a check code. The application solves the problem that the data updating operation of the existing memory has low updating/writing speed when the scene of frequently updating data is needed.

Description

Key data processing method applied to memory, device and equipment

Technical Field

The present application relates to the field of data management technologies, and in particular, to a method, a memory, a device, and an apparatus for processing key data applied to a memory.

Background

As the update speed and amount of data increases, the storage and management of data updates becomes more and more important, and the amount of re-writable memory in a storage device is also increasing, for example: FLASH memory and electrically erasable programmable read-only memory EEPROM memory. The FLASH memory FLASH memory is not easy to lose storage content after power failure, and is a nonvolatile memory, so that the FLASH memory FLASH memory has the advantages of low power consumption, high storage density, erasability, convenience in updating and the like. And thus are widely used as memory cells in chips.

At present, in the prior art, the data updating operation of the rewritable memory is direct naked operation, taking a data storage scheme of a FLASH as an example, when writing or updating data into the FLASH, the position of a corresponding storage block (generally 4K byte) in the memory is calculated according to an address to be updated/written, the whole data is read from the FLASH into a random access memory RAM, then the data to be updated is updated in the RAM, then the data on the storage block corresponding to the FLASH is erased, and finally the data in the RAM is written back into the storage block.

However, the inventors found that the prior art has at least the following technical problems: when used in a scenario requiring frequent data update, there is a problem in that the update/write speed is slow when the data update operation of the existing memory is performed.

Disclosure of Invention

The application provides a key data processing method, a memory, a device and equipment applied to a memory, which are used for solving the problem that the update/write speed of the data update operation of the existing memory is slow when the key data processing method, the memory, the device and the equipment are used for a scene requiring frequent data update.

In a first aspect, the present application provides a key data processing method applied to a memory, including:

carrying out space pre-division processing on a storage space of a memory according to pre-stored data to obtain a plurality of data Identification (ID) ranges and a plurality of data storage areas, and determining a data type-storage area mapping relation according to the plurality of ID ranges and the plurality of data storage areas;

Acquiring an instruction to be operated, acquiring data to be processed when the instruction to be operated is detected to be a data updating/writing instruction, and performing ID allocation processing according to the data to be processed and the data type-storage area mapping relation to acquire an ID to be written, an address range to be stored, a data area to be stored and a data item deleting space, wherein the address range to be stored is in the data area to be stored;

determining a standby space according to the address range to be stored, the data area to be stored, the residual storage space and the data item deleting space;

When the length of the standby space is detected to be larger than the length of the data to be processed, writing the data to be processed into the standby space according to a preset data format, and generating a check code;

and determining the ID to be written, the length of the data to be processed and the check code as additional attribute data and writing the additional attribute data into the standby space according to the preset data format.

In one possible implementation manner, the data identifier ID allocation process according to the data to be processed and the data type-storage area mapping relationship includes: determining a target data type according to the data to be processed; determining a target storage address range according to the target data type and the data type-storage area mapping relation; when the starting address of the target storage address range is detected to be smaller than the end address, attribute data traversing each stored data is read from the starting address, wherein the attribute data of the stored data comprises a used ID and a stored data state; when the stored data state is detected to be in an idle state, determining a target ID range according to the used ID corresponding to the stored data state; when the starting ID of the target ID range is detected to be greater than or equal to the end ID, traversing each ID from the starting ID until the first unused ID in the target ID range is obtained, and determining the ID to be written and a plurality of used storage spaces corresponding to the used IDs before the first unused ID.

In one possible implementation manner, the data identifier ID allocation process according to the data to be processed and the data type-storage area mapping relationship further includes: recording attribute data of the stored data into a used array when the stored data state is detected to be in a use state, or recording attribute data of the stored data into a deleted array when the stored data state is detected to be in a deletion state; determining a start address of the next stored data according to the attribute array of the stored data and the stored data, determining the start address of the next stored data as a start address, and returning to the step of reading the attribute data traversing each stored data from the start address; and determining an address range to be stored, a data area to be stored and a data item deleting space according to the attribute data of the stored data in the used array and the attribute data of the stored data in the deleted array.

In one possible implementation manner, the determining the standby space according to the address range to be stored, the data area to be stored, the remaining storage space and the deleted data item space includes: reading the data to be judged from the head address of the data area to be stored to obtain attribute data of each group of data to be judged; determining the data state and the read address of the data to be judged according to the attribute data of each group of data to be judged; and when the data state of the data to be judged is detected to be an idle state, determining a standby space according to the address range to be stored, the read address and the deleted data item space.

In one possible implementation manner, after determining the standby space according to the address range to be stored, the data area to be stored, the remaining storage space and the deleted data item space, the method further includes: when the length of the standby space is detected to be smaller than the length of the data to be processed and the sum of the length of the standby space and the length of the deleted data item space is larger than the length of the data to be processed, performing space arrangement processing on all the stored data areas to obtain a target free space, wherein the target free space comprises at least one free area, and the length of the free area is larger than the length of the data to be processed; writing the data to be processed into an idle area in the target idle space according to a preset data format, and generating a check code; and determining the ID to be written, the length of the data to be processed and the check code as additional attribute data and writing the additional attribute data into a first idle area in the target idle space according to the preset data format.

In one possible implementation manner, the performing a spatial arrangement process on all the storage data areas to obtain a target free space includes: sequentially reading each group of stored data in the storage data area from the first address, and acquiring state data of the group of stored data being read; when the state data of the group of stored data being read is detected to be in a use state, copying the group of stored data being read into a RAM, reading the next group of stored data and acquiring the state data of the next group of stored data; when detecting that the state data of the group of stored data being read is in a deleting state, directly reading the next group of stored data and acquiring the state data of the next group of stored data; and when the state data of the next group of stored data is detected to be in an idle state, deleting all the data in the storage data area, and writing the stored data in the RAM into the storage data area.

In one possible implementation manner, before the generating the check code, the method further includes: when the fact that the data to be processed are all written into the idle area in the target idle space is detected, a completion mark is generated; writing the completion identifier into a space between the data to be processed and the check code in a free area in the target free space before generating the check code, and further comprising: when the fact that the data to be processed are all written into the idle area in the target idle space is detected, a completion mark is generated; and writing the completion identification into a space between the data to be processed and the check code in a free area in the target free space.

In one possible implementation, the method further includes: when the instruction to be operated is detected to be a data reading instruction, acquiring an ID to be read; and traversing and reading the state data and the stored ID of each stored data in the memory from the beginning in sequence, and reading the stored data corresponding to the stored ID when the state data of the stored data is detected to be in a use state and the stored ID is consistent with the ID to be read.

In a second aspect, the present application provides a memory, using a key data processing method as described in the first aspect as applied to a memory, the memory comprising a plurality of memory blocks and at least one newly added memory block, wherein the number of the newly added memory blocks is determined according to data parameters to be processed, memory block parameters and expected design operational lifetime.

In a third aspect, the present application provides a key data processing apparatus for use in a memory, comprising:

The space processing module is used for carrying out space pre-division processing on the storage space of the memory according to pre-stored data to obtain a plurality of ID ranges and a plurality of data storage areas, and determining a mapping relation between the data types and the storage areas according to the plurality of ID ranges and the plurality of data storage areas;

the ID distribution module is used for acquiring an instruction to be operated, and acquiring data to be processed when the instruction to be operated is detected to be a data updating/writing instruction; performing ID allocation processing according to the data to be processed and the data type-storage area mapping relation to obtain an ID to be written, an address range to be stored, a data area to be stored and a data item deleting space, wherein the address range to be stored is in the data area to be stored;

the operation module is used for determining a standby space according to the address range to be stored, the data area to be stored, the residual storage space and the data item deleting space;

The data processing module is used for writing the data to be processed into the standby space according to a preset data format and generating a check code when the length of the standby space is detected to be larger than the length of the data to be processed;

the data processing module is further configured to determine the ID to be written, the length of the data to be processed, and the check code as additional attribute data, and write the additional attribute data into the standby space according to the preset data format.

In a fourth aspect, the present application provides a key data processing apparatus for use in a memory, comprising: at least one processor and storage means;

the storage device stores computer-executable instructions;

The at least one processor executes computer-executable instructions stored by the storage device, causing the at least one processor to perform the key data processing method as described in the first aspect as applied to the memory.

In a fifth aspect, the present application provides a computer-readable storage medium having stored therein computer-executable instructions which, when executed by a processor, implement a key data processing method as described in the first aspect applied to a memory.

The application provides a key data processing method, a memory, a device and equipment applied to the memory. And when the acquired data updating/writing instruction of the to-be-operated instruction is detected, carrying out ID allocation processing according to the acquired to-be-processed data and the data type-storage area mapping relation to acquire a to-be-written ID, a to-be-stored address range, a to-be-stored data area and a deleted data item space, and then determining a standby space. When the length of the standby space is detected to be greater than the length of the data to be processed, the data to be processed is written into the standby space according to a preset data format, a check code is generated, and finally the ID to be written and the length of the data to be processed and the check code are determined to be additional attribute data and are written into the standby space according to the preset data format. The data processing process can directly write the data to be processed into the standby space in the data block without naked operation, and the writing speed is faster for writing small data such as key data by a granularity writing mode smaller than the data block.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions of the prior art, the drawings that are needed in the embodiments or the description of the prior art will be briefly described below, it will be obvious that the drawings in the following description are some embodiments of the present application, and that other drawings can be obtained according to these drawings without inventive effort to a person skilled in the art.

Fig. 1 is a schematic diagram of an application scenario of a key data processing method applied to a memory according to an embodiment of the present application;

fig. 2 is a flow chart of a key data processing method applied to a memory according to an embodiment of the present application;

FIG. 3 is a schematic diagram of a mapping relationship between data types and storage areas according to an embodiment of the present application;

Fig. 4 is a schematic diagram of a data ID allocation process according to an embodiment of the present application;

FIG. 5 is a schematic flow chart of a spatial arrangement process according to an embodiment of the present application;

FIG. 6 is a schematic diagram of a key data processing device applied to a memory according to an embodiment of the present application;

fig. 7 is a schematic hardware structure of a key data processing device applied to a memory according to an embodiment of the present application.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

Currently, the inventor finds that the FLASH bare operation repeatedly performs four steps of reading, changing, erasing and writing back every time of updating, and the minimum erasing unit is one memory block BLCOK according to the characteristics of FLASH, so that the unit of each operation is one or more BLCOK. Given the data written each time, especially when the data needs to be updated frequently, if one or more BLOCKs are arbitrarily used as data processing operation units, the time consumption is significantly increased when the data is processed by bare operations, resulting in a problem of slow writing/updating of the data in the memory. In addition, for data that needs to be updated frequently, if the data are updated on the same BLOCK, the BLOCK is frequently erased, so that the service life of the FLASH is significantly reduced. The number of memory block erasures for FLASH is limited to 10 tens of thousands of times. For high frequency updated data, such as system time, it is assumed that 1 second is updated once. If no special processing is done, the lifetime of the corresponding memory block of the FLASH memory will run out soon.

In order to solve the above technical problems, the embodiments of the present application provide the following technical ideas for solving the problems: firstly, stored data are identified through a unique data identification ID, the stored data are operated and managed through the returned ID in the subsequent reading and deleting of the key data, when the residual storage space in one storage block is enough to store the key data needing to be written/updated, the key data to be written are directly stored in the residual space of the storage block, and the key data occupy small memory granularity, so that the key processing method of the memory can perform data processing operation in the storage block with smaller granularity than the storage block, the writing/updating speed of the key data is improved, the deletable data can be read according to the ID, the storage space is tidied, the utilization rate of the storage space is improved, the erasing times of the storage block are reduced, and the service life of the memory is prolonged.

Fig. 1 is a schematic application scenario diagram of a key data processing method applied to a memory according to an embodiment of the present application, where, as shown in fig. 1, the method includes: a terminal 101 and a server 102.

The terminal 101 is used for inputting an operation instruction page and displaying an operation result by a data manager. The server 102 is configured to receive the operation instruction and the data to be processed, and perform a corresponding data processing operation. Wherein the server 102 may be a chip containing memory. Fig. 2 is a flow chart of a key data processing method applied to a memory according to an embodiment of the present application, and an execution subject of the embodiment may be the server 102 in the embodiment shown in fig. 1, or may be other related devices of a computer, which is not particularly limited to this embodiment. In this embodiment, the memory is a memory device that needs to be written after being erased, and such memory devices include, but are not limited to, a FLASH memory device and an EEPROM.

As shown in fig. 2, the key data processing method applied to the memory includes:

s201: and carrying out space pre-division processing on the storage space of the memory according to pre-stored data to obtain a plurality of data Identification (ID) ranges and a plurality of data storage areas, and determining a data type-storage area mapping relation according to the plurality of ID ranges and the plurality of data storage areas.

Fig. 3 is a schematic diagram of a mapping relationship between data types and storage areas according to an embodiment of the present application.

In this embodiment, the pre-stored data may be pre-stored history data. By classifying and summarizing pre-stored data, data types possibly needing to be stored in data management work are obtained, a plurality of ID ranges and a plurality of data storage areas are divided according to the data types, each ID range corresponds to one data storage area, and each data storage area can only store one corresponding type of data. As shown in fig. 3, for example: the ID range of the RSA key is (0 x 10100-0 x 100200), and the data storage area of the RSA key is (0 x 4000-0 xA 000); the ECC key has an ID range of (0 x 10200-0 x 10300), and the data storage area of the ECC key is (0 xA 000-0 xC 000).

In the present embodiment, the data type-storage area mapping relationship refers to data reflecting the type of storage data in the memory and the index relationship of the divided storage areas in the memory.

As shown in fig. 3, in this embodiment, the main data stored in the memory is taken as an example of a key, and different key types have corresponding key data identification ID ranges and different key storage areas, and each key storage area is an address range. If the ID range corresponding to the symmetric key is (0 x 10000-0 x 100100), the storage area corresponding to the symmetric key is (0 x 2000-0 x 4000). Therefore, aiming at different key types, the corresponding storage area can be quickly positioned through the ID of the key, and then the quick reading of the data in the corresponding storage area is realized without searching the whole storage space.

S202: and acquiring an instruction to be operated, acquiring data to be processed when the instruction to be operated is detected to be a data updating/writing instruction, and carrying out ID allocation processing according to the data to be processed and the data type-storage area mapping relation to obtain an ID to be written, an address range to be stored, a data area to be stored and a data item deleting space, wherein the address range to be stored is in the data area to be stored.

In this embodiment, step S202 aims to find a data storage area corresponding to the data to be processed, retrieve the data stored in the storage area, and record the data in the global variable. And finding unused IDs for allocation by traversing ID data in the ID range corresponding to the data storage area.

Fig. 4 is a schematic diagram of a data ID allocation process according to an embodiment of the present application.

As shown in fig. 4, in an alternative embodiment of the present application, in step S202, data ID allocation processing is performed according to the data to be processed and the data type-storage area mapping relationship, including:

s202a: and determining the target data type according to the data to be processed.

S202b: determining a target storage address range according to the target data type and the data type-storage area mapping relation; when it is detected that the start address of the target storage address range is smaller than the end address, attribute data traversing each of the stored data is read from the start address, wherein the attribute data of the stored data includes the used ID and the stored data state.

Specifically, in this embodiment, step S202b may include:

b1: the target storage address range is determined assuming that the target storage address range is from a start address start_addr to an end address end_addr.

B2: it is detected whether start_addr is smaller than end_addr.

B3: if the start_addr is less than the end_addr, the attribute data traversing each of the stored data is read from the start address, wherein the attribute data of the stored data includes the used ID and the stored data state.

In this embodiment, if the detection result in step b2 is yes, it indicates that the data stored in the target storage address range may store the same data as the data to be processed. At this time, the attribute data of all the data stored in the target storage address range need to be read. The stored data states in this embodiment may include an idle state, a use state, and a delete state.

B4: it is detected whether the stored data state is an idle state.

S202c: when the stored data state is detected to be in an idle state, a target ID range is determined according to the used ID corresponding to the stored data state.

In this embodiment, the target ID range refers to an ID value section in which the ID of the stored data of the same data type as the data to be processed is located. The start ID (i.e., ID start sequence number start_id) and end ID (i.e., ID end sequence number end_id) are available from the target ID range. After determining the target ID range, it is also necessary to detect whether the start_id is smaller than the end_id.

S202d: when the starting ID of the target ID range is detected to be greater than or equal to the end ID, traversing each ID from the starting ID until the first unused ID in the target ID range is obtained, wherein the first unused ID is determined to be the ID to be written and a plurality of used storage spaces corresponding to the used IDs before the first unused ID.

In this embodiment, the process of traversing each ID refers to a process of sequentially reading the start ID from the start ID and then updating the obtained start ID, comparing the start ID with the used ID obtained in step S202b, and detecting whether or not there is no ID identical to the start ID being read in the stored data.

If the detection result is no, the step of adding 1 to the start ID being read and returning to step S202c to detect whether the start ID is smaller than the end ID.

If the detection result is yes, the ID being read is regarded as the first unused ID in the target ID range, and the first unused ID is determined as the code ID. Determining a plurality of used storage spaces corresponding to the used IDs before the first unused ID refers to determining the space size occupied by the stored data corresponding to each used ID before the used ID according to the mapping relation between each used ID before the used ID and the data type and storage area, and accumulating the space size.

In this embodiment, as shown in FIG. 4, the used array is recorded as g_use_ arry, and the deleted array is recorded as g_del_ arry. As can be seen from the above embodiments, when it is detected that the start_id is smaller than the end_id, it is also necessary to detect whether there is no start_id in the g_use_ arry and the g_del_ arry. When it is detected that there is no start_id in g_use_ arry and g_del_ arry, then accumulating the slot_size in g_use_ arry and g_del_ arry results in a total used g_used_size. When it is detected that the start_id exists in the g_use_ arry and the g_del_ arry, the start_id+1 is obtained as a new start_id, and the step of detecting whether the start_id is smaller than the end_id is returned to until it is detected that the start_id is not used. In this embodiment, g_used_size corresponds to a plurality of used memory spaces corresponding to used IDs preceding the first unused ID in the above embodiment. Then the first unused ID is determined as the ID to be written and the ID to be written is returned. When it is detected that the start_id is greater than or equal to the end_id, the ID allocation failure is returned. This may indicate that the storage space is full.

For step b4, when it is detected that the stored data state is not the idle state, it is further detected whether the stored data state is the use state.

In an optional embodiment of the present application, the data identifier ID allocation process is performed on the data to be processed and the data type-storage area mapping relationship in step S202, and the method further includes:

s202e: recording attribute data of the stored data into the used array when the stored data state is detected to be in a use state, or recording attribute data of the stored data into the deleted array when the stored data state is detected to be in a delete state; determining a start address of the next stored data according to the attribute array of the stored data and the stored data, determining the start address of the next stored data as the start address, and returning to the step of reading the attribute data traversing each stored data from the start address.

Specifically, in an alternative embodiment of the present application, step S202e includes:

e1: when the stored data state is detected to be a use state, attribute data of the stored data is recorded into the used array.

In this embodiment, as shown in fig. 4, it is assumed that the stored data is a slot, and when the slot is in a use state, the attribute of the slot is recorded in the used array g_use_ arry.

E2: when the state of the stored data is detected to be the deletion state, the attribute data of the stored data is recorded into the deleted array.

As shown in fig. 4, in this embodiment, when solt is in the delete state, the attribute of the slot is recorded in the deleted group g_del_ arry.

The deletion state in this embodiment refers to that the data state in the attribute data of the stored data is marked as delete deleted, and when the whole storage space is full of data, new data cannot be written again and new data still needs to be written later, the data deletion operation on the memory is actually executed to delete the data with the data state marked as deleted.

And e3: after steps e1 and e2 are performed, a start address of the next stored data is determined based on the attribute data of the stored data and the stored data, and the start address of the next stored data is determined as the start address, and then step b2 is returned.

In this embodiment, the attribute data of the stored data further includes an address length of the stored data, and the start address of the next stored data is the start address of the stored data being read plus the address length of the stored data. For example: when the start address of the stored data being read is start_addr1 and the address length of the stored data is slot_size, the start address of the next stored data is start_addr2=start_addr1+slot_size.

S202f: and determining an address range to be stored, a data area to be stored and a deleted data item space according to the attribute data of the stored data in the used array and the attribute data of the stored data in the deleted array.

In this embodiment, the address range to be stored refers to an address interval available for storing data to be processed in a data area to be stored, and the deleted data item space refers to an address interval occupied by stored data whose stored data state is a deleted state in all stored data.

S203: and determining a standby space according to the address range to be stored, the data area to be stored, the residual storage space and the deleted data item space.

In this embodiment, the standby space refers to an address interval that can be used to store data to be processed finally.

Specifically, in an alternative embodiment of the present application, step S203 includes:

S203a: and reading the data to be judged from the head address of the data area to be stored to obtain attribute data of each group of data to be judged.

S203b: and determining the data state and the read address of the data to be judged according to the attribute data of each group of data to be judged.

S203c: and when the data state of the data to be judged is detected to be in an idle state, determining a standby space according to the address range to be stored, the read address and the deleted data item space.

In this embodiment, the DATA to be judged refers to DATA stored in a DATA area to be stored, and in this embodiment, the DATA to be judged stored in the memory may include original DATA and attribute DATA for recording related information of the original DATA, where each set of attribute DATA packets of the DATA to be judged may include a DATA STATE, a DATA identifier ID, a DATA length SIZE, and a check code CRC32. For convenience of description, in this embodiment, the original data added with attribute data is referred to as a storage data slot (a group of data to be judged may be referred to as a slot). In this embodiment, only one BLOCK of memory is described, where the BLOCK is the smallest unit of erase in the memory, for example, NOR FLASH is typically 2K or 4K, and a memory typically has multiple BLOCKs, and so on for the data management process of the entire memory.

In this embodiment, a slot is specifically defined as follows:

STATE 4+ID 4+SIZE 4+DATA n+CRC32:4. Wherein STATE represents solt STATEs, which occupy 4 bytes in the data area to be stored, and the STATE definitions include an idle STATE, a use STATE, and a delete STATE, and define the STATE of the data after memory erase as the idle STATE. The ID is a unique identification of the original DATA DATA, the ID also occupies 4 bytes, the DATA identification ID can be automatically generated when the original DATA is stored in the memory by adopting an ID generation algorithm such as a self-increasing algorithm, a hash algorithm or a snowflake algorithm, and the like, and the ID can be used for quickly indexing the memory to find the corresponding original DATA when the subsequent DATA is read and deleted. SIZE is used to represent the value of the total length of the stored raw data and attribute data, and occupies 4 bytes. CRC32 also takes 4 bytes for data verification.

The data structure stored in the memory is shown in the following table:

For the first group of data to be judged, the first address is 0, the first read r_addr=0 is recorded, then 12 bytes of data corresponding to the first group of data to be judged are sequentially read, and the first three bytes of the slot structure are corresponding. After the STATE value of the slot is judged, when the STATE is in an idle STATE, the storage space where the r_addr read currently is located is not used, and the length calculation for determining the standby space can be directly performed. When STATE is in use, assuming that the last read address in the used array is r_addr1, the length of the last stored data slot in the used array is slot_size, and updating r_addr2=r_addr1+slot_size. When STATE is in a deleted STATE, the stored data is recorded into a deleted array, and if the previous deleted space in the deleted array is del_size1 and the length of the stored data slot is slot_size, the currently recorded deleted space del_size2=del_size1+slot_size is updated and the read address is r_addr2=r_addr1+slot_size. Further, assuming that the data area to be stored is flash_size, the address being read is r_addr, and the length of the deleted data item space is del_size, the spare space length free_size=flash_size-r_addr-del_size.

S204: and when the length of the standby space is detected to be greater than the length of the data to be processed, writing the data to be processed into the standby space according to a preset data format, and generating a check code.

In this embodiment, the length of data to be processed refers to an address range between the first address of the inactive space to the last address of the inactive space. When the length of the standby space is detected to be larger than the length of the data to be processed, the data to be processed can be completely stored in the standby space. In this embodiment, the preset data format is a format that is manually specified and has a certain data writing sequence, for example, the preset data format may be a specific definition format of slots in step S203 in the above embodiment. In this embodiment, the check code may be a code for checking whether the read data is data to be read when the data to be processed is read.

S205: and determining the ID to be written, the length of the data to be processed and the check code as additional attribute data and writing the additional attribute data into a standby space according to a preset data format.

In this embodiment, since the to-be-processed data is written, in order to facilitate subsequent data management, the to-be-written ID, the length of the to-be-processed data, and the check code are also required to be written as additional attribute data together with the to-be-processed data. In this embodiment, when the additional attribute data is written into the standby space, the status data of the data to be processed should be written first, then the ID to be written is written, then the length of the data to be processed is written, and finally the check code is stored in the standby space behind the data to be processed.

Based on the above embodiments, in an optional embodiment of the present application, after determining the inactive space according to the address range to be stored, the data area to be stored, the remaining storage space, and the deleted data item space in step S203, the method further includes:

Step A: and when the length of the standby space is detected to be smaller than the length of the data to be processed and the sum of the length of the standby space and the length of the deleted data item space is larger than the length of the data to be processed, performing space arrangement processing on all the storage data areas to obtain a target free space, wherein the target free space comprises at least one free area, and the length of the free area is larger than the length of the data to be processed.

And (B) step (B): writing the data to be processed into the idle area in the target idle space according to a preset data format, and generating a check code.

Step C: and determining the ID to be written, the length of the data to be processed and the check code as additional attribute data and writing the additional attribute data into a first idle area in the target idle space according to a preset data format.

In this embodiment, the space sorting process refers to a process of deleting all the original data corresponding to slots marked as deleted state on the memory when the write-in/update operation needs to be triggered again after the storage space on the memory is full, so as to obtain more free storage space for writing new data. In this embodiment, in order to avoid fragmentation of the storage space, the sorted free space may be uniformly placed behind the BLOCK.

In this embodiment, the free area in the target free space into which the data to be processed is written generally refers to the first free area, for example: the free area may be an address section corresponding to the first unused ID after the ID of 0x23 in table two in the above embodiment.

Specifically, in an optional embodiment of the present application, in step a, performing space adjustment processing on all the storage data areas to obtain a target free space, including:

a1: each set of stored data in the stored data area is read in sequence from the first address, and the status data of the set of stored data being read is acquired.

Fig. 5 is a schematic flow chart of a spatial arrangement process according to an embodiment of the present application.

As shown in fig. 5, in the present embodiment, a first set of stored data (hereinafter, simply referred to as a first slot) in a memory block is read from a first address in a memory data area, and then state data of the first slot is acquired. And detecting whether the state data of the first slot is in a use state.

A2: when the state data of the group of stored data being read is detected to be in a use state, the group of stored data being read is copied into the RAM, and the next group of stored data is read and the state data of the next group of stored data is acquired.

As shown in fig. 5, in this embodiment, if the first slot is detected to be in the use state, the content of the first slot is copied to the RAM, and the next slot is read from the first address after the length of the first slot, and the step of reading the state data of the slots is repeated.

If the first slot is detected not to be in the use state, continuing to detect whether the first slot is in the deletion state. If the first slot is detected to be in the deleting state, the next slot is read from the first address after the length of the first slot, and the step of reading the state data of the slot is returned.

Step S204c: when detecting that the state data of the group of stored data being read is in a deleted state, the next group of stored data is directly read and the state data of the next group of stored data is acquired.

A3: when the state data of the next group of stored data is detected to be in an idle state, all the data in the storage data area are deleted, and the stored data in the RAM are written into the storage data area.

As shown in fig. 5, assuming that the first slot is detected to be in a use state, the second slot is detected to be in a delete state, and the third slot is in an idle state, since the first slot is already copied to the RAM, at this time, all the data in the data storage area may be deleted, and the first slot in the RAM may be written back to the memory. Finishing the storage space arrangement.

Exemplary, as shown in the following table:

Assuming that the storage space before sorting is shown in the first storage data structure table in the above embodiment, the storage space after sorting is shown in the second storage data structure table, and only the data in the use state is in the storage space after sorting.

On the basis of the foregoing embodiment, as an optional embodiment of the present application, before generating the check code in step S204, the method further includes:

Step D: and when detecting that the data to be processed are completely written into the idle area in the target idle space, generating a completion mark.

Step E: writing the completion identification into a space between the data to be processed and the check code in the free area in the target free space.

In this embodiment, the completion identifier may be a character identifier automatically generated after all the data to be processed is written, and the location of the completion identifier where the completion identifier is written into the free area in the target free space may be an address after the data to be processed. The corresponding data format at this time is: STATE:4+id:4+size:4+data: n+completion flag: 4+CRC32:4. When only the completion identification is read later, a conclusion that the corresponding data to be processed is complete data can be obtained, corresponding operation is adopted, incomplete data can be selected to be deleted or marked as a state to be confirmed, and data management is facilitated. Likewise, before generating the check code in step B, the foregoing steps D and E may also be included, and the principles and procedures thereof will not be repeated herein.

Based on the foregoing embodiments, the method for processing key data applied to a memory provided in an optional embodiment of the present application further includes:

Step F: when the instruction to be operated is detected to be a data deleting instruction, acquiring a pre-deleting ID of the data to be deleted;

Step G: and reading the state data of the data to be deleted in the memory according to the pre-deletion ID, and marking the state data of the data to be deleted as a deletion state.

In this embodiment, because the storage space of the memory is limited, when the user needs to delete the stored data, the pre-delete ID of the data to be deleted may be obtained based on the operation of the user, and the ID in all the additional attribute data corresponding to the pre-delete ID may be quickly matched to the same ID as the pre-delete ID by traversing the ID in the additional attribute data, and the state data in the additional attribute data corresponding to the ID may be marked as a deleted state, and when the subsequent storage space is full and needs to be deleted, the stored data marked as a deleted state may be directly erased.

In an optional embodiment of the present application, the method for processing key data applied to a memory further includes:

Step H: and when the instruction to be operated is detected to be a data reading instruction, acquiring the ID to be read.

Step I: the state data and the stored ID of each stored data in the read memory are traversed in sequence from the beginning, and when the state data of the stored data is detected to be in a use state and the stored ID is consistent with the ID to be read, the stored data corresponding to the stored ID is read.

In this embodiment, when corresponding stored data needs to be read, only the ID to be read needs to be obtained based on the related operation of the user, and the stored data in the corresponding data access area can be quickly located through the ID to be read, and then the stored data is directly read, so that quick reading of the data is realized, and all the stored data in the whole memory does not need to be retrieved.

In summary, according to the key data processing method applied to the memory provided by the embodiment of the application, the space pre-dividing processing is performed on the storage space of the memory according to the pre-stored data to obtain a plurality of data Identification (ID) ranges and a plurality of data storage areas, and the mapping relation between the data types and the storage areas is determined according to the plurality of ID ranges and the plurality of data storage areas. And when the acquired data updating/writing instruction of the to-be-operated instruction is detected, carrying out ID allocation processing according to the acquired to-be-processed data and the data type-storage area mapping relation to acquire a to-be-written ID, a to-be-stored address range, a to-be-stored data area and a deleted data item space, and then determining a standby space. When the length of the standby space is detected to be greater than the length of the data to be processed, the data to be processed is written into the standby space according to a preset data format, a check code is generated, and finally the ID to be written and the length of the data to be processed and the check code are determined to be additional attribute data and are written into the standby space according to the preset data format. The data processing process can directly write the data to be processed into the standby space in the data block without naked operation, and the writing speed is faster for writing small data such as key data by a granularity writing mode smaller than the data block.

Meanwhile, when the occupied memory of the data to be processed is smaller than the length of the standby space in one storage block, the data can be directly written into/updated into the standby space, the space in the storage block is utilized to the greatest extent, the erasure of the storage block is reduced as much as possible, and therefore the service life of the storage block is prolonged, and the service life of the storage is prolonged.

Meanwhile, when the data to be processed is found to be written into the standby space in a shortage mode, the space occupied by the key data in a deleted state is released through space arrangement, the space of the storage block is utilized more greatly, the erasing times of the storage block are reduced, the purpose of balancing abrasion of the whole storage is achieved, and the service life of the storage is further prolonged.

The embodiment of the application also provides a memory, which is used for storing the data to be processed in the method, such as a system clock, a counter and the like, besides the key data, and can be used for storing the data which need to be frequently updated or changed, and comprises a plurality of original storage blocks and at least one newly-added storage block, wherein the number of the newly-added storage blocks is determined according to the parameters of the data to be processed, the parameters of the storage blocks and the expected service life.

In this embodiment, the data processing is completed by setting at least one newly added memory block and using the technical scheme in the above method embodiment.

In this embodiment, the parameters of the data to be processed may be the maximum occupied storage space size of the data to be processed and the update speed of the data to be processed, and the parameters of the storage block may be the storage space size of the storage block and the designed erasing time lifetime of the storage block. The expected operating life refers to the designed service life of the system or device that generates the data to be processed.

For example, assuming that the maximum occupied space of data to be processed generated by the system clock is 1KB each time, the space of one memory block is 4KB, the erasure time of a single memory block is 10 tens of thousands times, the update speed of data to be processed is once per minute, the expected working life of the system clock is 5 years, the total required update time is calculated to be n=5×356×24×60= 2563200 times, the update time supported by each memory block is u= (4 KB/1 KB) ×100000=400000, the required number of memory blocks is b=n/u= 65.048, namely, 65 memory blocks can fulfill the memory design requirement, and additional memory blocks are added on the basis to balance the memory data, generally, the number of added memory blocks is one third of the number of memory blocks originally required, namely, 22 blocks, and the required memory blocks are n=b+ (b/3) =87 blocks under consideration of wear balance. Thus, when the data is updated each time, the embodiment 1 is used to complete the writing/updating of the data to be processed, when the storage space of the first storage block is insufficient or full, the data on the first storage block is not erased immediately, but the second storage block is written in continuously, and so on, until all the allocated storage blocks are full, the corresponding data blocks are not erased.

In summary, the key data processing method applied to the memory provided in this embodiment avoids repeated erasure of one memory block in a multi-block balanced storage manner, thereby achieving the purpose of wear leveling of the FLASH memory, and further improving the service life of the whole FLASH memory.

Fig. 6 is a schematic structural diagram of a key data processing device applied to a memory according to an embodiment of the present application, where the device includes: a spatial processing module 61, an ID allocation module 62, an operation module 63, and a data processing module 64.

The spatial processing module 61 is configured to perform spatial pre-partitioning processing on a storage space of the memory according to pre-stored data, obtain a plurality of ID ranges and a plurality of data storage areas, and determine a mapping relationship between a data type and a storage area according to the plurality of ID ranges and the plurality of data storage areas.

The ID allocation module 62 is configured to obtain an instruction to be operated, and when detecting that the instruction to be operated is a data update/write instruction, obtain data to be processed; and carrying out ID allocation processing according to the data to be processed and the data type-storage area mapping relation to obtain an ID to be written, an address range to be stored, a data area to be stored and a data item deleting space, wherein the address range to be stored is in the data area to be stored.

The operation module 63 is configured to determine a standby space according to the address range to be stored, the data area to be stored, the remaining storage space, and the deleted data item space.

The data processing module 64 is configured to, when detecting that the length of the standby space is greater than the length of the data to be processed, write the data to be processed into the standby space according to a preset data format, and generate a check code.

The data processing module 65 is further configured to determine the ID to be written and the length and the check code of the data to be processed as additional attribute data and write the additional attribute data into the standby space according to a preset data format.

In an alternative embodiment of the present application, the ID allocation module 62 is specifically configured to: determining a target data type according to the data to be processed; determining a target storage address range according to the target data type and the data type-storage area mapping relation; when the starting address of the target storage address range is detected to be smaller than the end address, the attribute data of each stored data is read from the starting address, wherein the attribute data of the stored data comprises a used ID and a stored data state; when the stored data state is detected to be in an idle state, determining a target ID range according to the used ID corresponding to the stored data state; when the starting ID of the target ID range is detected to be greater than or equal to the end ID, traversing each ID from the starting ID until the first unused ID in the target ID range is obtained, wherein the first unused ID is determined to be the ID to be written and a plurality of used storage spaces corresponding to the used IDs before the first unused ID.

In an alternative embodiment of the present application, the ID allocation module 62 is further specifically configured to: recording attribute data of the stored data into the used array when the stored data state is detected to be in a use state, or recording attribute data of the stored data into the deleted array when the stored data state is detected to be in a delete state; determining a start address of the next stored data according to the attribute array of the stored data and the stored data, determining the start address of the next stored data as the start address, and returning to the step of reading the attribute data traversing each stored data from the start address; and determining an address range to be stored, a data area to be stored and a deleted data item space according to the attribute data of the stored data in the used array and the attribute data of the stored data in the deleted array.

In an alternative embodiment of the present application, the operation module 63 is specifically configured to: reading the data to be judged from the head address of the data area to be stored to obtain attribute data of each group of data to be judged; determining the data state and the read address of the data to be judged according to the attribute data of each group of data to be judged; and when the data state of the data to be judged is detected to be in an idle state, determining a standby space according to the address range to be stored, the read address and the deleted data item space.

In an alternative embodiment of the present application, the spatial processing module 61 is further configured to: when the length of the standby space is detected to be smaller than the length of the data to be processed and the sum of the length of the standby space and the length of the deleted data item space is larger than the length of the data to be processed, performing space arrangement processing on all the stored data areas to obtain a target free space, wherein the target free space comprises at least one free area, and the length of the free area is larger than the length of the data to be processed; writing the data to be processed into an idle area in a target idle space according to a preset data format, and generating a check code; and determining the ID to be written, the length of the data to be processed and the check code as additional attribute data and writing the additional attribute data into a first idle area in the target idle space according to a preset data format.

In an alternative embodiment of the present application, the spatial processing module 61 is specifically configured to: sequentially reading each group of stored data in the storage data area from the first address, and acquiring state data of the group of stored data being read; when detecting that the state data of the group of stored data being read is in a use state, copying the group of stored data being read into the RAM, reading the next group of stored data and acquiring the state data of the next group of stored data; when detecting that the state data of the group of stored data being read is in a deleting state, directly reading the next group of stored data and acquiring the state data of the next group of stored data; when the state data of the next group of stored data is detected to be in an idle state, all the data in the storage data area are deleted, and the stored data in the RAM are written into the storage data area.

In an alternative embodiment of the present application, the data processing module 64 is further configured to, before generating the check code: when detecting that the data to be processed are completely written into the idle area in the target idle space, generating a completion mark; writing the completion identification into a space between the data to be processed and the check code in the free area in the target free space.

In an alternative embodiment of the present application, the data processing module 64 is further configured to: when the instruction to be operated is detected to be a data deleting instruction, acquiring a pre-deleting ID of the data to be deleted; and reading the state data of the data to be deleted in the memory according to the pre-deletion ID, and marking the state data of the data to be deleted as a deletion state.

In an alternative embodiment of the application, the data processing module 65 is further configured to: when the instruction to be operated is detected to be a data reading instruction, acquiring an ID to be read; the state data and the stored ID of each stored data in the read memory are traversed in sequence from the beginning, and when the state data of the stored data is detected to be in a use state and the stored ID is consistent with the ID to be read, the stored data corresponding to the stored ID is read.

The key data processing device applied to the memory provided in this embodiment may be used to execute the technical scheme of the foregoing method embodiment, and its implementation principle and technical effect are similar, and this embodiment is not repeated here.

Fig. 7 is a schematic hardware structure of a key data processing device applied to a memory according to an embodiment of the present application, where, as shown in fig. 7, the device includes: at least one processor 701 and a storage 702.

Wherein the storage 702 is configured to store computer-executable instructions.

A processor 701 for executing computer-executable instructions stored in a storage device 702 to perform the steps involved in the above-described method embodiments. Reference may be made in particular to the relevant description of the embodiments of the method described above.

Alternatively, the memory device 502 may be separate or integrated with the processor 501.

When the memory device 502 is provided separately, the apparatus further comprises a bus 503 for connecting the memory device 502 and the processor 501.

The embodiment of the application also provides a computer readable storage medium, wherein computer executable instructions are stored in the computer readable storage medium, and when a processor executes the computer executable instructions, the key data processing method applied to the memory is realized.

The embodiment of the application also provides a computer program product, which comprises a computer program, wherein the computer program is executed by a processor to realize the key data processing method applied to a memory.

In the several embodiments provided by the present application, it should be understood that the disclosed apparatus and method may be implemented in other manners. For example, the above-described embodiments of the apparatus are merely illustrative, and for example, the above-described division of modules is merely a logical function division, and there may be other manners of dividing the modules when actually implemented, for example, multiple modules may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or modules, which may be in electrical, mechanical, or other forms.

The modules described above as separate components may or may not be physically separate, and components shown as modules may or may not be physical units, may be located in one place, or may be distributed over multiple network units. Some or all of the modules may be selected according to actual needs to implement the solution of this embodiment.

In addition, each functional module in the embodiments of the present invention may be integrated in one processing unit, or each module may exist alone physically, or two or more modules may be integrated in one unit. The units formed by the modules can be realized in a form of hardware or a form of hardware and software functional units.

The integrated modules, which are implemented in the form of software functional modules, may be stored in a computer readable storage medium. The software functional modules described above are stored in a storage medium and include instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) or processor to perform some of the steps of the methods of the various embodiments of the application.

It should be appreciated that the Processor may be a central processing unit (Central Processing Unit, abbreviated as CPU), or may be other general purpose Processor, digital signal Processor (DIGITAL SIGNAL Processor, abbreviated as DSP), application SPECIFIC INTEGRATED Circuit (ASIC), or the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of a method disclosed in connection with the present invention may be embodied directly in a hardware processor for execution, or in a combination of hardware and software modules in a processor for execution.

The memory may comprise a high-speed RAM memory, and may further comprise a non-volatile memory NVM, such as at least one magnetic disk memory, and may also be a U-disk, a removable hard disk, a read-only memory, a magnetic disk or optical disk, etc.

The bus may be an industry standard architecture (Industry Standard Architecture, ISA) bus, an external device interconnect (PERIPHERAL COMPONENT INTERCONNECT, PCI) bus, or an extended industry standard architecture (Extended Industry Standard Architecture, EISA) bus, among others. The buses may be divided into address buses, data buses, control buses, etc. For ease of illustration, the buses in the drawings of the present application are not limited to only one bus or to one type of bus.

The storage medium may be implemented by any type or combination of volatile or nonvolatile memory devices such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic or optical disk. A storage media may be any available media that can be accessed by a general purpose or special purpose computer.

An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an Application SPECIFIC INTEGRATED Circuits (ASIC). It is also possible that the processor and the storage medium reside as discrete components in an electronic device or a master device.

Those of ordinary skill in the art will appreciate that: all or part of the steps for implementing the method embodiments described above may be performed by hardware associated with program instructions. The foregoing program may be stored in a computer readable storage medium. The program, when executed, performs steps including the method embodiments described above; and the aforementioned storage medium includes: various media that can store program code, such as ROM, RAM, magnetic or optical disks.

To illustrate the technical solution of the application, but not to limit it; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the application.

Claims

1. A key data processing method applied to a memory, comprising:

Acquiring an instruction to be operated, acquiring data to be processed when the instruction to be operated is detected to be a data updating/writing instruction, and performing ID allocation processing according to the data to be processed and the data type-storage area mapping relation to acquire an ID to be written, an address range to be stored, a data area to be stored and a data item deleting space, wherein the address range to be stored is in the data area to be stored; the data identification ID allocation processing according to the data to be processed and the data type-storage area mapping relation comprises the following steps:

Determining a target data type according to the data to be processed;

determining a target storage address range according to the target data type and the data type-storage area mapping relation; when the starting address of the target storage address range is detected to be smaller than the end address, attribute data traversing each stored data is read from the starting address, wherein the attribute data of the stored data comprises a used ID and a stored data state;

When the stored data state is detected to be in an idle state, determining a target ID range according to the used ID corresponding to the stored data state;

when detecting that the starting ID of the target ID range is greater than or equal to the end ID, traversing each ID from the starting ID until the first unused ID in the target ID range is obtained, and determining the ID to be written and a plurality of used storage spaces corresponding to the used IDs before the first unused ID;

2. The method according to claim 1, wherein the data identification ID allocation process is performed according to the data to be processed and the data type-storage area mapping relationship, further comprising:

recording attribute data of the stored data into a used array when the stored data state is detected to be in a use state, or recording attribute data of the stored data into a deleted array when the stored data state is detected to be in a deletion state; determining a start address of the next stored data according to the attribute array of the stored data and the stored data, determining the start address of the next stored data as a start address, and returning to the step of reading the attribute data traversing each stored data from the start address;

And determining an address range to be stored, a data area to be stored and a data item deleting space according to the attribute data of the stored data in the used array and the attribute data of the stored data in the deleted array.

3. The method of claim 1, wherein the determining the inactive space based on the address range to be stored, the data area to be stored, the remaining storage space, and the deleted data item space comprises:

reading the data to be judged from the head address of the data area to be stored to obtain attribute data of each group of data to be judged;

Determining the data state and the read address of the data to be judged according to the attribute data of each group of data to be judged;

And when the data state of the data to be judged is detected to be an idle state, determining a standby space according to the address range to be stored, the read address and the deleted data item space.

4. The method of claim 1, wherein after determining the inactive space based on the address range to be stored, the data area to be stored, the remaining storage space, and the deleted data item space, further comprising:

when the length of the standby space is detected to be smaller than the length of the data to be processed and the sum of the length of the standby space and the length of the deleted data item space is larger than the length of the data to be processed, performing space arrangement processing on all the stored data areas to obtain a target free space, wherein the target free space comprises at least one free area, and the length of the free area is larger than the length of the data to be processed;

writing the data to be processed into an idle area in the target idle space according to a preset data format, and generating a check code;

and determining the ID to be written, the length of the data to be processed and the check code as additional attribute data and writing the additional attribute data into a first idle area in the target idle space according to the preset data format.

5. The method of claim 4, wherein the performing spatial arrangement on all the storage data areas to obtain the target free space comprises:

Sequentially reading each group of stored data in the storage data area from the first address, and acquiring state data of the group of stored data being read;

When the state data of the group of stored data being read is detected to be in a use state, copying the group of stored data being read into a RAM, reading the next group of stored data and acquiring the state data of the next group of stored data;

When detecting that the state data of the group of stored data being read is in a deleting state, directly reading the next group of stored data and acquiring the state data of the next group of stored data;

and when the state data of the next group of stored data is detected to be in an idle state, deleting all the data in the storage data area, and writing the stored data in the RAM into the storage data area.

6. The method of claim 4, wherein prior to generating the check code, further comprising:

when the fact that the data to be processed are all written into the idle area in the target idle space is detected, a completion mark is generated;

And writing the completion identification into a space between the data to be processed and the check code in a free area in the target free space.

7. The method as recited in claim 1, further comprising:

when the instruction to be operated is detected to be a data reading instruction, acquiring an ID to be read;

And traversing and reading the state data and the stored ID of each stored data in the memory from the beginning in sequence, and reading the stored data corresponding to the stored ID when the state data of the stored data is detected to be in a use state and the stored ID is consistent with the ID to be read.

8. A memory using the key data processing method applied to the memory according to any one of claims 1 to 7, characterized in that the memory includes a plurality of memory blocks and at least one newly added memory block, wherein the number of the newly added memory blocks is determined according to data parameters to be processed, memory block parameters, and expected design operating life.

9. A key data processing apparatus for use in a memory, comprising:

the ID distribution module is used for acquiring an instruction to be operated, and acquiring data to be processed when the instruction to be operated is detected to be a data updating/writing instruction; performing ID allocation processing according to the data to be processed and the data type-storage area mapping relation to obtain an ID to be written, an address range to be stored, a data area to be stored and a data item deleting space, wherein the address range to be stored is in the data area to be stored; the ID allocation module is specifically configured to: determining a target data type according to the data to be processed; determining a target storage address range according to the target data type and the data type-storage area mapping relation; when the starting address of the target storage address range is detected to be smaller than the end address, attribute data traversing each stored data is read from the starting address, wherein the attribute data of the stored data comprises a used ID and a stored data state; when the stored data state is detected to be in an idle state, determining a target ID range according to the used ID corresponding to the stored data state; when detecting that the starting ID of the target ID range is greater than or equal to the end ID, traversing each ID from the starting ID until the first unused ID in the target ID range is obtained, and determining the ID to be written and a plurality of used storage spaces corresponding to the used IDs before the first unused ID;

10. A key data processing apparatus applied to a memory, comprising: at least one processor and storage means;

the storage device stores computer-executable instructions;

The at least one processor executing computer-executable instructions stored by the storage device causes the at least one processor to perform the method of key data processing as claimed in any one of claims 1 to 7 applied to a memory.

11. A computer-readable storage medium having stored therein computer-executable instructions which, when executed by a processor, implement the key data processing method applied to a memory as claimed in any one of claims 1 to 7.